A packaged chip vertical electrical microconnection structure and a method for manufacturing the same

Abstract

The application discloses a packaged chip vertical electrical micro-connection structure and a preparation method thereof, and relates to the technical field of semiconductor packaging, and aims to solve the problem of easy breaking of lead wires caused by excessively large wire arc and excessively long lead wires in the prior art. The conductive paste is sprayed from the top to the bottom, and is applied to the back surface of the chip through the side wall of the chip from the exposed pads on the front surface of the chip, so that the input / output ports on the front surface of the chip are guided to the back surface. The lead wire attached to the surface of the chip by the conductive paste can solve the problem of easy breaking of lead wires caused by excessively large wire arc and excessively long lead wires. Meanwhile, the electrical connection in the vertical direction of the chip can be completed without the design of pre-added solder joints and related process steps. The reliability and integration degree can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a vertical electrical micro-connection structure for a packaged chip and its fabrication method. Background Technology

[0002] The casing used to mount semiconductor integrated circuit chips serves to house, fix, seal, and protect the chips, enhance their electrothermal performance, and act as a bridge between the chip's internal world and external circuits. The contacts on the chip are connected to the pins of the package via wires, and these pins, in turn, connect to other devices via wires on the printed circuit board. Semiconductor packaging assembles a large number of chips into a highly dense unit, then achieves electrical connections to the outside world through leads. Therefore, stable electrical connections are needed between chips, or between the chip's input / output ports and the package pins or pads on the substrate. Furthermore, to adapt to the development of modern semiconductor devices towards smaller size and more multifunctionality, packaging technology is increasingly focused on reducing the interconnect size of chips.

[0003] Therefore, developing reasonable and highly integrated micro-connection technologies is key to achieving high-density, high-reliability microelectronic packaging and assembly. Summary of the Invention

[0004] The purpose of this invention is to provide a vertical electrical micro-connection structure for packaged chips and its fabrication method, which solves the problem of easy breakage of leads caused by excessive arc and excessive length of leads in the prior art.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] In a first aspect, the present invention provides a vertical electrical micro-connection structure for a packaged chip, comprising:

[0007] Substrate; a substrate pin area is provided on the substrate;

[0008] A chip, wherein a front functional area is provided on the chip;

[0009] A conductive paste layer is provided on the back side of the chip near the substrate, on the front side of the chip opposite to the back side of the chip, and on the sidewall between the back side and the front side of the chip. The back side and the front side of the chip are not completely covered by the conductive paste layer, and the conductive paste layer on the back side of the chip is fixedly connected to the substrate. The conductive paste is led from the front side of the chip to the back side of the chip to form connecting pillars to connect the functional area on the front side of the chip and the pin area of ​​the substrate.

[0010] An insulating dielectric layer is disposed between the chip and the conductive paste layer.

[0011] In a second aspect, the present invention provides a method for fabricating a vertical electrical micro-connection structure for a packaged chip, the method comprising:

[0012] A layer of insulating material is applied to the functional area on the front of the chip.

[0013] An insulating material needs to be applied to the back of the chip where it connects to the substrate.

[0014] The applied insulating material is defined as the dielectric layer, which does not completely cover the back side and the front side of the chip;

[0015] The conductive paste is started from the functional area on the front side of the chip, passes through the chip sidewall, and is led from the front side of the chip to the back side of the chip to form a connection post that connects to the substrate.

[0016] The conductive paste is applied to the substrate pin area of ​​the substrate to connect the functional area on the front of the chip and the substrate pin area together, forming a vertical electrical micro-connection structure for the packaged chip.

[0017] Compared with existing technologies, this invention provides a vertical electrical micro-connection structure for packaged chips and its fabrication method. Through top-down spraying, conductive paste is applied from the exposed pads on the front side of the chip, passing through the chip sidewalls to the back side, thereby guiding the input / output ports on the front side to the back side. The conductive paste-attached leads to the chip surface solve the problem of lead breakage caused by excessive arc and length. Simultaneously, vertical electrical connections can be achieved without pre-adding solder joints or related process steps. Connecting the front input / output ports to the back side via attached leads reduces the requirements for the chip front-end design and fabrication process, simplifies the overall manufacturing process, and improves the applicability of vertical interconnects in packaged micro-connections. All electrical micro-connection leads are attached to the chip surface, making them less prone to breakage or detachment, thus improving reliability and integration. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0019] Figure 1 This is a schematic diagram of the vertical electrical micro-connection structure of the packaged chip provided by the present invention;

[0020] Figure 2 This is a schematic diagram of the vertical electrical micro-connection method for the packaged chip provided by the present invention;

[0021] Figure 3A schematic diagram illustrating the fabrication process of the vertical electrical micro-connection structure of the packaged chip based on electrofluid inkjet printing and a multi-axis linkage device provided by the present invention.

[0022] Figure 4 This is a schematic diagram illustrating the fabrication process of the vertical electrical micro-connection structure for the chip based on the flexible soft nozzle provided by the present invention.

[0023] Reference numerals: 1-Chip, 2-Substrate, 101-Functional area on the front of the chip, 102-Insulating dielectric layer, 103-Conductive paste layer, 104-Connecting post, 105-Substrate pin area, 106-Sidewall. Detailed Implementation

[0024] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0025] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0026] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0027] Currently, the micro-connection of chips in semiconductor packaging mainly relies on two methods: wire bonding and flip-chip bonding.

[0028] Wire bonding is a method that connects the pads of a chip to the pads of a package substrate using metal wires. The metal wires form the first bonding point with the chip pads, and then the metal wires are pulled to the second bonding point (usually the pads of the package substrate) for bonding. In this method, the metal wires act as an electrical connection bridge.

[0029] Flip-chip bonding uses a planar process, where input / output ports are led out from the pads on the functional area of ​​the chip via solder balls. An insulating dielectric layer is first applied to the chip, and windows are created in the pad areas using photolithography. Then, a metal transition layer is filled, followed by bottom metal deposition. Next, metal pillars are electroplated onto the deposited layer and heated and reflowed to form solder balls. Finally, the chip is flipped over and mounted onto an external circuit board, with adhesive filling the gaps between the bottom balls to achieve the final electrical connection between the chip and the substrate.

[0030] Among the commonly used methods mentioned above, wire bonding requires pads to be arranged around the chip on the package substrate, which occupies a certain package space. In addition, the metal wires have a certain length and curvature, making them prone to breakage. While flip-chip bonding can provide a larger number of input / output ports, it requires multiple process steps to be added in advance during the chip design phase. If the chip is not specifically designed for flip-chip bonding, it also needs to be redesigned and processed.

[0031] To address the aforementioned shortcomings, this solution provides a universal electrical connection technology that can form a reliable vertical interconnect with the carrier board and can be used on general chips without a pre-designed ball-mounting process.

[0032] Next, the solutions provided in the embodiments of this specification will be described in conjunction with the accompanying drawings:

[0033] Figure 1 This is a schematic diagram of the vertical electrical micro-connection structure of the packaged chip provided by the present invention. Figure 1As shown, the vertical electrical micro-connection structure of the packaged chip may include a substrate 2 and a chip 1. The substrate 2 is provided with a substrate pin area 105, and the chip 1 is provided with a chip front functional area 101. The vertical electrical micro-connection structure of the packaged chip also includes an insulating dielectric layer 102, a conductive paste layer 103, and connecting pillars 104. The conductive paste layer 103 is provided on the back side of the chip near the substrate 2, on the front side of the chip opposite to the back side, and on the sidewall 106 between the back side and the front side of the chip. The back side and the front side of the chip are not completely covered by the conductive paste layer 103, and the conductive paste layer 103 on the back side of the chip is fixedly connected to the substrate 2. The conductive paste is led from the front side of the chip to the back side of the chip to form connecting pillars 104 to connect the chip front functional area 101 and the substrate pin area 105. The insulating dielectric layer 102 is applied from the front pad area of ​​the chip to the back area where it needs to connect with the substrate, but it does not completely cover the pad area. The conductive paste starts from the front pad area of ​​the chip, passes through the chip sidewall, and is led from the front of the chip to the back of the chip, forming the connection pillars 104 that connect with the substrate. The conductive paste is also applied to the substrate pin area 105, and the connection pillars 104 and the substrate pin area 105 are connected together to form a stable electrical connection structure. The front pad area of ​​the chip is the front functional area of ​​the chip.

[0034] It should be noted that in practical applications, the chip may have multiple layers; these multiple layers of chips may be stacked and vertically connected; or, the chip and the substrate may be vertically interconnected. When the chip and the substrate are vertically interconnected, the active area on the front side of the chip faces upwards.

[0035] The sidewalls of the chip are stepped; the conductive paste layer and the insulating dielectric layer are coated by at least one of the following methods: microelectronic inkjet printing, dispensing, and photolithography.

[0036] The chip has input / output ports in its front functional area, which are connected to the back of the chip via attached leads; all electrical micro-connection leads of the chip are attached to the chip surface.

[0037] The conductive paste of the conductive paste layer can be any one of nano silver paste, nano silver ink, gold, copper, gold-palladium, and nickel;

[0038] The insulating dielectric layer can be any one of the insulating materials selected from SU-8, epoxy resin, and polyimide.

[0039] In forming the above Figure 1 When constructing a vertical electrical micro-connection structure for a packaged chip, the corresponding fabrication method can be combined with... Figure 2 Explanation:

[0040] Figure 2 This is a schematic diagram of the vertical electrical micro-connection method for the packaged chip provided by the present invention. Figure 2 As shown, the process may include the following steps:

[0041] Step 210: Apply a layer of insulating material to the functional area on the front of the chip.

[0042] Step 220: Apply an insulating material to the area on the back of the chip where it needs to connect to the substrate. This insulating material is designated as a dielectric layer, which does not completely cover the back and front of the chip. The partially covered area is the wiring area.

[0043] Step 230: Starting from the functional area on the front side of the chip, the conductive paste is passed through the chip sidewall and led from the front side of the chip to the back side of the chip to form a connecting post that connects to the substrate.

[0044] Step 240: Apply the conductive paste to the substrate pin area of ​​the substrate to connect the front functional area of ​​the chip and the substrate pin area together to form a vertical electrical micro-connection structure for the packaged chip.

[0045] Figure 2 The method described above involves a top-down spraying process to apply conductive paste from the exposed pads on the front side of the chip, through the chip's sidewalls, to the back side, thus guiding the input / output ports from the front to the back. The conductive paste-attached leads to the chip surface solve the problem of lead breakage caused by excessive arc and length. Furthermore, it allows for vertical electrical connections without the need for pre-designed solder joints or related process steps. Connecting the front input / output ports to the back side via attached leads reduces the requirements for the chip's front-end design and fabrication, simplifies the overall manufacturing process, and improves the applicability of vertical interconnects in the packaged micro-connects. Since all electrical micro-connection leads are attached to the chip surface, they are less prone to breakage or detachment, improving reliability and integration.

[0046] based on Figure 2 In addition to the method described herein, this specification also provides some specific implementation methods of this method, which will be described below.

[0047] Optionally, in practical applications, since the sidewalls of the chip are stepped, flexible nozzles can be used for spraying to achieve the desired coating effect when applying the conductive paste, or vertical electrical micro-connections of the packaged chip can be achieved using electrofluid inkjet printing and multi-axis linkage devices. This specification illustrates these two implementation methods, but actual implementations are not limited to these two. Methods that use patterned application of conductive paste, passing through the stepped sidewalls of the chip, to guide electrical connections from the front pads of the chip to the back of the chip, thereby achieving vertical interconnection between the chip and the substrate, all fall within the scope of this invention. The following sections will describe the two listed implementation methods:

[0048] Method 1: Fabrication of vertical electrical micro-connection structure for packaged chips based on electrofluid inkjet printing and multi-axis linkage device.

[0049] Electrohydraulic inkjet printing applies an electric field between the nozzle and the substrate, and the paste is sprayed onto the desired location by the drive and traction of the electric field. It can achieve high precision and high resolution patterning. The five-axis linkage device can change the spraying direction in all directions and at multiple angles, so it can achieve continuous spraying on steps.

[0050] Specifically, vertical electrical micro-connection of packaged chips based on electrofluid inkjet printing and multi-axis linkage devices can include:

[0051] A rotatable printhead is formed by combining the multi-axis linkage device with the electro-hydraulic inkjet printing method.

[0052] By adjusting the electric field, the rotatable movable nozzle is used to spray insulating material from the functional area on the front of the chip, covering the functional area on the front of the chip, and then continuously spraying it to the side wall of the chip, stopping at a preset height on the side wall.

[0053] The chip is inverted, and insulating material is sprayed from the back of the chip to a predetermined height on the sidewall, where it is cured to form an insulating dielectric layer.

[0054] A conductive paste is sprayed onto the insulating dielectric layer to cover the entire front functional area of ​​the chip;

[0055] The conductive paste is sprayed onto the back of the chip in accordance with the spraying method used to form the insulating dielectric layer;

[0056] After the conductive paste solidifies, it forms a stable electrical channel, resulting in a chip with complete coating.

[0057] The conductive paste is sprayed onto the substrate pin area, and the coated chip is mounted onto the PCB pads to complete the vertical electrical micro-connection of the packaged chip.

[0058] The above implementation steps can be combined Figure 3 Please provide an explanation. Figure 3 This is a schematic diagram illustrating the fabrication process of the vertical electrical micro-connection structure for the packaged chip based on electrofluid inkjet printing and a multi-axis linkage device, as provided by the present invention. Figure 3 As shown, firstly, a rotatable and movable nozzle is formed by a five-axis linkage device combined with electrohydraulic inkjet printing; then, by adjusting the electric field, insulating adhesive SU-8 is sprayed from the front pad of the chip, first covering half of the pad, and then continuously sprayed to the sidewall of the chip, stopping at half the height of the sidewall; subsequently, the chip is turned upside down, and insulating adhesive is sprayed on the back of the chip, continuously sprayed to the sidewall, where it merges with the stop point of the front spray; finally, it is cured to form an insulating dielectric layer.

[0059] Based on the existing insulating dielectric layer, conductive paste is sprayed onto the chip pads. First, the entire front side is covered with the conductive paste. Then, following the same spraying method, the conductive paste is sprayed onto the back side of the chip, continuing along the insulating dielectric layer. It is then allowed to cure, forming a stable electrical channel. Pins are sprayed onto the back side where electrical interconnection with the substrate is required, ensuring stable electrical connections during subsequent substrate mounting. Finally, conductive paste is sprayed onto the substrate pads, and the chip with sprayed pins, manufactured in this way, is mounted onto the PCB pads, forming an electrical connection from the top circuitry of the chip to the bottom circuitry.

[0060] The above-described first implementation method does not limit the nozzle material. By combining electrohydraulic inkjet printing and a multi-axis linkage device, high-precision and high-resolution graphics can be achieved. At the same time, the five-axis linkage device can be used to change the spraying direction in all directions and at multiple angles, so as to achieve continuous spraying at the step.

[0061] Implementation Method 2: Fabrication of a vertical electrical micro-connection structure for packaged chips based on a flexible soft nozzle.

[0062] Microelectronic inkjet printing based on flexible soft nozzles uses a flexible material nozzle to adapt to the irregular shape of the chip, ensuring continuous spraying of conductive paste and insulating adhesive when passing through the steps on the chip's sidewall.

[0063] Specifically, the vertical electrical micro-connection of the packaged chip based on the flexible soft nozzle may include:

[0064] The chip is fixed on a rotatable fixture, and an insulating dielectric layer and a conductive paste layer are sprayed onto the functional area on the front of the chip using a flexible material nozzle.

[0065] When spraying onto the sidewall, the chip is tilted using the clamp, and the flexible material nozzle changes its spraying direction according to the sidewall to complete the connection between the sidewall and the functional area on the front of the chip.

[0066] The chip is inverted, and the conductive paste is sprayed from the cut-off point of the sidewall to connect to the back of the chip;

[0067] The conductive paste is sprayed onto the substrate pin area, and the coated chip is mounted onto the PCB pads to complete the vertical electrical micro-connection of the packaged chip.

[0068] The above implementation steps can be combined Figure 4 Please provide an explanation. Figure 4 This is a schematic diagram illustrating the fabrication process of the vertical electrical micro-connection structure based on a flexible soft nozzle encapsulation chip provided by the present invention. Figure 4 As shown, the chip is first fixed on a rotatable fixture, and the insulating dielectric layer and conductive lead layer of the active area pads on the front are sprayed. When spraying to the sidewall, the fixture is used to tilt the chip. Since the nozzle is flexible, it will change its spraying direction according to the sidewall to complete the connection between the sidewall and the front. Then the chip is inverted and spraying continues from the conductive paste cutoff point on the sidewall to connect to the back of the chip. The back area is sprayed to form pins to facilitate subsequent mounting and electrical connection with the substrate. Finally, the chip is mounted together with the external circuit.

[0069] According to the chip electrical micro-connection method in the packaging system of the present invention, the input / output ports on the front side of the chip are guided to the back side of the chip through conductive paste, forming an electrical connection from the front to the back side of the chip, realizing vertical interconnection between the chip and the substrate, simplifying the process flow of micro-connection in the packaging system, and improving the electrical reliability performance of micro-connection.

[0070] The method of chip electrical micro-connection in this packaging system has the following advantages:

[0071] 1) When performing vertical interconnect packaging of chip and substrate, the active area on the front of the chip faces upward, which can provide a reliable micro-connection packaging method for chips that cannot be inverted.

[0072] 2) Connecting the front input / output ports of the chip to the back via surface-mount leads reduces the requirements for the chip front-end design and fabrication process, simplifies the overall processing flow, and improves the applicability of packaged micro-connection vertical interconnects.

[0073] 3) All electrical micro-connection leads of the chip are attached to the chip surface, making them less likely to break or fall off, which can improve reliability and integration.

[0074] In practical applications, the preparation method in the above embodiments can be implemented using a preparation apparatus and equipment, wherein the preparation equipment may further include a memory. The memory stores computer execution instructions for implementing the present invention, and its execution is controlled by a processor. The processor executes the computer execution instructions stored in the memory, thereby implementing the preparation method provided in the embodiments of the present invention.

[0075] The memory can be read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, random access memory (RAM) or other types of dynamic storage devices capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed discs, laser discs, optical discs, universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited to these. The memory can exist independently and be connected to the processor via communication lines. The memory can also be integrated with the processor.

[0076] Optionally, the computer execution instructions in the embodiments of the present invention may also be referred to as application code, and the embodiments of the present invention do not specifically limit this.

[0077] Those skilled in the art will readily recognize that, based on the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein, the present invention can be implemented in hardware or a combination of hardware and computer software. Whether a function is implemented in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of the present invention.

[0078] The processor described in this specification may also function as a memory. The memory stores computer execution instructions for carrying out the present invention, and its execution is controlled by the processor. The processor executes the computer execution instructions stored in the memory, thereby implementing the method provided in the embodiments of the present invention.

[0079] The memory can be read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, random access memory (RAM) or other types of dynamic storage devices capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed discs, laser discs, optical discs, universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited to these. The memory can exist independently and be connected to the processor via communication lines. The memory can also be integrated with the processor.

[0080] The methods disclosed in the above embodiments of the present invention can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above methods can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of the present invention can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0081] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present invention are performed entirely or partially. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal, a user equipment, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video disc (DVD); or it can be a semiconductor medium, such as a solid-state drive (SSD).

[0082] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0083] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A method for fabricating a vertical electrical micro-connection structure for a packaged chip, characterized in that, This is used to fabricate vertical electrical micro-connection structures for packaged chips. The vertical electrical micro-connection structures for packaged chips include: Substrate; a substrate pin area is provided on the substrate; A chip, wherein a front functional area is provided on the chip; A conductive paste layer is provided on the back side of the chip near the substrate, on the front side of the chip opposite to the back side of the chip, and on the sidewall between the back side and the front side of the chip. The back side and the front side of the chip are not completely covered by the conductive paste layer, and the conductive paste layer on the back side of the chip is fixedly connected to the substrate. The conductive paste is led from the front side of the chip to the back side of the chip to form connecting pillars to connect the functional area on the front side of the chip and the pin area of ​​the substrate. An insulating dielectric layer is disposed between the chip and the conductive paste layer; the chip has multiple layers; the multiple chips are stacked and vertically connected; or, the chip and the substrate are vertically interconnected, with the active area on the front side of the chip facing upwards; the sidewalls of the chip are stepped, and when the conductive paste is applied, the vertical electrical micro-connection of the packaged chip is performed based on electrofluid inkjet printing and a multi-axis linkage device. The method includes: A layer of insulating material is applied to the functional area on the front of the chip. An insulating material is applied to the back of the chip where it connects to the substrate; and the applied insulating material is defined as an insulating dielectric layer, which does not completely cover the back and front of the chip. The conductive paste is started from the functional area on the front side of the chip, passes through the chip sidewall, and is led from the front side of the chip to the back side of the chip to form a connection post that connects to the substrate. The conductive paste is applied to the substrate pin area of ​​the substrate to connect the functional area on the front of the chip and the substrate pin area together to form a vertical electrical micro-connection structure for the packaged chip. The vertical electrical micro-connection of the packaged chip based on electrofluid inkjet printing and multi-axis linkage device specifically includes: A rotatable printhead is formed by combining the multi-axis linkage device with the electro-hydraulic inkjet printing method. By adjusting the electric field, the rotatable movable nozzle is used to spray insulating material from the functional area on the front of the chip, covering the functional area on the front of the chip, and then continuously spraying it to the side wall of the chip, stopping at a preset height on the side wall. The chip is inverted, and insulating material is sprayed from the back of the chip to a predetermined height on the sidewall, where it is cured to form an insulating dielectric layer. A conductive paste is sprayed onto the insulating dielectric layer to cover the entire front functional area of ​​the chip; The conductive paste is sprayed onto the back of the chip in accordance with the spraying method used to form the insulating dielectric layer; After the conductive paste solidifies, it forms a stable electrical channel, resulting in a chip with complete coating. The conductive paste is sprayed onto the substrate pin area, and the coated chip is mounted onto the PCB pads to complete the vertical electrical micro-connection of the packaged chip.

2. The method for fabricating a vertical electrical micro-connection structure for a packaged chip according to claim 1, characterized in that, When applying the conductive paste, vertical electrical micro-connections are made to the packaged chip using a flexible nozzle.

3. The method for fabricating a vertical electrical micro-connection structure for a packaged chip according to claim 2, characterized in that, The vertical electrical micro-connection of the packaged chip based on the flexible soft nozzle specifically includes: The chip is fixed on a rotatable fixture, and an insulating dielectric layer and a conductive paste layer are sprayed onto the functional area on the front of the chip using a flexible material nozzle. When spraying onto the sidewall, the chip is tilted using the clamp, and the flexible material nozzle changes its spraying direction according to the sidewall to complete the connection between the sidewall and the functional area on the front of the chip. The chip is inverted, and the conductive paste is sprayed from the cut-off point of the sidewall to connect to the back of the chip; The conductive paste is sprayed onto the substrate pin area, and the coated chip is mounted onto the PCB pads to complete the vertical electrical micro-connection of the packaged chip.

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