Electronic device including two high electron mobility transistors

Abstract

This disclosure relates to an electronic device having two high electron mobility transistors stacked on top of each other and sharing a source electrode, a drain electrode, and a gate electrode. For example, each of these electrodes extends perpendicular to both transistors. For example, the source and drain electrodes electrically contact the conductive channels of each transistor, such that the channels are electrically connected in parallel.

Description

[0001] Cross-reference to related applications

[0002] This application is a translation of and claims priority to French patent application No. 2103561 entitled “ELECTRONIC DEVICE COMPRISING TWOHIGH ELECTRON MOBILITY TRANSISTORS” filed on 7 April 2021, which is incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure relates to the field of electronics, and for example, to the field of power electronics. For instance, this disclosure relates to an electronic device having two high electron mobility transistors.

[0004] The device according to this disclosure is, for example, arranged to allow for better integration of two high electron mobility transistors.

[0005] In this respect, the arrangement provided in this disclosure enables the acquisition of a compact device relative to a single high electron mobility transistor, which allows for an increase in the current density that may flow through the device. Background Technology

[0006] High electron mobility transistors (“HEMTs”) are now widely used in overclocking and as switches for power electronic converters.

[0007] In this respect, HEMT transistors are typically made of layers of III-V semiconductor material as well as, for example, III-N semiconductor material layers. Summary of the Invention

[0008] This disclosure provides an electronic device comprising two high electron mobility transistors, referred to as a first transistor and a second transistor for illustrative purposes. Each of the first and second transistors is disposed in a stack, referred to as a first stack and a second stack for illustrative purposes. The first and second stacks extend from an interface to the front and back sides of the electronic device, respectively. Each of the first and second stacks includes a barrier layer extending from the interface and a channel layer capable of forming a conductive layer in the form of a two-dimensional electron gas. The two transistors share a source electrode and a drain electrode, which are arranged such that conductive paths that may be formed by the two conductive layers are connected in parallel. The two transistors also share a gate electrode capable of applying an on or off state to one of the two conductive layers.

[0009] Therefore, according to this disclosure, the density of high electron mobility transistors can be increased without increasing the surface area occupied by the electronic device.

[0010] Furthermore, the parallel arrangement of the conductive layers of the two transistors can increase the current that may flow through the electronic device, thus paving the way for higher power applications.

[0011] Furthermore, the electronic device according to this disclosure does not require resizing of its included high electron mobility transistors.

[0012] Furthermore, the parallel connection of conductive paths can limit the resistivity Ron of electronic devices.

[0013] In one implementation, the interface includes an insulating layer inserted between two stacked barrier layers. In some implementations, the insulating layer comprises silicon dioxide.

[0014] The implementation of the insulating layer enables efficient insulation between the two barrier layers.

[0015] This insulating layer also simplifies the assembly of two high-mobility transistors. In fact, two high-mobility transistors can be assembled through molecular bonding between the two transistors.

[0016] According to one implementation, the source electrode and the drain electrode intersect with the insulating layer, and the source electrode and the drain electrode each extend on either side of the insulating layer to electrically contact the two conductive layers.

[0017] According to one implementation, the aforementioned electronic device includes pads, referred to as source pads for the purposes of description, which are arranged on the front side and are capable of making electrical contact with the source electrode.

[0018] According to one embodiment, the above-described electronic device includes a contact support having two high electron mobility transistors located thereon via a barrier layer on a second transistor.

[0019] According to one implementation, the aforementioned electronic device includes a pad, referred to as a gate pad for the purposes of description, which is arranged on the front side and is capable of electrically contacting the gate electrode.

[0020] According to one implementation, the first stack is located on a contact support via its channel layer, the contact support forming a conductive contact pad electrically connected to the drain electrode; in some implementations, the contact support comprises doped silicon.

[0021] According to one implementation model, the first stack and the second stack are essentially the same.

[0022] In one implementation mode, the first transistor and the second transistor have the same threshold voltage.

[0023] According to one implementation mode, the first transistor and the second transistor have different first threshold voltages and second threshold voltages from each other.

[0024] According to one implementation, the first transistor and the second transistor are enhancement-high electron mobility transistors.

[0025] According to one implementation mode, the first transistor and the second transistor are depletion-type high electron mobility transistors.

[0026] In one implementation, the source electrode is cascaded with a metal-oxide-semiconductor gate field-effect transistor.

[0027] According to one implementation, the two channel layers comprise GaN and the barrier layer comprises an AlGaN ternary alloy. Attached Figure Description

[0028] Other features and advantages of this disclosure will become apparent from the following detailed description with reference to the accompanying drawings, in which:

[0029] Figure 1 This is a simplified representation of a HEMT transistor shown along a cross-section perpendicular to the front side;

[0030] Figure 2A This is a simplified representation of an electronic device along a cross-sectional plane according to the present disclosure;

[0031] Figure 2B This indicates that it will be able to make an electrical connection. Figure 2A A schematic diagram of the gate pad offset positioning of the gate electrode of an electronic device;

[0032] Figure 2C The front view of the aforementioned device shows that it will be able to make electrical connections. Figure 2A The representation of the gate pad offset positioning of the gate electrode in an electronic device;

[0033] Figure 3 This is a simplified representation of an electronic device along a cross-sectional plane according to the present disclosure, wherein the first transistor and the second transistor are normally open transistors and are cascaded;

[0034] Figure 4 This is a simplified representation of the steps for forming the first transistor in accordance with the terms of this disclosure;

[0035] Figure 5 This is a simplified representation of the steps for forming the second transistor according to the terms of this disclosure;

[0036] Figure 6 This is a simplified representation of the assembly steps according to the terms of this disclosure; and

[0037] Figure 7 It is a simplified representation of the steps involved in forming pads that are intended to make electrical contacts between the source and gate electrodes. Detailed Implementation

[0038] Figure 1 HEMT transistor 10 is shown. This HEMT transistor 10 has a stack 13 extending from a front side 11 to a back side 12. The stack 13 includes an insulating layer 14, a barrier layer 15, and a channel layer 16. The channel layer 16 is capable of forming a conductive layer 16a in the form of a two-dimensional electron gas layer. Specifically, the conductive layer 16a extends from an interface 15a within the channel layer 16, the interface 15a being formed between the barrier layer 15 and the channel layer 16.

[0039] The III-V semiconductor materials selected for forming the barrier layer 15 and / or the channel layer 16 may include gallium nitride (GaN), aluminum nitride (AlN), and Al x Ga 1-x N x Ternary alloys, gallium arsenide (GaAs), AlGaAs, or InGaAs ternary alloys. For example, barrier layer 15 and channel layer 16 may comprise an AlaGaN compound and GaN, respectively. Insulating layer 14 may comprise a dielectric material, such as silicon dioxide (SiO2) or silicon nitride (Si3N4).

[0040] The HEMT transistor 10 also includes a source electrode 17 and a drain electrode 18 that are electrically in contact with the conductive layer 16a. For example, the source electrode 17 and drain electrode 18 are exposed through the front side 11 and extend through the insulating layer 14 and the barrier layer 15 to reach the interface 15a and electrically contact the conductive layer 16a. The source electrode 17 and drain electrode 18 may partially or entirely intersect with the conductive layer 16a. The source electrode 17 and drain electrode 18 may comprise a metallic material, such as aluminum, that fills trenches formed in the stack 13.

[0041] HEMT transistor 10 also includes a gate electrode 19, which is designed to apply a voltage Vg that controls the state of conductive layer 16a. For example, once the potential difference (denoted as Vg-Vs) between the gate electrode 19 and the source electrode 17 is greater than the threshold voltage Vth characteristic of HEMT transistor 10, the transistor is in the on state. Conversely, once Vg-Vs is less than Vth, HEMT transistor 10 is in the off state and thus acts as an off switch.

[0042] Therefore, depending on the value of the threshold voltage Vth, such as its sign, if the threshold voltage Vth of the HEMT transistor is negative, the HEMT transistor may be in depletion (normally on) mode, or if the threshold voltage Vth of the HEMT transistor is positive, the HEMT transistor may be in enhancement (normally off) mode.

[0043] However, such high electron mobility transistors have an on-resistivity Ron (Ron is the on-drain / source resistance) that limits the strength of the current that may flow through the conductive layer.

[0044] In this respect, the main parameters affecting resistivity Ron are:

[0045] Surface resistance of the channel layer;

[0046] Contact resistance between the conductive layer and the source and drain electrodes;

[0047] The resistivity of the wiring metal in the chip;

[0048] The resistance sensed in the final component in which high electron mobility transistors are integrated.

[0049] To overcome this problem, the resistivity Ron of high electron mobility transistors (HEMTs) can be significantly reduced by increasing their surface area. However, there are situations where the space available for integrating HEMTs is limited, making such a solution unthinkable.

[0050] As an alternative, optimizing the parameters affecting resistivity Ron could be considered. However, such a solution remains complex to implement because it requires both complete size control of the high electron mobility transistor and verification of methods for manufacturing such transistors.

[0051] This disclosure provides an apparatus whose arrangement allows for a greater integration density of high electron mobility transistors without significantly increasing the space occupied by the aforementioned apparatus.

[0052] Of course, this disclosure is not limited to the described embodiments, and alternative embodiments may be introduced therein without departing from the framework of this disclosure.

[0053] Furthermore, it should be understood that the various accompanying drawings associated with this specification are given for illustrative purposes only and are in no way intended to limit this disclosure. For example, it should be clear that relative proportions or dimensions may not be respected.

[0054] Throughout the description, layers or interfaces are assumed to be planar and extend along a plane parallel to the (0, x, y) plane of an orthogonal (0, x, y, z) reference system. Furthermore, once the reference is along the representation of the cross-section, the cross-section is perpendicular to all planes formed by the layers, and for example, perpendicular to the (0, x, y) plane. It should also be understood that as long as the reference is stacked, the stack will be stacked along the z-direction of the (0, x, y, z) orthogonal reference system.

[0055] This disclosure relates to an electronic device having two high electron mobility transistors stacked on top of each other and having a source electrode, a drain electrode, and a gate electrode.

[0056] For example, each of these electrodes extends perpendicular to both transistors. For example, the source and drain electrodes electrically contact the conductive channel of each transistor, such that the channels are electrically connected in parallel.

[0057] This configuration serves as an example in several ways. In fact, parallelizing the conductive channels of the two transistors can increase the intensity of the current that might flow through the electronic device without increasing its surface area. Furthermore, this parallelization can reduce the on-resistivity Ron of the electronic device.

[0058] Figure 2A An example of an electronic device 100 according to an exemplary embodiment of the present disclosure is shown.

[0059] Therefore, the electronic device 100 according to this disclosure includes two high electron mobility transistors (“HEMT transistors”). For example, the electronic device 100 includes a first HEMT transistor 101 and a second HEMT transistor 102 separated by an insulating layer 200 from the front side 100a to the back side 100b. In some implementations, the insulating layer 200 includes silicon dioxide.

[0060] The first transistor 101 and the second transistor 102 each include a stack, referred to for descriptive purposes as first stack 201 and second stack 202, respectively. Each of these stacks may, for example, include a III-V semiconductor material, such as a III-N semiconductor material. Specifically, the III-V semiconductor material may be selected from gallium nitride (GaN), aluminum nitride (AlN), and Al... x Ga 1-x N-ternary alloys, or those selected from gallium arsenide (GaAs) and its compounds (AlGaAs, InGaAs).

[0061] The first stack 201 and the second stack 202 each include a barrier layer and a channel layer. For example, the first stack 201 includes a first barrier layer 201a and a first channel layer 201b from the insulating layer 200 to the front side 100a. Similarly, the second stack 202 includes a second barrier layer 202a and a second channel layer 202b from the insulating layer 200 to the back side 100b.

[0062] As an example and in accordance with this disclosure, the barrier layer may include Al x Ga 1-x N-ternary alloys, while the channel layer may include GaN.

[0063] Furthermore, the barrier layer can have a thickness ranging from 1 nm to 100 nm.

[0064] The channel layer can have a thickness ranging from 10 nm to 2 μm.

[0065] According to the terminology of this disclosure, stack 201 or 202 is capable of forming a two-dimensional electron gas layer (2DEG), which forms a conductive layer.

[0066] The conductive layer within the stack extends into the channel layer from the interface between the barrier layer and the channel layer formed in the underlying layer under consideration.

[0067] Therefore, the first stack 201 includes a first conductive layer 201c extending from the first interface formed between the first barrier layer 201a and the first trench layer 201b in the first trench layer 201b.

[0068] The second stack 202 includes a second conductive layer 202c extending from a second interface formed between the second barrier layer 202a and the second channel layer 202b in the second channel layer 202b.

[0069] Electronic device 100 includes a source electrode 203 and a drain electrode 204 that are in electrical contact with one or the other of a first conductive layer 201c and a second conductive layer 202c. It should be noted that different types of electrical contacts are known to electrically connect the source electrode 203 and the drain electrode 204 to the conductive layers 201c, 202c: in particular, ohmic, tunnel, or Schottky contacts.

[0070] In some implementations, the source electrode 203 and the drain electrode 204 intersect with the insulating layer 200 and each extends on either side of the insulating layer 200 to make electrical contact with the first conductive layer 201c and the second conductive layer 202c.

[0071] Electronic device 100 may include a pad referred to as source pad 206, which is disposed on one side (e.g., front side 100a) and is capable of electrically contacting source electrode 203. In some implementations, source pad 206 comprises doped silicon.

[0072] The electronic device 100 may also include a contact support 207 on which two high electron mobility transistors are disposed. A second channel layer 202b is in contact with, for example, the surface of the contact support 207. At this point, the contact support is intended to electrically contact the drain electrode 204. In some implementations, the contact support 207 may include doped silicon.

[0073] When a HEMT transistor is conducting, the conductive layer of the HEMT transistor is designed to ensure current conduction between the source and drain electrodes of the HEMT transistor under consideration.

[0074] The electronic device 100 according to this disclosure also includes a gate electrode 205. In some implementations, the gate electrode 205 is shared by the first transistor 101 and the second transistor 102.

[0075] The gate electrode 205 extends along the z-direction, for example, perpendicular to the plane formed by the insulating layer 200, and remains away from one and the other of the first conductive layer 202a and the second conductive layer 202c.

[0076] Electronic device 100 may include pads, referred to for the purposes of description as gate pad 208, which are arranged on one side (e.g., front side 100a) and are capable of electrically contacting the gate electrode. Figure 2B For example, gate pad 208 is offset from the two HEMT transistors 101 and 102, thus eliminating the risk of electrical contact with the first conductive layer 201c. "Offset" refers to a gate pad disposed outside the outline defining one of the first and second transistors. At this point, Figure 2C This is a representation of device 100 based on a front view (along a plane parallel to the (0, x, y) plane). The dashed line defines the active region ZA of the electronic device, within which any contact between the gate electrode and one or the other of the barrier layer and channel layer is avoided.

[0077] Therefore, the gate electrode 205 is arranged to drive or control the state of one of the first transistor 101 and the second transistor 102. For example, this control is performed by applying a potential Vg to the gate electrode 205, such as the potential difference DDP between the gate electrode 205 and the source electrode 203, denoted as Vg-Vs.

[0078] Therefore, once Vg-Vs is greater than the threshold voltage Vth characteristic of each of transistors 101 and 102, transistors 101 and 102 are in the on state. Conversely, once Vg-Vs is less than Vth, transistors 101 and 102 are in the off state and thus act as off switches.

[0079] Therefore, depending on the value of the threshold voltage Vth, if the threshold voltage Vth of the HEMT transistor is negative, the HEMT transistor can be in depletion (e.g., normally on) mode, or if the threshold voltage Vth of the HEMT transistor is positive, the HEMT transistor can be in enhancement (normally off) mode.

[0080] Therefore, the HEMT transistors that may be considered in this disclosure can be normally on or depletion-type, such as depletion-type high electron mobility transistors, or normally off or enhancement-type, such as enhancement-type high electron mobility transistors.

[0081] In the architecture provided by this invention, the first conductive layer 201c and the second conductive layer 202c are connected in parallel. Therefore, if each of the first transistor and the second transistor has the same on-resistance Ron, the on-resistance Ron of the electronic device is equal to the resistance Ron / 2.

[0082] In other words, by simply stacking high electron mobility transistors, it is possible to obtain electronic devices with low on-resistance without modifying the geometry of the aforementioned transistors.

[0083] In some implementations, the first stack 201 and the second stack 202 are essentially the same.

[0084] In some implementations, the first transistor and the second transistor still have the same threshold voltage Vth.

[0085] In some implementations, the first transistor and the second transistor each have different first threshold voltages Vth1 and second threshold voltages Vth2. Therefore, according to this configuration, one or the other of the first and second transistors can be turned on or off at different times by controlling a single gate electrode. This configuration is able to "distribute" the current spikes that may occur when the two transistors switch to the on state.

[0086] Figure 3 An electronic device 100 according to an embodiment of the present disclosure is shown. Figure 3 This embodiment includes information about Figure 2A Most of the features described.

[0087] In some implementations, the first transistor 101 and the second transistor 102 are normally on. In other words, these two transistors are conducting with respect to zero potential difference Vg-Vs.

[0088] Therefore, in order to apply a non-zero threshold voltage to the electronic device 100, two transistors 101 and 102 are cascaded with a MOSFET transistor 300.

[0089] For example, the drain D of the MOSFET transistor 300 rests on the source pad 206 and includes a source S electrically connected to the gate pad 208.

[0090] Therefore, according to this embodiment, the gate G of the MOSFET transistor can be voltaged at the level of the source electrode 203.

[0091] This disclosure also relates to a method for manufacturing the aforementioned electronic device 100.

[0092] For example, the method includes forming a first transistor 101 ( Figure 4 The steps are as follows.

[0093] For example, the formation of the first transistor 101 includes epitaxially growing a first stack 201 on a first surface of a first substrate 400 (e.g., a silicon substrate). The epitaxial growth may in particular include first forming a first channel layer 201b and then forming a first barrier layer 201a.

[0094] After epitaxial growth, a first insulating layer 200a is formed covering the first barrier layer 201a. The first insulating layer 200a includes, for example, silicon dioxide or silicon nitride.

[0095] Then, after the deposition of the insulating layer 200a, a first source electrode 203a, a first drain electrode 204a, and a first gate electrode 205a are formed. For example, the first source electrode 203a extends from the free surface of the first insulating layer and intersects integrally with the first insulating layer and the first stack 201. The first drain electrode 204a extends from the free surface of the first insulating layer to the first conductive layer 201c. The first gate electrode 205a extends from the free surface of the first insulating layer to the first stack and remains away from the barrier layer 201a.

[0096] The manufacturing method includes forming a second transistor 102. Figure 5 The steps are as follows.

[0097] For example, the formation of the second transistor 102 includes epitaxially growing a second stack 202 on a first surface of a second substrate 500 (e.g., a silicon substrate). The epitaxial growth may in particular include first forming a second channel layer 202b and then forming a second barrier layer 202a.

[0098] After epitaxial growth, a second insulating layer 200b is formed covering the second barrier layer 202a. The second insulating layer 200b includes, for example, silicon dioxide or silicon nitride.

[0099] Then, after the deposition of the second insulating layer 200b, a second source electrode 203b, a second drain electrode 204b, and a second gate electrode 205b are formed. For example, the second source electrode 203b extends from the free surface of the second insulating layer to the second conductive layer 202c. The second drain electrode 204b extends from the free surface of the second insulating layer to integrally intersect with the second insulating layer and the second stack 202. The second gate electrode 205a extends from the free surface of the first insulating layer toward the second stack and remains away from the barrier layer 202a.

[0100] These three electrodes 203b, 204b and 205b extend, for example, from the free surface of the second insulating layer 200b to the second stack 202.

[0101] In some implementations, the drain electrode extends all the way to the interface formed between the second stack 202 and the second substrate 500.

[0102] The manufacturing method also includes assembling the first transistor 101 and the second transistor 102. Figure 6The assembly step is performed by bringing the first insulating layer 200a into contact with the second insulating layer 200b and aligning the first source electrode 203a, the first drain electrode 204a, and the first gate electrode 205a with the second source electrode 203b, the second drain electrode 204b, and the second gate electrode 205b, respectively.

[0103] In other words, the assembly of the first insulating layer and the second insulating layer forms the insulating layer 200. The assembly of the first source electrode 203a and the second source electrode 203b forms the source electrode 203. The assembly of the first drain electrode 204a and the second drain electrode 204b forms the drain electrode 204. The assembly of the first gate electrode 205a and the second gate electrode 205b forms the gate electrode 205.

[0104] It should also be noted that this assembly step can be performed in a board-to-board manner. More specifically, the method may include forming a plurality of first transistors on a first substrate and a plurality of second transistors on a second substrate. The two substrates are then assembled to place each first transistor opposite to a second transistor.

[0105] In some implementations, assembly may include pick-and-place steps. For example, each first transistor may be individually placed on each second transistor formed on a second substrate.

[0106] In some implementations, the first and second transistors are monolithically processed and then assembled in pairs.

[0107] In the final step, source pads and gate pads are formed by thinning and patterning the first substrate (e.g., by etching). Figure 7 ).

[0108] In some implementations, the electronic device according to this disclosure is implemented in a power management / consumption system.

[0109] For example, the management system may include an energy storage component and the aforementioned energy consumption path. The storage component may be, for example, a battery or accumulator.

[0110] The power consumption path can be an electric motor. Therefore, in some implementations, the electronic device 100 according to this disclosure is implemented in an electric vehicle (car, truck, bicycle, train).

[0111] An electronic device (100) can be summarized as comprising two high electron mobility transistors, referred to as a first transistor (101) and a second transistor (102) for descriptive purposes, each of the first transistor (101) and the second transistor (102) being stacked, referred to as a first stack (201) and a second stack (202) for descriptive purposes, and an insulating layer (200) is inserted between them, the first stack (201) and the second stack (202) extending from the insulating layer (200) to the front side (100a) and the back side (100b) of the electronic device, respectively, and each starting from the insulating layer (200). The transistors include a barrier layer (202a, 201a) and a channel layer (201b), the channel layer (201b) being able to form a conductive layer (201c, 202c) in the form of a two-dimensional electron gas. The two transistors share a source electrode (203) and a drain electrode (204), the source electrode (203) and the drain electrode (204) being arranged such that conductive paths that may be formed by the two conductive layers (201c, 202c) are connected in parallel. The two transistors (101, 102) also share a gate electrode (205), the gate electrode (205) being able to apply an on state or an off state to one of the two conductive layers.

[0112] The insulating layer (200) may include a dielectric material, and in some implementations, silicon dioxide.

[0113] The source electrode (203) and drain electrode (204) can pass through the insulating layer and each extends on either side of the insulating layer (200) to electrically contact the two conductive layers (201c, 202c).

[0114] The aforementioned electronic device may include pads, referred to for descriptive purposes as source pads, which are arranged on the front side and capable of making electrical contact with the source electrode (203).

[0115] The aforementioned electronic device may include a contact support having two high electron mobility transistors located thereon via a barrier layer (202a, 201a) on the second transistor.

[0116] The aforementioned electronic device may include pads, referred to for descriptive purposes as gate pads, which are arranged on the front side and are capable of making electrical contact with the gate electrode (205).

[0117] The first and second stacks can be substantially the same.

[0118] The first transistor and the second transistor can have the same threshold voltage.

[0119] The first transistor and the second transistor can each have a first threshold voltage and a second threshold voltage that are different from each other.

[0120] The first transistor and the second transistor can be enhancement-high electron mobility transistors.

[0121] The first transistor and the second transistor can be depletion-type high electron mobility transistors.

[0122] The source electrode (203) can be cascaded with a metal-oxide-semiconductor gate field-effect transistor.

[0123] The two channel layers comprise GaN and the barrier layer comprises an AlGaN ternary alloy.

[0124] The various embodiments described above can be combined to provide other embodiments. If needed, aspects of the embodiments can be modified to employ the concepts of various embodiments to provide other embodiments.

[0125] These and other changes can be made to the embodiments based on the above detailed description. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed as including all possible embodiments and the full scope of equivalents to which such claims are entitled. Therefore, the claims are not limited to this disclosure.

Claims

1. An electronic device, comprising: The first high electron mobility transistor; as well as The second highest electron mobility transistor, The first high electron mobility transistor includes a first stack extending from an insulating layer to a first surface of the electronic device, and the second high electron mobility transistor includes a second stack extending from the insulating layer to a second surface of the electronic device, the second surface being opposite to the first surface. The first stack and the second stack each include a barrier layer starting from the insulating layer and a channel layer capable of forming a conductive region of a two-dimensional electron gas. The first high electron mobility transistor and the second high electron mobility transistor together have a source electrode, a drain electrode, and a gate electrode, and The source electrode and the drain electrode each intersect the insulating layer and each contact the conductive region of the channel layer of the first stack and the conductive region of the channel layer of the second stack.

2. The device according to claim 1, wherein the insulating layer comprises silicon dioxide.

3. The device according to claim 1 further includes a source pad, the source pad being disposed on the first surface and in contact with the source electrode.

4. The device of claim 1, further comprising a contact support on the channel layer of the second high electron mobility transistor.

5. The device of claim 1, further comprising a gate pad disposed on the first surface and in contact with the gate electrode.

6. The device of claim 1, wherein the first stack and the second stack are mirror images of each other.

7. The device of claim 1, wherein the first high electron mobility transistor and the second high electron mobility transistor have the same threshold voltage.

8. The device of claim 1, wherein the first high electron mobility transistor has a first threshold voltage, and the second high electron mobility transistor has a second threshold voltage, the second threshold voltage being different from the first threshold voltage.

9. The device of claim 1, wherein the first high electron mobility transistor and the second high electron mobility transistor are enhancement-mode high electron mobility transistors.

10. The device of claim 1, wherein the first high electron mobility transistor and the second high electron mobility transistor are depletion-type high electron mobility transistors.

11. The device of claim 10, further comprising a metal-oxide-semiconductor field-effect transistor, wherein the source electrode is coupled to the drain terminal of the metal-oxide-semiconductor field-effect transistor, and the gate electrode is coupled to the source terminal of the metal-oxide-semiconductor field-effect transistor.

12. The device of claim 1, wherein each of the channel layers comprises GaN and each of the barrier layers comprises an AlGaN ternary alloy.

13. A structure comprising: Dielectric layer; A first stack, on a first surface of the dielectric layer, the first stack includes a first III-V semiconductor layer and a second III-V semiconductor layer, wherein the first III-V semiconductor layer is closer to the first surface of the dielectric layer than the second III-V semiconductor layer; The second stack, on the second surface of the dielectric layer opposite to the first surface, includes a third III-V semiconductor layer and a fourth III-V semiconductor layer, wherein the third III-V semiconductor layer is closer to the second surface of the dielectric layer than the fourth III-V semiconductor layer. as well as The first electrode is in contact with both the second III-V semiconductor layer and the fourth III-V semiconductor layer.

14. The structure of claim 13, comprising a gate electrode and a second electrode, the second electrode being in contact with both the second III-V semiconductor layer and the fourth III-V semiconductor layer, the gate electrode being located between the first electrode and the second electrode.

15. The structure of claim 13, wherein the second III-V semiconductor layer and the fourth III-V semiconductor layer are gallium nitride.

16. The structure of claim 13, wherein the first III-V semiconductor layer and the third III-V semiconductor layer are aluminum gallium nitride.

17. The structure of claim 14, further comprising a conductive layer on the fourth III-V semiconductor layer, the conductive layer being in contact with the first electrode, and the second electrode extending from the second III-V semiconductor layer toward the conductive layer and terminating before reaching the conductive layer.

18. A method comprising Accepting a first entity and a second entity, each of the first entity and the second entity including: The stack includes an insulating layer having a first surface and a second surface opposite to the first surface, a first layer of a first III-V semiconductor material on the second surface of the insulating layer, and a second layer of a second III-V semiconductor material on the first layer; as well as An electrode extends from the first surface of the insulating layer to the second layer of the second III-V semiconductor material and includes a source electrode, a gate electrode, and a drain electrode. as well as The first body and the second body are bonded together by the first surface of the insulating layer, and the source electrode, the gate electrode, and the drain electrode of the first body are aligned with the source electrode, the gate electrode, and the drain electrode of the second body. The source electrode and the drain electrode each intersect with the insulating layer and each contact the second layer of the first body and the second layer of the second body.

19. The method of claim 18, further comprising: The first body is formed on a conductive substrate; as well as After bonding, the conductive substrate is thinned and patterned.

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