Semiconductor device and method of forming a capacitor structure

Abstract

The present disclosure relates to semiconductor devices and methods of forming capacitor structures. A semiconductor device includes a first device over a substrate, the first device including a gate stack including a gate electrode material; a source / drain region in the substrate adjacent to the gate stack; a first isolation region surrounding the gate stack; a gate contact over and in contact with the gate stack, the gate contact including a gate contact material; and a second isolation region surrounding the gate contact; and a second device over the substrate, the second device including a first parallel capacitor, the first parallel capacitor including a first electrode, the first electrode including the gate electrode material, the first isolation region separating the first electrode; and a second parallel capacitor over the first parallel capacitor, the second parallel capacitor including a second electrode connected to the first electrode, the second electrode including the gate contact material, adjacent second electrodes separated by the second isolation region.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices and methods for forming capacitor structures. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously increases the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0004] According to one embodiment of this disclosure, a semiconductor device is provided, comprising: a first dielectric layer disposed on a semiconductor substrate; a second dielectric layer disposed on the first dielectric layer; a transistor disposed on a first region of the semiconductor substrate, wherein the transistor comprises: a gate stack disposed in the first dielectric layer, wherein the gate stack comprises a layer of gate dielectric material and a layer of gate electrode material; and a gate contact disposed in the second dielectric layer, wherein the gate contact is connected to the gate stack, wherein the gate contact comprises a gate contact material; and a capacitor structure disposed on a second region of the semiconductor substrate, wherein the capacitor structure comprises: a first electrode and a second electrode. An electrode is located in the first dielectric layer, wherein the first electrode and the second electrode comprise the gate electrode material; a plurality of first electrode contacts are located in the second dielectric layer, wherein the first electrode contacts are located above and connected to the first electrode, wherein the first electrode contacts comprise the gate contact material; and a plurality of second electrode contacts are located in the second dielectric layer, wherein the second electrode contacts are located above and connected to the second electrode, wherein the second electrode contacts comprise the gate contact material, wherein each first electrode contact on the first electrode is adjacent to at least one corresponding second electrode contact on the second electrode.

[0005] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a substrate; a first device located on the substrate, wherein the first device includes: a gate stack including a gate electrode material; a source / drain region located in the substrate and adjacent to the gate stack; a first isolation region surrounding the gate stack; a gate contact located on and in contact with the gate stack, wherein the gate contact includes a gate contact material; and a second isolation region surrounding the gate contact; and a second device located on the substrate, wherein the second device includes: a first parallel capacitor including a first electrode, wherein the first electrode includes the gate electrode material, wherein the first isolation region separates the first electrode; and a second parallel capacitor located on the first parallel capacitor, wherein the second parallel capacitor includes a second electrode connected to the first electrode, wherein the second electrode includes the gate contact material, wherein adjacent second electrodes are separated by the second isolation region.

[0006] According to another embodiment of this disclosure, a method for forming a capacitor structure is provided, the method comprising: depositing a dummy gate material on a semiconductor substrate; patterning the dummy gate material to form a dummy electrode; forming a spacer along the sidewall of the dummy electrode; depositing an isolation material on and between the dummy electrodes; removing the dummy gate material to form a recess; depositing a gate dielectric material in the recess; and forming a first electrode of the capacitor structure, including depositing a gate electrode material on the gate dielectric material within the recess. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 An example of a FinFET structure according to some embodiments is shown in a 3D view.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E , Figure 11F , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13 , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 15 , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17 , Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 18E , Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 20 , Figure 21A , Figure 21B , Figure 21C , Figure 21D , Figure 22A , Figure 22B , Figure 23 , Figure 24A , Figure 24B , Figure 25 , Figure 26A and Figure 26B These are various views of intermediate stages in the fabrication of capacitor structures and FinFET structures according to some embodiments.

[0010] Figure 27 An example of a capacitor structure according to some embodiments is shown in a three-dimensional view.

[0011] Figure 28 An example of an interdigitated capacitor structure according to some embodiments is shown in a three-dimensional view.

[0012] Figure 29 and Figure 30 This is a plan view of an intermediate stage in the manufacture of an interdigitated capacitor structure according to some embodiments.

[0013] Figure 31A and Figure 31B This is a cross-sectional view of an intermediate stage in the fabrication of a capacitor structure and a planar transistor structure according to some embodiments. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] In addition, this document may use spatially related terms (e.g., "below," "under," "down," "above," "up," etc.) to facilitate the description of the relationship between one element or feature shown in the accompanying drawings and another element(s) or feature(s). Besides the orientations shown in the accompanying drawings, these spatially related terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted similarly.

[0016] Various embodiments describe processes for forming capacitor structures. Capacitor structures may be, for example, metal-insulator-metal (MIM) capacitors, metal-oxide-metal (MOM) capacitors, finger metal-oxide-metal (FMOM) capacitors, etc. The capacitor structures described herein include a bottom electrode formed simultaneously with the gate electrode of a transistor, using the same process as forming the gate electrode of the transistor. In this way, additional electrodes can be formed in the capacitor structure to increase capacitance without additional processing steps. Contacts can be formed with the bottom electrode, which also provide additional capacitance. Electrode contacts can be formed simultaneously with the gate contacts and / or source / drain contacts of the transistor, using the same process as forming the gate contacts and / or source / drain contacts of the transistor. In this way, the capacitance of the capacitor structure can be increased without additional processing steps. The techniques described herein may include processes suitable for forming n-type and / or p-type transistors and may be applicable to different types of transistors.

[0017] Figures 1 to 27 It is a capacitor structure 120 according to some embodiments (see Figures 26A-26B ) and FinFET structure 119 (see Figures 21C-21DVarious views of intermediate stages in the manufacturing process of the device. In some embodiments, the capacitor structure 120 and the FinFET structure 119 are simultaneously formed on the same substrate 50 and are formed using at least some of the same process steps. In some embodiments, the capacitor structure 120 and the FinFET structure 119 are formed using exactly the same process steps. In this way, the capacitor structure 120 can be formed without using additional process steps or masks, which can reduce the manufacturing cost of the device.

[0018] Some embodiments discussed herein are presented in the context of transistors formed using a post-gate process (e.g., FinFET or planar FET). In other embodiments, a gate-first process may be used. Furthermore, some embodiments consider aspects used in other devices, such as nanostructured (e.g., nanosheets, nanowires, gate-all-around, etc.) field-effect transistors (NSFETs).

[0019] First turn Figure 1 An example of a FinFET according to some embodiments is shown in a 3D view. Figure 1 The FinFET shown is an example structure used subsequently in the fabrication of FinFET structure 119 (see [link]). Figures 21C-21D This is a reference for discussing the process steps used in ). Figure 1 The FinFET shown includes a fin 52 on a substrate 50 (e.g., a semiconductor substrate). An isolation region 56 is disposed in the substrate 50, and the fin 52 protrudes above adjacent isolation regions 56 (e.g., shallow trench isolation (STI) regions 56). Although the isolation regions 56 are described / shown as separate from the substrate 50, as used herein, the term "substrate" may be used to refer only to the semiconductor substrate, or may be used to refer to the semiconductor substrate including the isolation regions. Furthermore, although the fin 52 is shown as being a single continuous material with the substrate 50, the fin 52 and / or the substrate 50 may comprise a single material or multiple materials. In this context, the fin 52 refers to the portion extending between adjacent isolation regions 56.

[0020] A gate dielectric layer 92 extends along the sidewalls of fin 52 and is located above the top surface of fin 52. A gate electrode layer 94 is located above the gate dielectric layer 92. Source / drain regions 82 are disposed on the opposite sides of fin 52 with respect to the gate dielectric layer 92 and the gate electrode layer 94. Figure 1Reference cross sections used in the following figures are also shown. Cross section CC is along the longitudinal axis of the gate electrode layer 94 and in a direction, for example, perpendicular to the current flow direction between the source / drain regions 82 of the FinFET. Cross section DD is perpendicular to cross section CC and along the longitudinal axis of fin 52, and in a direction, for example, the current flow direction between the source / drain regions 82 of the FinFET. Cross section EE is parallel to cross section CC and extends through the source / drain regions 82 of the FinFET. These reference cross sections are referenced in subsequent figures for clarity.

[0021] Figures 2 to 7 These are various views of intermediate stages in the manufacture of capacitor structure 120 and FinFET structure 119 according to some embodiments. Figure 2 , Figure 3 , Figure 4 , Figure 6 and Figure 7 It shows along Figure 1 The reference cross section CC shown is transistor region 50X, but has multiple fins / FinFETs, and capacitor region 50C is also shown. Figure 5 A plan view of capacitor region 50C and transistor region 50X is shown.

[0022] exist Figure 2 A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and the substrate can be doped (e.g., doped with p-type or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide, etc.; or combinations of the foregoing.

[0023] According to some embodiments, substrate 50 is shown having capacitor region 50C and transistor region 50X. Capacitor region 50C is the region in which one or more capacitor structures 120 are formed, and transistor region 50X is the region in which one or more transistors (e.g., FinFET structure 119) are formed. A single capacitor region 50C and a single transistor region 50X are shown in the figure, but the substrate can have any suitable number of capacitor regions 50C or transistor regions 50X of any suitable size. Other types of devices or structures besides capacitors can also be formed in capacitor region 50C, and other types of devices or structures besides transistors can also be formed in transistor region 50X. Capacitor region 50C can be physically separated from transistor region 50X (as shown by separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between capacitor region 50C and transistor region 50X. Furthermore, transistor region 50X can include an n-type region for forming an n-type device, a p-type region for forming a p-type device, or both an n-type region and a p-type region. The n-type and p-type regions of transistor region 50X can be referred to as "type regions" in this paper.

[0024] According to some embodiments, in Figure 3 In this embodiment, fins 52 are formed in the substrate 50 within the transistor region 50X. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in the substrate 50 by etching trenches in the substrate 50. This etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching can be anisotropic. In some embodiments, the etching also etches the substrate 50 in the capacitor region 50C, such as... Figure 3 As shown in the image.

[0025] The fin 52 can be patterned using any suitable method. For example, the fin 52 can be patterned using one or more photolithography processes that include dual patterning or multiple patterning processes. Typically, dual patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the created patterns to have smaller spacing, for example, than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin. In some embodiments, a mask (or other layer) may be retained on the fin 52.

[0026] According to some embodiments, in Figure 4In this embodiment, an insulating material 54 is formed on the substrate 50 and between adjacent fins 52 in the transistor region 50X. The insulating material 54 can be an oxide (e.g., silicon oxide), a nitride, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-curing in a remote plasma system to convert it into another material, such as an oxide), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material 54 is formed such that excess insulating material 54 covers the fin 52. Although the insulating material 54 is shown as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surfaces of the substrate 50 and the fin 52. Subsequently, a filler material as discussed above can be formed on the liner.

[0027] Still referencing Figure 4 A removal process can be applied to the insulating material 54 to remove excess insulating material 54 above the fin 52. In some embodiments, a planarization process can be used, such as chemical mechanical polishing (CMP), etching back, or a combination of the foregoing. The planarization process exposes the fin 52 so that, after the planarization process is completed, the top surfaces of the fin 52 and the insulating material 54 are flush. In embodiments where the mask remains on the fin 52, the planarization process can expose or remove the mask so that, after the planarization process is completed, the top surface of the mask or the fin 52 is flush with the top surface of the insulating material 54, respectively. Figure 4 As shown, after performing the planarization process, the top surfaces of the insulating material 54 in the capacitor region 50C and the transistor region 50X can be substantially flush.

[0028] According to some embodiments, in Figure 5 and Figure 6 In the middle, the insulating material 54 is recessed to form a shallow trench isolation (STI) area 56. Figure 5 A plan view of capacitor region 50C and transistor region 50X is shown. Figure 6 It shows crossing Figure 5The cross-sectional view of reference section CC shown. The insulating material 54 is recessed such that the upper portion of the fin 52 in transistor region 50X protrudes between adjacent STI regions 56. Furthermore, the top surface of STI region 56 may have a flat surface (as shown), a convex surface, a concave surface (e.g., dish-shaped), or a combination thereof. The top surface of STI region 56 can be formed as flat, convex, and / or concave by suitable etching. STI region 56 can be recessed using an acceptable etching process, such as an etching process selective for the material of insulating material 54 (e.g., etching the material of insulating material 54 at a faster rate than etching the material of fin 52). For example, an oxide removal process utilizing dilute hydrofluoric acid (dHF) can be used, but other processes are also possible.

[0029] about Figures 2 to 6 The described process is merely one example of how fins 52 in transistor region 50X can be formed. In some embodiments, fins 52 can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over the top surface of substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoethelic structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoethelic structure protrudes relative to the dielectric layer to form a fin. Furthermore, in some embodiments, heteroethelic structures can be used for fins 52. For example, Figure 6 The fin 52 can be recessed, and a different material can be epitaxially grown on the recessed fin 52. In such an embodiment, the fin 52 comprises a recessed material and an epitaxial growth material disposed on the recessed material. In a further embodiment, a dielectric layer can be formed on the top surface of the substrate 50, and trenches can be etched through the dielectric layer. A heteroepitaxial structure can then be epitaxially grown in the trench using a different material than the substrate 50, and the dielectric layer can be recessed such that the heteroepitaxial structure protrudes relative to the dielectric layer to form the fin 52. In some embodiments of epitaxially growing homoepitaxial or heteroepitaxial structures, the epitaxial growth material can be doped in situ during growth, which avoids prior and subsequent implantation, but in-situ and implantation doping can be used together.

[0030] Furthermore, it may be advantageous to epitaxially grow a material different from the material in the p-type region of transistor region 50X in the n-type region. In various embodiments, the upper part of fin 52 may be made of silicon-germanium (Si... x Ge 1-x(where x can be in the range of 0 to 1), formed from silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, or II-VI compound semiconductors, etc. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, or gallium phosphide, etc.

[0031] In addition, Figure 6 In this embodiment, suitable wells (not shown) may be formed in fin 52 and / or substrate 50. In some embodiments, a P-well may be formed in the n-type region of transistor region 50X, and an N-well may be formed in the p-type region of transistor region 50X. In some embodiments, a P-well or N-well may be formed in both the n-type and p-type regions of transistor region 50X. In some embodiments, a P-well and / or N-well may be formed in capacitor region 50C.

[0032] In embodiments with different well types, different implantation steps for the n-type and p-type regions of transistor region 50X can be implemented using photoresist and / or other masks (not shown). For example, photoresist can be formed over fin 52 and STI region 56 in the n-type region. The photoresist is patterned to expose the p-type region of transistor region 50X. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in p-type region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into the n-type region. The n-type impurities can be equal to or less than 10 18 cm -3 (For example, in about 10) 16 cm -3 To about 10 18 cm -3 Phosphorus, arsenic, or antimony, etc., are injected into the region at a concentration between [a certain value, e.g., ...

[0033] Following implantation in the p-type region, photoresist is formed over the fin 52 and STI region 56 in the p-type region. The photoresist is patterned to expose the n-type region of transistor region 50X. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region, and the photoresist can be used as a mask to substantially prevent p-type impurities from being implanted into the p-type region. The p-type impurities can be equal to or less than 10. 18 cm -3 (For example, in about 10)16 cm -3 To about 10 18 cm -3 Boron, boron fluoride, or indium, etc., are implanted into the region at a concentration between [a certain value, e.g., ...

[0034] After implantation into the n-type and p-type regions, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be doped in situ during growth, which can avoid implantation; however, in-situ and implantation doping can be used together.

[0035] According to some embodiments, in Figure 7 In this process, a dummy dielectric layer 60 is formed on the fin 52 in the transistor region 50X. Figure 7 Along with Figure 6 The same cross-sectional view (CC) is shown. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, or a combination thereof, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed over the capacitor region 50C and the transistor region 50X, including over the dummy dielectric layer 60. In some embodiments, a mask layer 64 is then formed over the dummy gate layer 62. The dummy gate layer 62 can be deposited and then planarized, for example by CMP. The mask layer 64 can then be deposited over the dummy gate layer 62. The dummy gate layer 62 can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, polycrystalline silicon germanium (polycrystalline SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 62 can be made of other materials that offer high etch selectivity compared to etching of isolation regions (e.g., STI region 56 and / or dummy dielectric layer 60). For example, mask layer 64 can comprise one or more layers of silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across capacitor region 50C and transistor region 50X. It should be noted that the dummy dielectric layer 60 is shown only to cover fin 52 for illustrative purposes. In some embodiments, the dummy dielectric layer 60 can be deposited such that it covers STI region 56, extending over STI region 56 and between dummy gate layer 62 and STI region 56.

[0036] Figures 8 to 27Various additional steps for manufacturing the device of the embodiment are shown. The structure shown in transistor region 50X can be applied to both n-type and p-type regions. The differences (if any) in the structure of the n-type and p-type regions of transistor region 50X are described in the text accompanying each figure.

[0037] Figures 8 to 21D Plan view or cross-sectional view showing features in capacitor region 50C and / or transistor region 50X. Figure 8 , Figure 13 , Figure 15 and Figure 17 This is a plan view of capacitor region 50C and transistor region 50X. Sections AA and BB are illustrated in capacitor region 50C, and sections CC and DD are illustrated in transistor region 50X. Sections CC and DD correspond to... Figure 1 The diagram shows sections CC and DD. Section AA is parallel to section CC, section BB is parallel to section DD, and sections AA and CC are perpendicular to sections BB and DD. Section AA may be aligned with or not aligned with section CC, and section BB may be aligned with or not aligned with section DD.

[0038] Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 14A , Figure 16A , Figure 18A , Figure 19A and Figure 21A The capacitor region 50C is along the cross section AA (e.g., as shown in the image). Figure 8 The cross-sectional view shown in the figure. Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 14B , Figure 16B , Figure 18B , Figure 19B and Figure 21B This is a cross-sectional view of capacitor region 50C along section BB. Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 14C , Figure 16C , Figure 18C and Figure 19C This is a cross-sectional view of transistor region 50X along section CC. Figure 9D , Figure 10D , Figure 11D , Figure 12D , Figure 14D , Figure 16D , Figure 18D and Figure 19D This is a cross-sectional view of transistor region 50X along section DD.

[0039] According to some embodiments, in Figure 8 and Figures 9A-9D In this process, mask layer 64 is patterned to form mask 74, and dummy gate layer 62 is patterned to form dummy gate 72. As previously described, Figure 8 A floor plan is shown. Figures 9A-9D The corresponding cross-sectional view is shown. Mask layer 64 (see [reference]) can be processed using acceptable photolithography and etching techniques. Figure 7 The mask 74 is patterned to form a dummy gate 72. The pattern of the mask 74 can then be transferred to the dummy gate layer 62 to form the dummy gate 72. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 using an acceptable etching technique to form the dummy gate 72. The dummy gate 72 extends over the STI region 56 in the capacitor region 50C and covers the corresponding channel region 58 of the fin 52 in the transistor region 50X. Each dummy gate 72 can be separated from the adjacent dummy gate 72 entity using the pattern of the mask 74.

[0040] In some embodiments, the dummy gate 72 in capacitor region 50C is patterned to form two discrete structures corresponding to the two bottom electrodes of the capacitor structure. For example... Figure 8 and Figures 9A-9B The dummy gate 72 shown has been patterned to form a first dummy bottom electrode 95A' and a second dummy bottom electrode 95B'. The first dummy bottom electrode 95A' and the second dummy bottom electrode 95B' will then be processed to form a capacitor structure 120 (see [link]). Figures 26A-26B and Figure 27 The first bottom electrode 95A and the second bottom electrode 95B (see) Figure 17 and Figures 18A-18B ).

[0041] In some embodiments, the longitudinal direction of the dummy gate 72 in transistor region 50X is substantially perpendicular to the longitudinal direction of the corresponding fin 52, such as... Figure 8 and Figures 9C-9D As shown in the image. Figure 8 and Figures 9A-9BIt is also shown that the longitudinal direction of the dummy gate 72 (e.g., dummy bottom electrodes 95A' and 95B') in capacitor region 50C is parallel to the longitudinal direction of the dummy gate 72 in transistor region 50X. In other embodiments, the longitudinal direction of the dummy gate 72 in capacitor region 50C is perpendicular to the longitudinal direction of the dummy gate 72 in transistor region 50X. In some embodiments, the dummy gate 72 in capacitor region 50C may include both parallel and perpendicular portions, or may include portions that are neither parallel nor perpendicular to the longitudinal direction of the dummy gate 72 in transistor region 50X (e.g., circular, tilted, irregular, etc.).

[0042] Figure 8 and Figures 9A-9B The first dummy bottom electrode 95A' and the second dummy bottom electrode 95B' shown are illustrated as examples. In other embodiments, the dummy bottom electrodes 95A' and 95B' may have different sizes, shapes, or arrangements than those shown. As a non-limiting example, in other embodiments, the dummy bottom electrodes 95A' and 95B' may include arrangements of more than two electrodes, "L-shaped" electrodes, or interdigitated "finger-like" structures. The following describes... Figures 28-30 An example of an interdigitated capacitor structure 130 is described, but other shapes or arrangements are also possible.

[0043] According to some embodiments, in Figures 10A-10D In this configuration, gate sealing spacers 80 and 86 are formed in capacitor region 50C and transistor region 50X. Gate sealing spacer 80 is formed on the exposed surfaces of dummy gate 72, mask 74, and / or fin 52. For example, gate sealing spacer 80 can be formed by performing thermal oxidation or deposition followed by anisotropic etching. Gate sealing spacer 80 can be formed of silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0044] After forming the gate sealing spacer 80, implantation of lightly doped source / drain (LDD) regions (not explicitly shown) can be performed in transistor region 50X. In embodiments where transistor region 50X includes different device types, the methods described above for... Figure 6The implantation is performed using a technique similar to the one discussed. For example, a mask, such as a photoresist, can be formed over the n-type region of transistor region 50X while exposing the p-type region of transistor region 50X. An impurity of an appropriate type (e.g., p-type) can be implanted into the exposed fins 52 in the p-type region. The mask can then be removed. Subsequently, a mask, such as a photoresist, can be formed over the p-type region while exposing the n-type region. An impurity of an appropriate type (e.g., n-type) can be implanted into the exposed fins 52 in the n-type region. The mask can then be removed. The n-type impurity can be any n-type impurity discussed above, and the p-type impurity can be any p-type impurity discussed above. The impurity concentration of the lightly doped source / drain region can be approximately 10. 15 cm -3 To about 10 19 cm -3 Annealing can be used to repair implantation damage and reactivate the implanted impurities. In some embodiments, impurities are also implanted into capacitor region 50C.

[0045] According to some embodiments, still refer to Figures 10A-10D A gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. For example, the gate spacer 86 can be formed by conformally depositing an insulating material and subsequently anisotropically etching the insulating material. The insulating material of the gate spacer 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof. The gate spacer 86 can be formed from a single layer of insulating material or from multiple layers of various insulating materials.

[0046] It should be noted that the above disclosure generally describes the process for forming the spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, or steps in a different sequence can be used (e.g., the gate seal spacer 80 may not be etched before forming the gate spacer 86 that can produce the "L-shaped" gate seal spacer, its spacers or layers may be formed and removed, etc.). Furthermore, n-type devices and p-type devices can be formed using different structures and steps. For example, the LDD region of an n-type device may be formed before forming the gate seal spacer 80, while the LDD region of a p-type device may be formed after forming the gate seal spacer 80.

[0047] According to some embodiments, in Figures 11A-11DIn this embodiment, epitaxial source / drain regions 82 are formed in fins 52 within transistor region 50X. The epitaxial source / drain regions 82 are formed in fins 52 such that each dummy gate 72 in transistor region 50X is disposed between a correspondingly adjacent pair of epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into and penetrate fins 52. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance such that the epitaxial source / drain regions 82 do not short-circuit the subsequently formed gate of the resulting FinFET. The material of the epitaxial source / drain regions 82 may be selected to apply stress in the corresponding channel region 58, thereby improving performance.

[0048] The epitaxial source / drain region 82 in the n-type region of transistor region 50X can be formed, for example, by masking the p-type region of transistor region 50X and etching the source / drain region of fin 52 in the n-type region to form a recess in fin 52. Then, the epitaxial source / drain region 82 in the n-type region is epitaxially grown in the recess. The epitaxial source / drain region 82 can include any acceptable material, such as a material suitable for n-type FinFETs. For example, if fin 52 is silicon, the epitaxial source / drain region 82 in the n-type region can include a material that applies tensile strain in the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 82 in the n-type region can have a surface protruding from the corresponding surface of fin 52 and can have a small facet.

[0049] The epitaxial source / drain region 82 in the p-type region can be formed by masking the n-type region and etching the source / drain region of the fin 52 in the p-type region to form a recess in the fin 52. The epitaxial source / drain region 82 in the p-type region is then epitaxially grown in the recess. The epitaxial source / drain region 82 can include any acceptable material, such as materials suitable for p-type FinFETs. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the p-type region can include a material that applies compressive stress in the channel region 58, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 82 in the p-type region can have a surface protruding from the corresponding surface of the fin 52 and can have a facet.

[0050] The epitaxial source / drain regions 82 and / or fins 52 can be formed by implanting dopant, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. 19 cm -3 To about 10 21cm -3 Between. The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 82 can be doped in situ during growth.

[0051] As a result of the epitaxial process used to form epitaxial source / drain regions 82 in the n-type and / or p-type regions of transistor region 50X, the upper surface of the epitaxial source / drain regions 82 has small facets that extend laterally outward beyond the sidewalls of fin 52. This is in Figure 11E and Figure 11F As shown in the figure, it shows along Figure 1 The example cross-sectional view of the cross-section EE is shown. In some embodiments, these planes cause adjacent source / drain regions 82 of the same FinFET to merge, such as... Figure 11E As shown in the diagram. In other embodiments, after the epitaxial process is completed, adjacent source / drain regions 82 remain separated, as illustrated. Figure 11F As shown. In Figure 11E and Figure 11F In the illustrated embodiment, the gate spacer 86 in transistor region 50X is formed as a portion extending above the STI region 56 covering the sidewalls of fin 52, thereby preventing epitaxial growth. In some other embodiments, in transistor region 50X, the spacer etching used to form the gate spacer 86 can be adjusted to remove spacer material, thereby allowing the epitaxial growth region to extend to the surface of the STI region 56.

[0052] According to some embodiments, in Figures 12A-12D In the middle, the first interlayer dielectric (ILD) 88 is deposited on Figures 11A-11D The structure shown is above the first ILD 88. The first ILD 88 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the mask 74, the gate spacer 86, and the epitaxial source / drain region 82. The CESL 87 may include a dielectric material (e.g., silicon nitride, silicon oxide, silicon oxynitride, etc.) having an etch rate lower than that of the material of the overlying first ILD 88.

[0053] According to some embodiments, in Figure 13 and Figures 14A-14DIn this process, a planarization process, such as CMP, can be performed to make the top surface of the first ILD 88 flush with the top surface of the dummy gate 72 or the mask 74. Figure 13 A floor plan is shown. Figures 14A-14D The corresponding cross-sectional view is shown. For clarity, Figure 13 Gate sealing spacer 80 and CESL 87 are not shown. The planarization process may also remove the mask 74 on the dummy gate 72, as well as portions of the gate sealing spacer 80 and gate spacer 86 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, gate sealing spacer 80, gate spacer 86, and first ILD 88 are flush. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 88. In some embodiments, the mask 74 may be retained, in which case the planarization process flushes the top surface of the first ILD 88 with the top surface of the mask 74.

[0054] According to some embodiments, in Figure 15 and Figures 16A-16D In one or more etching steps, the dummy gate 72 and mask 74 (if present) are removed to form the recess 90. Figure 15 A floor plan is shown. Figures 16A-16D The corresponding cross-sectional view is shown. For clarity, Figure 15 Gate sealing spacer 80 and CESL 87 are not shown. A portion of the dummy dielectric layer 60 located in the recess 90 may also be removed. In some embodiments, only the dummy gate 72 is removed, while the dummy dielectric layer 60 is retained and exposed through the recess 90. In some embodiments, the dummy dielectric layer 60 is removed from the recess 90 in a first region of the die (e.g., a core logic region) and retained in the recess 90 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 72 while little or no etching of the first ILD 88 or gate spacer 86. In some embodiments, the recess 90 may expose a portion of the STI region 56. Each recess 90 in transistor regions 50X exposes and / or covers the channel region 58 of the corresponding fin 52, and each channel region 58 is disposed between an adjacent pair of epitaxial source / drain regions 82. During removal, the dummy dielectric layer 60 can be used as an etch stop layer while the dummy gate 72 is being etched. The dummy dielectric layer 60 can then be optionally removed after the dummy gate 72 has been removed.

[0055] According to some embodiments, in Figure 17 and Figures 18A-18DIn the recess 90, a gate dielectric layer 92 and a gate electrode layer 94 are formed in the recess 90, bottom electrodes 95A and 95B are formed in the capacitor region 50C, and a gate stack 97 is formed in the transistor region 50X. Figure 17 A floor plan is shown. Figures 18A-18D The corresponding cross-sectional view is shown. For clarity, Figure 17 Gate sealing spacers 80 and CESL 87 are not shown. Figure 18E It shows Figure 18D A detailed view of region 89. The gate dielectric layer 92 comprises one or more layers deposited in the recess 90, for example, deposited on the top surface and sidewalls of the fin 52 and on the sidewalls of the gate sealing spacer 80 / gate spacer 86. The gate dielectric layer 92 may also be formed on the top surface of the first ILD 88. In some embodiments, the gate dielectric layer 92 comprises one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, or metal silicate. For example, in some embodiments, the gate dielectric layer 92 comprises an interface layer of silicon oxide formed by thermal or chemical oxidation and an overlying high-k dielectric material, such as hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof, of metal oxides or silicates. The gate dielectric layer 92 may include a dielectric layer having a k value greater than about 7.0. Methods for forming the gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, and PECVD, etc. In embodiments where some portions of the dummy dielectric layer 60 remain in the recess 90, the gate dielectric layer 92 may include the material of the dummy dielectric layer 60 (e.g., silicon oxide, etc.).

[0056] Gate electrode layers 94 are deposited on top of gate dielectric layers 92 and fill the remaining portion of recesses 90. Gate electrode layers 94 may comprise metal-containing materials, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers of the foregoing. For example, although in Figures 18A-18D A single gate electrode layer 94 is shown, but the gate electrode layer 94 may include any number of liner layers 94A, any number of work function adjustment layers 94B, and filler material 94C, such as Figure 18E As shown. After filling the recess 90, a planarization process, such as CMP, can be performed to remove excess material from the gate dielectric layer 92 and the gate electrode layer 94, which are located above the top surface of the ILD 88.

[0057] The remaining portion of the material of the gate electrode layer 94 and the remaining portion of the gate dielectric layer 92 in transistor region 50X form the gate stack 97 of the resulting FinFET. The gate electrode layer 94 and the gate dielectric layer 92 may also be collectively referred to as the “alternate gate” or “gate structure”. The gate stack 97 may extend along the sidewall of the channel region 58 of the fin 52.

[0058] According to some embodiments, the remaining portion of the material of the gate electrode layer 94 in the capacitor region 50C forms the first bottom electrode 95A and the second bottom electrode 95B of the capacitor structure 120. In this way, the bottom electrodes 95A-B of the capacitor structure can be formed simultaneously with the gate stack 97 of the FinFET structure 119.

[0059] Additional electrodes for the capacitor structure can be formed without the use of additional masks or other additional process steps by stacking the electrodes together with the gate of the transistor. In some embodiments, one of the bottom electrodes 95A-B may be connected to a "high" terminal (e.g., high voltage) and the other of the bottom electrodes 95A-B may be connected to a "low" terminal (e.g., low voltage). In some embodiments, both the "high" and "low" bottom electrodes are formed using the same process, for example, both are formed using a process for n-type devices or both are formed using a process for p-type devices. In other embodiments, the "high" bottom electrode is formed using a process for n-type devices, while the "low" bottom electrode is formed using a process for p-type devices. In other embodiments, the "high" bottom electrode is formed using a process for p-type devices, while the "low" bottom electrode is formed using a process for n-type devices.

[0060] The capacitance between the first bottom electrode 95A and the second bottom electrode 95B (in) Figure 18B and one(These are schematically shown in some subsequent figures) This increases the total capacitance of capacitor structure 120. In some cases, bottom electrodes 95A-B can be considered as parallel lateral capacitors that increase the capacitance of capacitor structure 120. In some embodiments, bottom electrodes 95A-B may have a rectangular shape with a length L1 ranging from about 100 nm to about 10,000 nm, or a width W1 ranging from about 10 nm to about 100 nm, but other sizes or shapes are possible. In some embodiments, bottom electrodes 95A-B may be spaced apart by a distance D1 ranging from about 10 nm to about 1000 nm, but other distances are also possible. In some cases, the size or distance may be selected based on the operating voltage of the device. In some embodiments, the additional capacitance provided to capacitor structure 120 by bottom electrodes 95A-B can be controlled by controlling the length L1, width W1, and / or separation distance D1. For example, increasing the length L1 of bottom electrodes 95A-B or decreasing the separation distance D1 can increase the additional capacitance. In some embodiments, more than two bottom electrodes 95 may be used, or one or more of the bottom electrodes 95 may include two or more separate portions. In this way, the capacitance of the resulting capacitor structure 120 can also be controlled.

[0061] The formation of the gate dielectric layer 92 in both the n-type and p-type regions of transistor region 50X can occur simultaneously, such that the gate dielectric layer 92 in both types of regions (e.g., n-type and p-type regions) is formed using the same process and the same material, and the formation of the gate electrode layer 94 can also occur simultaneously, such that the gate electrode layer 94 in both types of regions is formed using the same process and the same material. Therefore, the gate dielectric layer 92 and the gate electrode layer 94 in capacitor region 50C can be formed from the same corresponding materials as the gate dielectric layer 92 and the gate electrode layer 94 in transistor region 50X.

[0062] In some embodiments, the gate dielectric layer 92 in the n-type region of transistor region 50X can be formed using a different process than that used in the p-type region of transistor region 50X. In this way, the gate dielectric layer 92 and / or the gate electrode layer 94 can be made of different materials in each type of region, and they can be formed in each type of region using different processes. In some embodiments, the gate dielectric layer 92 and the gate electrode layer 94 in capacitor region 50C can be formed using the processes and materials used for the n-type region of transistor region 50X, or using the processes and materials used for the p-type region of transistor region 50X. For example, both bottom electrodes 95A-B can be formed using the same processes and materials, which can correspond to either the processes and materials used for the n-type region or the processes and materials used for the p-type region. In some embodiments, one of the bottom electrodes 95A-B is formed using the processes and materials used for the n-type region, while the other of the bottom electrodes 95A-B is formed using the processes and materials used for the p-type region. When different processes are used, various masking steps can be used to mask and expose appropriate areas.

[0063] According to some embodiments, in Figures 19A-19D In this configuration, a gate mask 96 is formed over a gate dielectric layer 92 and / or a gate electrode layer 94. The gate mask 96 may be disposed between opposing portions of a gate spacer 86. In some embodiments, forming the gate mask 96 includes recessing the gate dielectric layer 92 and / or the gate electrode layer 94 to form a recess directly above the gate dielectric layer 92 and / or the gate electrode layer 94, between opposing portions of the gate spacer 86. The recess is filled with the gate mask 96 comprising one or more layers of dielectric material (e.g., silicon nitride or silicon oxynitride, etc.), followed by a planarization process to remove excess dielectric material extending over the first ILD 88. The gate mask 96 is optional and may be omitted in some embodiments. In such embodiments, the gate dielectric layer 92 and the gate electrode layer 94 may remain flush with the top surface of the first ILD 88.

[0064] For example Figures 19A-19D As shown, the second ILD 108 is deposited on top of the first ILD 88. In some embodiments, the second ILD 108 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD. The electrode contact 111 is subsequently formed. Figure 20 and Figures 21A-21B ) and gate contact 110 ( Figure 21C and Figure 21DIt penetrates the second ILD 108 and the gate mask 96 (if present) to contact the top surface of the recessed gate electrode layer 94.

[0065] According to some embodiments, in Figure 20 and Figures 21A-21D In the middle, electrode contact 111, gate contact 110 and source / drain contact 112 are formed through the second ILD 108 and the first ILD 88. Figure 20 A plan view of capacitor region 50C is shown. Figures 21A-21B A cross-sectional view of capacitor region 50C is shown, and Figures 21C-21D A cross-sectional view of transistor region 50X is shown. Electrode contacts 111 include electrode contact 111A connected to the first bottom electrode 95A and electrode contact 111B connected to the second bottom electrode 95B, as shown... Figure 20 , Figure 21A and Figure 21B As shown in the image.

[0066] As an example of forming electrode contacts 111 and gate contacts 110, openings for electrode contacts 111 and gate contacts 110 may be formed through the second ILD 108 and gate mask 96 (if present). In some embodiments, openings for source / drain contacts 112 may also be formed through the first ILD 88 and the second ILD 108. These openings may be formed using acceptable photolithography and etching techniques. A liner (not shown) and conductive material, such as a diffusion barrier layer, adhesion layer, etc., are formed in the openings. The liner may include titanium, titanium nitride, tantalum, or tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, or nickel, etc. A planarization process, such as CMP, may be performed to remove excess material from the surface of the second ILD 108. The remaining liner and conductive material form electrode contacts 111, gate contacts 110, and source / drain contacts 112 in the openings. An annealing process can be performed to form silicide at the interface between the epitaxial source / drain region 82 and the source / drain contact 112.

[0067] In capacitor region 50C, electrode contacts 111A-B are physically and electrically coupled to bottom electrodes 95A-B. In transistor region 50X, source / drain contacts 112 are physically and electrically coupled to epitaxial source / drain region 82, and gate contact 110 is physically and electrically coupled to gate electrode 106. Electrode contacts 111, gate contacts 110, and source / drain contacts 112 can be formed in different processes or in the same process. In some embodiments, electrode contacts 111 and gate contacts 110 are formed using the same process. In some embodiments, the top surfaces of the second ILD 108, electrode contacts 111, gate contacts 110, and / or source / drain contacts 112 are flush. Although each of the source / drain contacts 112 and the gate contact 110 is shown to have the same cross-section, it should be understood that each of the source / drain contacts 112 and the gate contact 110 may be formed with different cross-sections to avoid short circuits in the contacts. Although electrode contacts 111A and 111B are shown to have the same cross-section, it should be understood that electrode contacts 111A and 111B may be formed with different cross-sections. In some embodiments, electrode contacts 111 have a spacing P1 ranging from about 20 nm to about 200 nm. In some embodiments, electrode contacts 111A and 111B are separated by a distance D2 ranging from about 10 nm to about 100 nm. In other embodiments, electrode contacts 111 may have different sizes, numbers, or arrangements than those shown.

[0068] Figure 21C and Figure 21DA FinFET structure 119 according to some embodiments is shown. In some embodiments, subsequent processing of the transistor region 50X and the FinFET structure 119 is not shown in the following figures, but in some embodiments, similar processing steps to those described below for the capacitor region 50C may be performed on the transistor region 50X. It should be understood that the disclosed FinFET embodiments can also be applied to nanostructure devices, such as nanostructured (e.g., nanosheets, nanowires, gate-all-around, etc.) field-effect transistors (NSFETs). In NSFET embodiments, the fins are replaced by nanostructures formed by patterning an alternating stack of channel layers and sacrificial layers. Dummy gate stacks and source / drain regions are formed in a manner similar to those described in the embodiments above. After the dummy gate stack is removed, the sacrificial layer may be partially or completely removed in the channel region. Replacement gate structures are formed in a manner similar to those described in the embodiments above, and the replacement gate structures may partially or completely fill the openings left by removing the sacrificial layer, and the replacement gate structures may partially or completely surround the channel layer in the channel region of the NSFET device. The ILD and contacts to the replacement gate structure and source / drain regions can be formed in a manner similar to the embodiments described above. The nanostructured device can be formed as disclosed in U.S. Patent Application Publication No. 2016 / 0365414, which is incorporated herein by reference in its entirety.

[0069] The formation of the bottom electrodes 95A-B and electrode contacts 111A-B as described herein allows for the addition of capacitor structure 120. Figures 26A-27 ) capacitor. Figure 22A It shows something similar to Figure 20 The floor plan shown Figure 22B It shows something similar to Figure 21B The cross-sectional view shown. As previously mentioned, the capacitance between the bottom electrodes 95A-B (in...) Figures 22A-22B (Illustrated schematically) This increases the capacitance of capacitor structure 120. Furthermore, electrode contacts 111A-B as described herein can also increase the capacitance of capacitor structure 120. For example, as... Figures 22A-22BAs schematically shown, the capacitance between electrode contact 111A and adjacent electrode contact 111B can also contribute to the total capacitance of capacitor structure 120. In some cases, the pair of electrode contacts 111A-B can be considered as parallel lateral capacitors or additional electrode groups that increase the capacitance of capacitor structure 120. In this way, the capacitance of the capacitor structure can be increased without increasing the area of ​​the capacitor structure or without forming additional electrodes at the top of the capacitor structure. In some embodiments, the additional capacitance provided by electrode contacts 111A-B can be controlled by controlling the spacing (e.g., spacing distance D2), number, or arrangement of electrode contacts 111A-B. For example, increasing the number of pairs of electrode contacts 111A-B or decreasing the spacing distance D2 can increase the additional capacitance. In some cases, the use of bottom electrodes 95A-B and electrode contacts 111A-B as described herein can increase the capacitance of the capacitor structure by up to about 15%, but larger increases are also possible. In some embodiments, the capacitance contributed by the bottom electrodes 95A-B can be in the range of about 5% to about 10% of the total capacitance, and the capacitance contributed by the electrode contacts 111A-B can be in the range of about 2.5% to about 5% of the total capacitance. Other capacitances are also possible.

[0070] Figures 23 to 27 Various views of intermediate steps in forming capacitor structure 120 according to some embodiments are shown. Figure 23 and Figures 24A-24B Electrodes 116A' and 116B' are shown in the dielectric layer 114 formed on electrode contacts 111A-B. Figures 25-27Additional electrodes 116A-B are shown in an additional dielectric layer 115 formed above dielectric layer 114. Electrode 116A' in dielectric layer 114 is electrically coupled to electrode contact 111A and bottom electrode 95A, and electrode 116B' in dielectric layer 114 is electrically coupled to electrode contact 111B and bottom electrode 95B. Electrodes 116A in dielectric layer 115 are electrically coupled to each other and to electrode 116A' through via 117A, and electrodes 116B in dielectric layer 115 are electrically coupled to each other and to electrode 116B' through via 117B. Electrodes 116A' and 116B' form a parallel lateral capacitor, and each electrode 116A forms a parallel lateral capacitor with its corresponding electrode 116B. The capacitance of a pair of electrodes 116A'-B' and each pair of electrodes 116A-B increases the total capacitance of capacitor structure 120. In this manner, bottom electrode 95A, electrode contact 111A, electrode 116A', and electrode 116A form the first capacitor electrode 121A of capacitor structure 120, while bottom electrode 95B, electrode contact 111B, electrode 116B', and electrode 116B form the second capacitor electrode 121B of capacitor structure 120. In some embodiments, one of capacitor electrodes 121A-B can be connected to a "high" terminal (e.g., high voltage), and the other of capacitor electrodes 121A-B can be connected to a "low" terminal (e.g., low voltage).

[0071] In some embodiments, electrodes 116A'-B' and / or electrodes 116A-B are formed using the same process used to form the metallization patterns, wires, etc., of the device. For example, the metallization patterns, wires, etc., can be those that can be formed over transistor region 50X. For instance, a first metallization pattern of the device can be formed in dielectric layer 114, and subsequent metallization patterns can be formed in subsequently formed dielectric layer 115. In this way, in some cases, dielectric layer 114 and / or dielectric layer 115 can be considered as an intermetallic dielectric (IMD) layer. Electrodes 116A'-B' and / or electrodes 116A-B can be formed using suitable processes, such as damascene processes, dual damascene processes, or other processes. In some embodiments, electrodes 116A'-B' and / or electrodes 116A-B vertically overlap with bottom electrodes 95A-B, and electrodes 116A'-B' and / or electrodes 116A-B can have similar dimensions or shapes to bottom electrodes 95A-B.

[0072] Turning Figure 23 and Figures 24A-24B According to some embodiments, electrodes 116A'-B' are formed in a dielectric layer 114 above bottom electrodes 95A-B. Figure 23 A floor plan is shown. Figures 24A-24BThe corresponding cross-sectional view is shown. Electrode 116A' is physically and electrically coupled to electrode contact 111A, and electrode 116B' is physically and electrically coupled to electrode contact 111B. (As shown) Figure 23 and Figure 24B As schematically shown, in addition to the capacitance between electrode contacts 111A-B and the bottom electrode 95A-B, the capacitance between electrodes 116A'-B' provides some of the total capacitance of capacitor structure 120. In some embodiments, electrodes 116A'-B' may have a length L1 relative to the bottom electrode 95A-B (see [reference]). Figure 18A Different lengths, or can have a width W1 similar to the bottom electrode 95A-B (see...). Figure 18B Different widths. For example, electrode 116A'-B' can have a length greater than L1 or a width greater than W1, but other combinations of length and width are also possible.

[0073] As a formation Figure 23 and Figures 24A-24B In the example of electrodes 116A'-B' shown, a dielectric layer 114 can be formed over the second ILD 108 and electrode contacts 111A-B. The dielectric layer 114 can be similar to the second ILD 108 and can be formed using similar techniques. Other materials or techniques are possible. An optional etch stop layer (not shown) can be formed between the second ILD 108 and the dielectric layer 114. Openings corresponding to the pattern of electrodes 116A'-B' can then be patterned in the dielectric layer 114, where the openings expose the surfaces of the electrode contacts 111A-B. Conductive material can be deposited within the openings to form electrodes 116A'-B'. The conductive material can be similar to that used for electrode contacts 111A-B, gate contact 110, and source / drain contact 112 (see [link to documentation]). Figures 21A-21D The conductive materials described herein can be formed in a similar manner. Other conductive materials or deposition techniques are also possible. A planarization process can be performed to remove excess conductive material from the dielectric layer 114. Figures 24A-24B Electrodes 116A'-B' are shown as having substantially vertical sidewalls, but in other embodiments, electrodes 116A'-B' may have sloping sidewalls, curved sidewalls, or other sidewall profiles.

[0074] Turning Figure 25 and Figures 26A-26B According to some embodiments, additional electrodes 116A-B are formed on electrodes 116A'-B'. Figure 25 A floor plan is shown. Figures 26A-26BA corresponding cross-sectional view is shown. Electrodes 116A-B may include multiple sets of electrodes 116A-B formed in multiple dielectric layers 115 above electrodes 116A'-B'. In some embodiments, electrodes 116A-B are physically and electrically coupled to features above or below vias 117A-B. For example, in the bottommost dielectric layer 115 above dielectric layer 114, electrode 116A is physically and electrically coupled to electrode 116A' via one or more vias 117A, and electrode 116B is physically and electrically coupled to electrode 116B' via one or more vias 117B. Each subsequent electrode 116A in dielectric layer 115 is physically and electrically coupled to the electrode 116A below via one or more vias 117A, and each subsequent electrode 116B in dielectric layer 115 is physically and electrically coupled to the electrode 116B below via one or more vias 117B. Figure 25 and Figure 26B As schematically shown, the capacitance between each pair of electrodes 116A-B provides additional capacitance to the capacitor structure 120. Electrodes 116A-B may have similar dimensions to or different from electrodes 116A'-B'. Vias 117A-B may or may not overlap with the bottom electrodes 95A-B, and may or may not be aligned with any electrode contacts 111A-B. In some embodiments, via 117A may be located on the side of the capacitor structure 120 opposite to via 117B to reduce the risk of voltage breakdown and / or increase the breakdown voltage of the device. Other arrangements are also possible.

[0075] Electrodes 116A-B and vias 117A-B in dielectric layer 115 can be formed using suitable processes, such as damascene, dual damascene, or other processes. Electrodes 116A-B and corresponding vias 117A-B in dielectric layer 115 can be formed using separate deposition steps or the same deposition steps. Electrodes 116A-B or vias 117A-B can be formed of a material similar to that of electrodes 116A'-B' and can be formed using similar techniques. Each dielectric layer 115 can be formed of one or more layers of material, and in some embodiments may include an etch stop layer. The material of dielectric layer 115 may include materials similar to those described for dielectric layer 114 or the second ILD 108, or may include different materials.

[0076] Figure 27 A three-dimensional view of a capacitor structure 120 according to some embodiments is shown. Figure 27 The capacitor structure 120 shown is similar to Figure 25 and Figures 26A-26B The capacitor structure 120 is shown. For clarity, Figure 27 Some features have been omitted. Figure 27 The capacitor structure 120 shown includes a first capacitor electrode 121A and a second capacitor electrode 121B. The first capacitor electrode 121A includes a bottom electrode 95A, a plurality of electrode contacts 111A, an electrode 116A', and a plurality of electrodes 116A connected through a plurality of vias 117A. The second capacitor electrode 121B includes a bottom electrode 95B, a plurality of electrode contacts 111B, an electrode 116B', and a plurality of electrodes 116B connected through a plurality of vias 117B. Figure 27 The capacitor structure 120 shown is an example, and in other embodiments, the capacitor structure 120 may have features with different arrangements or numbers, or these features may have different sizes or shapes. For example, the number or arrangement of electrode contacts 111A-B or vias 117A-B may differ from that shown in the figure. As another example, the number of pairs of electrodes 116A-B may also differ from that shown in the figure. In other embodiments, the capacitor structure 120 may include zero pairs, one pair, or more than two pairs of electrodes 116A-B formed in a dielectric layer 115 over electrodes 116A'-B'. In this way, the capacitance of the capacitor structure 120 can be controlled by controlling the number of groups of electrodes 116A-B formed over electrodes 116A'-B'.

[0077] As mentioned earlier, capacitor electrodes 121A-B can have the same characteristics as... Figures 25-27 The capacitor structure 120 shows different shapes or arrangements. As an example, Figures 28-30 A capacitor structure 130 with capacitor electrodes 121A-B having interdigitated "finger-like" features is shown according to some embodiments. In some cases, the capacitor structure 130 may be considered a finger metal-oxide-metal (FMOM) capacitor. Figure 28 A three-dimensional view of capacitor structure 130 is shown. Figure 29 A plan view through electrode contacts 111A-B is shown. Figure 30 A plan view through the topmost electrodes 116A-B is shown. For clarity, Figures 28-30 Some features are not shown in the image. Figures 28-30The capacitor structure 130 shown has a first capacitor electrode 121A with three fingers and a second capacitor electrode 121B with four fingers. However, in other embodiments, capacitor electrodes 121A-B may have more or fewer fingers, or may have the same number of fingers. In some embodiments, the fingers of one layer may be oriented in a different direction than the fingers of another layer (e.g., oriented perpendicular to the fingers of another layer). The fingers of capacitor electrodes 121A-B may have a different arrangement or orientation than those shown in the figures, and all suitable variations are considered to be within the scope of this disclosure.

[0078] According to some embodiments, reference Figure 29 The bottom electrodes 95A-B and capacitor electrodes 121A-B of capacitor structure 130 are shown. Similar to capacitor structure 120, the bottom electrodes 95A-B may be formed simultaneously with the gate stack 97 (not shown). The capacitance between the bottom electrodes 95A-B and between the electrode contacts 111A-B increases the total capacitance of capacitor structure 130. The arrangement of the electrode contacts 111A-B shown is an example, and the electrode contacts 111A-B may have a different arrangement than shown. In some embodiments, the fingers of capacitor electrodes 121A-B may have a length L2 in the range of about 100 nm to about 10,000 nm, or may have a width W3 in the range of about 10 nm to about 100 nm. In some embodiments, the spacing distance D3 between capacitor electrodes 121A-B is in the range of about 10 nm to about 1000 nm. Other lengths, widths, or distances are also possible.

[0079] Figures 1 to 26B An embodiment is shown in which the FinFET structure 119 is formed in transistor region 50X; however, in other embodiments, other transistor structures may be formed in transistor region 50X. As an example, Figures 31A-31B An embodiment is shown in which a capacitor structure 220 is formed in a capacitor region 50C and a planar transistor 219 is formed in a transistor region 50X. Figures 31A-31B It is a cross-sectional view, in which, Figure 31A As shown along section BB, Figure 31B It is shown along a cross section similar to section DD. Figures 31A-31B Some features of the structure shown are similar to those of the target Figures 1-26BThe features described herein, and not all details of all features, are repeated. Planar transistor 219 may be n-type or p-type, and capacitor structure 220 may include features formed using n-type and / or p-type processes. Similar to capacitor electrodes 121A-B of capacitor structures 120 or 130, capacitor structure 220 includes capacitor electrodes 221A-B, which include bottom electrodes 295A-B, electrode contacts 211A-B, electrodes 116A'-B', and may include electrode 116A-B (not shown). The bottom electrodes 295A-B and electrode contacts 211A-B are formed to provide additional capacitance to capacitor structure 220. Figures 31A-31B The embodiment shown is an example, and other capacitor structures 220 or planar transistors 219 are possible.

[0080] In some embodiments, the planar transistor 219 includes an STI region 256 formed in a transistor region 50X of the substrate 50. In some embodiments, the planar transistor 219 includes a gate stack 297, which includes a gate dielectric layer 292 formed on the substrate 50 and a gate electrode layer 294 formed on the gate dielectric layer 292. A gate spacer 286 may be formed along the sidewalls of the gate stack 297, and an etch stop layer 287 may be formed on the gate spacer 286, the gate stack 297, the substrate 50, and the STI region 256. The source / drain region 282 may be formed in the substrate 50 using, for example, one or more implantation processes.

[0081] In some embodiments, capacitor structure 220 is formed on STI region 256 in capacitor region 50C of substrate 50, but in other embodiments, capacitor structure 220 is formed on substrate 50. In some embodiments, bottom electrodes 295A-B are formed using the same process as forming gate stack 297 of planar transistor 219. For example, gate dielectric layer 292 may be formed in capacitor region 50C and gate electrode layer 294 may be formed on gate dielectric layer 292 in capacitor region 50C. Bottom electrodes 295A-B of capacitor structure 220 are formed by gate electrode layer 294, similar to bottom electrodes 95A-B of capacitor structure 120 being formed by gate electrode layer 94, as previously described.

[0082] A first ILD 88 and a second ILD 108 may be formed over the etch stop layer 287. In capacitor region 50C, electrode contacts 211A-B may extend through the second ILD 108 to physically and electrically couple bottom electrodes 295A-B. In transistor region 50X, source / drain contacts 210 may extend through the first ILD 88 and the second ILD 108 to physically and electrically couple source / drain regions 282, and gate contact 212 may extend through the second ILD to physically and electrically couple gate stack 297. In some embodiments, the same process may be used to form electrode contacts 211A-B, source / drain contacts 210, and / or gate contact 212. Electrodes 116A'-B' may be formed in the dielectric layer 114 in capacitor region 50C, on electrode contacts 211A-B, and wires 216 may be formed in the dielectric layer 114 in transistor region 50X. In some embodiments, electrodes 116A'-B' can be formed using the same process as forming wire 216. Subsequently, groups of electrodes 116A-B and groups of vias 117A-B (not shown) can be formed on electrodes 116A'-B', similar to... Figures 26A-26B The features shown are illustrated. In this way, capacitor structure 220 can be formed in capacitor region 50C, and planar transistor 219 can be formed in transistor region 50X.

[0083] The embodiments described herein offer several advantages. The techniques described herein allow for increasing the capacitance of a capacitor structure without the use of additional process steps or masks. The techniques include forming a bottom electrode of the capacitor structure in the same device layer as the gate stack of the transistor, and forming electrode contacts in the same device layer as the contacts of the transistor. The bottom electrode and electrode contacts can serve as additional parallel capacitors for the capacitor structure. Therefore, the capacitance of the capacitor structure can be increased without increasing the area of ​​the capacitor structure or its vertical height above the substrate. This can reduce the manufacturing cost of forming the capacitor structure. The techniques described herein are fully compatible with back-end process (BEOL) processes or various process technologies used to form different types of transistors (e.g., CMOS process technology, FinFET process technology, etc.). The capacitance of the capacitor structure can be adjusted by controlling the configuration of the bottom electrode and / or electrode contacts (e.g., size, shape, spacing, etc.).

[0084] According to embodiments of this disclosure, a device includes: a first dielectric layer located on a semiconductor substrate; a second dielectric layer located on the first dielectric layer; a transistor located on a first region of the semiconductor substrate, wherein the transistor includes: a gate stack located in the first dielectric layer, wherein the gate stack includes a gate dielectric material layer and a gate electrode material layer; and a gate contact located in the second dielectric layer, wherein the gate contact is connected to the gate stack, wherein the gate contact includes a gate contact material; and a capacitor structure located on a second region of the semiconductor substrate, wherein the capacitor structure includes: a first electrode and a second electrode located in the first dielectric layer, wherein the first electrode and the second electrode include a gate electrode material; a first electrode contact located in the second dielectric layer, wherein the first electrode contact is located on and connected to the first electrode, wherein the first electrode contact includes a gate contact material; and a second electrode contact located in the second dielectric layer, wherein the second electrode contact is located on and connected to the second electrode, wherein the second electrode contact includes a gate contact material, wherein each first electrode contact on the first electrode is adjacent to at least one corresponding second electrode contact on the second electrode. In one embodiment, the capacitor structure further includes: a third electrode located above and connected to the first electrode contact, and a fourth electrode located above and connected to the second electrode contact. In one embodiment, the third electrode has the same shape as the first electrode, and the fourth electrode has the same shape as the second electrode. In one embodiment, the capacitor structure is located on an isolation region in a semiconductor substrate. In one embodiment, the gate electrode material is different from the gate contact material. In one embodiment, the capacitor structure further includes a gate dielectric material located on the first and second electrodes. In one embodiment, the transistor is a FinFET (Fin Field-Effect Transistor). In one embodiment, the transistor is n-type.

[0085] According to embodiments of this disclosure, a semiconductor device includes: a substrate; a first device located on the substrate, wherein the first device includes: a gate stack including a gate electrode material; a source / drain region located in the substrate and adjacent to the gate stack; a first isolation region surrounding the gate stack; a gate contact located on and in contact with the gate stack, wherein the gate contact includes a gate contact material; and a second isolation region surrounding the gate contact; and a second device located on the substrate, wherein the second device includes: a first parallel capacitor including a first electrode including a gate electrode material, wherein the first isolation region separates the first electrode; and a second parallel capacitor located on the first parallel capacitor, wherein the second parallel capacitor includes a second electrode connected to the first electrode, wherein the second electrode includes a gate contact material, wherein adjacent second electrodes are separated by the second isolation region. In one embodiment, the first electrode has interdigitated fingers. In one embodiment, each first electrode is connected to a corresponding second electrode. In one embodiment, the semiconductor device includes a third parallel capacitor located above the second parallel capacitor, wherein the third parallel capacitor includes a third electrode connected to the second electrode, and each third electrode is connected to a corresponding second electrode. In one embodiment, the first device is a planar transistor. In one embodiment, the top surfaces of the second isolation region, the second electrode, and the gate contact are flush. In one embodiment, the semiconductor device includes a first spacer along the sidewalls of the gate stack and a second spacer along the sidewalls of the first electrode, wherein the first spacer and the second spacer are made of the same material. In one embodiment, the first parallel capacitor and the second parallel capacitor together provide a capacitance between 7.5% and 15% of the total capacitance of the second device.

[0086] According to one embodiment of this disclosure, a method of forming a capacitor structure includes: depositing a dummy gate material on a semiconductor substrate; patterning the dummy gate material to form a dummy electrode; forming a spacer along the sidewalls of the dummy electrode; depositing an isolation material on and between the dummy electrodes; removing the dummy gate material to form a recess; depositing a gate dielectric material in the recess; and forming a first electrode of the capacitor structure, including depositing a gate electrode material on the gate dielectric material within the recess. In one embodiment, the semiconductor substrate includes fins, wherein the gate dielectric material and the gate electrode material are deposited on the fins to form a gate stack of a transistor structure. In one embodiment, the method includes: forming a second electrode on a first electrode, wherein forming the second electrode includes depositing a first dielectric material on the first electrode; patterning a first opening of the first electrode in the first dielectric material to expose the first electrode; and filling the first opening with a first conductive material. In one embodiment, the method includes: forming a third electrode on a second electrode, wherein forming the third electrode includes depositing a second dielectric material on the second electrode; patterning a second opening of the second electrode in the second dielectric material to expose the second electrode; and filling the second opening with a second conductive material.

[0087] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0088] Example 1 is a semiconductor device comprising: a first dielectric layer disposed on a semiconductor substrate; a second dielectric layer disposed on the first dielectric layer; a transistor disposed on a first region of the semiconductor substrate, wherein the transistor comprises: a gate stack disposed in the first dielectric layer, wherein the gate stack comprises a layer of gate dielectric material and a layer of gate electrode material; and a gate contact disposed in the second dielectric layer, wherein the gate contact is connected to the gate stack, wherein the gate contact comprises a gate contact material; and a capacitor structure disposed on a second region of the semiconductor substrate, wherein the capacitor structure comprises: a first electrode and a second electrode disposed on a first region of the semiconductor substrate; and a gate contact disposed on a second region of the semiconductor substrate. In the first dielectric layer, the first electrode and the second electrode include the gate electrode material; a plurality of first electrode contacts are located in the second dielectric layer, wherein the first electrode contacts are located above and connected to the first electrode, and wherein the first electrode contacts include the gate contact material; and a plurality of second electrode contacts are located in the second dielectric layer, wherein the second electrode contacts are located above and connected to the second electrode, and wherein the second electrode contacts include the gate contact material, wherein each first electrode contact on the first electrode is adjacent to at least one corresponding second electrode contact on the second electrode.

[0089] Example 2 is a semiconductor device according to Example 1, wherein the capacitor structure further includes: a third electrode located on and connected to the plurality of first electrode contacts; and a fourth electrode located on and connected to the plurality of second electrode contacts.

[0090] Example 3 is a semiconductor device according to Example 2, wherein the third electrode has the same shape as the first electrode and the fourth electrode has the same shape as the second electrode.

[0091] Example 4 is a semiconductor device according to Example 1, wherein the capacitor structure is located on an isolation region in the semiconductor substrate.

[0092] Example 5 is a semiconductor device according to Example 1, wherein the gate electrode material is different from the gate contact material.

[0093] Example 6 is a semiconductor device according to Example 1, wherein the capacitor structure further includes a gate dielectric material located on the first electrode and the second electrode.

[0094] Example 7 is a semiconductor device according to Example 1, wherein the transistor is a FinFET (Fin Field-Effect Transistor).

[0095] Example 8 is a semiconductor device according to Example 1, wherein the transistor is n-type.

[0096] Example 9 is a semiconductor device comprising: a substrate; a first device disposed on the substrate, wherein the first device includes: a gate stack including a gate electrode material; a source / drain region disposed in the substrate and adjacent to the gate stack; a first isolation region surrounding the gate stack; a gate contact disposed on and in contact with the gate stack, wherein the gate contact includes a gate contact material; and a second isolation region surrounding the gate contact; and a second device disposed on the substrate, wherein the second device includes: a first parallel capacitor including a first electrode, wherein the first electrode includes the gate electrode material, wherein the first isolation region separates the first electrode; and a second parallel capacitor disposed on the first parallel capacitor, wherein the second parallel capacitor includes a second electrode connected to the first electrode, wherein the second electrode includes the gate contact material, wherein adjacent second electrodes are separated by the second isolation region.

[0097] Example 10 is a semiconductor device according to Example 9, wherein the first electrode has interdigitated fingers.

[0098] Example 11 is a semiconductor device according to Example 9, wherein each first electrode is connected to a corresponding plurality of second electrodes.

[0099] Example 12 is a semiconductor device according to Example 9, further comprising: a third parallel capacitor located above the second parallel capacitor, wherein the third parallel capacitor includes a third electrode connected to the second electrode, wherein each third electrode is connected to a corresponding plurality of second electrodes.

[0100] Example 13 is a semiconductor device according to Example 9, wherein the first device is a planar transistor.

[0101] Example 14 is a semiconductor device according to Example 9, wherein the top surfaces of the second isolation region, the second electrode, and the gate contact are flush.

[0102] Example 15 is a semiconductor device according to Example 9, further comprising: a first spacer along the sidewall of the gate stack and a second spacer along the sidewall of the first electrode, wherein the first spacer and the second spacer are made of the same material.

[0103] Example 16 is a semiconductor device according to Example 9, wherein the first parallel capacitor and the second parallel capacitor together provide a capacitance between 7.5% and 15% of the total capacitance of the second device.

[0104] Example 17 is a method of forming a capacitor structure, the method comprising: depositing a dummy gate material on a semiconductor substrate; patterning the dummy gate material to form a dummy electrode; forming a spacer along the sidewalls of the dummy electrode; depositing an isolation material on and between the dummy electrodes; removing the dummy gate material to form a recess; depositing a gate dielectric material in the recess; and forming a first electrode of the capacitor structure, including depositing a gate electrode material on the gate dielectric material within the recess.

[0105] Example 18 is the method according to Example 17, wherein the semiconductor substrate includes fins, wherein the gate dielectric material and the gate electrode material are deposited on the fins to form a gate stack of a transistor structure.

[0106] Example 19 is the method according to Example 17, further comprising forming a second electrode on the first electrode, wherein forming the second electrode comprises: depositing a first dielectric material on the first electrode; patterning a first opening of the first electrode in the first dielectric material to expose the first electrode; and filling the first opening with a first conductive material.

[0107] Example 20 is the method according to Example 19, further comprising forming a third electrode on the second electrode, wherein forming the third electrode comprises: depositing a second dielectric material on the second electrode; patterning a second opening of the second electrode in the second dielectric material to expose the second electrode; and filling the second opening with a second conductive material.

Claims

1. A semiconductor device, comprising: The first dielectric layer is located on the semiconductor substrate; The second dielectric layer is located on top of the first dielectric layer; A transistor, located on a first region of the semiconductor substrate, wherein the transistor comprises: A gate stack, located in the first dielectric layer, wherein the gate stack includes a layer of gate dielectric material and a layer of gate electrode material; and A gate contact, located in the second dielectric layer, wherein the gate contact substantially contacts the top surface of the gate stack, wherein the gate contact comprises a gate contact material; and A capacitor structure is located on a second region of the semiconductor substrate, wherein the capacitor structure includes: The first electrode and the second electrode are located in the first dielectric layer, wherein the first electrode and the second electrode include the gate electrode material; A plurality of first electrode contacts are located in the second dielectric layer, wherein the first electrode contacts substantially contact the top surface of the first electrode, and wherein the first electrode contacts include the gate contact material; and A plurality of second electrode contacts are located in the second dielectric layer, wherein the second electrode contacts substantially contact the top surface of the second electrode, wherein the second electrode contacts include the gate contact material, wherein each first electrode contact on the first electrode is adjacent to at least one corresponding second electrode contact on the second electrode, wherein the second electrode contact corresponding to the first electrode contact is the second electrode contact closest to the first electrode contact.

2. The semiconductor device according to claim 1, wherein, The capacitor structure also includes: A third electrode is located on and connected to the plurality of first electrode contacts; and The fourth electrode is located above and connected to the plurality of second electrode contacts.

3. The semiconductor device according to claim 2, wherein, The third electrode has the same shape as the first electrode, and the fourth electrode has the same shape as the second electrode.

4. The semiconductor device according to claim 1, wherein, The capacitor structure is located on an isolation region in the semiconductor substrate.

5. The semiconductor device according to claim 1, wherein, The gate electrode material is different from the gate contact material.

6. The semiconductor device according to claim 1, wherein, The capacitor structure further includes a gate dielectric material located on the first electrode and the second electrode.

7. The semiconductor device according to claim 1, wherein, The transistor is a FinFET (Fin Field Effect Transistor).

8. The semiconductor device according to claim 1, wherein, The transistor is n-type.

9. A semiconductor device, comprising: Substrate; A first device, located on the substrate, wherein the first device includes: Gate stack, including gate electrode material; The source / drain region is located in the substrate and adjacent to the gate stack; A first isolation region laterally surrounds the gate stack, wherein the first isolation region is above the substrate and extends along the sidewalls of the gate stack; A gate contact, located above and in contact with the gate stack entity, wherein the gate contact comprises a first conductive material; and A second isolation region laterally surrounds the gate contact; and A second device, located on the substrate, wherein the second device includes: A first parallel capacitor includes a first electrode, wherein the first electrode includes the gate electrode material, and wherein the first isolation region laterally separates the first electrode; and A second parallel capacitor is located above the first parallel capacitor, wherein the second parallel capacitor includes a second electrode substantially connected to the first electrode, wherein the second electrode includes the first conductive material, wherein adjacent second electrodes are laterally separated by the second isolation region, and wherein at least one second electrode on one first electrode is arranged in a straight line between two second electrodes on another first electrode.

10. The semiconductor device according to claim 9, wherein, The first electrode has interdigitated fingers.

11. The semiconductor device according to claim 9, wherein, Each first electrode is connected to a corresponding plurality of second electrodes.

12. The semiconductor device according to claim 9, further comprising: A third parallel capacitor is located above the second parallel capacitor, wherein the third parallel capacitor includes a third electrode connected to the second electrode, and each third electrode is connected to a corresponding plurality of second electrodes.

13. The semiconductor device according to claim 9, wherein, The first device is a planar transistor.

14. The semiconductor device according to claim 9, wherein, The top surfaces of the second isolation region, the second electrode, and the gate contact are flush.

15. The semiconductor device according to claim 9, further comprising: A first spacer along the sidewall of the gate stack and a second spacer along the sidewall of the first electrode, wherein the first spacer and the second spacer are made of the same material.

16. The semiconductor device according to claim 9, wherein, The first parallel capacitor and the second parallel capacitor together provide between 7.5% and 15% of the total capacitance of the second device.

17. A method for forming a capacitor structure, the method comprising: Deposit a dummy gate material on a semiconductor substrate; The dummy gate material is patterned to form a dummy electrode; A spacer is formed along the sidewall of the dummy electrode; An insulating material is deposited on and between the dummy electrodes; Remove the dummy gate material to form a recess; Deposit gate dielectric material in the recess; The first and second electrodes forming the capacitor structure include depositing a gate electrode material on the gate dielectric material within the recess; as well as Forming a third electrode on the first electrode and a fourth electrode on the second electrode includes directly depositing a first conductive material on the first electrode and the second electrode, wherein each third electrode on the first electrode is laterally adjacent to at least one fourth electrode on the second electrode.

18. The method according to claim 17, wherein, The semiconductor substrate includes fins, wherein the gate dielectric material and the gate electrode material are deposited on the fins to form a gate stack of a transistor structure.

19. The method of claim 17, wherein, The formation of the third electrode also includes: A first dielectric material is deposited on the first electrode and the second electrode; Patterning a first opening in the first dielectric material to expose the first electrode and the second electrode; and The first opening is filled with the first conductive material.

20. The method of claim 19, further comprising forming a fifth electrode on the third electrode, wherein, Forming the fifth electrode includes: A second dielectric material is deposited on the third electrode; Patterning a second opening in the second dielectric material to expose each third electrode; and The second opening is filled with a second conductive material, wherein the second conductive material extends continuously over the third electrode.

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