Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a first active pattern on a substrate, a pair of first source / drain patterns on the first active pattern and a first channel pattern between the pair of first source / drain patterns, wherein the first channel pattern includes a plurality of semiconductor patterns stacked on and spaced apart from each other, a first gate electrode on the first channel pattern, a first gate cut pattern adjacent to the first channel pattern and penetrating the first gate electrode, and a first residual pattern between the first gate cut pattern and the first channel pattern. The first residual pattern covers an outermost sidewall of at least one semiconductor pattern of the plurality of semiconductor patterns of the first channel pattern. The first gate electrode includes a first extension vertically stacked with the first residual pattern on an upper portion of the first gate electrode.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2021-0047789, filed on April 13, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0002] The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more specifically, to a semiconductor device including a field-effect transistor and a method of manufacturing the semiconductor device. Background Technology

[0003] Semiconductor devices include integrated circuits, which include metal-oxide-semiconductor field-effect transistors (MOSFETs). As the size and design rules of semiconductor devices continue to shrink, the size of MOSFETs is also shrinking. This shrinking of MOSFETs degrades the operating characteristics of semiconductor devices. Therefore, various studies have been conducted to develop methods for manufacturing semiconductor devices that achieve excellent performance while overcoming the limitations caused by the high integration density of semiconductor devices. Summary of the Invention

[0004] Some exemplary embodiments of the present invention provide semiconductor devices with increased reliability and improved electrical characteristics.

[0005] Some exemplary embodiments of the present invention provide methods for manufacturing semiconductor devices with increased reliability and improved electrical characteristics.

[0006] According to some exemplary embodiments conceived in this invention, a semiconductor device may include: a first active pattern located on a substrate; a pair of first source / drain patterns located on the first active pattern and a first channel pattern located between the pair of first source / drain patterns, the first channel pattern including a plurality of semiconductor patterns stacked and spaced apart from each other; a first gate electrode located on the first channel pattern; a first gate dicing pattern adjacent to the first channel pattern and penetrating the first gate electrode; and a first residual pattern located between the first gate dicing pattern and the first channel pattern. The first residual pattern may cover the outermost sidewall of at least one of the plurality of semiconductor patterns of the first channel pattern. The first gate electrode may include a first extension located on an upper portion of the first gate electrode, and the first extension may be vertically stacked with the first residual pattern.

[0007] According to some exemplary embodiments of the present invention, a semiconductor device may include: a logic region including logic cells; and a memory region including static random access memory (SRAM) cells. The logic cells may include: a first active pattern; a first channel pattern located on the first active pattern; the first channel pattern including a plurality of semiconductor patterns stacked and spaced apart from each other; a first gate electrode located on the first channel pattern; and a first gate dicing pattern adjacent to and penetrating the first gate electrode. The SRAM cells may include: a second active pattern; a second channel pattern located on the second active pattern, the second channel pattern including a plurality of separate semiconductor patterns stacked and spaced apart from each other; a second gate electrode located on the second channel pattern; a second gate dicing pattern adjacent to and penetrating the second gate electrode; and a residual pattern located between the second gate dicing pattern and the second channel pattern. The first gate electrode may have a ring gate structure in which the first gate electrode surrounds the plurality of semiconductor patterns of the first channel pattern. The residual pattern may cover the outermost sidewall of at least one of the separate plurality of semiconductor patterns of the second channel pattern. The second gate electrode may be located on the top surface, bottom surface, and sidewall of at least one of the separated semiconductor patterns in the second channel pattern, and may not be located on the outermost sidewall of the at least one semiconductor pattern included in the plurality of semiconductor patterns in the second channel pattern.

[0008] According to some exemplary embodiments conceived in this invention, a semiconductor device may include: a first active pattern and a second active pattern, located on a substrate; a pair of first source / drain patterns located on the first active pattern and a first channel pattern located between the pair of first source / drain patterns; a pair of second source / drain patterns located on the second active pattern and a second channel pattern located between the pair of second source / drain patterns, the first channel pattern including a plurality of semiconductor patterns stacked and spaced apart from each other, and the second channel pattern including a plurality of separate semiconductor patterns stacked and spaced apart from each other; a gate electrode located on the first channel pattern and the second channel pattern; a gate dielectric layer located between the gate electrode and the first channel pattern and the second channel pattern; a gate spacer located on at least one sidewall of the gate electrode; a first gate dicing pattern adjacent to the first channel pattern and penetrating the gate electrode; and a second gate dicing pattern adjacent to the second channel pattern. The first gate dicing pattern is adjacent to and penetrates the gate electrode; a first residual pattern is located between the first gate dicing pattern and the first channel pattern; a gate overlay pattern is located on the gate electrode and on the first and second gate dicing patterns; an interlayer dielectric layer is located on the gate overlay pattern; an active contact is located through the interlayer dielectric layer and has an electrical connection to at least one of the pair of first source / drain patterns and / or the pair of second source / drain patterns; a gate contact is located through the interlayer dielectric layer and the gate overlay pattern and has an electrical connection to the gate electrode; a first metal layer is located on the interlayer dielectric layer, the first metal layer including a first power line on the first gate dicing pattern, a second power line on the second gate dicing pattern, and a plurality of first wirings located between the first power line and the second power line, the first wirings being correspondingly electrically connected to the active contact and the gate contact; and a second metal layer is located on the first metal layer. The second metal layer may include a plurality of second wirings electrically connected to the first metal layer. The first residual pattern may cover the first outermost sidewall of at least one of the plurality of semiconductor patterns of the first channel pattern. The top surface of the first residual pattern may have an increased height in the direction from the first channel pattern toward the first gate dicing pattern.

[0009] According to some exemplary embodiments of the present invention, a method of manufacturing a semiconductor device may include: forming a stacked pattern on an active pattern of a substrate, the stacked pattern including a plurality of sacrificial layers and a plurality of semiconductor patterns alternately stacked on the active pattern; forming a sacrificial pattern extending across the stacked pattern on the stacked pattern; forming an interlayer dielectric layer on the sacrificial pattern; forming a gate dicing pattern penetrating a portion of the sacrificial pattern; selectively etching the sacrificial pattern using an etching process to form an external region exposing the stacked pattern; forming a residual pattern during the etching process of the sacrificial pattern based on allowing a portion of the sacrificial pattern to remain between the gate dicing pattern and the stacked pattern; forming an internal region between the plurality of semiconductor patterns of the stacked pattern based on selectively removing the sacrificial layer of the stacked pattern, exposing the sacrificial layer to the external region; and forming a gate electrode filling the internal and external regions. Attached Figure Description

[0010] Figure 1 , Figure 2 and Figure 3 A conceptual diagram illustrating the logic unit of a semiconductor device demonstrating some example embodiments of the concept according to the present invention is shown.

[0011] Figure 4 A plan view of a semiconductor device illustrating some example embodiments of a concept according to the present invention is shown.

[0012] Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E They show the following along Figure 4 The sectional view taken from lines A-A', B-B', C-C', D-D', and E-E'.

[0013] Figure 6 The demonstration is shown Figure 5D An enlarged view of an example of part M depicted in the image.

[0014] Figure 7 The demonstration is shown Figure 5D An enlarged view of an example of part M depicted in the image.

[0015] Figure 8 and Figure 9 It shows along Figure 4 The line E-E' shows a cross-sectional view of a semiconductor device illustrating some exemplary embodiments of the concept according to the present invention.

[0016] Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C and Figure 16D A cross-sectional view is shown illustrating a method of manufacturing a semiconductor device according to some exemplary embodiments of the concept of the present invention.

[0017] Figure 17 A simplified plan view of a semiconductor chip illustrating some example embodiments of the concept according to the present invention is shown.

[0018] Figure 18 The demonstration is shown Figure 17 A plan view of the SRAM cells in the memory region depicted in the image.

[0019] Figure 19 It shows along Figure 18 A sectional view taken by line A-A'. Detailed Implementation

[0020] Figure 1 , Figure 2 and Figure 3 A conceptual diagram illustrating the logic unit of a semiconductor device demonstrating some example embodiments of the concept according to the present invention is shown.

[0021] Reference Figure 1 A single-height cell (SHC) can be provided. For example, a substrate 100 may have a first power line M1_R1 and a second power line M1_R2 thereon. The first power line M1_R1 may be a path for providing the drain voltage VDD (e.g., the supply voltage). The second power line M1_R2 may be a path for providing the source voltage VSS (e.g., the ground voltage).

[0022] A single-height cell SHC can be defined between the first power line M1_R1 and the second power line M1_R2. The single-height cell SHC may include a PMOSFET region PR and an NMOSFET region NR. For example, the single-height cell SHC may have a CMOS structure disposed between the first power line M1_R1 and the second power line M1_R2.

[0023] Each of the PMOSFET region PR and the NMOSFET region NR may have a first width W1 in the first direction D1. The first height HE1 may be defined as the length of a single-height cell SHC in the first direction D1. The first height HE1 may be the same as or substantially the same as the distance (e.g., pitch) between the first power line M1_R1 and the second power line M1_R2.

[0024] A single-height SHC can constitute a logic unit. In this specification, a logic unit can represent a logic device that performs a specific function, such as AND, OR, XOR, XNOR, and an inverter. For example, a logic unit may include transistors for constituting a logic device and wiring connecting the transistors to each other.

[0025] Reference Figure 2 A dual-height cell (DHC) can be provided. For example, a substrate 100 may have a first power line M1_R1, a second power line M1_R2, and a third power line M1_R3 disposed thereon. The first power line M1_R1 may be located between the second power line M1_R2 and the third power line M1_R3. The third power line M1_R3 may be a path for providing the source voltage VSS.

[0026] A dual-height cell DHC can be defined between the second power line M1_R2 and the third power line M1_R3. The dual-height cell DHC may include a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2.

[0027] The first NMOSFET region NR1 can be adjacent to the second power line M1_R2. The second NMOSFET region NR2 can be adjacent to the third power line M1_R3. The first PMOSFET region PR1 and the second PMOSFET region PR2 can be adjacent to the first power line M1_R1. When viewed in a plan view, the first power line M1_R1 can be located between the first PMOSFET region PR1 and the second PMOSFET region PR2.

[0028] The second height HE2 can be defined as the length of the dual-height unit DHC in the first direction D1. The second height HE2 can be... Figure 1 The first height HE1 is approximately twice that of the second height. The first PMOSFET region PR1 and the second PMOSFET region PR2 of the dual-height cell DHC can operate together as a single PMOSFET region.

[0029] Therefore, a dual-height unit (DHC) can have a channel size ratio including the above. Figure 1The PMOS transistors in the single-height cell SHC discussed herein have large channel dimensions. For example, the channel size of the PMOS transistors included in the dual-height cell DHC can be approximately twice the channel size of the PMOS transistors included in the single-height cell SHC. In summary, the dual-height cell DHC can operate at a higher speed than the single-height cell SHC. In the inventive concept, Figure 2 The dual-height cell DHC shown can be defined as a multi-height cell. Although not shown, a multi-height cell may include a tri-height cell whose cell height is approximately three times that of a single-height cell SHC.

[0030] Reference Figure 3 The base 100 may be provided with a two-dimensional positioning first single-height unit SHC1, a second single-height unit SHC2, and a dual-height unit DHC. The first single-height unit SHC1 may be located between the first power line M1_R1 and the second power line M1_R2. The second single-height unit SHC2 may be located between the first power line M1_R1 and the third power line M1_R3. The second single-height unit SHC2 may be adjacent to the first single-height unit SHC1 in the first direction D1.

[0031] The dual-height unit DHC can be located between the second power line M1_R2 and the third power line M1_R3. The dual-height unit DHC can be adjacent to the first single-height unit SHC1 and the second single-height unit SHC2 in the second direction D2.

[0032] The separation structure DB can be located between the first single-height unit SHC1 and the dual-height unit DHC, and between the second single-height unit SHC2 and the dual-height unit DHC. The separation structure DB can electrically separate the active region of the dual-height unit DHC from the active regions of each of the first single-height unit SHC1 and the second single-height unit SHC2.

[0033] Figure 4 A plan view of a semiconductor device illustrating some example embodiments of a concept according to the present invention is shown. Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E They show the following along Figure 4 The sectional view taken from lines A-A', B-B', C-C', D-D', and E-E'. Figure 6 The demonstration is shown Figure 5D An enlarged view of an example of part M depicted in the image. Figure 4 and Figures 5A to 5E The semiconductor device shown is Figure 3 Detailed examples of the first single-height unit SHC1 and the second single-height unit SHC2.

[0034] Reference Figure 4 and Figures 5A to 5E The first single-height cell SHC1 and the second single-height cell SHC2 may be disposed on the substrate 100. Each of the first single-height cell SHC1 and the second single-height cell SHC2 may include a logic transistor included in a logic circuit. The substrate 100 may be a compound semiconductor substrate or a semiconductor substrate including silicon, germanium, or silicon-germanium. For example, the substrate 100 may be a silicon substrate.

[0035] The substrate 100 may have a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2. Each of the first PMOSFET region PR1, the second PMOSFET region PR2, the first NMOSFET region NR1, and the second NMOSFET region NR2 may extend in a second direction D2. The first single-height unit SHC1 may include the first NMOSFET region NR1 and the first PMOSFET region PR1, and the second single-height unit SHC2 may include the second PMOSFET region PR2 and the second NMOSFET region NR2.

[0036] A first active pattern AP1 and a second active pattern AP2 may be defined on the substrate 100 by a trench TR formed on the upper portion of the substrate 100. The first active pattern AP1 may be disposed on each of a first PMOSFET region PR1 and a second PMOSFET region PR2. The second active pattern AP2 may be disposed on each of a first NMOSFET region NR1 and a second NMOSFET region NR2. The first active pattern AP1 and the second active pattern AP2 may extend in a second direction D2. The first active pattern AP1 and the second active pattern AP2 may be vertical projections of the substrate 100. In some example embodiments, at least one of the first active pattern AP1 and the second active pattern AP2 may be in a static random access memory (SRAM) cell. In some example embodiments, at least one of the first active pattern AP1 and the second active pattern AP2 may be in a logic cell.

[0037] The trench TR may be filled with a device isolation layer ST. The device isolation layer ST may include a silicon oxide layer. The device isolation layer ST may not cover either the first channel pattern CH1 or the second channel pattern CH2, which will be discussed below.

[0038] The spacer layer OLI can be disposed between the device isolation layer ST and the first active pattern AP1 and the second active pattern AP2. The spacer layer OLI can directly cover the sidewalls of each of the first active pattern AP1 and the second active pattern AP2. For example, the spacer layer OLI can directly cover the sidewalls of the trench TR. The spacer layer OLI can directly cover the bottom surface of the trench TR. For example, the spacer layer OLI can include a silicon oxide layer, a silicon nitride layer, or a combination thereof. In some exemplary embodiments of the inventive concept, the spacer layer OLI can include the same material as the device isolation layer ST, and in this case, no boundary may appear between the spacer layer OLI and the device isolation layer ST.

[0039] A first channel pattern CH1 may be disposed on a first active pattern AP1. A second channel pattern CH2 may be disposed on a second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked sequentially (e.g., a plurality of semiconductor patterns stacked and spaced apart from each other). The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be spaced apart from each other in a vertical direction or a third direction D3. It will be understood that the elements "spaced apart" from each other may be isolated from each other and not in direct contact.

[0040] Each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). For example, each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include crystalline silicon.

[0041] Multiple first source / drain patterns SD1 can be disposed on a first active pattern AP1. Multiple first recesses RS1 can be formed on the upper portion of the first active pattern AP1. The first source / drain patterns SD1 can be disposed in corresponding first recesses RS1. The first source / drain patterns SD1 can be impurity regions having a first conductivity type (e.g., p-type). A first channel pattern CH1 can be disposed between a pair (or pairs) of first source / drain patterns SD1. For example, a pair of first source / drain patterns SD1 can be interconnected by stacked first semiconductor patterns SP1, second semiconductor patterns SP2, and third semiconductor patterns SP3.

[0042] Multiple second source / drain patterns SD2 can be disposed on the second active pattern AP2. Multiple second recesses RS2 can be formed on the upper portion of the second active pattern AP2. The second source / drain patterns SD2 can be disposed in the corresponding second recesses RS2. The second source / drain patterns SD2 can be impurity regions having a second conductivity type (e.g., n-type). A second channel pattern CH2 can be disposed between a pair of second source / drain patterns SD2. For example, the pair of second source / drain patterns SD2 can be interconnected by a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 (which can be referred to as multiple separate semiconductor patterns of the second channel pattern CH2) stacked and spaced apart from each other.

[0043] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be epitaxial patterns formed by a selective epitaxial growth process. For example, each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can have a top surface at the same or substantially the same level as the top surface of the third semiconductor pattern SP3. As another example, each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can have a top surface at a level higher than the top surface of the third semiconductor pattern SP3.

[0044] As described herein, the “level” or “height” of a surface, end, structure, etc., can refer to the distance in a third direction D3 from a common (e.g., identical) reference location (e.g., the upper and / or lower surface of substrate 100). Therefore, when the first element is described herein as being at a level or height higher than that of the second element, the first element may be farther away from the common reference location (e.g., the upper and / or lower surface of substrate 100) in a third direction D3 than the second element. Furthermore, when the first element is described herein as being at a level or height lower than that of the second element, the first element may be closer to the common reference location (e.g., the upper and / or lower surface of substrate 100) in a third direction D3 than the second element. Moreover, when the first element is described herein as being at the same or substantially the same level as the second element, the first element may be equally farther away from / closer to the common reference location (e.g., the upper and / or lower surface of substrate 100) in a third direction D3 as the second element.

[0045] The first source / drain pattern SD1 may include a semiconductor element (e.g., SiGe) whose lattice constant is greater than that of the semiconductor element of the substrate 100. Therefore, a pair of first source / drain patterns SD1 can provide compressive stress to the first channel pattern CH1. The second source / drain pattern SD2 may include the same semiconductor element as the semiconductor element of the substrate 100 (e.g., Si).

[0046] Each of the first source / drain patterns SD1 may include a first semiconductor layer SEL1 and a second semiconductor layer SEL2 on the first semiconductor layer SEL1. (Return to reference) Figure 5A The cross-sectional shape of the first source / drain pattern SD1 in the second direction D2 will be described below.

[0047] The first semiconductor layer SEL1 may cover the inner wall of the first recess RS1. The first semiconductor layer SEL1 may have a thickness that decreases in the direction from its lower portion toward its upper portion. For example, the thickness of the first semiconductor layer SEL1 on the bottom surface of the first recess RS1 in the third direction D3 may be greater than the thickness of the first semiconductor layer SEL1 on the upper portion of the first recess RS1 in the second direction D2. The first semiconductor layer SEL1 may be shaped like a U along the contour of the first recess RS1.

[0048] The second semiconductor layer SEL2 can fill the remaining portion of the first recess RS1 that is filled with the first semiconductor layer SEL1. The second semiconductor layer SEL2 can have a larger volume than the first semiconductor layer SEL1. For example, the ratio of the volume of the second semiconductor layer SEL2 to the total volume of the first source / drain pattern SD1 can be greater than the ratio of the volume of the first semiconductor layer SEL1 to the total volume of the first source / drain pattern SD1.

[0049] Each of the first semiconductor layer SEL1 and the second semiconductor layer SEL2 may include silicon germanium (SiGe). For example, the first semiconductor layer SEL1 may contain germanium (Ge) at a relatively low concentration. In some exemplary embodiments of the inventive concept, the first semiconductor layer SEL1 may include silicon (Si) and may not include germanium (Ge). The first semiconductor layer SEL1 may have a germanium concentration of about 0 at% to about 10 at%.

[0050] The second semiconductor layer SEL2 may contain germanium (Ge) at a relatively high concentration. For example, the second semiconductor layer SEL2 may have a germanium (Ge) concentration of about 30 at% to about 75 at%. The germanium concentration of the second semiconductor layer SEL2 may be increased on the third direction D3. For example, the second semiconductor layer SEL2 adjacent to the first semiconductor layer SEL1 may have a germanium concentration of about 40 at%, but the upper portion of the second semiconductor layer SEL2 may have a germanium concentration of about 60 at%.

[0051] The first semiconductor layer SEL1 and the second semiconductor layer SEL2 may include impurities (e.g., boron) that give the first source / drain pattern SD1 a p-type conductivity. The impurity concentration (e.g., atomic percentage) of the second semiconductor layer SEL2 may be greater than that of the first semiconductor layer SEL1.

[0052] The first semiconductor layer SEL1 can reduce or prevent stacking faults between the substrate 100 and the second semiconductor layer SEL2, and between the second semiconductor layer SEL2 and the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The presence of stacking faults increases channel resistance. Stacking faults can easily occur at the bottom of the first recess RS1. Therefore, it is preferable that the first semiconductor layer SEL1 adjacent to the bottom of the first recess RS1 has a relatively large thickness to reduce or prevent stacking faults.

[0053] While replacing the sacrificial layer SAL with the first part PO1, the second part PO2, and the third part PO3 of the gate electrode GE, which will be discussed below, the first semiconductor layer SEL1 can protect the second semiconductor layer SEL2. For example, the first semiconductor layer SEL1 can reduce or prevent the second semiconductor layer SEL2 from being etched by the etch material used to etch the sacrificial layer SAL.

[0054] The gate electrode GE can be configured to extend in a first direction D1, while crossing a first channel pattern CH1 and a second channel pattern CH2. The gate electrode GE can be arranged in a second direction D2 with a first pitch. Each of the gate electrodes GE can be vertically stacked with the first channel pattern CH1 and the second channel pattern CH2. Here, the gate electrode GE vertically stacked with the first channel pattern CH1 can be referred to as the first gate electrode on the first channel pattern CH1.

[0055] The gate electrode GE may include a first part PO1 placed between the first semiconductor pattern SP1 and the active pattern AP1 or AP2, a second part PO2 placed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third part PO3 placed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and a fourth part PO4 on the third semiconductor pattern SP3.

[0056] Refer again Figure 5A In the PMOSFET region PR, the gate electrode GE can have different widths at its first part PO1, second part PO2, and third part PO3. For example, the maximum width of the third part PO3 in the second direction D2 can be greater than the maximum width of the second part PO2 in the second direction D2. The maximum width of the first part PO1 in the second direction D2 can be greater than the maximum width of the third part PO3 in the second direction D2.

[0057] Return to reference Figure 5D and Figure 5EThe gate electrode GE may be disposed on at least one of the top surface TS, bottom surface BS, and sidewalls SW1 and SW2 of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. In this sense, the transistor according to some example embodiments may be a three-dimensional field-effect transistor (e.g., MBCFET or GAAFET) in which the gate electrode GE three-dimensionally surrounds the first channel pattern CH1 and the second channel pattern CH2.

[0058] For example, the first single-height unit SHC1 may have a first boundary BD1 and a second boundary BD2 that are opposite to each other in the second direction D2. The first boundary BD1 and the second boundary BD2 may extend in the first direction D1. The first single-height unit SHC1 may have a third boundary BD3 and a fourth boundary BD4 that are opposite to each other in the first direction D1. The third boundary BD3 and the fourth boundary BD4 may extend in the second direction D2.

[0059] The gate dicing pattern CT can be located on the boundary of each of the first single-height cell SHC1 and the second single-height cell SHC2 in the second direction D2. For example, the gate dicing pattern CT can be located on the third boundary BD3 and the fourth boundary BD4 of the first single-height cell SHC1. The gate dicing pattern CT can be arranged along the third boundary BD3 at a first pitch. The gate dicing pattern CT can be arranged along the fourth boundary BD4 at a first pitch. When viewed in a plan view, the gate dicing pattern CT on the third boundary BD3 and the fourth boundary BD4 can be positioned to be stacked with the corresponding gate electrode GE. The gate dicing pattern CT can include a dielectric material, such as a silicon oxide layer, a silicon nitride layer, or a combination thereof.

[0060] The gate dicing pattern CT can separate the gate electrode GE on the first single-height cell SHC1 from the gate electrode GE on the second single-height cell SHC2. The gate dicing pattern CT can be positioned between the gate electrode GE on the first single-height cell SHC1 and the gate electrode GE on the second single-height cell SHC2, the gate electrodes GE being aligned with each other in a first direction D1. For example, the gate dicing pattern CT can divide a gate electrode GE extending in the first direction D1 into multiple gate electrodes GE.

[0061] Return to reference Figure 4 At least one of the gate cut patterns CT may not be placed on the boundary of the cell, but may be placed inside the cell. For example, the gate cut pattern CT may be located between the second PMOSFET region PR2 and the second NMOSFET region NR2 of the second single-height cell SHC2.

[0062] The gate cleaving pattern CT can be spaced apart from an adjacent region among regions PR1, PR2, NR1, and NR2 at various distances. For example, the first gate cleaving pattern CT1 can penetrate the second gate electrode GE2 and can be spaced apart from the adjacent first PMOSFET region PR1 at a first distance DI1. The second gate cleaving pattern CT2 can penetrate the second gate electrode GE2 and can be spaced apart from the adjacent first NMOSFET region NR1 at a second distance DI2. The first distance DI1 can be greater than the second distance DI2.

[0063] Return to reference Figure 4 and Figures 5A to 5E A pair of gate spacers GS may be located on opposite sidewalls of the fourth portion PO4 of the gate electrode GE. The gate spacers GS may extend along the gate electrode GE in a first direction D1. The top surface of the gate spacers GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacers GS may be coplanar with the top surface of the first interlayer dielectric layer 110, which will be discussed below. The gate spacers GS may comprise at least one selected from SiCN, SiCON, and SiN. Alternatively, the gate spacers GS may each comprise a multilayer formed from at least two selected from SiCN, SiCON, and SiN.

[0064] The gate overlay pattern GP can be disposed on the gate electrode GE and can be understood as being on the first gate dicing pattern CT1 and the second gate dicing pattern CT2. The gate overlay pattern GP can extend along the gate electrode GE in a first direction D1. The gate overlay pattern GP can include a material having etch selectivity relative to the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120, which will be discussed below. For example, the gate overlay pattern GP can include at least one selected from SiON, SiCN, SiCON, and SiN.

[0065] The gate dielectric layer GI can be disposed between the gate electrode GE and the first channel pattern CH1, and between the gate electrode GE and the second channel pattern CH2. The gate dielectric layer GI can cover the top surface TS, bottom surface BS, and opposing sidewalls SW1 and SW2 of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The gate dielectric layer GI can cover the top surface of the device isolation layer ST below the gate electrode GE. The gate dielectric layer GI can cover the sidewalls of the gate dicing pattern CT (see...). Figure 5D and Figure 5E ).

[0066] In some exemplary embodiments of the present invention, the gate dielectric layer GI may include one or more of a silicon oxide layer, a silicon oxynitride layer, and a high-k dielectric layer. The high-k dielectric layer may include a material whose dielectric constant is greater than that of the silicon oxide layer. For example, the high-k dielectric material may include at least one selected from hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0067] In some exemplary embodiments, the semiconductor device conceived according to the present invention may include a negative capacitance field-effect transistor using a negative capacitor. For example, the gate dielectric layer GI may include a ferroelectric material layer exhibiting ferroelectric properties and a paraelectric material layer exhibiting paraelectric properties.

[0068] Ferroelectric material layers can have negative capacitance, and paraelectric material layers can have positive capacitance. For example, when two or more capacitors are connected in series, and when each capacitor has positive capacitance, the total capacitance can be reduced to less than the capacitance of each individual capacitor. Conversely, when at least one of the two or more capacitors connected in series has negative capacitance, the total capacitance can have a positive value that is greater than the absolute value of the capacitance of each individual capacitor.

[0069] When a ferroelectric material layer with negative capacitance is connected in series with a paraelectric material layer with positive capacitance, there can be an increase in the total capacitance of the two connected ferroelectric and paraelectric material layers. This increase in total capacitance can be used to allow transistors including ferroelectric material layers to have a subthreshold swing of less than about 60 mV / decade at room temperature.

[0070] The ferroelectric material layer can possess ferroelectric properties. The ferroelectric material layer can include at least one selected from, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, and lead zirconium titanium oxide. For example, hafnium zirconium oxide can be a material in which hafnium oxide is doped with zirconium (Zr). As another example, hafnium zirconium oxide can be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0071] The ferroelectric material layer may also include impurities doped therein. For example, the impurities may include at least one selected from aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of impurities included in the ferroelectric material layer can vary depending on the ferroelectric material included in the ferroelectric material layer.

[0072] When the ferroelectric material layer includes hafnium oxide, the ferroelectric material layer may include at least one of the impurities such as gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al) and yttrium (Y).

[0073] When the impurity is aluminum (Al), the ferroelectric material layer may comprise approximately 3 atomic percent to approximately 8 atomic percent aluminum. In this specification, the impurity ratio may be the ratio of aluminum to the sum of hafnium and aluminum.

[0074] When the impurity is silicon (Si), the ferroelectric material layer may comprise about 2 atomic percent to about 10 atomic percent of silicon. When the impurity is yttrium (Y), the ferroelectric material layer may comprise about 2 atomic percent to about 10 atomic percent of yttrium. When the impurity is gadolinium (Gd), the ferroelectric material layer may comprise about 1 atomic percent to about 7 atomic percent of gadolinium. When the impurity is zirconium (Zr), the ferroelectric material layer may comprise about 50 atomic percent to about 80 atomic percent of zirconium.

[0075] The paraelectric material layer may have paraelectric properties. The paraelectric material layer may include, for example, at least one selected from silicon oxide and high-k metal oxides. The metal oxide included in the paraelectric material layer may include, for example, at least one selected from hafnium oxide, zirconium oxide, and aluminum oxide, but the inventive concept is not limited thereto.

[0076] The ferroelectric material layer and the paraelectric material layer may contain the same material. The ferroelectric material layer may have ferroelectric properties, but the paraelectric material layer may not. For example, when both the ferroelectric and paraelectric material layers contain hafnium oxide, the hafnium oxide contained in the ferroelectric material layer may have a different crystal structure than the hafnium oxide contained in the paraelectric material layer.

[0077] The ferroelectric material layer can have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material layer can range, for example, from about 0.5 nm to about 10 nm. Because ferroelectric materials have their own critical thickness for exhibiting ferroelectric properties, the thickness of the ferroelectric material layer can depend on the ferroelectric material itself.

[0078] For example, the gate dielectric layer GI may include a single ferroelectric material layer. As another example, the gate dielectric layer GI may include multiple ferroelectric layers spaced apart from each other. The gate dielectric layer GI may have a stacked structure in which multiple ferroelectric material layers and multiple paraelectric material layers are stacked alternately.

[0079] The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be disposed on the gate dielectric layer GI and may be adjacent to the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The first metal pattern may include a work function metal that controls the threshold voltage of the transistor. The thickness and composition of the first metal pattern can be adjusted to achieve the desired threshold voltage of the transistor. For example, the first portion PO1, the second portion PO2, and the third portion PO3 of the gate electrode GE may be formed from the first metal pattern or the work function metal.

[0080] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include nitrogen (N) and at least one metal selected from titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). Furthermore, the first metal pattern may also include carbon (C). The first metal pattern may include multiple stacked active power metal layers.

[0081] The second metal pattern may include a metal whose resistance is less than that of the first metal pattern. For example, the second metal pattern may include at least one metal selected from tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the fourth part PO4 of the gate electrode GE may include the first metal pattern and the second metal pattern on the first metal pattern.

[0082] Return to reference Figure 5B Internal spacers IP can be provided on the first NMOSFET region NR1 and the second NMOSFET region NR2. The internal spacers IP can be positioned accordingly between the second source / drain pattern SD2 and the first portion PO1, the second portion PO2, and the third portion PO3 of the gate electrode GE. The internal spacers IP can be in direct contact with the second source / drain pattern SD2. The internal spacers IP can separate the second source / drain pattern SD2 from each of the first portion PO1, the second portion PO2, and the third portion PO3 of the gate electrode GE.

[0083] A first interlayer dielectric layer 110 may be disposed on a substrate 100. The first interlayer dielectric layer 110 may cover a gate spacer GS and a first source / drain pattern SD1 and a second source / drain pattern SD2. The first interlayer dielectric layer 110 may have a top surface that is coplanar or substantially coplanar with the top surface of the gate cover pattern GP and the top surface of the gate spacer GS. A second interlayer dielectric layer 120 may be disposed on the first interlayer dielectric layer 110, which is on and covers the gate cover pattern GP. A third interlayer dielectric layer 130 may be disposed on the second interlayer dielectric layer 120. A fourth interlayer dielectric layer 140 may be disposed on the third interlayer dielectric layer 130. For example, the first interlayer dielectric layer 110 to the fourth interlayer dielectric layer 140 may include silicon oxide layers.

[0084] Each of the first single-height unit SHC1 and the second single-height unit SHC2 may have a pair of separation structures DB facing each other in a second direction D2 on its opposite sides. For example, the pair of separation structures DB may be respectively arranged on the first boundary BD1 and the second boundary BD2 of the first single-height unit SHC1. The separation structure DB may extend in the first direction D1 parallel to the gate electrode GE. The pitch between the separation structure DB and its adjacent gate electrode GE may be the same as the first pitch.

[0085] The separation structure DB can penetrate the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120, and can extend into the first active pattern AP1 and the second active pattern AP2. The separation structure DB can penetrate the upper portion of each of the first active pattern AP1 and the second active pattern AP2. The separation structure DB can electrically separate the active region of each of the first single-height cell SHC1 and the second single-height cell SHC2 from the active region of the other cell.

[0086] The active contact AC can be configured to penetrate the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120, and correspondingly have electrical connections to the first source / drain pattern SD1 and the second source / drain pattern SD2. A pair of active contacts AC can be disposed on opposite sides of the gate electrode GE. When viewed in a plan view, the active contact AC can have a strip shape extending in the first direction D1.

[0087] The active contact AC can be a self-aligned contact. For example, a gate cover pattern GP and a gate spacer GS can be used to form the active contact AC in a self-aligned manner. The active contact AC can cover at least a portion of the sidewall of, for example, the gate spacer GS. Although not shown, the active contact AC can cover a portion of the top surface of the gate cover pattern GP.

[0088] A silicide pattern SC may be correspondingly positioned between the active contact AC and the first source / drain pattern SD1, and between the active contact AC and the second source / drain pattern SD2. The active contact AC can be electrically connected to one of the first source / drain pattern SD1 and the second source / drain pattern SD2 via the silicide pattern SC. The silicide pattern SC may include a metal silicide, for example, at least one selected from titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0089] Return to reference Figure 5C At least one active contact AC on the first single-height unit SHC1 can electrically connect the first source / drain pattern SD1 of the first PMOSFET region PR1 to the second source / drain pattern SD2 of the first NMOSFET region NR1. The active contact AC can extend from the second source / drain pattern SD2 of the first NMOSFET region NR1 to the first source / drain pattern SD1 of the first PMOSFET region PR1 in a first direction D1. The active contact AC can include a first body BP1 on the first source / drain pattern SD1 and a second body BP2 on the second source / drain pattern SD2. The first body BP1 can be connected to the top surface of the first source / drain pattern SD1 via a silicide pattern SC, and the second body BP2 can be connected to the top surface of the second source / drain pattern SD2 via a silicide pattern SC. The active contact AC can also include a protrusion PRP disposed between the first body BP1 and the second body BP2. The protrusion PRP can be disposed on the device isolation layer ST between the first PMOSFET region PR1 and the first NMOSFET region NR1.

[0090] The protrusion PRP can extend from the first body BP1 toward the device isolation layer ST, while traveling along the inclined sidewall of the first source / drain pattern SD1. The protrusion PRP can extend from the second body BP2 toward the device isolation layer ST, while traveling along the inclined sidewall of the second source / drain pattern SD2. The protrusion PRP may have a bottom surface lower than the bottom surface of each of the first body BP1 and the second body BP2. The bottom surface of the protrusion PRP may be positioned higher than the device isolation layer ST. For example, the protrusion PRP may span the first interlayer dielectric layer 110 and be spaced apart from the device isolation layer ST.

[0091] According to some exemplary embodiments of the present invention, the active contact AC can be connected not only to the top surface of the first source / drain pattern SD1 via the first body BP1, but also to the inclined sidewall of the first source / drain pattern SD1 via the protrusion PRP. For example, the protrusion PRP can increase the contact area between the active contact AC and the first source / drain pattern SD1. Therefore, a reduction in resistance between the active contact AC and the first source / drain pattern SD1 is possible. Similarly, the protrusion PRP can cause a reduction in resistance between the active contact AC and the second source / drain pattern SD2. In summary, it is possible to improve the operating speed of the semiconductor device according to some exemplary embodiments of the present invention.

[0092] The gate contact GC can be configured to penetrate the second interlayer dielectric layer 120 and the gate overlay pattern GP, ​​and have an electrical connection to the corresponding gate electrode GE (e.g., electrically connected to the corresponding gate electrode GE and / or configured to be electrically connected to the corresponding gate electrode GE). When viewed in a plan view, the gate contact GC on the first single-height cell SHC1 can be positioned stacked with the first PMOSFET region PR1. For example, the gate contact GC on the first single-height cell SHC1 can be disposed on the first active pattern AP1 (see...). Figure 5A ).

[0093] On the gate electrode GE, the gate contact GC can be freely positioned without any location restrictions. For example, the gate contact GC on the second single-height cell SHC2 can be located in the filling of the second PMOSFET region PR2, the second NMOSFET region NR2, and the trench TR (see...). Figure 4 On the device isolation layer ST.

[0094] In some exemplary embodiments of the inventive concept, reference is made to... Figure 5A and Figure 5C The active contact AC may have an upper portion adjacent to the gate contact GC, and the upper portion of the active contact AC may be filled with an upper dielectric pattern UIP. The upper dielectric pattern UIP may have a bottom surface that is lower than the bottom surface of the gate contact GC. For example, the upper dielectric pattern UIP may cause the active contact AC adjacent to the gate contact GC to have a top surface that is lower than the bottom surface of the gate contact GC. Therefore, it is possible to reduce or prevent short circuits caused by contact between the gate contact GC and its adjacent active contact AC.

[0095] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may cover the sidewalls and bottom surface of the conductive pattern FM. The barrier pattern BM may include a combination of a metal layer and a metal nitride layer. The metal layer may include at least one selected from titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include at least one selected from titanium nitride (TiN) layer, tantalum nitride (TaN) layer, tungsten nitride (WN) layer, nickel nitride (NiN) layer, cobalt nitride (CoN) layer, and platinum nitride (PtN) layer.

[0096] The first metal layer M1 can be disposed in the third interlayer dielectric layer 130, and therefore disposed on the second interlayer dielectric layer 120. For example, the first metal layer M1 may include a first power line M1_R1, a second power line M1_R2, a third power line M1_R3, and a first wiring M1_I. The lines M1_R1, M1_R2, M1_R3, and M1_I of the first metal layer M1 can extend parallel to each other in the second direction D2. The first power line M1_R1 can be on the first gate dicing pattern CT1 (e.g., vertically stacked with the first gate dicing pattern CT1), the second power line M1_R2 can be on the second gate dicing pattern CT2, and the first wiring M1_I can be correspondingly electrically connected to the active contact AC and the gate contact GC (e.g., the separate first wiring M1_I can be electrically connected to either the active contact AC or the gate contact GC).

[0097] For example, the first power line M1_R1 and the second power line M1_R2 can be respectively disposed on the third boundary BD3 and the fourth boundary BD4 of the first single-height unit SHC1. The first power line M1_R1 can extend along the third boundary BD3 in the second direction D2. The second power line M1_R2 can extend along the fourth boundary BD4 in the second direction D2.

[0098] The first wiring M1_I of the first metal layer M1 can be arranged along the first direction D1 with a second pitch. The second pitch can be smaller than the first pitch. Each of the first wirings M1_I can have a smaller line width than each of the first power line M1_R1, the second power line M1_R2, and the third power line M1_R3.

[0099] The first metal layer M1 may further include a first via VI1. The first via VI1 may be disposed below lines M1_R1, M1_R2, M1_R3, and M1_I of the first metal layer M1. The first via VI1 can electrically connect the active contact AC to one of lines M1_R1, M1_R2, M1_R3, and M1_I of the first metal layer M1. The first via VI1 can electrically connect the gate contact GC to one of lines M1_R1, M1_R2, M1_R3, and M1_I of the first metal layer M1.

[0100] Specific lines in the first metal layer M1 and the first via VI1 beneath it can be formed by separate processes. For example, specific lines in the first metal layer M1 and the first via VI1 beneath it can both be formed by a single damascene process. Semiconductor devices according to some example embodiments can be manufactured using sub-20nm processes.

[0101] The second metal layer M2 can be disposed in the fourth interlayer dielectric layer 140, and therefore can be on the first metal layer M1. The second metal layer M2 can include a plurality of second wirings M2_I that can be electrically connected to the first metal layer M1. The second wirings M2_I of the second metal layer M2 can all have a linear or strip shape extending in the first direction D1. For example, the second wirings M2_I can extend parallel to each other in the first direction D1.

[0102] The second metal layer M2 may also include a second via VI2 correspondingly disposed below the second wiring M2_I. A specific line of the first metal layer M1 can be electrically connected to a corresponding line of the second metal layer M2 through the second via VI2. The specific line of the second metal layer M2 and the second via VI2 below it can be formed simultaneously by a dual damascene process.

[0103] The first metal layer M1 and the second metal layer M2 may have their lines comprise the same or different conductive materials. For example, the lines of the first metal layer M1 and the second metal layer M2 may comprise at least one metallic material selected from aluminum, copper, tungsten, molybdenum, and cobalt. Although not shown, other metal layers (e.g., M3, M4, M5, etc. (not shown)) may be additionally stacked on the fourth interlayer dielectric layer 140. Each of the stacked metal layers may include wiring for routing between cells.

[0104] Return to reference Figure 5D The following will describe in detail the first gate electrode GE1, the gate dicing patterns CT1 and CT2, and the residual patterns RPP1, RPP2, and RPP3 in the gate electrode GE. The first gate electrode GE1 may be on the first channel pattern CH1. The first gate electrode GE1 may be on both the first channel pattern CH1 and the second channel pattern CH2.

[0105] A first gate dicing pattern CT1 penetrating the first gate electrode GE1 can be disposed on a third boundary BD3 between the first PMOSFET region PR1 and the second PMOSFET region PR2. The first gate dicing pattern CT1 can be adjacent to the first channel pattern CH1 (e.g., in the first direction D1 and / or the second direction D2). A second gate dicing pattern CT2 penetrating the first gate electrode GE1 can be disposed on a fourth boundary BD4 adjacent to the first NMOSFET region NR1. The second gate dicing pattern CT2 can be adjacent to the second channel pattern CH2 (e.g., in the first direction D1 and / or the second direction D2).

[0106] A first residual pattern RPP1 may be positioned between a first gate dicing pattern CT1 and a first channel pattern CH1 on the second PMOSFET region PR2. A second residual pattern RPP2 may be positioned between the first gate dicing pattern CT1 and the first channel pattern CH1 on the first PMOSFET region PR1. A third residual pattern RPP3 may be positioned between a second gate dicing pattern CT2 and a second channel pattern CH2 on the first NMOSFET region NR1. For example, at least... Figure 5D As shown, the third residual pattern RPP3 can cover the outermost sidewall of at least one of the separated semiconductor patterns SP1 to SP3 of the second channel pattern CH2.

[0107] Each of the first residual patterns RPP1 to the third residual patterns RPP3 may include polysilicon, silicon oxide, or any combination thereof. In some example embodiments, at least one selected from the first residual patterns RPP1 to the third residual patterns RPP3 may be configured such that a region adjacent to one of the first channel pattern CH1 and the second channel pattern CH2 may include polysilicon, and a region adjacent to the gate cleavage pattern CT may include silicon oxide.

[0108] For example, each of the first semiconductor patterns SP1, SP2, and SP3 of the first channel pattern CH1 on the first PMOSFET region PR1 may include a top surface TS, a first sidewall SW1, a second sidewall SW2 opposite to the first sidewall SW1, and a bottom surface BS. The second sidewall SW2 may be the outermost sidewall of the semiconductor pattern. As shown, the second residual pattern RPP2 may cover the outermost sidewall SW2 of at least one (or all) of the semiconductor patterns SP1 to SP3 of the first channel pattern CH1. The gate electrode GE (e.g., the first gate electrode GE1) may cover the top surface TS, the first sidewall SW1, and the bottom surface BS (and thus may be on the top surface TS, the first sidewall SW1, and the bottom surface BS). The gate electrode GE may not cover the second sidewall SW2, thus exposing it. It will be understood that an element “covering” the surface of another element may directly contact the surface of the other element to shield that surface without exposing it.

[0109] The top surface TS, bottom surface BS, and first sidewall SW1 can be covered by the gate dielectric layer GI. The top surface TS, bottom surface BS, and first sidewall SW1 can face the gate electrode GE across the gate dielectric layer GI. The second sidewall SW2 can be uncovered by the gate dielectric layer GI. The second sidewall SW2 can be covered by the second residual pattern RPP2.

[0110] The second residual pattern RPP2 may have a third sidewall SW3 that is in direct contact with the second sidewall SW2 of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The second residual pattern RPP2 may have a fourth sidewall SW4 that is opposite to the third sidewall SW3 and in direct contact with the first gate dicing pattern CT1. The third sidewall SW3 of the second residual pattern RPP2 may have a portion that is not in contact with (e.g., not in direct contact with) any of the semiconductor patterns of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3, and this portion of the third sidewall SW3 may be covered by the gate dielectric layer GI.

[0111] The detailed descriptions of the first residual pattern RPP1 and the third residual pattern RPP3 may be the same as, substantially the same as, or similar to the detailed descriptions of the second residual pattern RPP2 discussed above.

[0112] The first gate electrode GE1 on the first single-height unit SHC1 may include a first extension EXP1, a second extension EXP2, and a main portion MIP between the first extension EXP1 and the second extension EXP2 on its upper portion (e.g., the upper portion of the first gate electrode GE1 relative to the distal portion of the first gate electrode GE1 relative to the substrate 100). The first extension EXP1 may be disposed on and vertically stacked with the second residual pattern RPP2 (e.g., stacked on a third direction D3). The first extension EXP1 may be adjacent to the first gate dicing pattern CT1 across the gate dielectric layer GI.

[0113] The second extension EXP2 can be disposed on the third residual pattern RPP3 and vertically stacked with the third residual pattern RPP3. The second extension EXP2 can cross the gate dielectric layer GI and be adjacent to the second gate dicing pattern CT2. Since the first gate electrode GE1 on the first single-height cell SHC1 includes the first extension EXP1 and the second extension EXP2, the first gate electrode GE1 can be shaped like a T.

[0114] The main portion MIP may be a portion covering the first channel pattern CH1 and the second channel pattern CH2 of the first gate electrode GE1. The main portion MIP may have a first length L1 in the first direction D1. The first length L1 may be less than a second length L2, where the second length L2 is the distance between the first gate dicing pattern CT1 and the second gate dicing pattern CT2. In some exemplary embodiments of the present invention, the second residual pattern RPP2 and the third residual pattern RPP3 may allow the main portion MIP of the first gate electrode GE1 to have a length (e.g., the first length L1) smaller than the maximum length of the first gate electrode GE1 (e.g., the second length L2).

[0115] As discussed above, according to some exemplary embodiments of the present invention, a relatively small first length L1 can be assigned to the gate electrode GE of the semiconductor device. Reducing the length of the gate electrode GE can reduce its volume. As a result, the parasitic capacitance between the gate electrode GE and its adjacent active contact AC can be reduced. Additionally, the parasitic capacitance between the gate electrode GE and its adjacent first source / drain pattern SD1 and second source / drain pattern SD2 can also be reduced. The reduction in parasitic capacitance can lead to an improvement in the operating speed and electrical characteristics of the semiconductor device.

[0116] According to some example embodiments, each of the first channel pattern CH1 and the second channel pattern CH2 can be formed from a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 (or an extremely thin nanosheet), thus allowing for a thin bulk structure. The semiconductor device according to some example embodiments can have fully depleted device properties. Figure 5D As shown, even when the first gate electrode GE1 according to some example embodiments does not cover the second sidewall SW2 of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3, punch-through will not occur between the source and the drain. Therefore, the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 can operate as normal transistor bodies.

[0117] Return to reference Figure 5E The second gate electrode GE2, gate dicing patterns CT1 and CT2, and residual patterns RPP1, RPP2 and RPP3 in the gate electrode GE will be described in detail below.

[0118] The first gate dicing pattern CT1, which penetrates the second gate electrode GE2, can be disposed on the third boundary BD3 between the first PMOSFET region PR1 and the second PMOSFET region PR2. The second gate dicing pattern CT2, which penetrates the second gate electrode GE2, can be disposed on the fourth boundary BD4 adjacent to the first NMOSFET region NR1.

[0119] A first residual pattern RPP1 may be placed between a first gate dicing pattern CT1 and a first channel pattern CH1 on a second PMOSFET region PR2. A third residual pattern RPP3 may be placed between a second gate dicing pattern CT2 and a second channel pattern CH2 on a first NMOSFET region NR1. According to some example embodiments, a second residual pattern RPP2 may be omitted between the first gate dicing pattern CT1 and the first channel pattern CH1 on the first PMOSFET region PR1. In this sense, a semiconductor device according to some example embodiments may be configured such that a residual pattern RPP may be inserted or omitted between the gate dicing pattern CT and one of the channel patterns CH1 and CH2.

[0120] Each of the first semiconductor patterns SP1, SP2, and SP3 of the first channel pattern CH1 on the first PMOSFET region PR1 may include a top surface TS, a first sidewall SW1, a second sidewall SW2 opposite to the first sidewall SW1, and a bottom surface BS. Since the second residual pattern RPP2 is omitted, the second gate electrode GE2 may cover all of the top surface TS, bottom surface BS, first sidewall SW1, and second sidewall SW2 of each of the first semiconductor patterns SP1, SP2, and SP3. Therefore, the second gate electrode GE2 may surround each of the plurality of semiconductor patterns SP1 to SP3 of the first channel pattern CH1. For example, the second gate electrode GE2 on the first PMOSFET region PR1 may have a gate-all-around structure where the second gate electrode GE2 completely surrounds the channel.

[0121] The first gate dicing pattern CT1 penetrating the second gate electrode GE2 may have a wider width than the first gate dicing pattern CT1 penetrating the first gate electrode GE1 (see...). Figure 5D The smaller width W2 of W1. When the distance (e.g., DI1) between the first gate dicing pattern CT1 and the first channel pattern CH1 on the first PMOSFET region PR1 increases due to the width of the first gate dicing pattern CT1, the second residual pattern RPP2 can be omitted.

[0122] For example, a first distance DI1 can be defined as the distance between a first gate diced pattern CT1 and its adjacent first channel pattern CH1 on a first PMOSFET region PR1. A second distance DI2 can be defined as the distance between a second gate diced pattern CT2 and a second channel pattern CH2 on a first NMOSFET region NR1. The first distance DI1 can be greater than the second distance DI2. Because the first distance DI1 has a relatively large value, no residual pattern RPP can be formed between the first gate diced pattern CT1 and the first channel pattern CH1 on the first PMOSFET region PR1. Because the second distance DI2 has a relatively small value, a third residual pattern RPP3 can be formed between the second gate diced pattern CT2 and the second channel pattern CH2 on the first NMOSFET region NR1.

[0123] According to the present invention, the spacing between the gate dicing pattern CT and the channel pattern CH1 or CH2 can be adjusted to control whether a residual pattern RPP is formed and also to control the size of the residual pattern RPP. In some exemplary embodiments of the present invention, the first distance DI1 and the second distance DI2 can be the same as or substantially the same as each other.

[0124] When the second gate electrode GE2 is completely covered as... Figure 5E When the second gate electrode GE2 is arranged in a ring gate structure around the channel pattern shown on the first PMOSFET region PR1, the channel control capacitance can be increased. However, the parasitic capacitance will increase due to the increase in the length and volume of the second gate electrode GE2.

[0125] Therefore, according to some exemplary embodiments of the present invention, in transistor regions where operating speed is more important than channel control capacity, residual pattern RPP can be provided to give the gate electrode GE a reduced length, and in transistor regions where channel control capacity is more important than operating speed, residual pattern RPP can be omitted to give the gate electrode GE a ring gate structure.

[0126] Reference Figure 6 The following will describe an example of the second residual pattern RPP2 in detail. The second residual pattern RPP2 may include a convex region PRT.

[0127] The protruding region PRT of the second residual pattern RPP2 can protrude from the third sidewall SW3 of the second residual pattern RPP2 toward the first part PO1, the second part PO2, and the third part PO3 of the first gate electrode GE1. For example, at least... Figure 6 As shown, the protruding region PRT can therefore be at least partially vertically superimposed on one or more of the semiconductor patterns SP1 to SP3 of the first channel pattern CH1 (e.g., superimposed on the third direction D3).

[0128] For example, the uppermost protruding region PRT can directly cover the first region RG1 of the bottom surface BS of the third semiconductor pattern SP3. The remaining second region RG2 of the bottom surface BS of the third semiconductor pattern SP3 can be covered by the gate dielectric layer GI.

[0129] The third semiconductor pattern SP3 may have a third width W3 in the first direction D1. The first region RG1 of the third semiconductor pattern SP3 may have a fourth width W4 in the first direction D1. The fourth width W4 may be the same as or substantially the same as the width of the uppermost protruding region PRT. The ratio of the fourth width W4 to the third width W3 (W4 / W3) may be in the range of about 0.05 to about 0.2. Figure 5D and Figure 5E As shown, the highlighted area PRT can be omitted.

[0130] Such as at least Figures 6 to 7 As shown, the top surface TOS of the second residual pattern RPP2 may have a concave profile. For example, the top surface TOS of the second residual pattern RPP2 may have a height (horizontal) that increases in the direction from the third semiconductor pattern SP3 toward the first gate dicing pattern CT1.

[0131] Figure 7 The demonstration is shown Figure 5D An enlarged view of an example of part M depicted in the image. (See reference...) Figure 7 The top surface TOS of the second residual pattern RPP2 can be lower than the bottom surface BS of the third semiconductor pattern SP3 (e.g., at a lower level or height), and therefore can be at a lower height than the uppermost semiconductor pattern of the first channel pattern CH1 (e.g., the third semiconductor pattern SP3). For example, the second residual pattern RPP2 may not cover the second sidewall SW2 of the third semiconductor pattern SP3. Figure 7 As shown, the second residual pattern RPP2 may cover the outermost sidewall (e.g., SW2) of at least one semiconductor pattern (e.g., SP1 and SP2) below the uppermost semiconductor pattern (e.g., SP3) of the first channel pattern CH1. As further shown, the first gate electrode GE1 may surround (e.g., completely surround in at least the first direction D1 and the third direction D3) the uppermost semiconductor pattern (e.g., SP3). The uppermost semiconductor pattern may be isolated from direct contact with the second residual pattern RPP2.

[0132] The first gate electrode GE1 may cover the entirety of the top surface TS, bottom surface BS, first sidewall SW1, and second sidewall SW2 of the third semiconductor pattern SP3. The first gate electrode GE1 may have a ring gate structure in which the first gate electrode GE1 completely surrounds the third semiconductor pattern SP3. However, the first gate electrode GE1 may not cover the second sidewall SW2 of the first semiconductor pattern SP1 and the second semiconductor pattern SP2.

[0133] According to some example embodiments, the top surface TOS of the second residual pattern RPP2 can be adjusted so that at least one of the semiconductor patterns SP1, SP2, and SP3 selected from the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 is configured to be completely surrounded by the first gate electrode GE1. Therefore, it is possible to increase the transistor's operating speed without significantly reducing the channel control capacity.

[0134] Figure 8 and Figure 9 It shows along Figure 4 The following is a cross-sectional view of a semiconductor device, taken along line E-E', illustrating some exemplary embodiments of the concept according to the present invention. Figures 8 to 9 In the description of the example embodiments shown, references to the above will be omitted. Figure 4 and Figures 5A to 5E The technical features discussed will be described in detail, and their differences will be discussed in detail.

[0135] Reference Figure 8The first residual pattern RPP1 can be placed between the first gate dicing pattern CT1 and the first channel pattern CH1 on the second PMOSFET region PR2. According to some example embodiments, the second residual pattern RPP2 can be placed between the first gate dicing pattern CT1 and the first channel pattern CH1 on the first PMOSFET region PR1. The second residual pattern RPP2 can be omitted between the first gate dicing pattern CT1 and the first channel pattern CH1 on the first PMOSFET region PR1, and the third residual pattern RPP3 can be omitted between the second gate dicing pattern CT2 and the second channel pattern CH2 on the first NMOSFET region NR1. For example, the second residual pattern RPP2 and the third residual pattern RPP3 can be omitted on the first single-height cell SHC1.

[0136] When the first single-height cell SHC1 has a cell property requiring channel control capacity greater than operating speed compared to the second single-height cell SHC2, the second residual pattern RPP2 and the third residual pattern RPP3 can be selectively omitted only on the first single-height cell SHC1. Therefore, the second gate electrode GE2 located on the first single-height cell SHC1 can have a ring gate structure in which the second gate electrode GE2 surrounds the semiconductor patterns SP1 to SP3 of the first channel pattern CH1.

[0137] Reference Figure 9 Each of the first gate dicing pattern CT1 and the second gate dicing pattern CT2 may have an increased width in the first direction D1. For example, the first gate dicing pattern CT1 may have a sidewall that is in direct contact with the sidewall of the first channel pattern CH1 on the second PMOSFET region PR2. The first gate dicing pattern CT1 may also have opposing sidewalls that are in direct contact with the sidewall of the first channel pattern CH1 on the first PMOSFET region PR1.

[0138] The first gate dicing pattern CT1 can be in direct contact with the second sidewall SW2 of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 included in the first channel pattern CH1. Since the first gate dicing pattern CT1 is in direct contact with the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3, the aforementioned residual patterns RPP1, RPP2, and RPP3 can be omitted.

[0139] According to some example embodiments, the gate dicing pattern CT can have an increased width, so that even in the absence of residual pattern RPP, the gate electrode GE may not cover the second sidewalls SW2 of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. Since the gate electrode GE does not cover the second sidewalls SW2 of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3, it is possible to reduce the parasitic capacitance caused by the gate electrode GE.

[0140] According to some example embodiments, a gate cleavage pattern CT with increased width can cause the above-mentioned... Figure 5D The first extension EXP1 and the second extension EXP2 discussed in the previous section are omitted. Therefore, it is possible to further reduce the parasitic capacitance caused by the gate electrode GE.

[0141] Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C and Figure 16D A cross-sectional view is shown illustrating a method of manufacturing a semiconductor device according to some exemplary embodiments of the present invention. In detail, Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A and Figure 16A It shows along Figure 4 A sectional view taken by line A-A'. Figure 12B , Figure 13B , Figure 14B , Figure 15B and Figure 16B It shows along Figure 4 The sectional view taken by line B-B'. Figure 12C , Figure 13C , Figure 14C , Figure 15C and Figure 16C It shows along Figure 4 A sectional view taken by line C-C'. Figure 10B , Figure 11B , Figure 12D , Figure 13D , Figure 14D , Figure 15D and Figure 16D It shows along Figure 4 A sectional view taken by line D-D'.

[0142] Reference Figure 10A and Figure 10B A substrate 100 may be provided, comprising a first PMOSFET region PR1 and a second PMOSFET region PR2, and a first NMOSFET region NR1 and a second NMOSFET region NR2. A sacrificial layer SAL and an active layer ACL may be alternately formed and stacked on the substrate 100. The sacrificial layer SAL may comprise one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and the active layer ACL may comprise another of silicon (Si), germanium (Ge), and silicon-germanium (SiGe).

[0143] For example, the sacrificial layer SAL may include silicon germanium (SiGe), and the active layer ACL may include silicon (Si). Each of the sacrificial layers in the SAL may have a germanium concentration of about 10 at% to about 30 at%.

[0144] Mask patterns can be formed accordingly on the first PMOSFET region PR1 and the second PMOSFET region PR2, as well as the first NMOSFET region NR1 and the second NMOSFET region NR2 on the substrate 100. The mask patterns can all have a linear or strip shape extending in the second direction D2.

[0145] A patterning process can be performed that uses a mask pattern as an etching mask to form a trench TR defining a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 can be formed on each of the first PMOSFET region PR1 and the second PMOSFET region PR2. The second active pattern AP2 can be formed on each of the first NMOSFET region NR1 and the second NMOSFET region NR2.

[0146] A stacked pattern STP can be formed on each of the first active pattern AP1 and the second active pattern AP2. The stacked pattern STP may include a sacrificial layer SAL and an active layer ACL that are stacked alternately on top of each other. During the patterning process, the stacked pattern STP can be formed together with the first active pattern AP1 and the second active pattern AP2.

[0147] A device isolation layer ST can be formed to fill the trench TR. For example, a dielectric layer can be formed on the entire surface of the substrate 100 to cover the stacked pattern STP and the first active pattern AP1 and the second active pattern AP2. The dielectric layer can be recessed until the stacked pattern STP is exposed, thereby forming the device isolation layer ST.

[0148] The device isolation layer ST may include a dielectric material, such as a silicon oxide layer. A stacked pattern STP may protrude upwards from the device isolation layer ST. For example, the stacked pattern STP may protrude vertically upwards from the device isolation layer ST.

[0149] Reference Figure 11A and Figure 11B Sacrificial patterns PP can be formed on the substrate 100 that travel (e.g., extend) across the stacked pattern STP. Each of the sacrificial patterns PP can be formed as a linear or strip shape extending in a first direction D1. The sacrificial patterns PP can be arranged along a second direction D2 at a specific pitch.

[0150] For example, the formation of the sacrificial pattern PP may include forming a sacrificial layer on the entire surface of the substrate 100, forming a hard mask pattern MP on the sacrificial layer, and using the hard mask pattern MP as an etch mask to pattern the sacrificial layer. The sacrificial layer may include a polysilicon layer.

[0151] A pair of gate spacers GS can be formed on opposite sidewalls of each of the sacrificial patterns PP. Formation of the gate spacers GS may include conformally forming a gate spacer layer over the entire surface of the substrate 100 and anisotropically etching the gate spacer layer. The gate spacer layer may include at least one selected from SiCN, SiCON, and SiN. Alternatively, the gate spacer layer may be a multilayer comprising at least two selected from SiCN, SiCON, and SiN.

[0152] Reference Figures 12A to 12D A first recess RS1 can be formed in a stacked pattern STP on a first active pattern AP1. A second recess RS2 can be formed in a stacked pattern STP on a second active pattern AP2. During the formation of the first recess RS1 and the second recess RS2, the device isolation layer ST can be further recessed on opposite sides of each of the first active pattern AP1 and the second active pattern AP2 (see...). Figure 12C ).

[0153] For example, a hard mask pattern MP and a gate spacer GS can be used as an etching mask, allowing a stacked pattern STP on a first active pattern AP1 to be etched to form a first recess RS1. The first recess RS1 can be formed between a pair of sacrificial patterns PP. A second recess RS2 in a stacked pattern STP on a second active pattern AP2 can be formed using the same method used to form the first recess RS1.

[0154] An active layer ACL can be used to form a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 sequentially stacked between adjacent first recesses RS1. An active layer ACL can also be used to form a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 sequentially stacked between adjacent second recesses RS2. A first channel pattern CH1 can be formed from the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 between adjacent first recesses RS1. A second channel pattern CH2 can be formed from the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 between adjacent second recesses RS2. Therefore, the first channel pattern CH1 and the second channel pattern CH2 can be formed from a stacked pattern STP.

[0155] Reference Figures 13A to 13D A first source / drain pattern SD1 can be formed in the corresponding first recess RS1. For example, a first selective epitaxial growth (SEG) process can be performed, using the inner wall of the first recess RS1 as a seed layer to form the first semiconductor layer SEL1. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 exposed to the first recess RS1, as well as the substrate 100, can be used as seeds for growing the semiconductor layer SEL1. For example, the first SEG process can include chemical vapor deposition (CVD) or molecular beam epitaxy (MBE).

[0156] The first semiconductor layer SEL1 may include a semiconductor element (e.g., SiGe) whose lattice constant is greater than that of the semiconductor element included in the substrate 100. The first semiconductor layer SEL1 may contain germanium (Ge) at a low concentration. In some exemplary embodiments of the present invention, the first semiconductor layer SEL1 may include only silicon (Si) and may not include germanium (Ge). The first semiconductor layer SEL1 may have a germanium concentration of about 0 at% to about 10 at%.

[0157] The first semiconductor layer SEL1 can undergo a second selective epitaxial growth (SEG) process to form a second semiconductor layer SEL2. The second semiconductor layer SEL2 can be formed to completely fill the first recess RS1. The second semiconductor layer SEL2 can contain germanium (Ge) at a relatively high concentration. For example, the second semiconductor layer SEL2 can have a germanium (Ge) concentration of about 30 at% to about 75 at%.

[0158] The first semiconductor layer SEL1 and the second semiconductor layer SEL2 can form a first source / drain pattern SD1. Impurities can be implanted in situ during the first and second SEG processes. Alternatively, impurities can be implanted into the first source / drain pattern SD1 after its formation. The first source / drain pattern SD1 can be doped to have a first conductivity type (e.g., p-type).

[0159] A second source / drain pattern SD2 can be formed in the corresponding second recess RS2. For example, a third selective epitaxial growth (SEG) process can be performed, using the inner wall of the second recess RS2 as a seed to form the second source / drain pattern SD2. The second source / drain pattern SD2 may include, for example, the same semiconductor element as the semiconductor element of the substrate 100 (e.g., Si). The second source / drain pattern SD2 may be doped to have a second conductivity type (e.g., n-type). An internal spacer IP can be formed accordingly between the second source / drain pattern SD2 and the sacrificial layer SAL.

[0160] Reference Figures 14A to 14D A first interlayer dielectric layer 110 can be formed on the sacrificial pattern PP to cover the first source / drain pattern SD1 and the second source / drain pattern SD2, the hard mask pattern MP, and the gate spacer GS. For example, the first interlayer dielectric layer 110 may include a silicon oxide layer.

[0161] The first interlayer dielectric layer 110 can be planarized until the top surface of the sacrificial pattern PP is exposed. The planarization of the first interlayer dielectric layer 110 can be achieved using etch-back or chemical mechanical polishing (CMP) processes. The hard mask pattern MP can be completely removed during the planarization process. As a result, the first interlayer dielectric layer 110 can have a top surface that is coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0162] Photolithography can be used to selectively open portions of the sacrificial pattern PP. For example, it is possible to selectively open portions of the sacrificial pattern PP on the third boundary BD3 and the fourth boundary BD4 of the first single-height cell SHC1. The opened portions of the sacrificial pattern PP can be selectively etched and removed. The space removed by the sacrificial pattern PP (e.g., at least a portion of the sacrificial pattern PP) can be filled with a dielectric material to form gate dicing patterns CT1 or CT2. Thus, gate dicing patterns CT1 and / or CT2 can be formed to penetrate at least a portion of the sacrificial pattern PP, and gate dicing patterns CT1 and / or CT2 can be formed based on the following steps: selectively opening portions of the sacrificial pattern PP using photolithography, selectively removing portions of the sacrificial pattern PP, and forming gate dicing patterns CT1 and / or CT2 based on providing dielectric material to the space removed by the sacrificial pattern PP.

[0163] Reference Figure 15A and Figure 15D The exposed sacrificial pattern PP can be selectively removed. Removal of the sacrificial pattern PP can create an external region ORG that exposes the first channel pattern CH1 and the second channel pattern CH2 (see...). Figure 15D Therefore, an etching process can be used to selectively etch the sacrificial pattern PP to form an external region ORG that exposes one or more of the stacked patterns STP (e.g., the first channel pattern CH1 and / or the second channel pattern CH2).

[0164] The removal of the sacrificial pattern PP and the etching process thereof may include performing a wet etching process using an etchant capable of selectively etching polysilicon. When a relatively small distance is provided between the gate diced pattern CT1 or CT2 and the channel pattern CH1 or CH2, it becomes difficult to introduce etchant between them. Therefore, the sacrificial pattern PP may remain between the gate diced pattern CT1 or CT2 and the channel pattern CH1 or CH2 without being removed. In this sense, the sacrificial pattern PP may have a much smaller etching rate at its portion adjacent to the gate diced pattern CT1 or CT2 than at its remainder. During the wet etching process, the etching rate relative to the portion of the sacrificial pattern PP remaining between the gate diced pattern CT1 or CT2 and the channel pattern CH1 or CH2 (e.g., a stacked pattern STP) (e.g., the portion adjacent to the gate diced pattern CT1 or CT2) may be less than the etching rate relative to the removed remainder of the sacrificial pattern PP (e.g., the portion away from the gate diced pattern CT1 or CT2). Therefore, residual patterns RPP1, RPP2, and RPP3 can be formed by the portions of the sacrificial pattern PP retained between the gate dicing patterns CT1 and CT2 and the channel patterns CH1 and CH2, while the remaining portions of the sacrificial pattern PP are removed. Thus, based on allowing one or more portions of the sacrificial pattern PP to remain between one or more gate dicing patterns CT1 and / or CT2 and the stacked pattern STP, residual patterns RPP1, RPP2, and / or RPP3 can be formed during the etching process, thereby forming the external region ORG.

[0165] For example, a first residual pattern RPP1 can be formed between the first gate dicing pattern CT1 and the first channel pattern CH1 on the second PMOSFET region PR2. A second residual pattern RPP2 can be formed between the first gate dicing pattern CT1 and the first channel pattern CH1 on the first PMOSFET region PR1. A third residual pattern RPP3 can be formed between the second gate dicing pattern CT2 and the second channel pattern CH2 on the first NMOSFET region NR1.

[0166] The sacrificial layer SAL of the stacked pattern STP exposed to the outer region ORG can be selectively removed to form the inner region IRG (see Figure 15DFor example, an etching process can be performed to selectively etch the sacrificial layer SAL of the stacked pattern STP exposed to the external region ORG, such that the sacrificial layer SAL can be removed and the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 can be retained. The etching process can have a high etching rate relative to silicon-germanium with a relatively high germanium concentration. For example, the etching process can have a high etching rate relative to silicon-germanium with a germanium concentration greater than about 10 at%.

[0167] During the etching process, the sacrificial layer SAL can be removed from the first PMOSFET region PR1 and the second PMOSFET region PR2, and from the first NMOSFET region NR1 and the second NMOSFET region NR2. The etching process can be a wet etching process. The etching material used in the etching process can rapidly etch the sacrificial layer SAL, which has a relatively high germanium concentration. During the etching process, the first source / drain pattern SD1 on the first PMOSFET region PR1 and the second PMOSFET region PR2 can be protected by the first semiconductor layer SEL1, which has a relatively low germanium concentration. Since the first residual pattern RPP1, the second residual pattern RPP2, and the third residual pattern RPP3 also consist only of polysilicon and do not include germanium, any one of the first residual pattern RPP1, the second residual pattern RPP2, and the third residual pattern RPP3 may not be removed during the etching process.

[0168] Return to reference Figure 15D With the selective removal of the sacrificial layer SAL, the stacked first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3 can remain on each of the first active pattern AP1 and the second active pattern AP2. The removal of the sacrificial layer SAL can form a first internal region IRG1, a second internal region IRG2, and a third internal region IRG3.

[0169] For example, a first internal region IRG1 can be formed between an active pattern AP1 or AP2 and a first semiconductor pattern SP1, a second internal region IRG2 can be formed between the first semiconductor pattern SP1 and a second semiconductor pattern SP2, and a third internal region IRG3 can be formed between the second semiconductor pattern SP2 and a third semiconductor pattern SP3.

[0170] The first residual pattern RPP1, the second residual pattern RPP2, and the third residual pattern RPP3 can all directly contact and support the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. Even if the first internal region IRG1, the second internal region IRG2, and the third internal region IRG3 are formed, the first residual pattern RPP1, the second residual pattern RPP2, and the third residual pattern RPP3 can keep the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 in their shape without collapsing.

[0171] Reference Figures 16A to 16D A gate dielectric layer GI can be conformally formed on the exposed first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3 (for example, the gate dielectric layer GI can be formed on the exposed surfaces of the first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3 and can cover the exposed surfaces of the first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3). A gate electrode GE can be formed on the gate dielectric layer GI.

[0172] The gate electrode GE may include a first portion PO1, a second portion PO2, and a third portion PO3 correspondingly formed in the first inner region IRG1, the second inner region IRG2, and the third inner region IRG3, and may also include a fourth portion PO4 formed in the outer region ORG. Therefore, the gate electrode GE may be configured to fill the first inner region IRG1, the second inner region IRG2, the third inner region IRG3, and the outer region ORG.

[0173] The gate electrode GE can be recessed to have a reduced height. When the gate electrode GE is recessed, the upper portions of the first gate dicing pattern CT1 and the second gate dicing pattern CT2 can also be slightly recessed. A gate overlay pattern GP can be formed on the recessed gate electrode GE.

[0174] Return to reference Figure 4 and Figures 5A to 5E A second interlayer dielectric layer 120 may be formed on the first interlayer dielectric layer 110. The second interlayer dielectric layer 120 may include a silicon oxide layer. An active contact AC may be formed to penetrate the second interlayer dielectric layer 120 and the first interlayer dielectric layer 110 and to have electrical connections to the first source / drain pattern SD1 and the second source / drain pattern SD2. A gate contact GC may be formed to penetrate the second interlayer dielectric layer 120 and the gate overlay pattern GP and to have electrical connections to the gate electrode GE.

[0175] A pair of separation structures DB can be formed on opposite sides of each of the first single-height cell SHC1 and the second single-height cell SHC2. The separation structures DB can extend from the second interlayer dielectric layer 120 through the gate electrode GE into the active pattern AP1 or AP2. The separation structures DB may include a dielectric material, such as a silicon oxide layer or a silicon nitride layer.

[0176] A third interlayer dielectric layer 130 may be formed on the active contact AC and the gate contact GC. A first metal layer M1 may be formed in the third interlayer dielectric layer 130. A fourth interlayer dielectric layer 140 may be formed on the third interlayer dielectric layer 130. A second metal layer M2 may be formed in the fourth interlayer dielectric layer 140.

[0177] Figure 17 A simplified plan view of a semiconductor chip illustrating some example embodiments of the concept according to the present invention is shown. Figure 18 The demonstration is shown Figure 17 A plan view of the SRAM cells in the memory region depicted in the image. Figure 19 It shows along Figure 18 The sectional view taken by line A-A'. In the following... Figures 17 to 19 In the description of the example embodiments shown, references to the above-mentioned references will be omitted. Figure 4 and 5A The technical features discussed up to 5E are described in detail, and their differences will be discussed in detail.

[0178] Reference Figure 17 and Figure 18 A semiconductor chip SCC, such as a system-on-a-chip (SOC), processor, or application processor (AP), may include a logic region (LGR) and a memory region (MER). The logic region (LGR) may include, as referenced above... Figure 4 and Figures 5A to 5E The logical units discussed. The memory region MER can include static random access memory (SRAM) cells, SRC.

[0179] Reference Figure 17 , Figure 18 and Figure 19 A 6T cell can be used as the SRAM cell SRC in the memory region MER of the semiconductor chip SCC. For example, Figure 18 The SRAM cell SRC may include a first pull-up transistor and a second pull-up transistor, a first pull-down transistor and a second pull-down transistor, as well as a first transmission gate transistor and a second transmission gate transistor.

[0180] An SRAM cell SRC may include a first active pattern AP1 and a second active pattern AP2. For example, an SRAM cell SRC may include two first active patterns AP1 and two second active patterns AP2.

[0181] A pair of gate electrodes GE can be configured to extend across the first active pattern AP1 and the second active pattern AP2. The gate dicing pattern CT can be configured to penetrate the corresponding gate electrode GE.

[0182] Reference Figure 19 The gate cleaving pattern CT can be disposed between the first active pattern AP1 and its adjacent second active pattern AP2. The gate cleaving pattern CT can also be disposed between the first channel pattern CH1 and the second channel pattern CH2. For example... Figure 19 As shown, the SRAM cell SRC may include a first channel pattern CH1 on a first active pattern AP1, wherein the first channel pattern CH1 includes a plurality of semiconductor patterns SP1 to SP3 stacked and spaced apart from each other. Figure 19 As shown, the SRAM cell SRC may include a second channel pattern CH2 on a second active pattern AP2, wherein the second channel pattern CH2 includes a plurality of separate semiconductor patterns SP1 to SP3 stacked and spaced apart from each other. As shown, the gate electrode GE may be on the first channel pattern CH1, and the gate cleaved pattern CT may be adjacent to the first channel pattern CH1 and may penetrate the gate electrode GE. As shown, the gate electrode GE may be on the second channel pattern CH2, and the gate cleaved pattern CT may be adjacent to the second channel pattern CH2 and may penetrate the gate electrode GE.

[0183] The residual pattern RPP can be placed between the gate diced pattern CT and the first channel pattern CH1, and between the gate diced pattern CT and the second channel pattern CH2. The residual pattern RPP can directly contact the sidewalls of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. For example... Figure 19 As shown, the residual pattern RPP may cover the outermost sidewall (e.g., SW2) of at least one of the semiconductor patterns SP1 to SP3 of the first channel pattern CH1 and / or the second channel pattern CH2, and the gate electrode GE may be on the top surface (e.g., TS), bottom surface (e.g., BS), and sidewall of at least one semiconductor pattern of the first channel pattern CH1 and / or the second channel pattern CH2, and the gate electrode GE is not on the outermost sidewall (e.g., SW2) of at least one semiconductor pattern of the first channel pattern CH1 and / or the second channel pattern CH2.

[0184] In some example embodiments, similar to Figures 6 to 7The top surface of the residual pattern RPP (e.g., TOS) may have a concave profile, and the top surface of the residual pattern RPP may have an increased height in the direction from the first channel pattern CH1 and / or the second channel pattern CH2 toward the gate dicing pattern CT.

[0185] In some example embodiments, similar to Figure 6 The first sidewall (e.g., SW3) of the residual pattern RPP may contact (e.g., directly contact) the outermost sidewall (e.g., SW2), and the second sidewall (e.g., SW4) of the residual pattern RPP may contact (e.g., directly contact) the gate cut pattern CT, wherein the second sidewall (e.g., SW4) is opposite to the first sidewall (e.g., SW3), and the residual pattern RPP may include at least one protruding region (e.g., PRT) that protrudes beyond the first sidewall (e.g., SW3) and toward the gate electrode GE, such that at least one protruding region overlaps with at least a portion of the first channel pattern CH1 and / or the second channel pattern CH2 on the third direction D3.

[0186] In some example embodiments, similar to Figure 7 The top surface (e.g., TOS) of the residual pattern RPP may be lower than the uppermost semiconductor pattern (e.g., SP3) of the plurality of semiconductor patterns SP1 to SP3 of the first channel pattern CH1 and / or the second channel pattern CH2, at least one semiconductor pattern (e.g., SP2) is below the uppermost semiconductor pattern (SP3), and the gate electrode GE surrounds the uppermost semiconductor pattern (e.g., SP3).

[0187] In some exemplary embodiments of the present invention, such as Figure 8 As shown, it can be seen from Figure 4 The residual pattern RPP is omitted from the logic cell or the first single-height cell SHC1. For example, the SRAM cell SRC that requires high-speed operation can be configured such that the residual pattern RPP is set to reduce the parasitic capacitance of the gate electrode GE, and the first single-height cell SHC1 that requires precise operation can be configured such that the residual pattern RPP is omitted so that the gate electrode GE has a ring gate structure.

[0188] In some exemplary embodiments of the present invention, not only the SRAM cell SRC but also Figure 4 The logical unit may include, for example Figure 5D The residual patterns RPP1-RPP3 are shown. Whether residual patterns RPP1-RPP3 are included may depend on the cell characteristics discussed above.

[0189] The semiconductor device conceived according to the present invention can be configured such that a residual pattern is provided between the channel pattern and the gate dicing pattern, and the gate electrode is reduced in length and volume. Therefore, the parasitic capacitance of the gate electrode can be reduced, thereby improving the operating speed and electrical characteristics of the semiconductor device.

[0190] For semiconductor devices according to some exemplary embodiments of the present invention, the gate electrode can have a ring gate structure by omitting residual patterns from regions where channel control capacity is required, and the parasitic capacitance of the gate electrode can be reduced by setting the residual patterns in regions where high-speed operation is required.

[0191] Although some exemplary embodiments of the inventive concept have been discussed with reference to the accompanying drawings, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept. Therefore, it will be understood that the above exemplary embodiments are illustrative in all respects and not limiting.

Claims

1. A semiconductor device, the semiconductor device comprising: The first active pattern is located on the substrate; A pair of first source / drain patterns located on a first active pattern and a first channel pattern located between the pair of first source / drain patterns, the first channel pattern comprising a plurality of semiconductor patterns stacked on top of each other and spaced apart. The first gate electrode is located on the first channel pattern; The first gate dicing pattern is adjacent to the first channel pattern and penetrates the first gate electrode; as well as The first residual pattern is located between the first gate dicing pattern and the first channel pattern. Wherein, the first residual pattern covers the outermost sidewall of at least one of the plurality of semiconductor patterns of the first channel pattern, and The first gate electrode includes a first extension located on the upper portion of the first gate electrode, and the first extension is vertically stacked with the first residual pattern.

2. The semiconductor device according to claim 1, wherein, At least one of the plurality of semiconductor patterns in the first channel pattern includes a top surface, a bottom surface, a first sidewall, and a second sidewall opposite to the first sidewall. The second sidewall constitutes the outermost sidewall of at least one of the plurality of semiconductor patterns in the first channel pattern, and The first gate electrode is located on the top surface, the bottom surface, and the first sidewall, but not on the second sidewall.

3. The semiconductor device according to claim 1, wherein, The first residual pattern includes polysilicon, silicon oxide, or any combination thereof.

4. The semiconductor device according to claim 1, wherein, The top surface of the first residual pattern has a concave profile, and The top surface of the first residual pattern has an increased height in the direction from the first channel pattern toward the first gate dicing pattern.

5. The semiconductor device according to claim 1, wherein, The first sidewall of the first residual pattern is in direct contact with the outermost sidewall of at least one of the plurality of semiconductor patterns of the first channel pattern. The second sidewall of the first residual pattern is in direct contact with the first gate dicing pattern, and the second sidewall is opposite to the first sidewall. The first residual pattern includes at least one protruding region that extends beyond the first sidewall and faces the first gate electrode.

6. The semiconductor device according to claim 1, wherein, The top surface of the first residual pattern is lower than the uppermost semiconductor pattern among the plurality of semiconductor patterns of the first channel pattern. The at least one semiconductor pattern is located below the uppermost semiconductor pattern among the plurality of semiconductor patterns of the first channel pattern, and The first gate electrode surrounds the uppermost semiconductor pattern among the plurality of semiconductor patterns of the first channel pattern.

7. The semiconductor device according to claim 1, further comprising: The second active pattern is located on the substrate; A pair of second source / drain patterns located on a second active pattern and a second channel pattern located between the pair of second source / drain patterns, the second channel pattern comprising a plurality of separate semiconductor patterns stacked and spaced apart from each other, wherein a first gate electrode is located on both the first channel pattern and the second channel pattern; A second gate dicing pattern is adjacent to a second channel pattern and penetrates the first gate electrode; and The second residual pattern is located between the second gate dicing pattern and the second channel pattern. Wherein, the second residual pattern covers the outermost sidewall of at least one of the separated semiconductor patterns of the second channel pattern, and The first gate electrode further includes a second extension located on the upper portion of the first gate electrode, and the second extension is vertically stacked with the second residual pattern.

8. The semiconductor device according to claim 1, further comprising: The second active pattern is located on the substrate; A pair of second source / drain patterns located on a second active pattern and a second channel pattern located between the pair of second source / drain patterns, the second channel pattern comprising a plurality of separate semiconductor patterns stacked and spaced apart from each other, wherein a first gate electrode is located on both the first channel pattern and the second channel pattern; and The second gate dicing pattern is adjacent to the second channel pattern and penetrates the first gate electrode. The first gate electrode surrounds each of the multiple separate semiconductor patterns of the second channel pattern.

9. The semiconductor device according to claim 1, further comprising: The second active pattern is located on the substrate; A pair of second source / drain patterns located on a second active pattern and a second channel pattern located between the pair of second source / drain patterns, the second channel pattern comprising a plurality of separate semiconductor patterns stacked on top of each other and spaced apart; The second gate electrode is located on the second channel pattern; as well as The second gate dicing pattern is adjacent to the second channel pattern and penetrates the second gate electrode. The second gate electrode surrounds each of the plurality of separate semiconductor patterns of the second channel pattern.

10. The semiconductor device according to claim 9, wherein, The first active pattern is located in a static random access memory cell, and The second active pattern is located in the logic unit.

11. A semiconductor device, the semiconductor device comprising: Logical region, including logical units; as well as The memory region includes static random access memory cells. The logic unit includes: a first active pattern; a first channel pattern located on the first active pattern, the first channel pattern including a plurality of semiconductor patterns stacked and spaced apart from each other; a first gate electrode located on the first channel pattern; and a first gate dicing pattern adjacent to the first channel pattern and penetrating the first gate electrode. The static random access memory (SRAM) cell includes: a second active pattern; a second channel pattern located on the second active pattern, the second channel pattern comprising a plurality of separate semiconductor patterns stacked and spaced apart from each other; a second gate electrode located on the second channel pattern; a second gate dicing pattern adjacent to the second channel pattern and penetrating the second gate electrode; and a residual pattern located between the second gate dicing pattern and the second channel pattern. The first gate electrode has a ring gate structure in which the first gate electrode surrounds the plurality of semiconductor patterns of the first channel pattern. The residual pattern covers the outermost sidewall of at least one of the separated semiconductor patterns of the second channel pattern, and The second gate electrode is located on the top surface, bottom surface, and sidewall of at least one of the separated semiconductor patterns of the second channel pattern, but not on the outermost sidewall.

12. The semiconductor device according to claim 11, wherein, Residual patterns include polysilicon, silicon oxide, or any combination thereof.

13. The semiconductor device according to claim 11, wherein, The top surface of the residual pattern has a concave profile, and The top surface of the residual pattern has an increased height in the direction from the second channel pattern toward the second gate dicing pattern.

14. The semiconductor device according to claim 11, wherein, The first sidewall of the residual pattern is in direct contact with the outermost sidewall. The second sidewall of the residual pattern is in direct contact with the second gate dicing pattern, and the second sidewall is opposite to the first sidewall. The residual pattern includes at least one protruding area that extends beyond the first sidewall and toward the second gate electrode.

15. The semiconductor device according to claim 11, wherein, The top surface of the residual pattern is lower than the uppermost semiconductor pattern among the separated plurality of semiconductor patterns of the second channel pattern. At least one of the separated semiconductor patterns of the second channel pattern is located below the uppermost semiconductor pattern, and The second gate electrode surrounds the uppermost semiconductor pattern.

16. A semiconductor device, the semiconductor device comprising: The first active pattern and the second active pattern are located on the substrate; A pair of first source / drain patterns located on a first active pattern and a first channel pattern located between the pair of first source / drain patterns; A pair of second source / drain patterns located on a second active pattern and a second channel pattern located between the pair of second source / drain patterns, the first channel pattern comprising a plurality of semiconductor patterns stacked and spaced apart from each other, and the second channel pattern comprising a plurality of separate semiconductor patterns stacked and spaced apart from each other. The gate electrode is located on the first channel pattern and the second channel pattern; A gate dielectric layer is located between the gate electrode and the first channel pattern and the second channel pattern; A gate spacer is located on at least one sidewall of the gate electrode; The first gate dicing pattern is adjacent to the first channel pattern and penetrates the gate electrode; The second gate dicing pattern is adjacent to the second channel pattern and penetrates the gate electrode; The first residual pattern is located between the first gate dicing pattern and the first channel pattern; A gate overlay pattern is located on the gate electrode and the first gate dicing pattern and the second gate dicing pattern; Interlayer dielectric layer, located on the gate cover pattern; An active contact that penetrates the interlayer dielectric layer and has an electrical connection to at least one of the pair of first source / drain patterns and / or the pair of second source / drain patterns; A gate contact that penetrates the interlayer dielectric layer and the gate overlay pattern and has an electrical connection to the gate electrode; A first metal layer, located on an interlayer dielectric layer, includes: a first power line located on a first gate dicing pattern; a second power line located on a second gate dicing pattern; and a plurality of first wirings located between the first power line and the second power line, the first wirings being correspondingly electrically connected to active contacts and gate contacts; and The second metal layer is located on top of the first metal layer. The second metal layer includes multiple second wirings electrically connected to the first metal layer. Wherein, the first residual pattern covers the first outermost sidewall of at least one of the plurality of semiconductor patterns of the first channel pattern, and The top surface of the first residual pattern has an increased height in the direction from the first channel pattern toward the first gate dicing pattern.

17. The semiconductor device of claim 16, further comprising: The second residual pattern is located between the second gate dicing pattern and the second channel pattern. The second residual pattern covers the second outermost sidewall of at least one of the separated semiconductor patterns of the second channel pattern.

18. The semiconductor device according to claim 16, wherein, The gate electrode surrounds the separated plurality of semiconductor patterns of the second channel pattern.

19. The semiconductor device according to claim 16, wherein, The first sidewall of the first residual pattern is in direct contact with the first outermost sidewall of at least one of the plurality of semiconductor patterns of the first channel pattern. The second sidewall of the first residual pattern is in direct contact with the first gate dicing pattern, and the second sidewall is opposite to the first sidewall. The first residual pattern includes at least one protruding region that extends beyond the first sidewall and faces the gate electrode.

20. The semiconductor device of claim 16, wherein, The top surface of the first residual pattern is lower than the uppermost semiconductor pattern among the plurality of semiconductor patterns of the first channel pattern. At least one semiconductor pattern in the plurality of semiconductor patterns of the first channel pattern is located below the uppermost semiconductor pattern in the plurality of semiconductor patterns of the first channel pattern, and The gate electrode surrounds the uppermost semiconductor pattern among the plurality of semiconductor patterns of the first channel pattern.

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