Semiconductor memory device and method of manufacturing the same

Abstract

The present application relates to a semiconductor memory device and a manufacturing method thereof. A semiconductor memory device and a method of manufacturing the same can be provided. The semiconductor memory device includes a substrate having a complementary metal-oxide semiconductor (CMOS) circuit, a gate stack having interlayer insulating layers and conductive patterns alternately stacked in a vertical direction on the substrate, a plurality of channel structures passing through the gate stack, each channel structure having a first end portion protruding above the gate stack, and a plurality of conductive layers disposed above the gate stack. Each of the plurality of conductive layers is in contact with the first end portion of at least one of the channel structures.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to electronic devices, and more specifically, to semiconductor memory devices with vertical channel structures and methods of manufacturing such semiconductor memory devices. Background Technology

[0002] Recently, the paradigm of the computing environment has shifted to ubiquitous computing, enabling the use of computer systems anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased rapidly. Typically, such portable electronic devices use memory systems employing semiconductor memory devices—in other words, data storage devices. These data storage devices serve as either the main memory or auxiliary memory devices in portable electronic devices.

[0003] The advantages of using semiconductor memory devices for data storage include: the absence of mechanical drivers, resulting in excellent stability and durability, increased information access speed, and reduced power consumption. Examples of data storage devices proposed as memory systems with these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces, and solid-state drives (SSDs).

[0004] Semiconductor memory devices are classified into volatile memory devices and non-volatile memory devices.

[0005] Although their read and write speeds are relatively low, non-volatile memory devices retain stored data even during power outages. Therefore, they are used when data that should be retained regardless of power supply is required. Representative examples of non-volatile memory devices include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Flash memory is classified into NOR and NAND types. Summary of the Invention

[0006] Embodiments of this disclosure may provide a semiconductor memory device comprising: a substrate having a complementary metal-oxide-semiconductor (CMOS) circuit; a gate stack having interlayer insulating layers and conductive patterns alternately stacked on the substrate in a vertical direction; a plurality of channel structures passing through the gate stack, each channel structure having a first end protruding above the gate stack; and a plurality of conductive layers disposed above the gate stack. Each of the plurality of conductive layers contacts a first end of at least one of the plurality of channel structures.

[0007] Embodiments of this disclosure may provide a semiconductor memory device comprising: a bit line; a plurality of cell strings connected at a first end to the bit line; and a discharge cell connected between a source line and a second end of the plurality of cell strings. The plurality of cell strings may include at least one drain selection transistor and a plurality of memory cells connected in series between the bit line and the discharge cell, and the outermost memory cell among the memory cells may be electrically connected to the discharge cell.

[0008] Embodiments of this disclosure may provide a method for manufacturing a semiconductor memory device, the method comprising the steps of: forming a memory cell array on a first substrate, the memory cell array comprising: a gate stack having interlayer insulating layers and conductive patterns alternately stacked in a vertical direction; a plurality of channel structures extending through the gate stack and extending at their ends into the first substrate; and a memory layer extending from between the plurality of channel structures and the gate stack to between the first substrate and the ends of the plurality of channel structures; forming bit lines connected to the memory cell array; removing the first substrate to expose the memory layer; removing a portion of the memory layer to expose the ends of the plurality of channel structures; and forming a plurality of conductive layers over the gate stack that contact the ends of at least one of the plurality of channel structures. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figure 2 This is an example of an embodiment according to the present disclosure. Figure 1 A diagram of a memory cell array.

[0011] Figure 3 This is an example Figure 2 A circuit diagram of any one of the multiple memory blocks.

[0012] Figure 4 This is an example Figure 1 A cross-sectional view of the memory cell array.

[0013] Figures 5A to 5F, Figure 6 , Figure 7 , Figures 8A to 8D as well as Figure 9A and Figure 9B These are cross-sectional and plan views illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0014] Figure 10 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0015] Figure 11 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0016] The specific structural or functional descriptions of the embodiments of this disclosure described in this specification or application are for the purpose of describing embodiments of this disclosure only. These descriptions should not be construed as limiting the embodiments described in this specification or application.

[0017] In the following description, various embodiments of the present disclosure will be described more fully with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown, enabling those skilled in the art to readily implement the technical ideas of the present disclosure.

[0018] Various embodiments of this disclosure relate to a semiconductor memory device capable of connecting each of a plurality of cell strings included in a memory block to a source line via a discharge transistor, and a method of manufacturing the semiconductor memory device.

[0019] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0020] Reference Figure 1 The semiconductor memory device 10 may include peripheral circuitry PC and memory cell array 20.

[0021] The peripheral circuit PC can be configured to control programming operations for storing data in the memory cell array 20, reading operations for outputting data stored in the memory cell array 20, or erasing operations for erasing data stored in the memory cell array 20.

[0022] In an implementation, the peripheral circuit PC may include a voltage generator 31, a line decoder 33, control logic 35, and a page buffer group 37.

[0023] The memory cell array 20 may include multiple memory blocks. The memory cell array 20 can be connected to the row decoder 33 via word line WL and to the page buffer group 37 via bit line BL.

[0024] Control circuit 35 can control peripheral circuit PC in response to command CMD and address ADD.

[0025] The voltage generator 31 can generate various operating voltages such as pre-erase voltage, erase voltage, ground voltage, programming voltage, verification voltage, pass voltage, and read voltage based on the control circuit 35.

[0026] The row decoder 33 can select a memory block based on the control circuit 35. The row decoder 33 can be configured to apply an operating voltage to the word line WL connected to the selected memory block.

[0027] Page buffer group 37 can be connected to memory cell array 20 via bit line BL. Page buffer group 37 can temporarily store data received from input / output circuitry (not shown) during programming operations based on control circuitry 35. Page buffer group 37 can sense the voltage or current of bit line BL during read or verification operations based on control circuitry 35. Page buffer group 37 can select bit line BL based on control circuitry 35.

[0028] Structurally, the memory cell array 20 can overlap with a portion of the peripheral circuit PC.

[0029] Figure 2 This is an example of an embodiment according to the present disclosure. Figure 1 A diagram of a memory cell array.

[0030] Reference Figure 2 The memory cell array 20 may include multiple memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block may include multiple memory cells stacked on a substrate. The multiple memory cells may be arranged in the +X, +Y, and +Z directions. (Refer to...) Figure 3 and Figure 4 Describe the structure of each storage block in more detail.

[0031] Figure 3 This is an example Figure 2 A circuit diagram of any one of the multiple memory blocks.

[0032] Reference Figure 3 The storage block BLK1 may include multiple cell strings CS1 and CS2 connected to multiple bit lines BL, and a discharge unit DCU connected between the source line and the multiple cell strings CS1 and CS2.

[0033] Multiple cell strings CS1 and CS2 can be jointly connected to multiple word lines WL1 to WLn. Each of the multiple cell strings CS1 and CS2 can be connected to the source line SL through the discharge unit DCU. For example, the first cell string CS1, which is connected to multiple bit lines BL, can be connected to the source line SL through the first transistor DT1 of the discharge unit DCU. The second cell string CS2, which is connected to multiple bit lines BL, can be connected to the source line SL through the second transistor DT2 of the discharge unit DCU.

[0034] Each of the cell strings CS1 and CS2 may include at least one drain selection transistor DST connected to bit line BL, and a plurality of memory cells MC1 to MCn connected in series between the drain selection transistor DST and the first transistor DT1 or the second transistor DT2 of the discharge cell DCU. In other words, the memory cell MC1 located on the outermost part of the memory cells MC1 to MCn may be connected to the first transistor DT1 or the second transistor DT2 via serial line STL.

[0035] The gates of memory cells MC1 to MCn can be connected to multiple word lines WL1 to WLn spaced apart from each other, and can be stacked. The multiple word lines WL1 to WLn can be positioned between two or more drain select lines DSL1 and DSL2. The two or more drain select lines DSL1 and DSL2 can be spaced apart from each other at the same height.

[0036] Multiple unit strings CS1 and CS2 can be divided into string groups that are respectively connected to two or more drain select lines DSL1 and DSL2. Unit strings connected to the same bit line can be independently controlled by different drain select lines. Furthermore, unit strings connected to the same drain select line can be independently controlled by different bit lines.

[0037] The discharge unit DCU may include multiple transistors DT1 and DT2, and each of transistors DT1 and DT2 may electrically connect or disconnect multiple cell strings CS1 and CS2 from the source line SL in response to any of the multiple discharge signals DIS1 and DIS2.

[0038] For example, transistor DT1 can be connected between memory cell MC1 and source line SL in each cell string CS1, and can electrically connect or disconnect the channel of memory cell MC1 from the source line SL in response to discharge signal DIS1. Similarly, transistor DT2 can be connected between memory cell MC1 and source line SL in each cell string CS2, and can electrically connect or disconnect the channel of memory cell MC1 from the source line SL in response to discharge signal DIS2.

[0039] In the above embodiments, a transistor has been illustrated and described as being connected to each string group. However, a single unit string can be connected to the source line SL via a single transistor. In other words, each of the multiple unit strings CS1 and CS2 can be individually connected to or disconnected from the source line SL via a corresponding transistor.

[0040] In the above embodiment, the line connecting the multiple cell strings CS1 and CS2 to the multiple transistors DT1 and DT2 can be defined as a serial line STL. That is, the channels of cell strings CS1 and CS2 can be connected to transistors DT1 and DT2 via a serial line STL.

[0041] Figure 4 This is an example Figure 1 A cross-sectional view of the memory cell array.

[0042] Reference Figure 4 The memory cell array can be configured such that the lower structure U and the upper structure T are bonded to each other, and the serial line structure STL_S can be positioned above the upper structure T.

[0043] The upper structure T may include a gate stack GST separated from each other by a slit SI, a channel structure CH passing through the gate stack GST, a memory layer ML extending along the sidewall of each channel structure CH, a bit line 41 disposed below the gate stack GST, and a first connection structure C1.

[0044] The gate stack (GST) may include interlayer insulating layers (ILDs) and conductive patterns CP1 to CPn alternately stacked in a vertical direction. Each of the conductive patterns CP1 to CPn may include various conductive materials such as doped silicon layers, metal layers, metal silicide layers, and barrier layers, and may include two or more types of conductive materials. For example, each of the conductive patterns CP1 to CPn may include tungsten and a titanium nitride (TiN) layer surrounding the surface of the tungsten. Tungsten is a low-resistance metal and can reduce the resistance of the conductive patterns CP1 to CPn. The titanium nitride (TiN) layer is a barrier layer and can prevent direct contact between the tungsten and the interlayer insulating layer (ILD).

[0045] Among the conductive patterns CP1 to CPn, the first conductive pattern CP1 adjacent to bit line 41 can be used as the drain select line DSL. In an embodiment, two or more layers of conductive patterns adjacent to and continuously stacked with bit line 41 can be used as drain select lines. Conductive patterns (e.g., CP2 to CPn) that are vertically adjacent to each other and disposed above the drain select lines can be used as references above. Figure 3 The word lines described are WL1 to WLn.

[0046] The channel structure CH can pass vertically through the gate stack GST, and the first end of the channel structure CH can be formed to protrude from the gate stack GST. The channel structure CH can be formed as a hollow type. The channel structure CH may include a core insulating layer 11 filling the central region, a doped semiconductor layer 13 located at the lower end of the core insulating layer 11, and a channel layer 15 surrounding the surfaces of the core insulating layer 11 and the doped semiconductor layer 13. The channel layer 15 can be used as the channel region of the corresponding cell string. The channel layer 15 can be formed of a semiconductor material. In an embodiment, the channel layer 15 may include a silicon layer.

[0047] According to the above structure, a memory cell can be defined at the intersection of the channel structure CH and the conductive pattern used as a word line (e.g., CP2 to CPn), and a drain selection transistor can be defined at the intersection of the channel structure CH and the conductive pattern used as a drain select line (e.g., CP1). The memory cell can be connected in series with the drain selection transistor via the channel structure CH to form the above-mentioned reference. Figure 3 The described unit strings are CS1 and CS2.

[0048] The memory layer ML can be formed as a surface surrounding the channel structure CH. The memory layer ML may include a barrier insulating layer BI surrounding the channel layer 15 of the channel structure CH, a data storage layer DS surrounding the barrier insulating layer BI, and a tunnel insulating layer TI surrounding the data storage layer DS. The memory layer ML may be shorter than the channel structure CH in the vertical direction.

[0049] Bit line 41 can be disposed below the gate stack GST. Bit line 41 can be connected to the channel structure CH via contact plugs 27 that pass through multiple insulating layers 21, 25 and 27. Bit line 41 can be spaced apart from the substrate SUB via a first insulating structure 51 and a second insulating structure 81.

[0050] The first connection structure 1st_CS may include a first insulating structure 51 and a first connection structure C1 formed in the first insulating structure 51. The first connection structure C1 may include various conductive patterns 63, 65 and 67. The first insulating structure 51 may include two or more insulating layers 51A to 51D stacked between the bit line 41 and the second insulating structure 81.

[0051] The lower structure U may include a CMOS circuit structure CMOS with multiple transistors TR formed on the substrate SUB, and a second connection structure 2nd_CS formed on the CMOS circuit structure CMOS.

[0052] The second connection structure 2nd_CS may include a second insulating structure 81 formed on the substrate SUB and a second connection structure C2 formed in the second insulating structure 81. Each second connection structure C2 may include various conductive patterns 83, 85, 87, 89 and 91 embedded in the second insulating structure 81. The second insulating structure 81 may include two or more insulating layers 81A to 81D stacked sequentially.

[0053] The upper structure T and the lower structure U can be joined together by a bonding process to form a combined structure. For example, the exposed conductive pattern 67 of the first connecting structure 1nd_CS of the upper structure T and the exposed conductive pattern 91 of the second connecting structure 2nd_CS of the lower structure U can be arranged to face each other and can be joined together. The conductive pattern 67 and the conductive pattern 91 can be defined as bonding metals.

[0054] The serial line structure STL_S can be disposed on the upper structure T. The serial line structure STL_S may include multiple conductive layers 93 disposed above the gate stack GST and in contact with the channel structure CH protruding from the gate stack GST, multiple upper lines 99 disposed above the multiple conductive layers 93, and contact plugs CT respectively connecting the multiple conductive layers 93 and the multiple upper lines 99. The multiple conductive layers 93 may be at least two or more conductive layers.

[0055] The conductive layer 93 can be electrically connected to at least one channel structure CH. At least one channel structure CH commonly connected to a conductive layer 93 can be commonly connected to a serial line STL, such as... Figure 3 As shown.

[0056] The contact plug CT may include a contact conductive layer 95 and a diffusion barrier 97 surrounding the sidewalls of the contact conductive layer. Each contact plug CT may be electrically connected to a conductive layer 93 and an upper line 99.

[0057] Multiple top lines 99 can be arranged parallel to each other on the same layer, and each top line 99 can be connected to... Figure 3 The discharge unit DCU contains transistors DT1 and DT2.

[0058] As described above, the memory cell array according to embodiments of the present disclosure can be configured such that the gate stack GST does not include a source select line, and multiple channel structures CH corresponding to the cell string are connected to a string line disposed above the gate stack GST to connect to transistors DT1 and DT2 of the discharge cell DCU.

[0059] Figures 5A to 5F , Figure 6 , Figure 7 , Figures 8A to 8D as well as Figure 9A and Figure 9B These are cross-sectional and plan views illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0060] Figures 5A to 5F This is a cross-sectional view illustrating the steps of forming a memory cell array, a first linear array, and a first interconnection structure on a first substrate.

[0061] Reference Figure 5A The first material layer 111 and the second material layer 113 can be alternately stacked on the first substrate 101.

[0062] The first substrate 101 may be formed of a material with an etching rate different from that of the first material layer 111 and the second material layer 113. For example, the substrate 101 may include silicon.

[0063] In an embodiment, the first material layer 111 may be used as a reference above. Figure 4 The insulating material of the interlayer insulating layer (ILD) described herein. The second material layer 113 may be a material with an etch rate different from that of the first material layer 111. For example, the first material layer 111 may comprise silicon oxide, and the second material layer 113 may comprise silicon nitride. The following figures illustrate an embodiment in which the first material layer 111 is formed of an insulating material and the second material layer 113 is formed of a sacrificial layer. However, this disclosure is not limited thereto. The physical properties of the first material layer 111 and the second material layer 113 may vary. For example, the first material layer 111 may be a material used for reference above. Figure 4 The described interlayer insulation layer (ILD) is an insulating material. The second material layer 113 may include materials used for reference above. Figure 4 The conductive material with the described conductive patterns CP1 to CPn.

[0064] Reference Figure 5B A first mask pattern 121 with a first opening 125 can be formed on the stacked structure of the first material layer 111 and the second material layer 113. Subsequently, a channel hole 115 passing through the first material layer 111 and the second material layer 113 can be formed through the first opening 125 of the first mask pattern 121. The channel hole 115 can extend into the first substrate 101. Depending on the etching material used to form the channel hole 115, the channel hole 115 can be formed in various shapes.

[0065] In one embodiment, the channel hole 115 can be formed using a first etching material. The etching rate of the first material layer 111 and the second material layer 113 with respect to the first etching material can be higher than the etching rate of the first substrate 101 with respect to the first etching material. Therefore, the end of the channel hole 115 extending into the first substrate 101 can be formed to be narrower in width than the channel hole 115 passing through the first material layer 111 and the second material layer 113.

[0066] Reference Figure 5C A memory layer 137 and a channel structure 147 can be formed in the channel hole 115. The sidewalls of the channel structure 147 and the ends of the channel structure 147 extending into the first substrate 101 can be surrounded by the memory layer 137.

[0067] The steps of forming the memory layer 137 may include sequentially stacking a barrier insulating layer 135, a data storage layer 133, and a tunnel insulating layer 131 on the surface of each via 115. The barrier insulating layer 135, the data storage layer 133, and the tunnel insulating layer 131 may include the steps described above. Figure 4 The barrier insulating layer BI, data storage layer DS, and tunnel insulating layer TI are made of the same material. The memory layer 137 can be formed in a line shape, and the central region of the channel hole 115 can be defined by the memory layer 137.

[0068] Subsequently, a channel structure 147 can be formed by forming a channel layer 141 on the surface of the memory layer 137. The channel layer 141 may include a semiconductor layer serving as a channel region. For example, the channel layer 141 may include silicon.

[0069] In one embodiment, the channel layer 141 may be formed as a liner, and the central region of the channel via 115 may include a portion not filled by the channel layer 141. When the channel layer 141 is formed as a liner, the steps of forming the channel structure 147 may include filling the central region of the channel via 115 on the channel layer 141 with a core insulating layer 143, etching a portion of the core insulating layer 143 to define a recessed region in a portion of the central region of the channel via 115, and filling the recessed region with a doped semiconductor layer 145. The core insulating layer 143 may include an oxide, and the doped semiconductor layer 145 may include a conductive dopant. The conductive dopant may include an n-type dopant for a junction. The conductive dopant may include an anti-doped p-type dopant.

[0070] In one embodiment, the channel layer 141 may be formed to fill the central region of the channel via 115, and the core insulating layer 143 and the doped semiconductor layer 145 may be omitted. When the core insulating layer 143 and the doped semiconductor layer 145 are omitted, the step of forming the channel structure 147 may further include the step of doping the channel layer 141 with a conductive dopant.

[0071] Reference Figure 5D It can be removed Figure 5C A first insulating layer 151 is formed after the first mask pattern 121 shown.

[0072] Subsequently, a slit 153 can be formed. The slit 153 can penetrate the first insulating layer 151 and can penetrate the laminated structure of the first material layer 111 and the second material layer 113. The slit 153 can correspond to... Figure 4 The slit SI is shown. Subsequently, the horizontal space 155 can be defined by selectively removing the second material layer 113 exposed through the slit 153. The horizontal space 155 can be defined between the first material layers 111 that are perpendicular to each other.

[0073] Reference Figure 5E , Figure 5D The horizontal space 155 shown can be filled by the third material layer 157 through the slits 153. The third material layer 157 can be the one referenced above. Figure 4 The conductive patterns CP1 to CPn are described. A third material layer 157 may fill the horizontal space 155 to surround the channel structure 147 and the memory layer 137.

[0074] As described above, a gate stack 150 can be formed on the first substrate 101 by replacing the second material layer 113, which serves as a sacrificial layer, with a third material layer 157, which serves as a conductive pattern. The gate stack 150 may include a structure in which a first material layer 111, serving as an interlayer insulating layer, and a third material layer 157, serving as a conductive pattern, are alternately stacked. The gate stack 150 can be penetrated by a channel structure 147, and the channel structure 147 can extend into the first substrate 101. A memory layer 137 can extend from between the channel structure 147 and the gate stack 150 to between the end of the channel structure 147 and the first substrate 101.

[0075] The above reference Figure 3 The described storage block with multiple cell strings CS1 and CS2 can be referenced above. Figures 5A to 5E The described process is formed on the first substrate 101. Each cell string may include, as shown above, referenced. Figure 3 The description includes a series-connected drain-select transistor DST and memory cells MC1 to MCn. (Refer to the above.) Figure 3 The described drain-select transistor DST and memory cells MC1 to MCn can be defined in channel structure 147 and as shown in the figure. Figure 5E The intersections of the third material layer 157, which serves as a conductive pattern, are shown and can be connected in series via the channel structure 147.

[0076] Subsequently, a sidewall insulating layer 161 can be formed to cover the sidewalls of the gate stack 150. Afterward, a second insulating layer 163 can be formed extending to fill the interior of the slit 153 and cover the sidewall insulating layer 161 and the first insulating layer 151.

[0077] Reference Figure 5FA third insulating layer 171 may be formed on the second insulating layer 163. Subsequently, a contact plug 173 may be formed through the third insulating layer 171 or through the third insulating layer 171 and the second insulating layer 163. The contact plug 173 may extend to contact the channel structure 147.

[0078] Subsequently, a first linear array 175 can be formed. Linear array 175 may be bit lines coupled to contact plug 173. A first insulating structure 181 can then be formed to cover the first linear array 175. The first insulating structure 181 may include two or more insulating layers 181A to 181D. First connection structures 185, 189, 191, and 193 may be embedded in the first insulating structure 181, and the first connection structures 185, 189, 191, and 193 may be electrically connected via contact plugs (not shown).

[0079] The first connection structures 185, 189, 191 and 193 may include a first bonding metal 193 having a surface exposed to the outside of the first insulating structure 181.

[0080] Figure 6 This is a cross-sectional view illustrating the steps of forming a CMOS circuit and a second connection structure on a second substrate.

[0081] See Figure 6 This may include the step of forming a plurality of transistors 200 constituting a complementary metal-oxide-semiconductor (CMOS) circuit on the second substrate 201.

[0082] The second substrate 201 may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial layer formed by a selective epitaxial growth method.

[0083] Each transistor 200 may be formed in an active region of a second substrate 201 separated by an isolation layer 203. Each transistor 200 may include a gate insulating layer 207 and a gate electrode 209 stacked on the corresponding active region, and junctions 205a and 205b formed on both sides of the gate electrode 209 in the active region. Junctions 205a and 205b may include conductive dopants for implementing the corresponding transistors. Junctions 205a and 205b may include at least one of n-type dopant and p-type dopant.

[0084] After forming multiple transistors 200, a second connection structure 220 can be formed to connect to the transistors 200 forming the CMOS circuit, and a second insulating structure 211 can be formed to cover the second connection structure 220 and the transistors 200.

[0085] The second insulating structure 211 may include two or more insulating layers 211A to 211D. A second connection structure 220 may be embedded within the second insulating structure 211. Each second connection structure 220 may include multiple conductive patterns 213, 215, 217, 219, 221, and 223. The second insulating structure 211 and the second connection structure 220 may be modified in various ways and are not limited to the examples shown in the figures.

[0086] The conductive patterns 213, 215, 217, 219, 221 and 223 included in each of the second connection structures 220 may include a second bonding metal 223 having a surface exposed to the outside of the second insulating structure 211.

[0087] Figure 7 It is a cross-sectional view used to illustrate the steps of joining the first connecting structure and the second connecting structure together.

[0088] Reference Figure 7 The first substrate 101 and the second substrate 201 can be aligned such that the first bonding metal 193 on the first substrate 101 and the second bonding metal 223 on the second substrate 201 can contact each other. The first bonding metal 193 and the second bonding metal 223 can include various metals, such as copper.

[0089] Subsequently, the first bonding metal 193 and the second bonding metal 223 can be bonded to each other. For this purpose, the first bonding metal 193 and the second bonding metal 223 can be hardened after heat is applied to them. This disclosure is not limited thereto, and various processes for bonding the first bonding metal 193 and the second bonding metal 223 can be introduced.

[0090] Figures 8A to 8D This is a cross-sectional view illustrating the steps of forming a string line connecting to multiple cell strings on the gate stack 150.

[0091] Reference Figure 8A It can remove Figure 7 The first substrate 101 is shown. When the first substrate 101 is removed, the memory layer 137 can be used as an etch stop layer. Therefore, the channel layer 141 protruding from the gate stack 150 can be protected by the memory layer 137.

[0092] Reference Figure 8B The memory layer 137 protruding from the gate stack 150 can be removed to expose the channel layer 141. The exposed channel layer 141 can protrude from the gate stack 150.

[0093] Reference Figure 8CA conductive layer 301 in contact with the protruding channel layer 141 can be formed over the gate stack 150. The conductive layer 301 can be formed of a polysilicon layer. Therefore, the protruding portion of the channel structure 147 forming the channel layer 141 can extend into the conductive layer 301. Subsequently, a second mask pattern 303 can be formed on the conductive layer 301. The second mask pattern 303 can be formed to expose the second insulating layer 163 formed in the slit. Thereafter, the conductive layer 301 can be patterned by performing an etching process using the second mask pattern 303. The patterned conductive layer 301 can be formed of at least two or more conductive layers. The layout of the conductive layer 301 can be defined by the second mask pattern 303. In embodiments of this disclosure, the channel layers 141 of four adjacent channel structures 147 can be electrically interconnected with each other through a patterned conductive layer 301. The conductive layer 301 can be patterned in various ways. For example, the patterned conductive layer 301 may correspond to a channel structure 147 and may be electrically connected to the channel layer 141 of the corresponding channel structure 147.

[0094] Reference Figure 8D In removing Figure 8C Following the second mask pattern 303, an interlayer insulating layer 305 covering the conductive layer 301 can be formed. Subsequently, contact plugs 315 can be formed through the interlayer insulating layer 305. Each contact plug 315 can contact the patterned conductive layer 301. Each contact plug 315 may include a diffusion barrier 311 formed on the sidewall of a contact hole and a contact conductive layer 313 filling the contact hole.

[0095] Subsequently, an upper line 317 corresponding to and connected to the contact plug 315 can be formed on the interlayer insulating layer 305. The patterned conductive layer 301, contact plug 315, and upper line 317 described above can be defined as... Figure 3 Serial STL.

[0096] Figure 9A and Figure 9B This is a plan view illustrating the connection relationship between the contact plug and the upper line.

[0097] Reference Figure 9A Multiple contact plugs 315A and 315B passing through the interlayer insulation layer 305 can be respectively connected to multiple parallel upper lines 317A and 317B. Therefore, in Figure 8D Of the multiple channel structures 147 shown, four channel structures 147 connected to the patterned conductive layer 301 can be connected to a top line. Top lines 317A and 317B can be connected to... Figure 3 Transistors DT1 and DT2.

[0098] Reference Figure 9BAdjacent memory blocks BLK1 and BLK2 can share multiple top lines 317A, 317B, 317C, and 317D. For example, the contact plugs 315A of adjacent memory blocks BLK1 and BLK2 can be connected to a top line 317A, the contact plugs 315B of adjacent memory blocks BLK1 and BLK2 can be connected to a top line 317B, the contact plugs 315C of adjacent memory blocks BLK1 and BLK2 can be connected to a top line 317C, and the contact plugs 315D of adjacent memory blocks BLK1 and BLK2 can be connected to a top line 317D.

[0099] As described above, according to embodiments of this disclosure, the source selection transistor for controlling the connection between the source line and the cell string may not be disposed in the cell string structure, thereby simplifying the process steps. Furthermore, multiple cell strings can be selectively connected to the source line via serial lines and discharge cells, thereby preventing interference caused by the source selection transistor during read and programmable operations of the memory block.

[0100] Figure 10 This is a block diagram illustrating the configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0101] Reference Figure 10 The memory system 1100 may include a semiconductor memory device 1120 and a memory controller 1110.

[0102] Semiconductor memory device 1120 may include multiple channel structures configured to alternately stack through a multilayer structure in which multiple interlayer insulating layers and multiple gate electrodes are disposed. The multiple channel structures may include a barrier insulating layer, a charge storage layer, a tunnel insulating layer, a channel layer, and a core insulating layer. In one embodiment, the channel layer may be formed of a multilayer structure, and the multilayer structure may include a polysilicon layer and a silicon-germanium layer.

[0103] Semiconductor memory device 1120 may be a multi-chip package formed of multiple flash memory chips. Semiconductor memory device 1120 may be a reference... Figures 1 to 4 The semiconductor memory device described.

[0104] The memory controller 1110 can be configured to control the semiconductor memory device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 can be used as the operating memory of the CPU 1112. The CPU 1112 can perform overall control operations for data exchange with the memory controller 1110. The host interface 1113 may be configured with a data exchange protocol for a host connected to the memory system 1100. Furthermore, the error correction block 1114 can detect and correct errors included in the data read from the memory device 1120, and the memory interface 1115 can interface with the memory device 1120. Additionally, the memory controller 1110 may also include a read-only memory (ROM) or the like, which stores code data for connection to the host interface.

[0105] The aforementioned memory system 1100 may be a memory card or solid-state drive (SSD) equipped with a semiconductor memory device 1120 and a memory controller 1110. For example, when the memory system 1100 is an SSD, the memory controller 1110 may communicate with an external device (e.g., a host) via one of various interface protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect-Fast (PCI-E), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE) protocol.

[0106] Figure 11 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure.

[0107] Reference Figure 11 The computing system 1200 according to embodiments of this disclosure may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. Furthermore, if the computing system 1200 is a mobile device, it may also include a battery for providing operating voltage to the computing system 1200. It may also include an application chipset, a camera image processor (CIS), mobile DRAM, etc.

[0108] While exemplary embodiments of this disclosure have been disclosed for illustrative purposes, those skilled in the art will recognize that various modifications, additions, and substitutions are possible. Therefore, the scope of this disclosure must be defined by the appended claims and their equivalents, and not by their preceding description.

[0109] According to this disclosure, the channel of each of the plurality of cell strings included in a memory block can be connected to the source line via a discharge transistor. Therefore, the plurality of cell strings do not have source selection transistors, simplifying the manufacturing process. Furthermore, each cell string and source line can be selectively connected or disconnected, enabling the prevention of interference during programming and reading operations of the semiconductor memory device.

[0110] Cross-reference of related applications

[0111] This application claims priority to Korean Patent Application No. 10-2021-0048648, filed on April 14, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A substrate with complementary metal-oxide-semiconductor (CMOS) circuitry; A gate stack having an interlayer insulating layer and a conductive pattern alternately stacked on the substrate in a vertical direction; Multiple channel structures passing through the gate stack, each of the channel structures having a first end protruding above the gate stack; Multiple conductive layers are disposed above the gate stack; Multiple contacts, each contact being connected to a corresponding conductive layer among the multiple conductive layers; as well as Multiple upper lines, each upper line connecting to a corresponding contact among the multiple contacts, The plurality of conductive layers are disposed at the same height and spaced apart from each other in the lateral direction. Each of the plurality of conductive layers is in contact with the first end of at least one of the plurality of channel structures.

2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device further comprises upper lines respectively connected to the plurality of conductive layers.

3. The semiconductor memory device of claim 2, further comprising a discharge unit connected between each of the upper lines and the source lines.

4. The semiconductor memory device according to claim 3, wherein, The plurality of channel structures are selectively connected to the source line through the plurality of conductive layers, the upper line, and the discharge unit.

5. The semiconductor memory device according to claim 4, wherein, The discharge unit selectively connects at least one channel structure, which is commonly connected to each of the plurality of conductive layers, to the source line in response to a discharge signal.

6. The semiconductor memory device according to claim 1, wherein, The channel structure includes: A core insulation layer disposed in the central region of the channel structure; A doped semiconductor layer disposed in the central region of the channel structure and between the core insulating layer and the bit line; and A channel layer extending from between the doped semiconductor layer and the memory layer to between the core insulating layer and the memory layer, and between the source line and the core insulating layer.

7. The semiconductor memory device according to claim 6, wherein, A portion of the channel layer forms a protruding first end of the channel structure and extends into the conductive layer.

8. The semiconductor memory device of claim 1, further comprising a memory layer disposed between the sidewall of the channel structure and the gate stack.

9. The semiconductor memory device according to claim 8, wherein, The memory layer is formed to be shorter than the channel structure in the vertical direction.

10. The semiconductor memory device of claim 1, further comprising a bit line coupled to a second end of the channel structure, the bit line being disposed between the substrate and the gate stack.

11. The semiconductor memory device of claim 10, further comprising: A conductive connecting line is disposed on the lower layer of the bit line; An insulating structure that surrounds the conductive connecting wire; as well as A conductive connection structure passes through the insulating structure, thereby connecting the conductive connection line to the CMOS circuit.

12. A method for manufacturing a semiconductor memory device, the method comprising the following steps: A memory cell array is formed on a first substrate, the memory cell array comprising: a gate stack having interlayer insulating layers and conductive patterns alternately stacked in a vertical direction; a plurality of channel structures passing through the gate stack and extending at their ends into the first substrate; and a memory layer extending from between the plurality of channel structures and the gate stack to between the first substrate and the ends of the plurality of channel structures. Form bit lines connected to the memory cell array; Remove the first substrate to expose the memory layer; A portion of the memory layer is removed to expose the ends of the plurality of channel structures; A plurality of conductive layers are formed over the gate stack, which are in contact with the end of at least one of the plurality of channel structures; Multiple contacts are formed, each contact being connected to a corresponding conductive layer among the multiple conductive layers; and Multiple upper lines are formed, and each upper line is connected to a corresponding contact among the multiple contacts. The plurality of conductive layers are formed at the same height and spaced apart from each other in the lateral direction.

13. The method according to claim 12, further comprising the following step: An interlayer insulating layer is formed covering the plurality of conductive layers; A plurality of contact plugs are formed through the interlayer insulating layer, and the plurality of contact plugs are respectively connected to the plurality of conductive layers; as well as Multiple upper lines are formed on the interlayer insulation layer to connect with the plurality of contact plugs.

14. The method according to claim 12, wherein, The conductive pattern consists of a drain selection line and multiple word lines.

15. The method according to claim 12, further comprising the following steps: Before removing the first substrate: A first conductive connection structure is formed on the bit line; A complementary metal-oxide-semiconductor (CMOS) circuit is formed on the second substrate. A second conductive connection structure connected to the CMOS circuit is formed on the second substrate; as well as The first bonding metal of the first conductive connection structure and the second bonding metal of the second conductive connection structure are bonded to each other, so that the first conductive connection structure and the second conductive connection structure are connected to each other.

16. The method according to claim 15, in, The steps of forming the memory cell array further include the following steps: Forming a slit through the first and second material layers; and The second material layer is replaced by a third material layer through the slit. The first material layer includes the interlayer insulation layer. The third material layer includes the conductive pattern, and The second material layer is a sacrificial layer, and the etching rate of the second material layer is different from the etching rate of the interlayer insulating layer.

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