A display panel

Abstract

This invention relates to a display panel. A first conductive layer is disposed between the second active layer and the substrate. The first conductive layer includes a first gate corresponding to the second active layer. A second conductive layer is disposed on the side of the second active layer away from the substrate. The second conductive layer includes a second gate corresponding to the second active layer. A first operating voltage applied to the first gate is lower than a second operating voltage applied to the second gate. The first gate is either suspended or electrically connected to one of a high-voltage power supply line, a low-voltage power supply line, a reset signal line, and a ground line to reduce the intensity of the electric field formed between the second active layer and the first gate, thereby improving the stability of the thin-film transistor formed by the second active layer, the first gate, the second source, and the second drain, and avoiding the poor reliability of TFT devices formed by bottom gates in oxide thin-film transistors in the prior art.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel. Background Technology

[0002] Traditional Organic Light Emitting Diodes (OLEDs) typically use Low Temperature Poly-silicon (LTPS) thin-film transistors (TFTs) or Indium Gallium Zinc Oxide (IGZO) thin-film transistors. Each has its advantages and disadvantages: LTPS TFTs offer high electron mobility and stability; however, they suffer from high leakage current, requiring constant capacitor charging to maintain normal display, and can only support a minimum frequency of 30Hz, making low-frequency refresh rates impossible and resulting in higher power consumption. IGZO TFTs, on the other hand, offer lower leakage current, lower power consumption, and lower cost; however, they have lower electron mobility, and IGZO is unstable in air and prone to oxidation, leading to a shorter lifespan for the display panel.

[0003] Later, low-temperature polycrystalline oxide (LTPO) TFTs emerged, combining the advantages of both LTPS TFTs and IGZO TFTs, characterized by low leakage current and low power consumption. LTPO TFTs can achieve low-frequency displays of 1Hz, and by adjusting the display frequency according to the application scenario, they can effectively reduce the power consumption of the display panel.

[0004] In current LTPO TFTs, a first dielectric layer is disposed between the bottom gate and the active pattern of the oxide thin-film transistor, and a second dielectric layer is disposed between the top gate and the active pattern. Due to process limitations, the first dielectric layer has poor film quality and is difficult to adjust, resulting in poor reliability of the first dielectric layer. This makes it difficult to control the interface quality between the oxide active pattern and the first dielectric layer. When the device is operating, if the scan signal line is placed at a high potential (NVGH), an electric field is formed between the channel of the oxide thin-film transistor and the top and bottom gates, respectively. Over a long period of operation, the threshold voltage of the IGZO-TFT formed by the bottom gate will drift, resulting in poor reliability of the IGZO-TFT device formed by the bottom gate, and ultimately, poor reliability of the entire oxide thin-film transistor. Summary of the Invention

[0005] The purpose of this invention is to provide a display panel that can solve the problem of low reliability in current LTPO TFTs.

[0006] To address the aforementioned problems, the present invention provides a display panel comprising: a substrate; a first active layer disposed on one side of the substrate; a second active layer disposed on the side of the first active layer away from the substrate, the material of the second active layer comprising a metal oxide; a first conductive layer disposed between the substrate and the second active layer, the first conductive layer including a first gate corresponding to the second active layer; and a second conductive layer disposed on the side of the second active layer away from the substrate, the second conductive layer including a second gate corresponding to the second active layer; wherein a first operating voltage applied to the first gate is less than a second operating voltage applied to the second gate.

[0007] Furthermore, the spacing between the first gate and the second active layer is greater than or equal to the spacing between the second gate and the second passive layer.

[0008] Furthermore, the display panel further includes a third conductive layer disposed between the first active layer and the first conductive layer. The third conductive layer includes a third gate and a first capacitor electrode disposed corresponding to the first active layer. The first conductive layer further includes a second capacitor electrode disposed corresponding to the first capacitor electrode.

[0009] Furthermore, the display panel further includes: a fourth conductive layer disposed between the first conductive layer and the second active layer; the first conductive layer further includes: a third gate and a first capacitor electrode disposed corresponding to the first active layer; and the fourth conductive layer includes: a second capacitor electrode disposed corresponding to the first capacitor electrode.

[0010] Furthermore, the first gate is disposed in the same layer as the first active layer, and the material of the first gate is the same as the semiconductor material conductor of the first active layer.

[0011] Furthermore, the first conductive layer is disposed between the first active layer and the substrate, and the first conductive layer further includes a light-shielding portion disposed corresponding to the first active layer.

[0012] Furthermore, the first operating voltage range for the first gate is -7V to +1V.

[0013] Furthermore, the first gate is either left floating or electrically connected to one of a high-voltage power supply line, a low-voltage power supply line, a reset signal line, and a ground line.

[0014] Furthermore, the display panel further includes: a first thin-film transistor, a second thin-film transistor, a third thin-film transistor, a fourth thin-film transistor, a fifth thin-film transistor, a sixth thin-film transistor, and a seventh thin-film transistor; a first scan line, a second scan line, a third scan line, and a fourth scan line; a data line and a first light-emitting control signal line; the reset signal line includes: a first reset signal line and a second reset signal line; the source of the first thin-film transistor is electrically connected to the high-voltage power supply line, and its drain is electrically connected to the low-voltage power supply line; the source of the second thin-film transistor is electrically connected to the source of the first thin-film transistor, its drain is electrically connected to the data line, and its gate is electrically connected to the first scan line; the source of the third thin-film transistor is electrically connected to the first drain of the first thin-film transistor, and its drain is electrically connected to the gate of the first thin-film transistor; the third thin-film transistor includes a first gate and a second gate, and the first operating voltage connected to the first gate of the third thin-film transistor is less than the second operating voltage connected to its second gate; the first gate of the third thin-film transistor is either floating or electrically connected to one of the high-voltage power supply line, the low-voltage power supply line, the first reset signal line, the second reset signal line, and a ground line. The second gate of the third thin-film transistor is electrically connected to the second scan line; the source of the fourth thin-film transistor is electrically connected to the gate of the first thin-film transistor, and its drain is electrically connected to the first reset signal line; the fourth thin-film transistor includes the first gate and the second gate, and the first operating voltage connected to the first gate of the fourth thin-film transistor is less than the second operating voltage connected to the second gate; the first gate of the fourth thin-film transistor is either floating or electrically connected to one of the high-voltage power supply line, the low-voltage power supply line, the first reset signal line, the second reset signal line, and ground; the second gate of the fourth thin-film transistor is electrically connected to the third scan line; the gate of the fifth thin-film transistor is electrically connected to the first light-emitting control signal line, its source is electrically connected to the source of the first thin-film transistor, and its drain is electrically connected to the high-voltage power supply line; the gate of the sixth thin-film transistor is electrically connected to the first light-emitting control signal line, its source is electrically connected to the drain of the first thin-film transistor, and its drain is electrically connected to the low-voltage power supply line; the source of the seventh thin-film transistor is electrically connected to the drain of the sixth thin-film transistor, and its drain is electrically connected to the second reset signal line; its gate is electrically connected to the fourth scan line.

[0015] Furthermore, both the third and fourth thin-film transistors include the second active layer, the material of which is a metal oxide; the first thin-film transistor includes the first active layer, the material of which is low-temperature polycrystalline silicon.

[0016] The advantages of this invention are: a first conductive layer is provided between the second active layer and the substrate, the first conductive layer including a first gate corresponding to the second active layer; a second conductive layer is provided on the side of the second active layer away from the substrate, the second conductive layer including a second gate corresponding to the second active layer; a first operating voltage connected to the first gate is less than a second operating voltage connected to the second gate; the first gate is either suspended or electrically connected to one of a high-voltage power supply line, a low-voltage power supply line, a reset signal line, and a ground line, to reduce the intensity of the electric field formed between the second active layer and the first gate, thereby improving the stability of the thin-film transistor formed by the second active layer, the first gate, the second source, and the second drain, and avoiding the poor reliability of TFT devices formed by bottom gates in oxide thin-film transistors in the prior art.

[0017] In this invention, the spacing between the first gate and the second active layer is greater than or equal to the spacing between the second gate and the second active layer, so as to reduce the intensity of the electric field formed between the second active layer and the first gate, improve the stability of the thin film transistor formed by the second active layer, the first gate, the second source, and the second drain, and avoid the phenomenon of poor reliability of TFT devices formed by bottom gate in oxide thin film transistors in the prior art. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the display panel structure of Embodiment 1;

[0020] Figure 2 This is a schematic diagram illustrating the change of the threshold voltage over time when a voltage of 30V is simultaneously applied to the top and bottom gates of a dual-gate thin-film transistor using existing technology.

[0021] Figure 3 This is a schematic diagram illustrating the change of the threshold voltage over time when a voltage of 0V is applied to the top gate and a voltage of 30V is applied to the bottom gate in a dual-gate thin-film transistor using existing technology.

[0022] Figure 4 This is a schematic diagram illustrating the change of the threshold voltage over time when a voltage of 30V is applied to the top gate and a voltage of 0V is applied to the bottom gate in a dual-gate thin-film transistor, as shown in Example 1.

[0023] Figure 5 This is a circuit diagram of the display panel of Embodiment 1;

[0024] Figure 6 This is a schematic diagram of the display panel structure of Embodiment 2;

[0025] Figure 7 This is a schematic diagram of the display panel structure of Embodiment 3;

[0026] Figure 8 This is a schematic diagram of the structure of the first and second thin-film transistors of the display panel in Embodiment 4;

[0027] Figure 9 This is a circuit diagram of the display panel in Embodiment 5;

[0028] Figure 10 This is a circuit diagram of the display panel of Embodiment 6;

[0029] Figure 11 This is a circuit diagram of the display panel of Embodiment 7.

[0030] Explanation of reference numerals in the attached figures:

[0031] 100. Display panel;

[0032] 101. Substrate; 102. Buffer layer;

[0033] 103. First active layer; 104. First insulating layer;

[0034] 105. Third conductive layer; 106. Second insulating layer;

[0035] 107. Fourth conductive layer; 108. First interlayer insulating layer;

[0036] 109. Second active layer; 110. Third insulating layer;

[0037] 111. Second conductive layer; 112. Second interlayer insulating layer;

[0038] 113. First source; 114. First drain;

[0039] 115. Second source; 116. Second drain;

[0040] 117. First planarization layer; 118. First conductive layer;

[0041] 1181. First gate; 1182. Light-shielding portion;

[0042] 1111, Second gate; 1051, Third gate;

[0043] 1052, First capacitor plate; 1071, Second capacitor plate. Detailed Implementation

[0044] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings to fully introduce the technical content of the present invention to those skilled in the art, and to demonstrate that the present invention can be implemented, making the disclosed technical content of the present invention clearer and enabling those skilled in the art to more easily understand how to implement the present invention. However, the present invention can be embodied in many different forms of embodiments, and the scope of protection of the present invention is not limited to the embodiments mentioned herein. The following description of the embodiments is not intended to limit the scope of the present invention.

[0045] The directional terms used in this invention, such as "up", "down", "front", "back", "left", "right", "inner", "outer", and "side", are only for the directions shown in the accompanying drawings. The directional terms used herein are for the purpose of explaining and illustrating this invention, and not for limiting the scope of protection of this invention.

[0046] In the accompanying drawings, components with the same structure are indicated by the same numerical designation, and components with similar structures or functions are indicated by similar numerical designations. Furthermore, for ease of understanding and description, the dimensions and thicknesses of each component shown in the drawings are arbitrary, and the present invention does not limit the dimensions and thicknesses of each component.

[0047] Example 1

[0048] like Figure 1 As shown, this embodiment provides a display panel 100. The display panel 100 includes: a substrate 101, a buffer layer 102, a first active layer 103, a first insulating layer 104, a third conductive layer 105, a second insulating layer 106, a fourth conductive layer 107, a first interlayer insulating layer 108, a second active layer 109, a third insulating layer 110, a second conductive layer 111, a second interlayer insulating layer 112, a first source 113, a first drain 114, a second source 115, a second drain 116, a first planarization layer 117, and a first conductive layer 118.

[0049] The substrate 101 is made of materials including polyimide, polycarbonate, polyethylene terephthalate, and polyethylene naphthalate. Therefore, the substrate 101 has good impact resistance and can effectively protect the display panel 100.

[0050] The first conductive layer 118 is disposed between the substrate 101 and the second active layer 109. In this embodiment, the first conductive layer 118 is disposed between the first active layer 103 and the substrate 101. The first conductive layer 118 includes a light-shielding portion 1182 corresponding to the first active layer 103. The light-shielding portion 1182 shields the electric field formed by the non-coincidence of the charge centers of positive and negative ions inside the substrate 101 and the electric field formed at the interface of different film layers, preventing the electric field from affecting the working characteristics of the first active layer 103 and avoiding display image retention and ESD damage.

[0051] The first conductive layer 118 further includes a first gate 1181 corresponding to the second active layer 109. The first gate 1181 is made of a conductive metal, such as titanium, molybdenum, aluminum, copper, or nickel.

[0052] The buffer layer 102 covers the side of the first conductive layer 118 away from the substrate 101. The buffer layer 102 mainly serves a buffering function, and its material can be SiOx, SiNx, SiNOx, or a combination of SiNx and SiOx, etc.

[0053] The first active layer 103 is disposed on one side of the substrate 101. The first active layer 103 includes a first channel portion 1031 and first conductive portions 1032 located at both ends of the first channel portion 1031.

[0054] The first insulating layer 104 is disposed on the side of the first active layer 103 away from the substrate 101 and extends to cover the buffer layer 102. The first insulating layer 104 is mainly used to prevent short circuits from occurring between the first active layer 103 and the third conductive layer 105. The material of the first insulating layer 104 can be SiOx, SiNx, Al2O3, a combination of SiNx and SiOx, or a combination of SiOx, SiNx, and SiOx, etc.

[0055] The third conductive layer 105 is disposed on the side of the first insulating layer 104 away from the substrate 101. The third conductive layer 105 is disposed between the first active layer 103 and the second active layer 109; the third conductive layer 105 includes a third gate 1051 and a first capacitor plate 1052 corresponding to the first active layer 103. The third gate 1051 is disposed on the side of the first insulating layer 104 away from the substrate 101 and corresponds to the first channel portion 1031 of the first active layer 103. The material of the third gate 1051 can be Mo or a combination of Mo and Al, a combination of Mo and Cu, a combination of Mo, Cu, and IZO, a combination of IZO, Cu, and IZO, a combination of Mo, Cu, and ITO, a combination of Ni, Cu, and Ni, a combination of MoTiNi, Cu, and MoTiNi, a combination of NiCr, Cu, and NiCr, or CuNb, etc.

[0056] The second insulating layer 106 is disposed on the side of the third conductive layer 105 away from the substrate 101 and extends to cover the first insulating layer 104. The second insulating layer 106 is mainly used to prevent short circuits between the third conductive layer 105 and the fourth conductive layer 107. The material of the second insulating layer 106 can be SiOx, SiNx, Al2O3, a combination of SiNx and SiOx, or a combination of SiOx, SiNx, and SiOx, etc.

[0057] The fourth conductive layer 107 is disposed on the side of the second insulating layer 106 away from the substrate 101. The fourth conductive layer 107 is disposed between the third conductive layer 105 and the second active layer 109; the fourth conductive layer 107 also includes a second capacitor plate 1071 corresponding to the first capacitor plate 1052. The second capacitor plate 1071 is disposed on the side of the second insulating layer 106 away from the substrate 101 and corresponds to the first capacitor plate 1052. The second capacitor plate 1071 is used to couple with the first capacitor plate 1052 to form a storage capacitor Cst. The material of the second capacitor plate 1071 can be Mo or a combination of Mo and Al, a combination of Mo and Cu, a combination of Mo, Cu, and IZO, a combination of IZO, Cu, and IZO, a combination of Mo, Cu, and ITO, a combination of Ni, Cu, and Ni, a combination of MoTiNi, Cu, and MoTiNi, a combination of NiCr, Cu, and NiCr, or CuNb, etc.

[0058] The first interlayer insulating layer 108 is disposed on the side of the fourth conductive layer 107 away from the substrate 101 and extends to cover the second insulating layer 106. The material of the first interlayer insulating layer 108 may be SiOx, SiNx, or SiNOx, etc.

[0059] The second active layer 109 is disposed on the side of the first interlayer insulating layer 108 away from the substrate 101, and the material of the second active layer 109 includes metal oxide. In this embodiment, the material of the second active layer 109 is IGZO. The second active layer 109 includes a second channel portion 1091 and second conductive portions 1092 located at both ends of the second channel portion 1091.

[0060] The third insulating layer 110 is disposed on the side of the second active layer 109 away from the substrate 101 and extends to cover the first interlayer insulating layer 108. The third insulating layer 110 is mainly used to prevent short circuits between the second active layer 109 and the second conductive layer 111. The material of the third insulating layer 110 can be SiOx, SiNx, Al2O3, a combination of SiNx and SiOx, or a combination of SiOx, SiNx, and SiOx, etc.

[0061] The second conductive layer 111 is disposed on the side of the second active layer 109 away from the substrate 101, and the second conductive layer 111 includes a second gate 1111 corresponding to the second active layer 109. The second gate 1111 is disposed on the side of the third insulating layer 110 away from the substrate 101, and is corresponding to the second channel portion 1091 of the second active layer 109. The material of the second gate 1111 can be Mo or a combination of Mo and Al, a combination of Mo and Cu, a combination of Mo, Cu and IZO, a combination of IZO, Cu and IZO, a combination of Mo, Cu and ITO, a combination of Ni, Cu and Ni, a combination of MoTiNi, Cu and MoTiNi, a combination of NiCr, Cu and NiCr, or CuNb, etc.

[0062] The first operating voltage connected to the first gate 1181 is less than the second operating voltage connected to the second gate 1111. The first operating voltage connected to the first gate 1181 ranges from -7V to +1V. The first gate 1181 is either floating or electrically connected to one of a high-voltage power supply line, a low-voltage power supply line, a reset signal line, or a ground line; this reduces the intensity of the electric field formed between the second active layer 109 and the first gate 1181, improving the stability of the thin-film transistor formed by the second active layer 109, the first gate 1181, the second source 115, and the second drain 116, and avoiding the poor reliability of TFT devices formed by bottom gates in oxide thin-film transistors in the prior art.

[0063] The spacing between the first gate 1181 and the second active layer 109 is greater than or equal to the spacing between the second gate 1111 and the second active layer 109. This reduces the intensity of the electric field formed between the second active layer 109 and the first gate 1181, improves the stability of the thin-film transistor formed by the second active layer 109, the first gate 1181, the second source 115, and the second drain 116, and avoids the poor reliability of TFT devices formed by bottom gates in oxide thin-film transistors in the prior art.

[0064] The second interlayer insulating layer 112 is disposed on the side of the second conductive layer 111 away from the substrate 101 and extends to cover the third insulating layer 110. The second interlayer insulating layer 112 is mainly used to prevent short circuits from occurring between the second conductive layer 111 and the second source electrode 115 and the second drain electrode 116. The material of the second interlayer insulating layer 112 can be SiOx, SiNx, or SiNOx, etc.

[0065] The first source electrode 113 and the first drain electrode 114 are disposed on the same layer on the side of the second interlayer insulating layer 112 away from the substrate 101, and are respectively electrically connected to the two first conductive portions 1032 of the first active layer 103.

[0066] The second source 115 and the second drain 116 are disposed on the same layer on the side of the second interlayer insulating layer 112 away from the substrate 101, and are respectively electrically connected to the two second conductive portions 1092 of the second active layer 109. In this embodiment, the first source 113, the first drain 114, the second source 115 and the second drain 116 are all disposed on the same layer.

[0067] The first planarization layer 117 covers the first source 113, the first drain 114, the second source 115, and the second drain 116 on the side away from the substrate 101, and extends to cover the second interlayer insulating layer 112. The material of the first planarization layer 117 may be SiOx, SiNx, SiNOx, or a combination of SiNx and SiOx, etc.

[0068] like Figure 2 , Figure 3 and Figure 4 As shown, compared with the prior art, the difference ΔVth between the threshold voltage (Vth) before and after the use of the second active layer 109 in this embodiment is closest to 0, indicating that the PBTS (reliability quantification index) of the second active layer 109 in this embodiment is the best.

[0069] like Figure 5 As shown, the display panel 100 of this embodiment includes: a first thin-film transistor T1, a second thin-film transistor T2, a third thin-film transistor T3, a fourth thin-film transistor T4, a fifth thin-film transistor T5, a sixth thin-film transistor T6, a seventh thin-film transistor T7, a storage capacitor Cst, a first reset signal line Vi1, a second reset signal line Vi2, a first scan line Pscan-1, a second scan line Nscan-1, a third scan line Nscan-2, a fourth scan line Pscan-2, a data line Vdata, a low-voltage power supply line Vss, a high-voltage power supply line Vdd, and a first light emission control signal line EM-1.

[0070] In this embodiment, the source of the first thin-film transistor T1 is electrically connected to the high-voltage power supply line Vdd, and its drain is electrically connected to the low-voltage power supply line Vss. The first thin-film transistor T1 includes a first active layer 103, which is made of low-temperature polycrystalline silicon.

[0071] The source of the second thin-film transistor T2 is electrically connected to the source of the first thin-film transistor T1, its drain is electrically connected to the data line Vdata, and its gate is electrically connected to the first scan line Pscan-1.

[0072] In this embodiment, the source of the third thin-film transistor T3 is electrically connected to the drain of the first thin-film transistor T1, and its drain is electrically connected to the gate of the first thin-film transistor T1. The third thin-film transistor T3 includes a first gate 1181 and a second gate 1111. The first operating voltage connected to the first gate 1181 of the third thin-film transistor T3 is less than the second operating voltage connected to the second gate 1111. The first gate 1181 of the third thin-film transistor T3 is either floating or electrically connected to one of the high-voltage power supply line, the low-voltage power supply line, the first reset signal line, the second reset signal line, and the ground line. The second gate 1111 of the third thin-film transistor T3 is electrically connected to the second scan line Nscan-1. The third thin-film transistor T3 includes a second active layer 109, which is made of metal oxide. In this embodiment, the third thin-film transistor T3 includes a second active layer 109, which is made of metal oxide.

[0073] In this embodiment, the source of the fourth thin-film transistor T4 is electrically connected to the gate of the first thin-film transistor T1, and its drain is electrically connected to the first reset signal line Vi1. The fourth thin-film transistor T4 includes a first gate 1181 and a second gate 1111. The first operating voltage connected to the first gate 1181 of the fourth thin-film transistor T4 is less than the second operating voltage connected to the second gate 1111. The first gate 1181 of the fourth thin-film transistor T4 is either floating or electrically connected to one of the high-voltage power supply line, the low-voltage power supply line, the first reset signal line, the second reset signal line, and the ground line. The second gate 1111 of the fourth thin-film transistor T4 is electrically connected to the third scan line Nscan-2. The semiconductor layer of the fourth thin-film transistor T4 is made of metal oxide. The fourth thin-film transistor T4 includes a second active layer 109, which is also made of metal oxide. In this embodiment, the fourth thin-film transistor T4 includes a second active layer 109, which is made of metal oxide.

[0074] The gate of the fifth thin-film transistor T5 is electrically connected to the first light-emitting control signal line EM-1, its source is electrically connected to the source of the first thin-film transistor T1, and its drain is electrically connected to the high-voltage power supply line Vdd.

[0075] The gate of the sixth thin-film transistor T6 is electrically connected to the first light-emitting control signal line EM-1, its source is electrically connected to the drain of the first thin-film transistor T1, and its drain is electrically connected to the low-voltage power supply line Vss.

[0076] The source of the seventh thin-film transistor T7 is electrically connected to the drain of the sixth thin-film transistor T6, the drain of which is electrically connected to the second reset signal line Vi2, and the gate of which is electrically connected to the fourth scan line Pscan-2.

[0077] The first terminal of the storage capacitor Cst is electrically connected to the gate of the first thin-film transistor T1, and its second terminal is electrically connected to the drain of the fifth thin-film transistor T5.

[0078] In this design, the first operating voltage connected to the first gate 1181 of the third thin-film transistor T3 is less than the second operating voltage connected to the second gate 1111, and the spacing between the first gate 1181 and the second active layer 109 is greater than or equal to the spacing between the second gate 1111 and the second active layer 109. This reduces the intensity of the electric field formed between the second active layer 109 and the first gate 1181, improves the stability of the thin-film transistor formed by the second active layer 109, the first gate 1181, the second source 115, and the second drain 116, and avoids the poor reliability of TFT devices formed by bottom gates in oxide thin-film transistors in the prior art.

[0079] In this design, the first operating voltage connected to the first gate 1181 of the fourth thin-film transistor T4 is less than the second operating voltage connected to the second gate 1111, and the spacing between the first gate 1181 and the second active layer 109 is greater than or equal to the spacing between the second gate 1111 and the second active layer 109. This reduces the intensity of the electric field formed between the second active layer 109 and the first gate 1181, improves the stability of the thin-film transistor formed by the second active layer 109, the first gate 1181, the second source 115, and the second drain 116, and avoids the poor reliability of TFT devices formed by bottom gates in oxide thin-film transistors in the prior art.

[0080] The first thin-film transistor T1 includes a light-shielding portion 1182. The first thin-film transistor T1 uses the light-shielding portion 1182 to shield the electric field formed by the non-coincidence of the charge centers of positive and negative ions inside the substrate 101 and the electric field formed at the interface of different film layers, so as to avoid the electric field from affecting the working characteristics of the first active layer 103 and avoid display image retention and ESD damage.

[0081] In summary, the pixel circuit of the display panel 100 in this embodiment is a 7T1C circuit. In other embodiments, the pixel circuit of the display panel 100 may also be a 6T1C pixel circuit, a 6T2C pixel circuit, a 7T2C pixel circuit, an 8T1C pixel circuit, or an 8T2C pixel circuit.

[0082] Example 2

[0083] like Figure 6 As shown, this embodiment includes most of the technical features of embodiment 1. The difference between this embodiment and embodiment 1 is that the first gate 1181 and the first active layer 103 are disposed on the same layer in this embodiment. The material of the first gate 1181 is the same as the semiconductor material conductor of the first active layer 103, that is, the same as the material of the first conductive part 1032 of the first active layer 103. Therefore, the first active layer 103 and the first gate 1181 can be formed using the same photomask.

[0084] Example 3

[0085] like Figure 7 As shown, this embodiment includes most of the technical features of embodiment 1. The difference between this embodiment and embodiment 1 is that the fourth conductive layer 107 is disposed between the first conductive layer 118 and the second active layer 109. The first conductive layer 118 further includes a third gate 1051 and a first capacitor plate 1052 corresponding to the first active layer 103, and the fourth conductive layer 107 includes a second capacitor plate 1071 corresponding to the first capacitor plate 1052. In other words, the first gate 1181 is disposed in the same layer as the third gate 1051 and the first capacitor plate 1052, and the first gate 1181 is made of the same material as the third gate 1051 and the first capacitor plate 1052, so the first gate 1181, the third gate 1051 and the first capacitor plate 1052 can be formed using the same photomask.

[0086] Example 4

[0087] like Figure 8 As shown, this embodiment includes most of the technical features of Embodiment 1. The difference between this embodiment and Embodiment 1 is that: in this embodiment, the third conductive layer 105 is disposed between the first active layer 103 and the first conductive layer 118. The third conductive layer 105 includes: a third gate 1051 and a first capacitor plate 1052 corresponding to the first active layer 103. The first conductive layer 118 further includes: a second capacitor plate 1071 corresponding to the first capacitor plate 1052. In other words, the first gate 1181 and the second capacitor plate 1071 are disposed in the same layer, and the first gate 1181 and the second capacitor plate 1071 are made of the same material, so the first gate 1181 and the second capacitor plate 1071 can be formed using the same photomask.

[0088] Example 5

[0089] like Figure 9As shown, this embodiment includes most of the technical features of Embodiments 1, 2, 3 and 4. The difference between this embodiment and Embodiments 1, 2, 3 and 4 is that the display panel 100 in this embodiment also includes a second capacitor Cboost.

[0090] The first terminal of the second capacitor Cboost is electrically connected to the gate of the first thin-film transistor T1, and its second terminal is electrically connected to the gate of the second thin-film transistor T2.

[0091] Example 6

[0092] like Figure 10 As shown, this embodiment includes most of the technical features of Embodiments 1, 2, 3 and 4. The difference between this embodiment and Embodiments 1, 2, 3 and 4 is that the display panel 100 in this embodiment further includes: an eighth thin-film transistor T8, a second light-emitting control signal line EM-2, a third light-emitting control signal line EM-3 and a third reset signal line Vi3.

[0093] The gate of the seventh thin-film transistor T7 is electrically connected to the second light-emitting control signal line EM-2.

[0094] The gate of the eighth thin-film transistor T8 is electrically connected to the third light-emitting control signal line EM-3, its source is electrically connected to the source of the first thin-film transistor T1, and its drain is electrically connected to the third reset signal line Vi3.

[0095] Example 7

[0096] like Figure 11 As shown, this embodiment includes most of the technical features of embodiment 6. The difference between this embodiment and embodiment 6 is that the display panel 100 in this embodiment also includes a second capacitor Cboost.

[0097] The first terminal of the second capacitor Cboost is electrically connected to the gate of the first thin-film transistor T1, and its second terminal is electrically connected to the gate of the second thin-film transistor T2.

[0098] Furthermore, the above provides a detailed description of a display panel provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, include: substrate; A first active layer is disposed on one side of the substrate; A second active layer is disposed on the side of the first active layer away from the substrate, and the material of the second active layer includes metal oxide; A first conductive layer is disposed between the substrate and the second active layer, and the first conductive layer includes a first gate disposed corresponding to the second active layer; A second conductive layer is disposed on the side of the second active layer away from the substrate, and the second conductive layer includes a second gate disposed corresponding to the second active layer; Wherein, the first operating voltage of the first gate is less than the second operating voltage of the second gate, the first gate is disposed on the same layer as the first active layer, and the material of the first gate is the same as the semiconductor material conductor of the first active layer.

2. The display panel according to claim 1, characterized in that, The spacing between the first gate and the second active layer is greater than or equal to the spacing between the second gate and the second active layer.

3. The display panel according to claim 2, characterized in that, Also includes: A third conductive layer is disposed between the first active layer and the first conductive layer. The third conductive layer includes a third gate and a first capacitor electrode disposed corresponding to the first active layer. The first conductive layer further includes a second capacitor electrode disposed corresponding to the first capacitor electrode.

4. The display panel according to claim 2, characterized in that, Also includes: A fourth conductive layer is disposed between the first conductive layer and the second active layer. The first conductive layer further includes a third gate and a first capacitor electrode disposed corresponding to the first active layer. The fourth conductive layer includes a second capacitor electrode disposed corresponding to the first capacitor electrode.

5. The display panel according to claim 2, characterized in that, The first conductive layer further includes a light-shielding portion disposed corresponding to the first active layer.

6. The display panel according to claim 2, characterized in that, The first operating voltage range for the first gate is -7V to +1V.

7. The display panel according to claim 2, characterized in that, The first gate is either left floating or electrically connected to one of a high-voltage power supply line, a low-voltage power supply line, a reset signal line, and a ground line.

8. The display panel according to claim 7, characterized in that, The display panel further includes: a first thin-film transistor, a second thin-film transistor, a third thin-film transistor, a fourth thin-film transistor, a fifth thin-film transistor, a sixth thin-film transistor, and a seventh thin-film transistor; a first scan line, a second scan line, a third scan line, and a fourth scan line; a data line and a first light-emitting control signal line; the reset signal line includes: a first reset signal line and a second reset signal line; The source of the first thin-film transistor is electrically connected to the high-voltage power supply line, and its drain is electrically connected to the low-voltage power supply line. The source of the second thin-film transistor is electrically connected to the source of the first thin-film transistor, its drain is electrically connected to the data line, and its gate is electrically connected to the first scan line. The source of the third thin-film transistor is electrically connected to the first drain of the first thin-film transistor, and its drain is electrically connected to the gate of the first thin-film transistor; the third thin-film transistor includes a first gate and a second gate, and the first operating voltage connected to the first gate of the third thin-film transistor is less than the second operating voltage connected to the second gate; the first gate of the third thin-film transistor is either floating or electrically connected to one of the high-voltage power supply line, the low-voltage power supply line, the first reset signal line, the second reset signal line, and the ground line, and the second gate of the third thin-film transistor is electrically connected to the second scan line; The source of the fourth thin-film transistor is electrically connected to the gate of the first thin-film transistor, and its drain is electrically connected to the first reset signal line; the fourth thin-film transistor includes the first gate and the second gate, and the first operating voltage connected to the first gate of the fourth thin-film transistor is less than the second operating voltage connected to the second gate; the first gate of the fourth thin-film transistor is either floating or electrically connected to one of the high-voltage power supply line, the low-voltage power supply line, the first reset signal line, the second reset signal line, and the ground line, and the second gate of the fourth thin-film transistor is electrically connected to the third scan line; The gate of the fifth thin-film transistor is electrically connected to the first light-emitting control signal line, its source is electrically connected to the source of the first thin-film transistor, and its drain is electrically connected to the high-voltage power supply line. The gate of the sixth thin-film transistor is electrically connected to the first light-emitting control signal line, its source is electrically connected to the drain of the first thin-film transistor, and its drain is electrically connected to the low-voltage power supply line. The source of the seventh thin-film transistor is electrically connected to the drain of the sixth thin-film transistor, and its drain is electrically connected to the second reset signal line; its gate is electrically connected to the fourth scan line.

9. The display panel according to claim 8, characterized in that, Both the third thin-film transistor and the fourth thin-film transistor include the second active layer, and the material of the second active layer includes metal oxide; The first thin-film transistor includes the first active layer, and the material of the first active layer includes low-temperature polycrystalline silicon.

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