Backboard, photosensitive circuit and display panel

Abstract

The application provides a back plate, a photosensitive circuit and a display panel, the back plate comprising a driving unit and a photosensitive unit, the photosensitive unit comprising a light sensing subunit and a light reading subunit, the light sensing subunit comprising an amorphous silicon thin film transistor, the light reading subunit comprising a first polycrystalline silicon thin film transistor, and the driving unit comprising a second polycrystalline silicon thin film transistor. The application sets the light sensing sensor as an amorphous silicon thin film transistor, sets the light reading sensor and the driving sensor as polycrystalline silicon thin film transistors, utilizes the good compatibility of the amorphous silicon thin film transistor and the polycrystalline silicon thin film transistor, integrates the photosensitive unit and the driving unit in the back plate at the same time, constructs a high mobility back plate with photosensitive and driving functions at the same time, solves the problem that the light sensing back plate of the existing remote interactive display device is difficult to have both light sensing characteristics and back plate characteristics, and avoids the defects of high cost and complex process of the traditional externally-hung light sensing sensor.

Description

Technical Field

[0001] This application relates to the field of displays, and more particularly to a backplane, a photosensitive circuit, and a display panel. Background Technology

[0002] In the current display industry, human-computer interaction has become an important direction for the development of new display technologies. The addition of various sensors has provided more possibilities for different types of human-computer interaction functions.

[0003] The integration of light sensors into display panels provides a new solution for remote interaction. Amorphous silicon (a-Si) is a good photosensitive material, but due to its material properties, its mobility and on-state current are relatively low, which cannot meet the backplane requirements of high-end products. Currently, new self-emissive display panels require backplanes with higher mobility. However, high-mobility oxide thin-film transistors (IGZO) are mainly sensitive to blue and ultraviolet light, with poor sensing performance for green and red light, and poor process compatibility with amorphous silicon thin-film transistors. Low-temperature polycrystalline silicon thin-film transistors (LTPS), which also have high mobility, have poor photosensitivity and poor in-plane uniformity due to limitations in crystallization technology.

[0004] Therefore, existing remote interactive display devices suffer from the problem of having both light-sensing characteristics and backplane characteristics. Summary of the Invention

[0005] This invention provides a backplate, a photosensitive circuit, and a display panel to solve the problem that existing remote interactive display devices have a photosensitive backplate that cannot simultaneously possess both photosensitive characteristics and backplate characteristics.

[0006] To solve the above problems, the technical solution provided by the present invention is as follows:

[0007] The present invention provides a backplane, the backplane including a driving unit and a photosensitive unit, the photosensitive unit including a photosensitive subunit and a photoreading subunit, the photosensitive subunit including an amorphous silicon thin film transistor, the photoreading subunit including a first polycrystalline silicon thin film transistor, and the driving unit including a second polycrystalline silicon thin film transistor.

[0008] Optionally, in some embodiments of the present invention, the active regions of the first polycrystalline silicon thin-film transistor, the second polycrystalline silicon thin-film transistor, and the amorphous silicon thin-film transistor are disposed in the same layer.

[0009] Optionally, in some embodiments of the present invention, the channels of the first polycrystalline silicon thin-film transistor and the second polycrystalline silicon thin-film transistor are obtained by processing amorphous silicon material using a blue laser annealing process.

[0010] Optionally, in some embodiments of the present invention, the backplate further includes a light-shielding layer disposed on the photosensitive side of the substrate and covering the channels of the first polysilicon thin-film transistor and the second polysilicon thin-film transistor.

[0011] Optionally, in some embodiments of the present invention, both the amorphous silicon thin-film transistor and the first polycrystalline silicon thin-film transistor are N-type thin-film transistors.

[0012] Optionally, in some embodiments of the present invention, the output terminal of the amorphous silicon thin-film transistor is connected to the gate of the first polycrystalline silicon thin-film transistor.

[0013] Optionally, in some embodiments of the present invention, the amorphous silicon thin-film transistor is a bottom-gate structure, and the first polycrystalline silicon thin-film transistor and the second polycrystalline silicon thin-film transistor are top-gate or bottom-gate structures; the backplate further includes a light-shielding electrode, which is disposed on the side of the active region of the second polycrystalline silicon thin-film transistor away from the gate and is electrically connected to the source or drain of the second polycrystalline silicon thin-film transistor; the gate of the amorphous silicon thin-film transistor is disposed in the same layer as the light-shielding electrode and is made of the same material.

[0014] Optionally, in some embodiments of the present invention, the source and drain electrodes of the second polycrystalline silicon thin-film transistor, the source and drain electrodes of the first polycrystalline silicon thin-film transistor, and the source and drain electrodes of the amorphous silicon thin-film transistor are disposed in the same layer and are made of the same material.

[0015] The present invention also provides a photosensitive circuit, the photosensitive circuit including a photosensitive thin-film transistor and a photoreading thin-film transistor, wherein the gate of the photosensitive thin-film transistor is connected to a gate signal, the first electrode of the photosensitive thin-film transistor and the first electrode of the photoreading thin-film transistor are connected to a power supply signal, and the second electrode of the photosensitive thin-film transistor is electrically connected to the gate of the photoreading thin-film transistor.

[0016] Both the photosensitive thin-film transistor and the photoreading thin-film transistor are N-type thin-film transistors.

[0017] Meanwhile, the present invention also provides a display panel, the display panel including the back plate described in any embodiment of the present invention.

[0018] This invention provides a backplane, a photosensitive circuit, and a display panel. By using an amorphous silicon thin-film transistor as a photosensitive sensor, a first polycrystalline silicon thin-film transistor as a light readout sensor, and a first polycrystalline silicon thin-film transistor as a driving sensor, the photosensitive unit and the driving unit are integrated into the backplane simultaneously, taking advantage of the good compatibility between amorphous silicon thin-film transistors and polycrystalline silicon thin-film transistors. This creates a high-mobility backplane that simultaneously possesses photosensitive and driving functions, solving the problem that existing remote interactive display devices' photosensitive backplanes cannot simultaneously possess both photosensitive and backplane characteristics. It also avoids the disadvantages of traditional external photosensitive sensors, such as high cost and complex processes. Attached Figure Description

[0019] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0020] Figure 1 This is a schematic diagram of the structure of the back plate provided in an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of the fabrication structure of the backplate provided in an embodiment of the present invention;

[0022] Figure 3 The photosensitive circuit diagram provided for an embodiment of the present invention. Detailed Implementation

[0023] The technical solutions in the embodiments and / or examples of the present invention will be clearly and completely described below with reference to specific implementation schemes. Obviously, the embodiments and / or examples described below are only a part of the embodiments and / or examples of the present invention, and not all of them. Based on the embodiments and / or examples of the present invention, all other embodiments and / or examples obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0024] The directional terms used in this invention, such as [up], [down], [left], [right], [front], [back], [inside], [outside], [side], etc., are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrating and understanding this invention, and not for limiting it. The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature.

[0025] To address the problem that existing optical sensing backplanes of remote interactive display devices cannot simultaneously possess both optical sensing characteristics and backplane characteristics, embodiments of the present invention provide a backplane to solve this problem.

[0026] In one embodiment, please refer to Figure 1 , Figure 1 A schematic diagram of the structure of a backplane provided in an embodiment of the present invention is shown. As shown, the backplane provided in this embodiment of the present invention includes a driving unit and a photosensitive unit. The photosensitive unit includes a photosensitive subunit and a photoreading subunit. The photosensitive subunit includes an amorphous silicon thin-film transistor T1, the photoreading unit includes a first polycrystalline silicon thin-film transistor T2, and the driving unit includes a second polycrystalline silicon thin-film transistor T3.

[0027] This invention, through the use of amorphous silicon thin-film transistors as photosensitive sensors, first polycrystalline silicon thin-film transistors as photoreading sensors, and first polycrystalline silicon thin-film transistors as driving sensors, leverages the good compatibility between amorphous silicon and polycrystalline silicon thin-film transistors to integrate the photosensitive unit and driving unit simultaneously into a backplane. This constructs a high-mobility backplane that simultaneously possesses photosensitive and driving functions, solving the problem that existing remote interactive display devices' photosensitive backplanes cannot simultaneously possess both photosensitive and backplane characteristics. It also avoids the disadvantages of traditional external photosensitive sensors, such as high cost and complex processes.

[0028] In one embodiment, such as Figure 1 As shown, the backplate comprises, from bottom to top, the following layers: substrate 11, first metal layer 12, buffer layer 13, semiconductor active layer 14, gate insulating layer 15, second metal layer 16, interlayer insulating layer 17, third metal layer 18, passivation layer 19, electrode layer 20, and light-shielding layer 21.

[0029] Specifically, the substrate 11 can be a rigid substrate, such as a glass substrate, or a flexible substrate, such as a polyimide substrate. The buffer layer 13, the gate insulating layer 15, the interlayer insulating layer 17, and the passivation layer 19 are all insulating film layers used to block adjacent metal film layers. The materials of the buffer layer 13, the gate insulating layer 15, the interlayer insulating layer 17, and the passivation layer 19 include, but are not limited to, any one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiNOx), silicon nitride / silicon oxide (SiNx / SiOx), aluminum oxide / silicon nitride / silicon oxide (Al2O3 / SiNx / SiOx), and silicon oxide / silicon nitride / silicon oxide (SiOx / SiNx / SiOx).

[0030] The first metal layer 12, the semiconductor active layer 14, the second metal layer 16, and the third metal layer 18 form the amorphous silicon thin-film transistor T1, the first polycrystalline silicon thin-film transistor T2, and the second polycrystalline silicon thin-film transistor T3. The amorphous silicon thin-film transistor T1 is a bottom-gate structure thin-film transistor, while the first polycrystalline silicon thin-film transistor T2 and the second polycrystalline silicon thin-film transistor T3 are top-gate structures thin-film transistors.

[0031] Specifically, the first metal layer 12 includes a light-shielding electrode 121 and a gate 122 of the amorphous silicon thin-film transistor T1. The material of the first metal layer 12 includes, but is not limited to, molybdenum (Mo), molybdenum / aluminum (Mo / Al), molybdenum / copper (Mo / Cu), molybdenum / titanium / copper (MoTi / Cu), molybdenum / titanium / copper / molybdenum / titanium (MoTi / Cu / MoTi), titanium / aluminum / titanium (Ti / Al / Ti), titanium / copper / titanium (Ti / Cu / Ti), molybdenum / copper / indium tin oxide (Mo / Cu / ITO), molybdenum / copper / indium zinc oxide (Mo / Cu / IZO), and indium tin oxide / copper / indium zinc oxide (IZO / Cu / IZO).

[0032] The semiconductor active layer 14 includes the active region 143 of the amorphous silicon thin film transistor T1, the active region 142 of the first polycrystalline silicon thin film transistor T2, and the active region 141 of the second polycrystalline silicon thin film transistor T3. The active region 143 is made of amorphous silicon (a-Si) or other materials that are responsive to visible light. The active regions 142 and 141 of the first polycrystalline silicon thin film transistor T2 and the second polycrystalline silicon thin film transistor T3 are made of polycrystalline silicon (poly-Si). The active regions 142 and 141 respectively include a channel region and doped regions located on both sides of the channel region.

[0033] The second metal layer 16 includes the gate 162 of the first polysilicon thin-film transistor T2 and the gate 161 of the second polysilicon thin-film transistor T3. The material of the second metal layer 16 is similar to that of the first metal layer 12, including but not limited to molybdenum (Mo), molybdenum / aluminum (Mo / Al), molybdenum / copper (Mo / Cu), molybdenum / titanium / copper (MoTi / Cu), molybdenum / titanium / copper / molybdenum / titanium (MoTi / Cu / MoTi), titanium / aluminum / titanium (Ti / Al / Ti), titanium / copper / titanium (Ti / Cu / Ti), molybdenum / copper / indium tin oxide (Mo / Cu / ITO), molybdenum / copper / indium zinc oxide (Mo / Cu / IZO), and indium tin oxide / copper / indium zinc oxide (IZO / Cu / IZO).

[0034] The third metal layer 18 includes the source and drain 183 of the amorphous silicon thin-film transistor T1, the source and drain 182 of the first polycrystalline silicon thin-film transistor T2, and the source and drain 181 of the second polycrystalline silicon thin-film transistor T3. The source and drain of the amorphous silicon thin-film transistor T1 are respectively connected to the two ends of the active region 143, and the source or drain of the amorphous silicon thin-film transistor T1 is electrically connected to the gate of the first polycrystalline silicon thin-film transistor T2. The source and drain of the first polycrystalline silicon thin-film transistor T2 are respectively connected to the doped regions at both ends of the active region 142 through vias. The source and drain of the second polycrystalline silicon thin-film transistor T3 are respectively connected to the doped regions at both ends of the active region 141 through vias, and the source or drain of the second polycrystalline silicon thin-film transistor T3 is also connected to the light-shielding electrode 121 through vias. The light-shielding electrode 121 is used to block light rays incident on the substrate side into the channel of the second polysilicon thin-film transistor T3. Simultaneously, the light-shielding electrode 121 is connected to the source or drain of the second polysilicon thin-film transistor T3 to prevent threshold voltage drift and coupling between the light-shielding electrode 121 and the source / drain of the second polysilicon thin-film transistor T3, thus ensuring the driving characteristics of the second polysilicon thin-film transistor T3. The material of the third metal layer 18 is similar to that of the first metal layer 12, including but not limited to molybdenum (Mo), molybdenum / aluminum (Mo / Al), molybdenum / copper (Mo / Cu), molybdenum / titanium / copper (MoTi / Cu), molybdenum / titanium / copper / molybdenum / titanium (MoTi / Cu / MoTi), titanium / aluminum / titanium (Ti / Al / Ti), titanium / copper / titanium (Ti / Cu / Ti), molybdenum / copper / indium tin oxide (Mo / Cu / ITO), molybdenum / copper / indium zinc oxide (Mo / Cu / IZO), and indium tin oxide / copper / indium zinc oxide (IZO / Cu / IZO).

[0035] The light-shielding layer 21 is disposed on the passivation layer 19 and includes a first light-shielding portion 211 and a second light-shielding portion 212. The first light-shielding portion 211 is located on the second polysilicon thin-film transistor T3 and covers the channel region of the second polysilicon thin-film transistor T3. The first light-shielding portion 211 is used to block the influence of external light or laser pointer light on the second polysilicon thin-film transistor T3. The second light-shielding portion 212 is located on the first polysilicon thin-film transistor T2 and covers the channel region of the first polysilicon thin-film transistor T2. The second light-shielding portion 212 is used to block the influence of external light or laser pointer light on the first polysilicon thin-film transistor T2. The first light-shielding portion 211 and the second light-shielding portion 212 can be connected or spaced apart. The material of the light-shielding layer 21 includes, but is not limited to, black photoresist material, and the thickness of the light-shielding layer 21 ranges from 1 micrometer to 3 micrometers.

[0036] Accordingly, this invention provides a method for preparing a backplate, please refer to... Figure 2 , Figure 2 A schematic diagram of the fabrication structure of the backplate provided in an embodiment of the present invention is shown, as follows: Figure 2 As shown, the preparation method includes:

[0037] Step 1: Provide a substrate 11; fabricate a first metal layer 12 on the substrate 11; pattern the first metal layer 12 to obtain the gate 122 and the light-shielding electrode 121 of the amorphous silicon thin-film transistor; please refer to [link / reference needed] for details. Figure 2 (a)

[0038] Step 2: A buffer layer 13 is prepared on the first metal layer 12 using chemical vapor deposition; a semiconductor active layer 14 is prepared on the buffer layer 13, wherein the semiconductor active layer 14 is made of amorphous silicon or other photosensitive materials with visible light intensity response; the semiconductor active layer 14 is patterned to obtain the active region 143 of the amorphous silicon thin film transistor, the active region 142 of the first polycrystalline silicon thin film transistor, and the active region 141 of the second polycrystalline silicon thin film transistor; the active regions 142 and 141 are treated using a blue laser annealing process. The active regions 142 and 141 of the polycrystalline silicon material are obtained. The blue laser annealing (BLA) process is more compatible with the fabrication process of amorphous silicon, enabling the fabrication of the active regions 143 of the amorphous silicon material and 142 and 141 of the polycrystalline silicon material within the same backplane structure. Furthermore, the blue laser annealing process allows for deeper laser penetration, resulting in polycrystalline silicon films with high crystallinity, large grain size, and no grain boundary protrusions. This leads to high mobility and excellent anti-folding properties in thin-film transistors. For details, please refer to [link to relevant documentation]. Figure 2 (b)

[0039] Step 3: Fabricate a gate insulating layer 15 on the active region 142 and the active region 141; fabricate a second metal layer 16 on the gate insulating layer 15, and pattern the second metal layer 16 to obtain the gate 162 of the first polysilicon thin film transistor and the gate 161 of the second polysilicon thin film transistor; perform N-type doping on both ends of the active region 142 using the gate 162 as a photomask for self-alignment, and perform doping on both ends of the active region 141 using the gate 161 as a photomask for self-alignment; please refer to [link to details]. Figure 2 (c)

[0040] Step 4: Fabricate an interlayer insulating layer 17 on the gate layer 16; fabricate a third metal layer 18 on the interlayer insulating layer 17, and pattern the third metal layer 18 to obtain the source / drain electrodes 183 of the amorphous silicon thin-film transistor, the source / drain electrodes 182 of the first polycrystalline silicon thin-film transistor, and the source / drain electrodes 181 of the second polycrystalline silicon thin-film transistor; please refer to [link / reference] for details. Figure 2 (d)

[0041] Step 5: Prepare a slewing layer 19 on the third metal layer 18; prepare an electrode layer 20 on the passivation layer 19; please refer to [the relevant documentation] for details. Figure 2 Middle (e).

[0042] Step 6: Prepare a light-shielding layer 21 on the passivation layer 19, and pattern the light-shielding layer 21 to obtain a first light-shielding portion 211 and a second light-shielding portion 212; please refer to [link / reference] for details. Figure 2 (f)

[0043] Meanwhile, embodiments of the present invention also provide a photosensitive circuit, such as Figure 3 As shown, the photosensitive circuit includes:

[0044] A photosensitive thin-film transistor T1 and a photoreading thin-film transistor T2 are provided. The gate of the photosensitive thin-film transistor T1 is connected to the gate signal Gate. The first terminal of the photosensitive thin-film transistor T1 and the first terminal of the photoreading thin-film transistor T2 are connected to the power supply signal VDD. The second terminal of the photosensitive thin-film transistor T1 is electrically connected to the gate of the photoreading thin-film transistor T2.

[0045] The photosensitive thin-film transistor T1 is an amorphous silicon thin-film transistor, and the photoreading thin-film transistor T2 is an N-type polycrystalline silicon thin-film transistor.

[0046] The photosensitive thin-film transistor T1 operates in the TFT off-state region. Because the amorphous silicon has a very small off-state current, the gate voltage of the photoreading thin-film transistor T2 is very small, and T2 is in the off state. When the photosensitive thin-film transistor T1 receives light, the amorphous silicon is excited, generating a photocurrent. This increases the gate voltage of the photoreading thin-film transistor T2, turning it on. This allows the power supply signal VDD from the first terminal of the photoreading thin-film transistor T2 to be read and transmitted to its second terminal, where it is then sensed by an external circuit. By reading the electrical signal from the second terminal of the photoreading thin-film transistor T2, the external light signal can be identified, and thus its location can be determined.

[0047] By setting the photosensitive circuit with a matrix structure in the back panel, the position of the external visible light laser signal can be actively located, thereby satisfying remote laser interaction and improving the interactive performance of the display panel.

[0048] This invention also provides a display panel, which includes a backplate and a photosensitive circuit as described in any embodiment of this invention. Therefore, it has the technical features and beneficial effects of the backplate and photosensitive circuit described in any embodiment of this invention. Please refer to the above embodiments for details, which will not be repeated here.

[0049] In summary, this invention provides a backplane, a photosensitive circuit, and a display panel. By using an amorphous silicon thin-film transistor (TFT) as a photosensor, a first polycrystalline silicon TFT as a light readout sensor, and a first polycrystalline silicon TFT as a drive sensor, the good compatibility of TFTs and polycrystalline silicon TFTs allows the photosensitive unit and the drive unit to be integrated into the backplane simultaneously. This creates a high-mobility backplane with both photosensing and driving functions, solving the problem of existing remote interactive display devices where photosensing and backplane characteristics are difficult to simultaneously possess. It also avoids the drawbacks of traditional external photosensors, such as high cost and complex processes. Through a matrix-structured photosensitive circuit, the active positioning of external visible light laser signals enables laser-based remote interaction, improving the interactive performance of the display panel.

[0050] The backplate, photosensitive circuit, and display panel provided in the embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A backsheet characterized by, It includes a driving unit and a photosensitive unit. The photosensitive unit includes a photosensitive subunit and a photoreading subunit. The photosensitive subunit includes an amorphous silicon thin-film transistor. The photoreading subunit includes a first polycrystalline silicon thin-film transistor. The driving unit includes a second polycrystalline silicon thin-film transistor. The active regions of the first polycrystalline silicon thin-film transistor, the second polycrystalline silicon thin-film transistor, and the amorphous silicon thin-film transistor are disposed in the same layer. In this configuration, the gate of the amorphous silicon thin-film transistor is connected to a gate signal, the first electrode of the amorphous silicon thin-film transistor and the first electrode of the first polycrystalline silicon thin-film transistor are both connected to a power supply signal, and the second electrode of the amorphous silicon thin-film transistor is electrically connected to the gate of the first polycrystalline silicon thin-film transistor.

2. The backsheet of claim 1 wherein, The channels of the first polycrystalline silicon thin-film transistor and the second polycrystalline silicon thin-film transistor are obtained by processing amorphous silicon material using a blue laser annealing process.

3. The backplate as described in claim 1, characterized in that, The backplate also includes a light-shielding layer, which is disposed on the photosensitive side of the backplate and covers the channels of the first polysilicon thin-film transistor and the second polysilicon thin-film transistor.

4. The backplate as described in claim 1, characterized in that, The first polycrystalline silicon thin-film transistor is an N-type thin-film transistor.

5. The backplane of claim 4, wherein, The output terminal of the amorphous silicon thin-film transistor is connected to the gate of the first polycrystalline silicon thin-film transistor.

6. The backplate as described in claim 3, characterized in that, The amorphous silicon thin-film transistor has a bottom-gate structure, and the first polycrystalline silicon thin-film transistor and the second polycrystalline silicon thin-film transistor have a top-gate structure or a bottom-gate structure; the backplate also includes a light-shielding electrode, which is disposed on the side of the active region of the second polycrystalline silicon thin-film transistor away from the gate, and is electrically connected to the source or drain of the second polycrystalline silicon thin-film transistor; the gate of the amorphous silicon thin-film transistor is disposed in the same layer as the light-shielding electrode and is made of the same material.

7. The backsheet of claim 6 wherein, The source and drain electrodes of the second polycrystalline silicon thin-film transistor, the source and drain electrodes of the first polycrystalline silicon thin-film transistor, and the source and drain electrodes of the amorphous silicon thin-film transistor are disposed in the same layer and are made of the same material.

8. A photosensitive circuit, characterized by comprising: It includes a photosensitive thin-film transistor and a photoreading thin-film transistor. The gate of the photosensitive thin-film transistor is connected to a gate signal, the first electrode of the photosensitive thin-film transistor and the first electrode of the photoreading thin-film transistor are connected to a power supply signal, and the second electrode of the photosensitive thin-film transistor is electrically connected to the gate of the photoreading thin-film transistor. The photosensitive thin-film transistor is an amorphous silicon thin-film transistor, and the photoreading thin-film transistor is an N-type polycrystalline silicon thin-film transistor.

9. A display panel, characterized in that, Includes the backplate as described in any one of claims 1 to 7.

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