Mask layout and design method thereof and image sensor

Abstract

The present application provides a mask layout, a design method thereof and an image sensor. The mask layout comprises a plurality of first patterns corresponding to sub-pixels, a light transmission region surrounding the first patterns, and a second pattern passing through the light transmission region and connecting between adjacent first patterns. The connection structure can effectively ensure the lattice matching between silicon pillars during high temperature process, and play a similar role of seed crystal. There is no lattice mismatch between lateral PN structures, which greatly reduces the defects generated during etching process and epitaxial sealing trench, effectively reduces the dark current and white point of the image sensor. Moreover, the middle part of at least part of the second pattern extends along the first direction or along the second direction, which ensures that the substrate at the bottom of the connection structure can be easily penetrated, increases the process window, and at the same time retains the bottom trench for optical isolation between pixels.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a photomask layout and its design method, as well as an image sensor. Background Technology

[0002] As semiconductor process nodes advance and market demands for image sensor performance increase, pixel sizes are shrinking. However, the requirements for pixel signal-to-noise ratio are not decreasing; on the contrary, they are gradually increasing.

[0003] To resolve the contradiction between these two factors, the proportion of photodiodes in the pixel volume has been gradually increased to improve signal strength. However, this introduces a new problem: the need for good pinning at the silicon interfaces to reduce pixel dark current. Due to the limitations of photoresist resolution, photodiodes formed using ion implantation processes cannot simultaneously meet these requirements.

[0004] Currently, epitaxial fabrication of photodiodes is becoming a trend. Patent document CN202022348104.5 discloses an image sensor in which a lateral PN structure is formed at a predetermined position on a substrate; a P-type epitaxial layer, higher than the substrate surface and on the upper surface of the lateral PN structure, is formed on the upper surface of the lateral PN structure to create a pinning layer. The formation of a photodiode with a lateral PN structure does not require consideration of ion implantation depth limitations, and it facilitates control of the linewidth of the N-type region, thus making it very easy to adjust the Vo of the photodiode. pin (Voltage depleted).

[0005] The photodiodes fabricated using this method not only provide high capacitance along the entire depth of the substrate and ultra-high full-well electron capacity, but also provide ultra-low Vt. pin This facilitates circuit readout design. In addition to photodiodes, the pixel area of ​​an image sensor integrates functional transistors such as transmission transistors, reset transistors, and source follower amplifiers. These functional transistors are generally fabricated on the surface of an n-type substrate. However, for lateral PN structure photodiodes, deep trenches need to be drilled in the n-type substrate, followed by lateral etching to control the photodiode's dimensions. Then, an epitaxial layer is laterally grown on the remaining pillars to form a lateral PN structure. Finally, the trench is closed, and the functional transistors are fabricated on the substrate. To ensure the normal operation of the front-side transistors on the silicon wafer, intrinsic silicon is often regrowed on the front side after trench closure to serve as the transistor channel.

[0006] However, defects are easily formed during the epitaxial layer growth process, which not only affect the performance of photodiodes but also the performance of functional transistors. Designing mask patterns for forming photodiodes to reduce the difficulty of epitaxial processes has become a problem that needs to be solved. Summary of the Invention

[0007] The purpose of this invention is to provide a photomask layout and its design method, as well as an image sensor. The photomask layout is applied to the photolithography process and, when transferred to the substrate, allows for a certain degree of interconnection between the upper parts of the silicon pillars during the etching process to form silicon pillars, thus creating a connection structure.

[0008] Based on the above considerations, the present invention provides a mask layout design method for forming an image sensor, the image sensor comprising: a plurality of sub-pixels arranged in a first period, a first trench surrounding the sub-pixels, and a connection structure spanning the first trench and connected to adjacent sub-pixels; the mask layout is characterized in that it comprises: a plurality of first patterns corresponding to the sub-pixels, a light-transmitting area surrounding the first patterns, and a second pattern passing through the light-transmitting area and connected to adjacent first patterns; wherein the second pattern is provided to form the connection structure, and together with the light-transmitting area forms the first trench.

[0009] Preferably, the first pattern is arranged in a row along a first direction, and at least a portion of the middle part of the second pattern extends along the first direction.

[0010] Preferably, the first pattern is arranged in a row along the second direction, and at least a portion of the middle part of the second pattern extends along the second direction.

[0011] Preferably, at least a portion of the second pattern has a dimension along the first direction that is greater than its dimension along the second direction; and / or, at least a portion of the second pattern has a dimension along the second direction that is greater than its dimension along the first direction.

[0012] Preferably, the first direction is orthogonal to the second direction, and the second pattern is symmetrical.

[0013] Preferably, the second pattern includes one of an axisymmetric figure and a rotationally symmetric figure.

[0014] Preferably, at least a portion of the axisymmetric figure has its axis of symmetry extending along the first direction; and / or, at least a portion of the axisymmetric figure has its axis of symmetry extending along the second direction.

[0015] Preferably, the axes of symmetry of adjacent axisymmetric figures are orthogonal or coincident.

[0016] Preferably, the first pattern comprises an N-sided polygon, where N ≥ 3.

[0017] Preferably, the second pattern is provided between at least some of the N adjacent N-sided polygons.

[0018] Preferably, the second pattern has N ends, each of which is connected to a corner of the N-sided polygon.

[0019] Preferably, N=4, the first pattern includes quadrilaterals, and each end of the pattern intersects the sides of the quadrilaterals at a predetermined angle.

[0020] Preferably, the preset angle includes 180°.

[0021] Preferably, the image sensor includes: a second periodically arranged main pixel, the main pixel including M sub-pixels, the first groove also surrounding the main pixel; the light-transmitting area also correspondingly surrounds M second patterns, M≥2.

[0022] The present invention also provides a mask layout designed using the above-described design method and applied to an image sensor, as well as a corresponding image sensor.

[0023] The photomask pattern of the present invention is transferred to the substrate to form silicon pillars and the connection structure between the silicon pillars. During the epitaxial process, the connection structure can effectively ensure the lattice matching between the silicon pillars during the high temperature process, and play a role similar to seed crystal. There is no lattice mismatch between the lateral PN structures, which greatly reduces the defects generated during the etching process and the epitaxial closed trench, and effectively reduces the dark current and white point of the image sensor.

[0024] Furthermore, at least a portion of the middle of the second pattern extends along the first direction or along the second direction, ensuring that the substrate at the bottom of the connecting structure can be easily penetrated, increasing the process window, while retaining the bottom trench for optical isolation between pixels.

[0025] Furthermore, at least a portion of the second pattern has a dimension along the first direction that is larger than its dimension along the second direction; and / or, at least a portion of the second pattern has a dimension along the second direction that is larger than its dimension along the first direction. The second straight section prevents the interconnect structure from breaking during epitaxy and etching, and the interconnect structure serves as a fulcrum for the subsequent growth of the top intrinsic layer, while maintaining a small interconnect structure width to facilitate easier subsequent lateral etching through the substrate from the bottom to form a photodiode-isolated slit structure.

[0026] Furthermore, the second pattern includes one of axisymmetric and rotationally symmetric graphics, and the size and position of the second pattern can be adjusted according to the deep grooves with different opening sizes to meet the design requirements of highly integrated image sensors. Attached Figure Description

[0027] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings.

[0028] Figure 1A plan view showing the mask pattern of the mask layout according to Embodiment 1 of the present invention; Figure 2 A planar schematic diagram showing the mask layout of the image sensor according to Embodiment 1 of the present invention; Figure 3 A plan view showing the mask pattern of the mask layout according to Embodiment 2 of the present invention; Figure 4 A plan view showing the mask layout of the image sensor according to Embodiment 2 of the present invention; Figure 5 A plan view showing the mask pattern of the mask layout according to Embodiment 3 of the present invention; Figure 6 A planar schematic diagram showing the mask layout of the image sensor according to Embodiment 3 of the present invention; Figure 7 A plan view showing the mask pattern of the mask layout according to Embodiment 4 of the present invention; Figure 8 A planar schematic diagram of the mask layout of the image sensor according to Embodiment 4 of the present invention is shown.

[0029] Throughout the figures, the same or similar reference numerals denote the same or similar devices (modules) or steps. Detailed Implementation

[0030] To make the content of this invention clearer and easier to understand, the following description, in conjunction with the accompanying drawings, further illustrates the invention. Of course, this invention is not limited to this specific embodiment, and common substitutions well-known to those skilled in the art are also covered within the scope of protection of this invention.

[0031] It should be noted that in the following specific embodiments, in order to clearly illustrate the structure of the present invention and facilitate explanation, the structure in the accompanying drawings is not drawn to scale and has been partially enlarged, deformed and simplified. Therefore, it should be avoided to interpret this as a limitation of the present invention.

[0032] In existing technologies, deep trenches are formed by etching the substrate, and the epitaxial growth process must proceed from the bottom of the trenches upwards; otherwise, lattice dislocations are prone to occur. Furthermore, the linewidth at the intersections of the deep trenches used between lateral PN structures is relatively large, making it easy for voids to form during epitaxial growth and causing dislocations at the epitaxial layer interfaces. These dislocations can further lead to defects in subsequent epitaxial growth processes, thereby affecting the performance and yield of devices placed in this region.

[0033] Please refer to the reference. Figure 1 and Figure 2 Please refer to the following: Figure 1 and Figure 2 , Figure 1A plan view showing the mask pattern of the mask layout according to Embodiment 1 of the present invention; Figure 2 This is a planar schematic diagram of the mask layout of the image sensor according to Embodiment 1 of the present invention.

[0034] In the manufacturing process of an image sensor, before the gate is formed, a semiconductor substrate is etched to form an array of semiconductor island structures to form a plurality of sub-pixels and a first trench surrounding the semiconductor island structures. The semiconductor island structures are interconnected at least at their upper parts by at least one connection structure.

[0035] According to the present invention, a mask layout design method is provided, wherein a plurality of first patterns 101 are provided, the first patterns 101 are used to form the semiconductor island-shaped (not shown) structure to form the sub-pixel (not shown), a light-transmitting area surrounding the first patterns 101 and a second pattern 102 passing through the light-transmitting area and connected between adjacent first patterns 101.

[0036] The image sensor's mask pattern has several mask patterns arranged in an array. The first pattern 101 and the second pattern 102 are both non-transparent parts. When the image sensor's mask pattern is applied to the photolithography process, the mask pattern is transferred to the substrate.

[0037] The second pattern 102 is used to form the connection structure (not shown), and the second pattern 102 together with the light-transmitting area forms the first groove (not shown), thereby reducing defects generated by subsequent epitaxial processes.

[0038] Please refer to the reference. Figure 1 and Figure 2 The mask pattern has a first pattern 101 and a second pattern 102 connected together. The first pattern 101 can be a polygon, and the second pattern 102 can extend outward from the edge or corner of the first pattern 101.

[0039] like Figure 1 As shown, the first pattern 101 can be a quadrilateral. The first direction (horizontal as shown) is orthogonal to the second direction (vertical as shown). The first patterns 101 are arranged in rows along the first direction and in columns along the second direction.

[0040] like Figure 2 As shown, the second pattern 102 is symmetrical, for example, it can be cross-shaped, with its ends extending outward from the corners of the first pattern 101.

[0041] In Embodiment 1, the substrate may be a silicon substrate. The silicon substrate is etched using a first pattern 101 as a mask to form an array of silicon pillars (semiconductor island structures) within the silicon substrate (not shown). Deep trenches are formed around the silicon pillars in the light-transmitting area surrounding the first pattern. The silicon substrate is then etched using a second pattern 102 as a mask to form a connection structure spanning the deep trenches between the silicon pillars.

[0042] Using the intersecting second pattern 102 as a mask for etching substrate, by controlling the etching process conditions, the bottom of the interconnect position is etched out, which can make the bottom of the connection structure suspended, that is, only the upper part of each silicon pillar is connected to each other, and a connection structure spanning the top of the deep trench can be formed, thereby avoiding the defect influence of the <111> crystal hole on the subsequent epitaxial growth.

[0043] This invention utilizes a unique mask pattern to ensure a certain degree of interconnection between the upper parts of the silicon pillars during etching. This allows for the epitaxial growth of lateral PN structures both inside and outside the deep trench, while preserving the optically isolated slit structure. Due to the presence of the second pattern 102 between the first pattern 101, a cantilever connection structure is formed between the silicon pillars. During the epitaxial process, there is no lattice mismatch between the lateral PN structures. Furthermore, when the top of the trench is sealed during epitaxy, defects in epitaxial growth are significantly reduced, effectively minimizing dark current and white spots in the image sensor.

[0044] The first pattern 101 includes an N-sided polygon, where N ≥ 3.

[0045] The second pattern is provided between at least some of the N adjacent N-sided polygons.

[0046] The second pattern 102 is located inside the image sensor and is connected between N adjacent N-sided polygons. The second pattern 102 has N ends, and each end is connected to a corner of the N-sided polygon.

[0047] like Figure 2 As shown, in Embodiment 1, N = 4, and the N-sided polygon is a square. Located inside the image sensor, each corner of the first pattern 101 is connected to an axisymmetric second pattern 102. Adjacent first patterns 101 are connected through the ends of the second patterns 102.

[0048] Located around the image sensor, the N-sided polygon at the corner is connected to adjacent N-sided polygons by a second pattern 102. In Embodiment 1, the N-sided polygon is square, and the first pattern (excluding the corner) is connected to two second patterns 102, forming a connection structure between adjacent silicon pillars. The second patterns 102 are only provided between adjacent first patterns 101.

[0049] In another embodiment, the image sensor further includes a second periodically arranged main pixel (not shown). The main pixel comprises M sub-pixels, and the first trench also surrounds the main pixel. The light-transmitting area also corresponds to and surrounds M of the second pattern, where M ≥ 2.

[0050] Located inside the image sensor, the M sub-pixels corresponding to the same main pixel are connected by the second pattern 102. No second pattern 102 is provided between the main pixels; that is, the area between adjacent main pixels corresponding to adjacent first patterns 101 is a light-transmitting portion, and no second pattern 102 is provided between them. When the mask pattern is applied to the photolithography process of the image sensor, the substrate between adjacent silicon pillars corresponding to adjacent main pixels will be completely etched away subsequently.

[0051] The mask layout of this invention can design isolation trenches as short vias that are not directly connected to each other, thereby retaining finer silicon connections in the four corner directions of the silicon pillars. When the substrate is etched to a certain depth, a thin oxide layer is grown on the trench sidewalls to protect the silicon interconnect structure. Etching continues, and isotropic components are added, causing the bottom trenches to expand laterally. When the lateral etching reaches a sufficient width, the bottom of the silicon interconnect structure is completely etched and connected, thus suspending the entire interconnect structure to form the connection structure.

[0052] The trench is then closed by epitaxially growing a p-type doped layer. Due to growth priority, the top of the trench will close first, while a gap of a certain size will remain at the bottom. After closing the trench, the top of the substrate is smoothed by mechanical-chemical polishing, and then a top epitaxial layer is grown on it to fabricate a transistor.

[0053] Because of the interconnecting structures between the silicon pillars, lattice matching between them can be effectively ensured during high-temperature processes, acting similarly to seed crystals. Furthermore, due to the interconnecting structures along the angled connection lines of the silicon pillars, after the trench holes are closed at the top, there are no holes on the entire wafer surface. This avoids the influence of residual holes generated when the substrate is closed at the bottom, improving the quality of the top epitaxial layer and thus preventing any impact on surface-mount transistors.

[0054] One of the key aspects of process control for the lateral PN structure photodiode fabricated using the mask pattern described in this invention is the linewidth of the interconnect pattern. During the formation of the interconnect structure, it is necessary to ensure that the substrate at the bottom of the interconnect structure can be easily penetrated, increasing the process window and significantly reducing defects generated during the etching process and epitaxial trench sealing, thereby effectively reducing dark current and white spots in the image sensor.

[0055] In Embodiment 1, the second pattern is an axisymmetric, intersecting connection pattern with an intersection point in its center. Along the first and second directions, the width of the intersection point is greater than the width at other locations. Since a certain width is required for the connection structure to prevent breakage during epitaxy and etching, the second pattern needs to maintain a certain width. However, as the linewidth of the second pattern increases, the linewidth of the intersection point also increases. This can lead to the connection structure not being completely etched away during lateral etching, leaving a high concentration of N-type silicon between the silicon pillars, resulting in leakage. Furthermore, the inconsistency in linewidth between the intersection point and other locations can easily cause significant deviations in linewidth between the beam structures in actual manufacturing processes.

[0056] Please refer to the reference. Figure 3 and Figure 4 , Figure 3 A plan view showing the mask pattern of the mask layout according to Embodiment 2 of the present invention; Figure 4 This is a planar schematic diagram of the mask layout of the image sensor according to Embodiment 2 of the present invention.

[0057] In the second embodiment, the second pattern 203 can be an axisymmetric graphic, the middle part of which extends along the first direction (horizontally as shown in the figure), and each of the ends intersects the edge of the connected first pattern 101 at a predetermined angle.

[0058] The preset angle can be any angle and is not limited here. In Embodiment 1, the preset angle is an obtuse angle, and in Embodiment 2, the preset angle is 180°.

[0059] The second pattern 202 has a central portion extending along the first direction, the central portion including a first straight line portion C. The dimension of the first straight line portion C along the first direction is greater than the dimension along the second direction, for example, greater than twice the dimension along the second direction.

[0060] In Embodiment 2, the second pattern 202 further includes a second straight line portion A extending along the second direction. The second straight line portion A extends along the edge of the first pattern 101 and outwards from the corner of the first pattern 101. The second straight line portion A connects the first straight line portion C and the first pattern 101, and the extension line of the second straight line portion A intersects the extension line of the first straight line portion C. By designing the length of the second straight line portion A and its extension direction relative to the first pattern 101, it can accommodate deep grooves with different opening sizes.

[0061] In Embodiment 2, the first straight line portion C extends along the first direction, therefore, the axis of symmetry of the second pattern 202 extends along the first direction.

[0062] The linewidth of the first straight section C is less than or equal to the linewidth of the second straight section A, so as to avoid the second straight section A from being broken and thus unable to form a connection structure. Moreover, since the epitaxial growth direction of the overlapping line section is more than that of the second straight section A, by reducing the linewidth of the first straight section C, it is ensured that the substrate below the overlapping line section can be completely removed.

[0063] like Figure 3 As shown, the second pattern also has a connecting portion B that connects the first straight section and the second straight section. The extension direction of the first straight section C does not intersect with any of the first patterns and is orthogonal to the extension direction of the second straight section A. The first straight section C and the second straight section A are connected by the connecting portion B. The line width, line length and position of the connecting portion B can be adjusted according to the deep grooves with different opening sizes to meet the design requirements of highly integrated image sensors.

[0064] In Embodiment 2, the intersection point in the middle of the second pattern 102 has a linewidth dimension along the second direction, and its linewidth dimension is equal to the linewidth dimension of the first straight line portion C, thereby ensuring the consistency of the beam structure width in the epitaxial etching process and greatly reducing the deviation between beam structures. Furthermore, the thickness of the connecting structure can be easily adjusted to meet the influence of epitaxy and etching on the connecting structure in the actual process.

[0065] Figure 5 A plan view showing the mask pattern of the mask layout according to Embodiment 3 of the present invention; Figure 6 A planar schematic diagram of the mask layout of the image sensor according to Embodiment 3 of the present invention is shown.

[0066] In Embodiment 3, the second pattern 302 is an axisymmetric figure and includes a first straight line portion C' (middle part), a connecting portion B', and a second straight line portion A'.

[0067] The extension directions of the second straight line portion A in Embodiment 2 and the second straight line portion A' in Embodiment 3 are both parallel to one of the edges of the first pattern 101, but their extension directions relative to the first pattern 101 are different. As a result, the extension directions of the first straight line portion C in Embodiment 2 and the first straight line portion C' in Embodiment 3 are different, and the extension directions of the corresponding connecting portion B and connecting portion B' are also different.

[0068] In Embodiment 3, the first straight line portion C' extends along the second direction; therefore, the axis of symmetry of the second pattern 302 extends along the second direction. The dimension of the first straight line portion C' along the second direction is larger than its dimension along the first direction, for example, more than twice the dimension along the first direction. Second patterns with different extension directions can be designed based on the longitudinal and transverse opening dimensions of the deep trench.

[0069] In Embodiment 2, the axes of symmetry of adjacent second patterns 202 all extend along the first direction, and the axes of symmetry of second patterns 202 in the same row coincide. In Embodiment 3, the axes of symmetry of adjacent second patterns 302 all extend along the second direction, and the axes of symmetry of second patterns 302 in the same column coincide.

[0070] Figure 7 A plan view showing the mask pattern of the mask layout according to Embodiment 4 of the present invention; Figure 8 A planar schematic diagram of the mask layout of the image sensor according to Embodiment 4 of the present invention is shown.

[0071] In Embodiment 4, the symmetry axes of adjacent second patterns 402 extend in different directions. For example, the second pattern 402 whose symmetry axis extends along the first direction has a portion whose size along the first direction is greater than its size along the second direction, for example, more than twice the size along the second direction. The middle portion of the other second pattern 402 whose symmetry axis extends along the second direction has a portion whose size along the second direction is greater than its size along the first direction, for example, more than twice the size along the first direction. That is, the symmetry axes of adjacent second patterns 402 are orthogonal.

[0072] This invention utilizes a unique mask pattern to allow for a certain degree of interconnection between the upper parts of the silicon pillars during the etching process. This enables the epitaxial growth of lateral PN structures both inside and outside the deep trench, while preserving the optically isolated slit structure. During the epitaxial process, there is no lattice mismatch between the lateral PN structures, and the sealing of the top of the trench significantly reduces defects in epitaxial growth, effectively minimizing dark current and white spots in the image sensor.

[0073] Furthermore, at least a portion of the middle of the second pattern extends along the first direction or along the second direction, ensuring that the substrate at the bottom of the connecting structure can be easily penetrated, increasing the process window, while retaining the bottom trench for optical isolation between pixels.

[0074] Furthermore, at least a portion of the second pattern has a dimension along the first direction that is larger than its dimension along the second direction; and / or, at least a portion of the second pattern has a dimension along the second direction that is larger than its dimension along the first direction. The second straight section prevents the interconnect structure from breaking during epitaxy and etching, and the interconnect structure serves as a fulcrum for the subsequent growth of the top intrinsic layer, while maintaining a small interconnect structure width to facilitate easier subsequent lateral etching through the substrate from the bottom to form a photodiode-isolated slit structure.

[0075] Furthermore, the second pattern includes one of axisymmetric and rotationally symmetric graphics, and the size and position of the second pattern can be adjusted according to the deep grooves with different opening sizes to meet the design requirements of highly integrated image sensors.

[0076] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered exemplary and not restrictive in any way. Furthermore, it is clear that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude a plurality. Multiple elements recited in the apparatus claims may also be implemented by a single element. The terms "first," "second," etc., are used to denote names and do not indicate any particular order.

Claims

1. A method for designing a mask layout for forming an image sensor, the image sensor comprising: A plurality of sub-pixels arranged in a first period, a first trench surrounding the sub-pixels, and a connection structure spanning the first trench and connecting adjacent sub-pixels; The mask layout is characterized by comprising: a plurality of first patterns corresponding to the sub-pixels, a light-transmitting area surrounding the first patterns, and a second pattern passing through the light-transmitting area and connected to adjacent first patterns; wherein... The second pattern is set to form the connection structure and together with the light-transmitting area, forms the first trench; the mask pattern is used to form the photolithography process of the image sensor, and a connection structure is formed between the upper parts of the semiconductor island structure during the etching of the substrate to form the semiconductor island structure.

2. The design method as described in claim 1, characterized in that, The first pattern is arranged in a row along a first direction, and at least a portion of the middle part of the second pattern extends along the first direction.

3. The design method as described in claim 2, characterized in that, The first pattern is arranged in a row along the second direction, and at least part of the middle portion of the second pattern extends along the second direction.

4. The design method as described in claim 3, characterized in that, At least a portion of the middle portion of the second pattern has a dimension greater along the first direction than its dimension along the second direction; and / or, At least a portion of the middle part of the second pattern has a dimension along the second direction that is greater than its dimension along the first direction.

5. The design method as described in claim 4, characterized in that, The first direction is orthogonal to the second direction, and the second pattern is symmetrical.

6. The design method as described in claim 5, characterized in that, The second pattern includes one of an axisymmetric figure and a rotationally symmetric figure.

7. The design method as described in claim 6, characterized in that, At least a portion of the axisymmetric figure has its axis of symmetry extending along the first direction; and / or, at least a portion of the axisymmetric figure has its axis of symmetry extending along the second direction.

8. The design method as described in claim 7, characterized in that, The axes of symmetry of adjacent axisymmetric figures are orthogonal or coincident.

9. The design method as described in claim 4, characterized in that, The first pattern comprises an N-sided polygon, where N ≥ 3.

10. The design method as described in claim 9, characterized in that, The second pattern is provided between at least some of the N adjacent N-sided polygons.

11. The design method as described in claim 10, characterized in that, The second pattern has N ends, each of which is connected to a corner of the N-sided polygon.

12. The design method as described in claim 11, characterized in that, N=4, the first pattern includes quadrilaterals, and each end of the pattern intersects the sides of the quadrilaterals at a predetermined angle.

13. The design method as described in claim 12, characterized in that, The preset angle includes 180°.

14. The design method as described in claim 1, characterized in that, The image sensor includes: a second periodically arranged main pixel, the main pixel including M sub-pixels, the first groove also surrounding the main pixel; the light-transmitting area also correspondingly surrounds M second patterns, M≥2.

15. A mask layout for use in an image sensor, characterized in that, Designed using the design method described in any one of claims 1 to 14.

16. An image sensor, characterized in that, It is manufactured using the mask pattern as described in claim 15 during the formation process.

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