Doped sidewall spacers / etch stop layers for memory

Abstract

The present disclosure relates to doped sidewall spacers / etch stop layers for memory. Various embodiments of the present disclosure relate to an integrated circuit (IC) chip including a memory cell and having a sidewall spacer and / or etch stop layer that is doped to reduce charge accumulation at an interface between the sidewall spacer and the etch stop layer. The memory cell includes a bottom electrode, a data storage element overlying the bottom electrode, and a top electrode overlying the data storage element. The sidewall spacer overlies the bottom electrode on a common sidewall formed by the data storage element and the top electrode, and the etch stop layer lines the sidewall spacer. The sidewall spacer and the etch stop layer directly contact at the interface and form an electric dipole at the interface. The doping to reduce charge accumulation reduces an electric field generated by the electric dipole, thereby reducing the effect of the electric field on the memory cell.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more specifically, to a doped sidewall spacer / etch stop layer for a memory. Background Technology

[0002] Many modern electronic devices include non-volatile memory. Non-volatile memory is electronic memory that can store data even when power is off. Some promising candidates for next-generation non-volatile memory include magnetic random-access memory (MRAM). MRAM has a relatively simple structure and is compatible with complementary metal-oxide-semiconductor (CMOS) logic fabrication processes. Summary of the Invention

[0003] A first aspect of this disclosure relates to an integrated circuit (IC) chip, comprising: a bottom electrode; a data storage element overlying the bottom electrode; a top electrode overlying the data storage element; a sidewall spacer overlying the bottom electrode on a common sidewall formed by the data storage element and the top electrode; and an etch stop layer lining the sidewall spacer; wherein the sidewall spacer and the etch stop layer are in direct contact at an interface and form an electric dipole at the interface, and wherein the sidewall spacer and / or the etch stop layer are doped to reduce charge accumulation at the interface.

[0004] A second aspect of this disclosure relates to an integrated circuit (IC) chip, comprising: a bottom electrode; a magnetic tunnel junction (MTJ) element overlying the bottom electrode; a top electrode overlying the MTJ element; a sidewall spacer overlying the bottom electrode on the sidewall of the MTJ element; and an etch stop layer lining the sidewall spacer; wherein the etch stop layer is doped with an acceptor dopant and / or the sidewall spacer is doped with a donor dopant.

[0005] A third aspect of this disclosure relates to a method comprising: forming a data storage element and a top electrode stacked on a bottom electrode layer, wherein the data storage element is between the top electrode and the bottom electrode layer; forming a sidewall spacer on a first common sidewall formed by the data storage element and the top electrode; performing a first etch on the bottom electrode layer with the sidewall spacer in place to form a bottom electrode located below the data storage element; forming an etch stop layer covering the top electrode and lining a second common sidewall formed by the sidewall spacer and the bottom electrode; forming a via extending through the etch stop layer to the top electrode; and wherein forming the sidewall spacer includes doping the sidewall spacer, and / or wherein forming the etch stop layer includes doping the etch stop layer to reduce charge accumulation at an electric dipole between the etch stop layer and the sidewall spacer. Attached Figure Description

[0006] Various aspects of this disclosure can be best understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 Cross-sectional views of some embodiments of an integrated circuit (IC) chip are shown, which includes memory cells, wherein an etch stop layer is doped to reduce charge accumulation.

[0008] Figure 2 The description along Figure 1 Illustrations of nitrogen concentration curves for some embodiments of the etch stop layer.

[0009] Figure 3 It shows Figure 1 Top layout diagram of some embodiments of the memory cell.

[0010] Figures 4A-4H It shows Figure 1 Cross-sectional views of some alternative embodiments of the IC chip.

[0011] Figure 5 It shows Figure 1 Enlarged cross-sectional views of some more detailed embodiments of the IC chip.

[0012] Figures 6A-6C It shows Figure 5 Cross-sectional views of some alternative embodiments of the IC chip.

[0013] Figure 7A and Figure 7BCross-sectional views of some embodiments of an IC chip are shown, which includes memory cells integrated into separate single transistor single resistor (1T1R) cells, and wherein an etch stop layer is doped to reduce charge accumulation.

[0014] Figure 8 It shows Figure 7A and Figure 7B Top layout diagram of some embodiments of the IC chip.

[0015] Figure 9 It shows Figure 7B Cross-sectional views of some alternative embodiments of the IC chip.

[0016] Figures 10-15 , Figure 16A , Figure 16B and Figures 17-23 A series of cross-sectional views are shown of some embodiments of a method for forming an IC chip, which includes memory cells integrated into separate 1T1R cells, and wherein an etch stop layer is doped to reduce charge accumulation.

[0017] Figure 24 It shows Figures 10-15 , Figure 16A , Figure 16B and Figures 17-23 Block diagrams of some embodiments of the method.

[0018] Figures 25-27 It shows Figures 10-15 , Figure 16A , Figure 16B and Figures 17-23 A series of cross-sectional views of some first alternative embodiments of the method.

[0019] Figures 28-30 It shows Figures 10-15 , Figure 16A , Figure 16B and Figures 17-23 A series of cross-sectional views of some second alternative embodiments of the method.

[0020] Figures 31-33 It shows Figures 10-15 , Figure 16A , Figure 16B and Figures 17-23 A series of cross-sectional views of some third alternative embodiments of the method. Detailed Implementation

[0021] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0022] In addition, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used herein to facilitate the description of the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0023] An integrated circuit (IC) chip may include magnetic random access memory (MRAM) cells located in the interconnect structure of the IC chip. An MRAM cell may include a bottom electrode, a magnetic tunnel junction (MTJ) element above the bottom electrode, and a top electrode above the MTJ element. Furthermore, the MRAM cell may include sidewall spacers on a common sidewall formed by the MTJ element and the top electrode. The interconnect structure may include a top electrode via extending from the top electrode.

[0024] During the formation of the top electrode via, an intermetallic dielectric (IMD) layer is deposited on top of the MRAM cell, and the IMD layer is etched to form the via opening that exposes the top electrode. However, at least when the MRAM cell is small, the etchant used in the etching process may erode the sidewall spacers from the sides of the MTJ element and damage the MTJ element. For example, a small MRAM cell may be one in which the MTJ element has a width of less than about 22 nanometers or some other suitable value. To mitigate this concern, an etch stop layer can be deposited to cover the MRAM cell and line the sidewall spacers before depositing the IMD layer. The etch stop layer can then be used as an etch stop layer against the etching to prevent erosion of the sidewall spacers and, consequently, damage to the MTJ element.

[0025] Alumina can be used as the etch stop layer because the etchant used to perform the etching can be highly selective for the IMD layer relative to alumina. However, dipoles may form at the interface between the etch stop layer and the sidewall spacers, potentially leading to the accumulation of negative and positive charges at the interface in the etch stop layer and sidewall spacers, respectively. This charge accumulation can generate an electric field that degrades the coercive field of the MTJ element. For example, the electric field can reduce the coercive field, making it easier for the MTJ element to change between parallel and antiparallel states. Since these states are used to represent data, this degradation can further reduce data retention and decrease the reliability of the MRAM cell.

[0026] Various embodiments of this disclosure relate to memory cells including sidewall spacers and / or etch-stop layers, which are doped to reduce charge accumulation at the interface between the sidewall spacers and the etch-stop layer. For example, the memory cell can be as described above, but the etch-stop layer can be doped with acceptor dopant, and / or the sidewall spacers can be doped with donor dopant to reduce negative charge accumulation in the etch-stop layer. Acceptor dopant can induce holes that reduce negative charge. Donor dopant can induce electrons that cancel out positive charge in the sidewall spacers and / or bring the electronegativity of the sidewall spacers closer to that of the etch-stop layer, thereby reducing negative charge. In the case of an MRAM cell, the reduced charge accumulation can reduce or otherwise eliminate coercive field degradation. Therefore, MRAM cells can have high data retention and high reliability.

[0027] refer to Figure 1 A cross-sectional view 100 of some embodiments of an IC chip including a memory cell 102 is provided, wherein the etch stop layer 104 is doped (schematically shown by black dots) to reduce charge accumulation at the interface 106 between the etch stop layer 104 and the sidewall spacer 108. The memory cell 102 may be, for example, a spin-transfer torque (STT) MRAM cell, a spin-orbit torque (SOT) MRAM cell, some other suitable type of MRAM cell, a ferroelectric random access memory (FeRAM) cell, a resistive random access memory (RRAM), or some other suitable type of memory cell.

[0028] Memory cell 102 includes a bottom electrode 110, a data storage element 112 covering the bottom electrode 110, and a top electrode 114 covering the data storage element 112. A sidewall spacer 108 covers the bottom electrode 110 on a common sidewall formed by the data storage element 112 and the top electrode 114. Furthermore, the sidewall spacer 108 has a top surface recessed relative to the top surface of the top electrode 114, and has a pair of segments laterally sandwiched between the data storage element 112 and the top electrode 114. An etch stop layer 104 covers the sidewall spacer 108 and the top electrode 114. Furthermore, the etch stop layer 104 extends on the opposite side of the memory cell 102 and along the common sidewall formed by the sidewall spacer 108 and the bottom electrode 110.

[0029] The etch stop layer 104 and the sidewall spacer 108 are in direct contact at the interface 106 and are respectively doped and undoped. Further, the etch stop layer 104 and the sidewall spacer 108 form an electric dipole at the interface 106, and the etch stop layer 104 is doped to reduce charge accumulation at the interface 106. By reducing charge accumulation, this doping reduces the electric field generated by the electric dipole. Thus, the electric field has minimal impact on the electrical characteristics of the data storage element 112. Without this reduction, the electric field could substantially degrade the electrical characteristics of the data storage element 112. This could, in turn, cause failure of the memory cell 102 and / or reduce manufacturing yield.

[0030] As an example, suppose memory cell 102 is an MRAM cell and data storage element 112 is an MTJ element. Without doping, the electric field may substantially reduce the coercive voltage of the MTJ element, resulting in a potentially low coercive voltage. In some embodiments, this substantial reduction is more than 200 ozt or some other suitable amount. Due to this reduction, the MTJ element may be prone to changing between parallel and antiparallel states, and therefore the data retention and reliability of the MRAM cell may be poor. Therefore, at least in the case where memory cell 102 is an MRAM cell, doping can produce a higher coercive voltage, and thus result in good data retention and reliability.

[0031] An electric dipole may be formed, for example, due to a difference in oxygen areal density between the etch stop layer 104 and the sidewall spacers 108 and / or due to a large difference in electronegativity. In some embodiments, the electric dipole causes negative charge to accumulate in the etch stop layer 104 at interface 106, and positive charge to accumulate in the sidewall spacers 108 at interface 106. Such embodiments may occur, for example, when the etch stop layer 104 has a larger oxygen areal density and / or a smaller electronegativity than the sidewall spacers 108. In other embodiments, the electric dipole causes negative charge to accumulate in the sidewall spacers 108 at interface 106, and positive charge to accumulate in the etch stop layer 104 at interface 106. Such embodiments may occur, for example, when the etch stop layer 104 has a smaller oxygen areal density and / or a larger electronegativity than the sidewall spacers 108.

[0032] When negative charge accumulates in the etch stop layer 104, the etch stop layer 104 can be doped with an acceptor dopant. The acceptor dopant generates holes that cancel out the negative charge in the etch stop layer 104. When positive charge accumulates in the etch stop layer 104, the etch stop layer 104 can be doped with a donor dopant. The donor dopant generates electrons that cancel out the positive charge in the etch stop layer 104. The electric dipole has zero net charge, such that reducing the accumulated charge in the etch stop layer 104 has the effect of reducing the accumulated charge in the sidewall spacers 108, and vice versa.

[0033] An acceptor dopant is an atom with fewer valence electrons than the atom it replaces. For example, nitrogen can be an acceptor dopant when replacing oxygen in a metal oxide because nitrogen has five valence electrons while oxygen has six. Conversely, a donor dopant is an atom with more valence electrons than the atom it replaces. For example, chlorine can be a donor dopant when replacing oxygen in silicon oxide because chlorine has seven valence electrons while oxygen has six.

[0034] Continue to refer to Figure 1An intermetallic dielectric (IMD) layer 116 is overlaid on an etch stop layer 104, and a top electrode via 118t and a top electrode line 120t are inserted into the IMD layer 116. Furthermore, the top electrode via 118t extends from the top electrode line 120t to the top electrode 114. As will be seen below, the etch stop layer 104 can be used as an etch stop layer when etching is performed to form a via opening (within which the top electrode via 118t is formed). Therefore, the etchant used for etching can have a lower etch rate relative to the IMD layer 116 and the etch stop layer 104. This lower etch rate can be, for example, about 1 / 20th of the etch rate of the IMD layer 116. th 1 / 50 th 1 / 100 th Or some other suitable fraction of the etching rate. In some embodiments, the lower etching rate is or is less than about 26.6 angstroms per minute (A / min), about 10 A / min, or some other suitable value.

[0035] At least when the memory cell 102 is small, the etchant used for etching may erode the sidewall spacer 108 from the side without the etch stop layer 104 and damage the data storage element 112. For example, when the width W of the memory cell 102 is small... m The memory cell 102 can be small, typically less than about 22 nanometers or some other suitable value. However, because the etchant can have a lower etch rate relative to the IMD layer 116 against the etch stop layer 104, the etch stop layer 104 can prevent the sidewall spacers 108 and the data storage element 112 from being eroded and damaged. Furthermore, it has been recognized that doping the etch stop layer 104 to reduce charge accumulation at the interface 106 does not significantly affect this lower etch rate.

[0036] In some embodiments, the etchant also has a lower etch rate on the etch stop layer 104 relative to the sidewall spacer 108. For example, the etch rate of the etchant on the etch stop layer 104 may be about 1 / 20, 1 / 50, 1 / 100, or some other suitable fraction of the etch rate of the sidewall spacer 108. In some embodiments, when etched by this etchant or some other suitable etchant, the etch residues of the sidewall spacer 108 and the etch residues of the etch stop layer 104 result in the etch residues of the etch stop layer 104 having a higher boiling point than the etch residues of the sidewall spacer 108. It has been recognized that a higher boiling point corresponds to a lower etch rate, and a lower boiling point corresponds to a higher etch rate. For example, the etchant may be or include carbon tetrafluoride (e.g., CF4) or some other suitable etchant. In some embodiments, the etch residues of the etch stop layer 104 have a boiling point of about or greater than about -86 degrees Celsius or some other suitable value.

[0037] In some embodiments, the etch stop layer 104 is or comprises a metal oxide, and / or a dielectric having a high dielectric constant greater than about 3.9, 10, or some other suitable value. In some embodiments, the etch stop layer 104 without dopant is or comprises aluminum oxide (e.g., Al₂O₃). x ), tantalum oxide (e.g., TaO) x ), titanium dioxide (e.g., TiO2) x ), Ruthenium oxide (e.g., RuO) x ), silver oxide (e.g., AgO) x ), tungsten oxide (e.g., WO3) x ), vanadium oxide (e.g., VO) x ), tin oxide (e.g., SnO) x ), zirconium oxide (e.g., ZrO) x ), hafnium oxide (e.g., HfO) x ), Lanthanum oxide (e.g., LaO) x ), magnesium oxide (e.g., MgO) x ), calcium oxide (e.g., CaO) x ( ), some other suitable materials, or any combination thereof. Furthermore, in some embodiments, the dopant-free etch stop layer 104 has a metal atomic percentage of less than about 40%, 30%, or some other suitable value.

[0038] In some embodiments where the etch stop layer 104 is doped with an acceptor dopant, the acceptor dopant is or includes nitrogen (e.g., N), hydrogen (e.g., H), boron (e.g., B), lithium (e.g., Li), carbon (e.g., C), phosphorus (e.g., P), gallium (e.g., Ga), aluminum (e.g., Al), ammonia (e.g., NH3), some other suitable acceptor dopant, or any combination thereof. Therefore, the acceptor dopant can be metallic or non-metallic. In some embodiments where the etch stop layer 104 is doped with a metallic acceptor dopant, the percentage of metal atoms in the etch stop layer 104 is greater than about 40%, 50%, or some other suitable value. In some embodiments, doping the etch stop layer 104 with a metallic acceptor dopant can increase the percentage of metal atoms in the etch stop layer 104 from less than a threshold percentage to greater than a threshold percentage, where the threshold percentage is 40% or some other suitable percentage.

[0039] In some embodiments where the etch stop layer 104 is doped with an acceptor dopant, the etch stop layer 104 is or includes nitrogen-doped aluminum oxide (e.g., AlON), hydrogen-doped aluminum oxide (e.g., AlOH), boron-doped aluminum oxide (e.g., AlOB), carbon-doped aluminum oxide (e.g., AlOC), lithium-doped aluminum oxide (e.g., AlOLi), phosphorus-doped aluminum oxide (e.g., AlOP), nitrogen-doped tantalum oxide (e.g., TaON), nitrogen-doped titanium oxide (e.g., TiON), aluminum-doped tantalum oxide (e.g., TaAlO), aluminum-doped titanium oxide (e.g., TiAlO), and nitrogen-doped... Aluminum (e.g., AlN), nitrogen-doped titanium (e.g., TiN), nitrogen-doped ruthenium oxide (e.g., RuON), hydrogen-doped silver oxide (e.g., AgOH), nitrogen-doped tungsten oxide (e.g., WON), nitrogen-doped vanadium oxide (e.g., VON), hydrogen-doped strontium oxide (e.g., SnOH), hydrogen-doped zirconium oxide (e.g., ZrON), nitrogen-doped hafnium oxide (e.g., HfON), nitrogen-doped lanthanum oxide (e.g., LaON), hydrogen-doped magnesium oxide (e.g., MgOH), hydrogen-doped calcium oxide (e.g., CaOH), some other suitable doping materials, or any combination thereof.

[0040] In some embodiments, the thickness T of the etch stop layer 104 e For approximately 10-1000 angstroms, approximately 10-500 angstroms, approximately 500-1000 angstroms, or some other suitable value. If the thickness T... e If the thickness is too small (e.g., less than about 10 angstroms), the etch stop layer 104 may not be able to protect the sidewall spacers 108 from erosion during the formation of the top electrode via 118t, potentially damaging the data storage element 112. If the thickness T... e If the size is too large (e.g., greater than about 1000 angstroms), the scaling down of IC chips may be hindered.

[0041] In some embodiments, the doping concentration of the etch stop layer 104 is three times or more the concentration of any impurities in the etch stop layer 104 prior to doping, and / or three times or more the concentration of any impurities in the sidewall spacers 108. In some embodiments where the etch stop layer 104 is doped with nitrogen, the percentage of nitrogen in the etch stop layer 104 exceeds about 300 counts / second, 500 counts / second, or some other suitable value according to secondary-ion mass spectrometry (SIMS).

[0042] In some embodiments, the charging voltage of the etch stop layer 104 is lower than its charging voltage when it is undoped. For example, the charging voltage can be determined by a QUANTOX processing tool or some other suitable processing tool. For example, such a processing tool can introduce charge into the etch stop layer 104 until a neutral state is achieved. In some embodiments where the etch stop layer 104 is alumina doped with ammonia (e.g., NH3), the charging voltage can be or less than about 1.53 volts or some other suitable value.

[0043] In some embodiments, the sidewall spacer 108 is or includes silicon nitride (e.g., SiN). x Silicon carbide (e.g., SiC), silicon carbide (e.g., SiOC), silicon oxynitride (e.g., SiON), silicon oxide (e.g., SiO) x ), some other suitable materials, or any combination thereof. In some embodiments, the thickness T of the sidewall spacer 108 s The values ​​are approximately 10-1000 angstroms, approximately 10-500 angstroms, approximately 500-1000 angstroms, or some other suitable value. In at least some embodiments where the sidewall spacer 108 is substantially composed of silicon nitride, silicon carbide, or some other suitable oxygen-free material, the sidewall spacer 108 may include a native oxide layer at the interface 106. For example, the native oxide layer may promote the formation of an electric dipole at the interface 106.

[0044] In some embodiments, the bottom electrode 110 and / or the top electrode 114 is or includes tungsten (e.g., W), tantalum nitride (e.g., TaN), titanium nitride (e.g., TiN), ruthenium (e.g., Ru), molybdenum (e.g., Mo), carbon (e.g., C), some other suitable materials, or any combination thereof. In some embodiments, the thickness of the bottom electrode 110 and / or the thickness of the top electrode 114 is about 100-1000 angstroms, about 100-500 angstroms, about 500-1000 angstroms, or some other suitable thickness.

[0045] refer to Figure 2 ,against Figure 1 Some embodiments of the IC chip (where the etch stop layer 104 is nitrogen-doped) are described along... Figure 1 The curve 200 shows some embodiments of the nitrogen concentration curve 202 for line A. Curve 202 increases continuously from the sidewall of the etch stop layer 104 away from the memory cell 102 to the midpoint between the interface 106 and the sidewall spacer 108 facing the memory cell 102. Furthermore, curve 202 decreases continuously from this midpoint to the sidewall of the sidewall spacer 108. For embodiments of the memory cell 102 where negative and positive charges accumulate in the etch stop layer 104 and the sidewall spacer 108, respectively, nitrogen can be, for example, an acceptor dopant to reduce charge accumulation at the interface 106.

[0046] refer to Figure 3 Provided Figure 1 Top layout diagram 300 of some embodiments of memory cell 102. Figure 1 The cross-sectional view 100 can be taken, for example, along line B, but other suitable locations are also possible. The memory cell 102, the top electrode via 118t (shown in dashed lines), and the sidewall spacer 108 have a rounded top layout. Furthermore, a portion of the etch stop layer 104 shown in the top layout view 300 has a rounded top layout. However, note that outside of the top layout view 300, the etch stop layer 104 covers the sidewall spacer 108 and the memory cell 102 (see, for example...). Figure 1 In an alternative embodiment, the memory cell 102, the top electrode via 118t, the sidewall spacer 108, a portion of the etch stop layer 104, or any combination thereof, may have other suitable top layouts.

[0047] refer to Figures 4A-4H Provided Figure 1 Cross-sectional views 400A-400H show some alternative embodiments of the IC chip.

[0048] exist Figure 4A middle, Figure 1 The etch stop layer 104 is divided into a doped etch stop layer 104a and an undoped etch stop layer 104b. The doped etch stop layer 104a is located between the undoped etch stop layer 104b and the sidewall spacer 108. Furthermore, the doped etch stop layer 104a directly contacts the sidewall spacer 108 at the interface 106.

[0049] As described above, the etch stop layer 104 can protect the sidewall spacers 108 and the data storage element 112 when etching is performed to form a via opening (in which the top electrode via 118t is formed). The etchant used for etching can etch the doped portion of the etch stop layer 104 at a higher rate than the undoped portion of the etch stop layer 104. Therefore, the doped portion of the etch stop layer 104 can provide less protection than the undoped portion of the etch stop layer 104. Therefore, by dividing the etch stop layer 104 such that the undoped etch stop layer 104b is located on the outer surface of the etch stop layer 104 and the doped etch stop layer 104a is located on the inner surface of the etch stop layer 104, the protection of the etch stop layer 104 can be maximized while still reducing charge accumulation at the interface 106.

[0050] The doped etch stop layer 104a and the undoped etch stop layer 104b are related to... Figure 1The etch stop layer 104 described is the same, except that the doped etch stop layer 104a is doped and the undoped etch stop layer 104b is undoped. The doped etch stop layer 104a reduces charge accumulation at interface 106, and the undoped etch stop layer 104b provides enhanced etch protection when forming the top electrode via 118t.

[0051] In some embodiments, the thickness T of the doped etch stop layer 104a de For approximately 1-10 angstroms, approximately 1-5 angstroms, approximately 5-10 angstroms, or some other suitable value. If the thickness T... de If the doped etch stop layer 104a is too small (e.g., less than about 1 angstrom), it may not be able to reduce charge accumulation at the interface 106.

[0052] In some embodiments, the percentage of metal atoms in the undoped etch stop layer 104b is less than the percentage of metal atoms in the doped etch stop layer 104a. For example, the percentage of metal atoms in the undoped etch stop layer 104b may be less than about 40%, 30%, or some other suitable value, while the percentage of metal atoms in the doped etch stop layer 104a may be greater than about 40%, 50%, or some other suitable value. In some embodiments, the doping concentration of the doped etch stop layer 104a is three, five, ten, or more times the doping concentration of any impurities in the undoped etch stop layer 104b. In some embodiments, the undoped etch stop layer 104b is substantially composed of a first material, and the doped etch stop layer 104a is substantially composed of the first material and a dopant to reduce charge accumulation.

[0053] exist Figure 4B In this configuration, the sidewall spacer 108 is doped (schematically shown by black dots), instead of the etch stop layer 104, to reduce charge accumulation at the interface 106 between the etch stop layer 104 and the sidewall spacer 108. Therefore, the etch stop layer 104 is undoped, while the sidewall spacer 108 is doped.

[0054] In the case where positive charge accumulates in the sidewall spacer 108 at interface 106 and therefore negative charge accumulates in the etch stop layer 104 at interface 106, the sidewall spacer 108 may be doped with a donor dopant. In the case where negative charge accumulates in the sidewall spacer 108 at interface 106 and therefore positive charge accumulates in the etch stop layer 104 at interface 106, the sidewall spacer 108 may be doped with an acceptor dopant. In both cases, the dopant makes the electronegativity of the sidewall spacer 108 closer to that of the etch stop layer 104, thereby reducing charge accumulation.

[0055] As described above, by reducing charge accumulation, this doping reduces the electric field generated by the electric dipole. Thus, the electric field has minimal impact on the electrical characteristics of the data storage element 112. Without this reduction, the electric field could substantially degrade the electrical characteristics of the data storage element 112. This could, in turn, lead to failure of the memory cell 102 and / or reduced manufacturing yield.

[0056] In some embodiments where the sidewall spacer 108 is doped with a donor dopant, the donor dopant is or includes fluorine (e.g., F), chlorine (e.g., Cl), bromine (e.g., Br), some other suitable donor dopant, or any combination thereof. In some embodiments where the sidewall spacer 108 is doped with a donor dopant, the sidewall spacer 108 is or includes nitrogen-doped silicon oxide (e.g., SiON), sulfur-doped silicon nitride (e.g., SiSN), carbon-doped silicon nitride (e.g., SiNC), carbon-doped silicon phosphide (e.g., SiPC), fluorine-doped silicon oxide (e.g., SiOF), chlorine-doped silicon oxide (e.g., SiOCl), some other suitable dopant materials, or any combination thereof.

[0057] In some embodiments, the doping concentration of the sidewall spacer 108 is three times or more the concentration of any impurities in the sidewall spacer 108 before doping, and / or three times or more the concentration of any impurities in the etch stop layer 104. In some embodiments, the charging voltage of the sidewall spacer 108 is lower than its charging voltage when it is undoped. Similar to the etch stop layer 104, the charging voltage can be determined, for example, by a QUANTOX processing tool or some other suitable processing tool.

[0058] exist Figure 4C In, with Figure 4B Similarly, the sidewall spacers 108 are doped (schematically shown by black dots), instead of the etch stop layer 104 being doped. Furthermore, Figure 4B The sidewall spacers 108 are divided into doped sidewall spacers 108a and undoped sidewall spacers 108b. The doped sidewall spacers 108a are located between the undoped sidewall spacers 108b and the etch stop layer 104. Furthermore, the doped sidewall spacers 108a directly contact the etch stop layer 104 at the interface 106.

[0059] As described above, the etchant used to form the via opening (in which the top electrode via 118t is formed) may corrode the sidewall spacer 108 and the data storage element 112. An etch stop layer 104 protects the sidewall spacer 108 and the data storage element 112. However, in the event of failure of the etch stop layer 104, the sidewall spacer 108 can serve as the last line of protection for the data storage element 112.

[0060] The etchant can etch the doped portions of the sidewall spacer 108 at a higher rate than it etches the undoped portions. Therefore, the doped portions of the sidewall spacer 108 provide less protection to the data storage element 112 compared to the undoped portions. Thus, by dividing the sidewall spacer 108 such that the undoped sidewall spacer 108b is located at the data storage element 112 and the doped sidewall spacer 108a is located at the interface 106, the protection provided by the sidewall spacer 108 to the data storage element 112 can be maximized while still reducing charge accumulation at the interface 106.

[0061] The doped sidewall spacer 108a and the undoped sidewall spacer 108b are related to... Figure 1 and Figure 4B The sidewall spacer 108 is the same as described, except that the doped sidewall spacer 108a is doped and the undoped sidewall spacer 108b is undoped. The doped sidewall spacer 108a reduces charge accumulation at interface 106, and the undoped sidewall spacer 108b provides enhanced etch protection when forming the top electrode via 118t.

[0062] In some embodiments, the thickness T of the doped sidewall spacer 108a ds For approximately 10-100 angstroms, approximately 10-50 angstroms, approximately 50-100 angstroms, or some other suitable value. If the thickness T... ds If the doped sidewall spacer 108a is too small (e.g., less than about 50 angstroms), it may not be able to reduce charge accumulation at interface 106.

[0063] In some embodiments, the doping concentration of the doped sidewall spacer 108a is three, five, ten, or more times that of any impurity in the undoped sidewall spacer 108b. In some embodiments, the undoped sidewall spacer 108b is substantially composed of a first material, and the doped sidewall spacer 108a is substantially composed of the first material and a dopant to reduce charge accumulation.

[0064] exist Figure 4D In this process, the sidewall spacers 108 are also doped (schematically shown by black dots) to reduce charge accumulation at the interface 106 between the etch stop layer 104 and the sidewall spacers 108. Therefore, both the etch stop layer 104 and the sidewall spacers 108 are doped. The etch stop layer 104 can be, for example, related to... Figure 1 Doped as described, while the sidewall spacer 108 can, for example, be related to Figure 4B It was doped as described.

[0065] exist Figure 4EIn the process, the etch stop layer 104 is divided into a doped etch stop layer 104a and an undoped etch stop layer 104b, as per the description of the etch stop layer 104a. Figure 4A As described. Furthermore, the sidewall spacers 108 are divided into doped sidewall spacers 108a and undoped sidewall spacers 108b, as per [the description of the sidewall spacers]. Figure 4C As described.

[0066] exist Figure 4F In this configuration, the top surfaces of the sidewall spacer 108 and the top electrode 114 are curved. Furthermore, the bottom surface of the top electrode via 118t surrounds the top of the memory cell 102 and extends along the sidewall of the sidewall spacer 108. Therefore, the etch stop layer 104 is located below the top electrode via 118t and does not extend along the top surface of either the sidewall spacer 108 or the top surface of the top electrode 114.

[0067] exist Figure 4G In the memory cell 102, a first seed layer 402 is located between a bottom electrode 110 and a data storage element 112, and a second seed layer 404 is located between the data storage element 112 and a top electrode 114. The first seed layer 402 can be used as a crystalline seed during epitaxial growth or otherwise deposition of the data storage element 112, while the second seed layer 404 can be used as a seed during epitaxial growth or otherwise deposition of the top electrode 114.

[0068] In some embodiments, at the interface where the bottom electrode 110 directly contacts the first seed layer 402, the bottom electrode 110 is or comprises titanium nitride, and the first seed layer 402 is or comprises tantalum nitride. However, other suitable materials are also feasible. In some embodiments, at the interface where the top electrode 114 directly contacts the second seed layer 404, the top electrode 114 is or comprises tungsten, and the second seed layer 404 is or comprises ruthenium. However, other suitable materials are also feasible.

[0069] exist Figure 4H In the middle, the sidewall spacer 108 includes a sidewall spacer body 108c and a natural oxide layer 108d lining the sidewall spacer body 108c at interface 106. The sidewall spacer body 108c and its relation to... Figure 1 The sidewall spacer 108 described is identical, except that the native oxide layer 108d is the native oxide of the sidewall spacer body 108c. In some embodiments, the sidewall spacer body 108c is oxygen-free or substantially oxygen-free. In some embodiments, the sidewall spacer body 108c is or includes silicon nitride (e.g., SiN). x), silicon carbide (e.g., SiC), some other suitable oxygen-free material, or any combination thereof, and / or the native oxide layer 108d is or includes silicon oxynitride, silicon carbide, some other suitable oxide material, or any combination thereof.

[0070] Although Figures 4F-4H Described Figure 1 These are variations of the IC chip embodiments described, but these variations can also be applied to... Figures 4A-4E An embodiment of the IC chip in any of them. For example, Figure 4A The sidewall spacer 108 may include Figure 4H The sidewall spacer body 108c and the natural oxide layer 108d. Similarly, although Figures 4A-4E Described Figure 1 These are variations of the embodiments of the IC chip, but these variations can also be applied to... Figures 4F-4H An embodiment of the IC chip in any of them. For example, Figure 4H The side wall spacer 108 can be as follows Figure 4B Doped as in, and / or as Figure 4C They are divided into doped sidewall spacers 108a and undoped sidewall spacers 108b, as shown in the diagram.

[0071] refer to Figure 5 Provided Figure 1 A magnified cross-sectional view 500 shows some more detailed embodiments of the IC chip. The memory cell 102 is overlaid on the bottom electrode line 120b and electrically coupled to the bottom electrode line 120b through the bottom electrode via 118b and the bottom electrode barrier 502.

[0072] The bottom electrode block 502 is located below the memory cell 102 on the bottom surface of the bottom electrode 110 and forms a common sidewall with the bottom electrode 110 and the sidewall spacer 108. Furthermore, the bottom electrode block 502 is configured to prevent material from diffusing from below the memory cell 102 into the memory cell 102. For example, the bottom electrode block 502 may be configured to prevent copper or other suitable materials from diffusing into the memory cell 102 from the bottom electrode line 120b or some other suitable structure located below the memory cell 102. Diffusion of material into the memory cell 102 may alter the electrical characteristics of the memory cell 102, thereby reducing the performance of the memory cell 102 and / or reducing batch manufacturing yield.

[0073] The bottom electrode via 118b is located between the bottom electrode block 502 and the bottom electrode line 120b, and extends from the bottom electrode block 502 to the bottom electrode line 120b through the first via dielectric layer 504 and the second via dielectric layer 506. Furthermore, the bottom electrode via 118b includes a conductor 118b1 and a conductive liner 118b2. The conductive liner 118b2 covers the underside of the conductor 118b1 and extends along the bottom surface and sidewalls of the conductor 118b1.

[0074] In some embodiments, the conductive liner 118b2 is configured to enhance adhesion between the first and second via dielectric layers 504, 506 and the conductor 118b1. Furthermore, in some embodiments, the conductive liner 118b2 is configured to prevent material from diffusing from below the bottom electrode via 118b into the memory cell 102 (similar to diffusion into the bottom electrode barrier 502). As described above, diffusion into the memory cell 102 can degrade performance and / or reduce batch manufacturing yield.

[0075] The first and second via dielectric layers 504 and 506 are made of different materials and separate the IMD layer 116 into a lower and upper portion. Furthermore, a buffer layer 508 separates the etch stop layer 104 from the upper portion of the IMD layer 116. In an alternative embodiment, the first via dielectric layer 504 or the second via dielectric layer 506 is omitted. Furthermore, in an alternative embodiment, the buffer layer 508 is omitted.

[0076] Data storage element 112 is an MTJ element and includes a free element 112f, a reference element 112r, and a barrier element 112b. In alternative embodiments, data storage element 112 is a ferroelectric element or some other suitable data storage element. The free element 112f and the reference element 112r have separate magnetizations. The magnetization of the free element 112f can be freely changed, while the magnetization of the reference element 112r is fixed. When the magnetizations are parallel, charge carriers can tunnel through the barrier element 112b, and the memory cell 102 can have a low-resistance state. When the magnetizations are antiparallel, charge carriers are less likely to tunnel through the barrier element, and the memory cell 102 can be in a high-resistance state. Depending on whether the memory cell 102 is in a high-resistance state or a low-resistance state, the memory cell 102 stores binary "1" or "0". In some embodiments, the barrier element 112b is or includes magnesium oxide and / or some other suitable material.

[0077] In some embodiments, the bottom electrode block 502 is or includes tantalum nitride (e.g., TaN), titanium nitride (e.g., TiN), tungsten nitride (e.g., WN), tungsten carbide nitride (e.g., WCN), molybdenum nitride (e.g., MoN), some other suitable material, or any combination thereof. In some embodiments, the thickness of the bottom electrode block 502 is about 10-200 angstroms or some other suitable value. In some embodiments, the top surface of the conductor 118b1 has a recessed portion at the interface between the conductor 118b1 and the bottom electrode block 502. In some embodiments, the entire top surface of the conductor 118b1 may be substantially flush with the top surface of the second via dielectric layer 506.

[0078] In some embodiments, the first via dielectric layer 504 is or includes silicon carbide (e.g., SiC), silicon carbide (e.g., SiOC), tantalum carbide (e.g., TaOC), aluminum carbide (e.g., AlOC), some other suitable carbides or other materials, or any combination thereof. In some embodiments, the second via dielectric layer 506 is or includes silicon oxide (e.g., SiO2). x ), aluminum oxide (e.g., AlO) x ), tantalum oxide (e.g., TaO) x ), Hafnium oxide (HfO) x ), zirconium oxide (e.g., ZrO), x The dielectric material may be silicon dioxide (e.g., SiOC), some other suitable oxides or other materials, or any combination thereof. In some embodiments, the thickness of the first via dielectric layer 504 and / or the thickness of the second via dielectric layer 506 is about 50-500 angstroms or some other suitable value.

[0079] Although Figure 5 Used Figure 1 The embodiment of the sidewall spacer 108 and the etch stop layer 104, but Figures 4A-4H Embodiments of either the sidewall spacer 108 or the etch stop layer 104 are also feasible. For example, Figures 6A-6C Provided Figure 5 Cross-sectional views 600A-600C show some alternative embodiments of the IC chip, in which each uses Figures 4A-4C An embodiment of the sidewall spacer 108 and the etch stop layer 104.

[0080] refer to Figure 7ACross-sectional view 700A of some embodiments of an IC chip including memory cells 102 is provided, wherein the memory cells 102 are integrated into a single single transistor single resistor (1T1R) cell 702, and wherein the etch stop layer 104 is doped to reduce charge accumulation. Each memory cell 102 (and the corresponding sidewall spacer 108 and etch stop layer 104) is associated with... Figure 5 The descriptions are the same for the corresponding components.

[0081] The 1T1R cell 702 includes a separate drain region 704 and a separate drain-side conductive path 706. The drain regions 704 are doped regions of the substrate 708, and each has a doping type opposite to that of its adjacent regions on the substrate 708. Furthermore, the drain regions 704 are electrically isolated from each other by a trench isolation structure 710 and partially surround or define an access transistor 712 (partially shown) for individually selecting the memory cell 102. The trench isolation structure 710 extends to the top of the substrate 708 and comprises silicon oxide and / or some other suitable dielectric material. The substrate 708 may be, for example, a bulk silicon substrate or some other suitable semiconductor substrate.

[0082] A drain-side conductive path 706 electrically couples the drain region 704 to the memory cell 102. Furthermore, the drain-side conductive path 706 is formed by an interconnect structure 714 in which the memory cell 102 is disposed. The interconnect structure 714 includes multiple lines 120 and multiple vias 118. The multiple lines 120 include a top electrode line 120t and a bottom electrode line 120b. In some embodiments, the top electrode line 120t corresponds to a bit line BL. The multiple vias 118 include a top electrode via 118t. The horizontal vias 118 closest to the substrate 708 are located in an interlayer dielectric (ILD) layer 716, while the remaining horizontal vias 118 and lines 120 are located in an IMD layer 116. Furthermore, the multiple vias 118 and multiple lines 120 are covered by a first passivation layer 718 and a second passivation layer 720. The lines 120 and vias 118 can be or include, for example, copper, aluminum, some other suitable metal, or any combination thereof.

[0083] A peripheral region 722 on one side of the 1T1R cell 702 houses a peripheral device 724 (only one is shown). The peripheral device 724 can be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), a fin field-effect transistor (finFET), a gate-all-around field-effect transistor (GAA FET), or some other suitable type of semiconductor device. Each peripheral element 724 includes a pair of source / drain regions 726 in the substrate 708, a gate electrode 728, and a gate dielectric layer 730. The gate electrode 728 and the gate dielectric layer 730 are stacked between the source / drain regions 726 such that the gate dielectric layer 730 separates the gate electrode 728 from the substrate 708.

[0084] refer to Figure 7B Along with interception Figure 7A The cross-sectional view of 700A provides an orthogonal axis. Figure 7A A cross-sectional view 700B of some embodiments of the IC chip. The 1T1R cell 702 includes a separate memory cell 102, a separate drain-side conductive path 706, a separate access transistor 712, and a separate source-side conductive path 732. Each memory cell 102 (and corresponding sidewall spacers 108 and etch stop layers 104) is associated with... Figure 5 The descriptions are the same for the corresponding components.

[0085] Access transistor 712 is located on substrate 708, between substrate 708 and interconnect structure 714, and electrically isolated by trench isolation structure 710. Access transistor 712 includes a separate drain region 704, a separate source region 734, a separate gate dielectric layer 736, and a separate gate electrode 738. Gate electrode 738 is correspondingly overlaid on gate dielectric layer 736 and forms a word line in some embodiments. Drain and source regions 704 and 734 are doped regions of substrate 708, and each has a doping type opposite to that of adjacent regions of substrate 708. Drain region 704 is correspondingly adjacent to the drain side of gate electrode 738, and source region 734 is correspondingly adjacent to the source side of gate electrode 738. Access transistor 712 can be, for example, a MOSFET, a FinFET, a GAA FET, or some other suitable type of semiconductor device.

[0086] The drain-side conductive path 706 electrically couples the drain region 704 to the memory cell 102, and the source-side conductive path 732 electrically couples the source region 734 to the source line SL. The drain-side and source-side conductive paths 706 and 732 are formed by multiple lines 120 and multiple vias 118.

[0087] refer to Figure 8 Provided Figure 7A and Figure 7BTop layout diagram 800 of some embodiments of IC chips. Figure 7A and Figure 7B Cross-sectional views 700A and 700B can be taken, for example, along lines C and D or other suitable locations. The IC chip includes multiple IT1R cells 702 arranged in multiple rows and columns, thereby forming a memory array 802. Peripheral devices 724 surround the memory array 802 at a peripheral region 722 of the IC chip. The peripheral devices 724 can, for example, implement read / write circuitry and / or other suitable circuitry for operating the IT1R cells 702.

[0088] refer to Figure 9 Provided Figure 7B Cross-sectional view 900 of some alternative embodiments of the IC chip, in which the positions of the drain region 704 and the source region 734 are interchanged. Furthermore, memory cell 102 overlies the source region 734, opposite to the drain region 704.

[0089] Although Figure 7A , Figure 7B and Figure 9 Is using Figure 5 The memory cell embodiment, sidewall spacer embodiment, and etch stop layer embodiment are shown, but alternatively, they can be used. Figures 1-3 , Figures 4A-4H and Figures 6A-6C Examples of any one or a combination thereof. For example, Figure 4A The etch stop layer embodiment in the text can be used alternatively for Figure 7A , Figure 7B and Figure 9 The etch stop layer 104 is configured such that it includes a doped etch stop layer 104a and an undoped etch stop layer 104b. As another example, Figure 4C The sidewall spacer embodiment can be used alternatively for Figure 7A , Figure 7B and Figure 9 The sidewall spacer 108 in the middle includes a single doped sidewall spacer 108a and a single undoped sidewall spacer 108b.

[0090] refer to Figures 10-15 , Figure 16A , Figure 16B and Figures 17-23A series of cross-sectional views 1000-1500, 1600A, 1600B, and 1700-2300 are shown, illustrating some embodiments of a method for forming an IC chip, which includes memory cells integrated into individual 1T1R cells, and wherein an etch stop layer is doped to reduce charge accumulation. Cross-sectional views 1000-1500, 1600A, 1600B, and 1700-2300 may, for example, correspond to... Figure 7A And therefore it can be shown, for example Figure 7A and Figure 7B The formation of the IC chip. Furthermore, cross-sectional views 1000-1500, 1600A, 1600B, and 1700-2300 can, for example, be along... Figure 8 Cut off line C in the middle.

[0091] like Figure 10 As shown in cross-sectional view 1000, interconnect structure 714 is partially formed on and electrically coupled to a plurality of access transistors 712 (shown only partially) and peripheral devices 724. The access transistors 712 are individually and correspondingly located at the formed plurality of ITR cells 702, and the peripheral devices 724 are located at the peripheral region 722 of the formed IC chip. The access transistors 712 and peripheral devices 724 are formed on and partially by substrate 708 and are separated by trench isolation structures 710 extending into substrate 708. The access transistors 712 and peripheral devices 724 can be, for example, related to... Figure 7A and Figure 7B As described.

[0092] The interconnect structure 714 includes multiple lines 120 and multiple vias 118 stacked in a dielectric structure. The dielectric structure includes an ILD layer 716 and a first IMD layer 116a located above the ILD layer 716. The multiple lines 120 include multiple bottom electrode lines 120b along the top surface of the interconnect structure 714. The bottom electrode lines 120b are individually and correspondingly located at the formed IT1R cell 702. Furthermore, the bottom electrode lines 120b are correspondingly electrically coupled to the drain region 704 of the access transistor 712 via the underlying lines and vias.

[0093] like Figure 11As shown in cross-sectional view 1100, a first via dielectric layer 504 and a second via dielectric layer 506 are deposited or otherwise formed on the interconnect structure 714. Note that for the sake of drawing compactness, the lower portion of the interconnect structure 714 is omitted here and in the following figures. The first via dielectric layer 504 may be, for example, silicon carbide and / or some other suitable dielectric, and / or the second via dielectric layer 506 may be, for example, silicon-rich oxide and / or some other suitable dielectric. Furthermore, the first via dielectric layer 504 may have a thickness of, for example, about 250 angstroms, about 100-1000 angstroms, or some other suitable value, and / or the second via dielectric layer 506 may have a thickness of, for example, about 200 angstroms, about 100-1000 angstroms, or some other suitable value. In an alternative embodiment, the first via dielectric layer 504 or the second via dielectric layer 506 is omitted.

[0094] For example Figure 11 As shown in cross-sectional view 1100, the bottom electrode via 118b is formed to extend through the first and second via dielectric layers 504, 506 to the bottom electrode line 120b. The bottom electrode via 118b includes a separate conductor 118b1 and a separate conductive liner 118b2 correspondingly covering the underside of the conductor 118b1. The conductive liner 118b2 may, for example, be configured as a diffusion barrier against the material of the bottom electrode line 120b.

[0095] like Figure 12 As shown in cross-sectional view 1200, memory layer 1202 is deposited over bottom electrode via 118b and first and second via dielectric layers 504, 506. Memory layer 1202 includes a bottom electrode barrier layer 502l, a bottom electrode layer 110l above the bottom electrode barrier layer 502l, a data storage layer 112l above the bottom electrode layer 110l, and a top electrode layer 114l above the data storage layer 112l. Data storage layer 112l forms an MTJ including a reference layer 112rl, a barrier layer 112bl, and a free layer 112fl. The reference layer 112rl, barrier layer 112bl, and free layer 112fl can, for example, be respectively associated with... Figure 5 The reference element 112r, barrier element 112b, and free element 112f are described identically. The bottom electrode barrier layer 502l is configured to prevent material from diffusing from the bottom electrode via 118b to the data storage layer 112l. The data storage layer 112l is configured to store data, and although described as forming an MTJ, the data storage layer 112l may alternatively form or otherwise be some other suitable type of data storage layer.

[0096] For example Figure 12As shown in cross-sectional view 1200, a separate hard mask 1204 is formed and correspondingly located at the 1T1R cell 702. As will be seen below, the hard mask 1204 has a pattern for the memory cells of the 1T1R cell 702. The hard mask 1204 can be formed, for example, by depositing a hard mask layer over the top electrode layer 114l and subsequently patterning the hard mask layer into the hard mask 1204. The patterning can be performed, for example, by a photolithography / etching process or some other suitable patterning process.

[0097] like Figure 13 As shown in cross-sectional view 1300, with the hard mask 1204 in place, the top electrode layer 114l (see example) is... Figure 12 ) and data storage layer 112l (see example) Figure 12 The first etching is performed. The first etching stops on the bottom electrode layer 110l and transfers the pattern of the hard mask 1204 to the top electrode layer 114l and the data storage layer 112l to form separate top electrodes 114 and data storage elements 112 respectively located at the formed 1T1R cells 702. In addition, the first etching erodes the hard mask 1204, thereby reducing the thickness of the hard mask 1204.

[0098] like Figure 14 As shown in cross-sectional view 1400, a sidewall spacer layer 108l is deposited to cover the hard mask 1204 and the bottom electrode layer 110l, and further lining a common sidewall formed by the hard mask 1204, the top electrode 114, and the data storage element 112. Furthermore, the sidewall spacer layer 108l is undoped and can be deposited, for example, by atomic layer deposition (ALD) and / or some other suitable deposition process. The sidewall spacer layer 108l can be, for example, or include silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, silicon oxide, some other suitable dielectric, or any combination thereof.

[0099] like Figure 15 As shown in the cross-sectional view 1500, for the sidewall spacer layer 108l (see example...) Figure 14 A second etching is performed. The second etching back etches the sidewall spacer layer 108l to remove the horizontal segments of the sidewall spacer layer 108l and form a sidewall spacer 108, which is lining a common sidewall formed by the data storage element 112, the top electrode 114 and the hard mask 1204.

[0100] For example Figure 15 As shown in cross-sectional view 1500, with the sidewall spacer 108 and hard mask 1204 in place, the bottom electrode layer 110l (see example) is... Figure 14 ) and bottom electrode barrier layer 502l (see example) Figure 14A third etch is performed. The third etch stops on the second via dielectric layer 506 and removes the hard mask 1204. In an alternative embodiment, the hard mask 1204 remains after the third etch is completed. Furthermore, the third etch transfers the pattern of the hard mask 1204 and the sidewall spacers 108 to the bottom electrode layer 110l and the bottom electrode barrier layer 502l, thereby segmenting the bottom electrode layer 110l and the bottom electrode barrier layer 502l.

[0101] The segments of the bottom electrode layer 110l are individually and correspondingly located at the 1T1R cell 702, and are hereinafter referred to as bottom electrodes 110. Similarly, the segments of the bottom electrode barrier layer 502l are individually and correspondingly located at the 1T1R cell 702, and are hereinafter referred to as bottom electrode barriers 502. The bottom and top electrodes 110, 114 and the data storage element 112 together form a memory cell 102 at the 1T1R cell 702. Because the data storage element 112 is an MTJ element, the memory cell 102 is an MRAM cell. However, in an alternative embodiment, the memory cell 102 may be an FeRAM cell, an RRAM cell, or some other suitable type of memory cell.

[0102] Although the second and third etches are described as separate etches, in alternative embodiments, the second and third etches may be the same etch. For example, the second and third etches may be performed continuously in a single processing chamber from the start of the second etch to the end of the third etch.

[0103] like Figure 16A and Figure 16B The cross-sectional views 1600A and 1600B show the deposition of the etch stop layer 104. Figure 16A and Figure 16B In an alternative embodiment of the deposition, the resulting electric dipoles have different polarities. An etch stop layer 104 is deposited to cover the memory cell 102 and the second via dielectric layer 506, and further lining a common sidewall formed by the sidewall spacer 108, the bottom electrode 110, and the bottom electrode barrier 502. Furthermore, the etch stop layer 104 is undoped and can be deposited, for example, by ALD and / or some other suitable deposition process.

[0104] In some embodiments, the etch stop layer 104 is or comprises a metal oxide, and / or a high-k dielectric with a dielectric constant greater than about 3.9. In some embodiments, the etch stop layer 104 is or comprises aluminum oxide, tantalum oxide, titanium oxide, ruthenium oxide, silver oxide, tungsten oxide, vanadium oxide, tin oxide, zirconium oxide, hafnium oxide, lanthanum oxide, magnesium oxide, calcium oxide, some other suitable materials, or any combination thereof. In some embodiments, the percentage of metal atoms in the etch stop layer 104 is less than about 40% or some other suitable value.

[0105] During the deposition of the etch stop layer 104, an electric dipole (schematically shown by plus and minus signs) is formed at the interface 106 between the etch stop layer 104 and the sidewall spacer layer 108l. Figure 16A In this configuration, the electric dipole has a negative charge accumulated at interface 106 in the etch stop layer 104 and a positive charge accumulated at interface 106 in the sidewall spacer layer 108l. The electric dipole can be formed, for example, due to the etch stop layer 104 having a larger oxygen areal density and / or a smaller electronegativity than the sidewall spacer layer 108l. Figure 16B In this embodiment, the electric dipole has a negative charge accumulated in the sidewall spacer layer 108l at interface 106 and a positive charge accumulated in the etch stop layer 104 at interface 106. Such an embodiment may occur, for example, when the etch stop layer 104 has a smaller oxygen areal density and / or a greater electronegativity than the sidewall spacer layer 108l.

[0106] like Figure 17 As shown in cross-sectional view 1700, a plasma treatment process is performed on the etch stop layer 104 to dope (schematically shown by black dots) the etch stop layer 104, thereby reducing charge accumulation at interface 106. The plasma treatment process... Figure 16A or Figure 16B Initially, because of Figure 16 and Figure 16B It is an alternative.

[0107] In the case of negative charge accumulation in etch stop layer 104 (see example) Figure 16A The etch stop layer 104 may be doped with an acceptor dopant. The acceptor dopant generates holes that counteract the negative charge accumulated in the etch stop layer 104, and the acceptor dopant may be, for example, or include nitrogen, hydrogen, bromide, lithium, carbon, phosphorus, gallium, aluminum, ammonia, some other suitable elements, or any combination thereof. In the case of positive charge accumulation in the etch stop layer 104 (see example...), Figure 16B The etch stop layer 104 can be doped with a donor dopant. The donor dopant generates electrons that counteract the positive charge accumulated in the etch stop layer 104.

[0108] Plasma treatment may, for example, include generating a dopant-containing plasma 1702 and exposing the etch stop layer 104 to the plasma 1702. However, other suitable processes are also possible. In some embodiments where the etch stop layer 104 is or includes alumina, plasma treatment includes generating plasma from ammonia or some other suitable acceptor dopant and subsequently exposing the etch stop layer 104 to the plasma for about 30 seconds or some other suitable amount of time.

[0109] In some embodiments, after doping is complete, the etch stop layer 104 is or includes nitrogen-doped aluminum oxide, hydrogen-doped aluminum oxide, boron-doped aluminum oxide, carbon-doped aluminum oxide, lithium-doped aluminum oxide, phosphorus-doped aluminum oxide, nitrogen-doped tantalum oxide, nitrogen-doped titanium oxide, aluminum-doped tantalum oxide, aluminum-doped titanium oxide, nitrogen-doped aluminum, nitrogen-doped titanium, nitrogen-doped ruthenium oxide, hydrogen-doped silver oxide, nitrogen-doped tungsten oxide, nitrogen-doped vanadium oxide, hydrogen-doped strontium oxide, hydrogen-doped zirconium oxide, nitrogen-doped hafnium oxide, nitrogen-doped lanthanum oxide, hydrogen-doped magnesium oxide, hydrogen-doped calcium oxide, some other suitable doping materials, or any combination thereof. In some embodiments, when the etch stop layer 104 is doped with metal, the percentage of metal atoms in the etch stop layer 104 is greater than about 40% or some other suitable value at completion.

[0110] By reducing charge accumulation at interface 106, the electric field generated by the electric dipole is reduced. Thus, the electric field has minimal impact on the electrical characteristics of the data storage element 112. Without this reduction, the electric field could substantially degrade the electrical characteristics of the data storage element 112. For example, the electric field could degrade (e.g., reduce) the coercivity voltage of the data storage element 112. This could, in turn, lead to failure of the memory cell 102 and / or reduced manufacturing yield.

[0111] Although the etch stop layer 104 is described as being deposited undoped and then doped via plasma processing, the etch stop layer 104 can alternatively be deposited doped. In other words, the etch stop layer 104 can be doped simultaneously with a dopant deposited together, the dopant being configured to mitigate the electric dipole as described above. For example, such deposition can be performed by CVD and / or some other suitable deposition process. By depositing the etch stop layer 104 as doped, [the following can be omitted]. Figure 17 Plasma treatment.

[0112] In some embodiments where the etch stop layer 104 is or includes alumina, depositing the etch stop layer 104 by CVD may include exposing the etch stop layer 104 to a process gas comprising: 1) an aluminum source (e.g., trimethylaluminum (TMA) or some other suitable aluminum source); 2) water vapor (e.g., H2O); and 3) ammonia (e.g., NH3) or some other suitable dopant source. However, other suitable methods are also feasible.

[0113] like Figure 18 As shown in cross-sectional view 1800, the etch stop layer 104 is patterned to remove the etch stop layer 104 from the peripheral region 722 of the formed IC chip. The process for performing the patterning may include, for example: 1) forming a mask 1802 covering the memory cell 102 by photolithography; 2) performing etching on the etch stop layer 104 with the mask 1802 in place; and 3) removing the mask 1802. However, other suitable processes are also possible.

[0114] like Figure 19 As shown in cross-sectional view 1900, a buffer layer 508 is deposited to cover and line the etch stop layer 104 and the second via dielectric layer 506. Furthermore, a second IMD layer 116b is deposited to cover the buffer layer 508. In an alternative embodiment, the buffer layer 508 is omitted. The buffer layer 508 may, for example, be configured to enhance adhesion from the second IMD layer 116b to the etch stop layer 104 and / or the second via dielectric layer 506. Furthermore, the buffer layer 508 may, for example, be or comprise a dielectric oxide and / or some other suitable dielectric.

[0115] like Figure 20 As shown in cross-sectional view 2000, the second IMD layer 116b is patterned to form a plurality of via openings 2002 extending through the second IMD layer 116b and the buffer layer 508. The plurality of via openings 2002 include individual and corresponding top electrode via openings 2002t overlaid on the memory cell 102. The process for performing the patterning may include, for example, 1) forming a mask over the second IMD layer 116b by photolithography; 2) performing etching on the second IMD layer 116b and the buffer layer 508 with the mask in place; 3) stopping etching on the etch stop layer 104 and the first via dielectric layer 504; and 4) removing the mask. However, other suitable processes are also feasible.

[0116] In some embodiments, the etchant used for etching has a lower etch rate to the etch stop layer 104 relative to the second IMD layer 116b and the buffer layer 508. In other words, the etchant has high selectivity to the second IMD layer 116b and the buffer layer 508 relative to the etch stop layer 104. The lower etch rate can be, for example, about 1 / 20th of the etch rate of the second IMD layer 116b. th 1 / 50 th 1 / 100 th Or some other suitable fraction of the etching rate. In some embodiments, the lower etching rate is or is less than about 26.6 A / min, about 10 A / min, or some other suitable value. In some embodiments, the etchant also has a lower etching rate to the etch stop layer 104 relative to the sidewall spacer 108. In some embodiments, the etchant also has a lower etching rate to the first via dielectric layer 504 relative to the second IMD layer 116b, the buffer layer 508, and the second via dielectric layer 506.

[0117] At least when the memory cell 102 is small, the etchant used for etching may erode the sidewall spacer 108 from the side without the etch stop layer 104 and damage the data storage element 112. However, because the etchant can have a lower etch rate against the etch stop layer 104 relative to the second IMD layer 116b, the etch stop layer 104 can prevent the sidewall spacer 108 and the data storage element 112 from being eroded and damaged.

[0118] like Figure 21 As shown in cross-sectional view 2100, a fourth etch is performed through the via opening 2002 on the etch stop layer 104 and the first via dielectric layer 504. The fourth etch exposes the individual top surface of the top electrode 114, and also exposes the top surface of the line at the peripheral region 722.

[0119] like Figure 22 As shown in cross-sectional view 2200, the second IMD layer 116b is patterned to form a plurality of line openings 2202 overlapping with the via openings 2002. The process for performing the patterning may include, for example: 1) forming a mask over the second IMD layer 116b by photolithography; 2) performing etching on the second IMD layer 116b with the mask in place; and 3) removing the mask. However, other suitable processes are also possible. In some embodiments, during etching, mask material fills the via openings 2002 to protect the top electrode 114 from damage.

[0120] like Figure 23 As shown in the cross-sectional view 2300, multiple additional lines 120 and multiple additional vias 118 are formed to fill the via opening 2002 (see example). Figure 22 ) and line opening 2202 (see example) Figure 22 Multiple additional lines 120 respectively fill the line openings 2202 and include multiple top electrode lines 120t individually and correspondingly overlaid on the memory cell 102. Multiple additional vias 118 respectively fill the via openings 2002 and include multiple top electrode vias 118t individually and correspondingly located at the top electrode 114. Furthermore, the top electrode vias 118t respectively extend from the top electrode lines 120t to the top electrode 114.

[0121] The process for forming the additional line 120 and the additional via 118 may include, for example, 1) depositing a metal layer to fill the via opening 2002 and the line opening 2202; and 2) performing planarization on the metal layer and the second IMD layer 116b until the top surfaces of the second IMD layer 116b and the metal layer are flush with each other. However, other suitable methods are also possible.

[0122] For example Figure 23 As shown in cross-sectional view 2300, a first passivation layer 718 and a second passivation layer 720 are deposited on the second IMD layer 116b and the additional line 120. In an alternative embodiment, the first passivation layer 718 or the second passivation layer 720 is omitted. The first passivation layer 718 may be, for example, silicon carbide and / or some other suitable dielectric, and / or the second passivation layer 720 may be, for example, silicon oxide and / or some other suitable dielectric.

[0123] Although the reference method describes Figures 10-15 , Figure 16A , Figure 16B and Figures 17-23 However, it should be understood that Figures 10-15 , Figure 16A , Figure 16B and Figures 17-23 The structure shown is not limited to this method, but can be used independently of it. Although Figures 10-15 , Figure 16A , Figure 16B and Figures 17-23 Described as a series of actions, however it should be understood that the order of the actions may be changed in other embodiments. Although Figures 10-15 , Figure 16A , Figure 16B and Figures 17-23 A specific set of actions is shown and described, but some actions shown and / or described may be omitted in other embodiments. Furthermore, actions not shown and / or described may be included in other embodiments.

[0124] refer to Figure 24 Provided Figures 10-15 , Figure 16A , Figure 16B and Figures 17-23A block diagram 2400 shows some embodiments of the method.

[0125] At 2402, an interconnect structure is partially formed on the substrate, wherein the interconnect structure includes bottom electrode lines in the memory region. See example. Figure 10 .

[0126] At position 2404, a via dielectric layer is deposited over the interconnect structure. See example. Figure 11 .

[0127] At position 2406, a bottom electrode via is formed, extending through the via dielectric layer to reach the bottom electrode line. See example. Figure 11 .

[0128] At 2408, a barrier layer, a bottom electrode layer, an MTJ layer, and a top electrode layer are deposited and stacked on the bottom electrode via. See example. Figure 12 .

[0129] At 2410, a hard mask is formed above the top electrode layer. See example. Figure 12 .

[0130] At 2412, with the hard mask in place, a first etch is performed on the top electrode layer and the MTJ layer to form the top electrode and MTJ element, respectively, wherein the first etch stops on the bottom electrode layer. See, for example... Figure 13 .

[0131] At 2414, a sidewall spacer is formed on the sidewall of the MTJ element, covering the bottom electrode layer. See, for example... Figure 14 and Figure 15 .

[0132] At 2416, with the hard mask and sidewall spacers in place, a second etching is performed on the bottom electrode layer and the barrier layer to form the bottom electrode and bottom electrode barrier, respectively, wherein the top electrode and bottom electrode, along with the MTJ element, form a memory cell. See, for example... Figure 15 .

[0133] At 2418, an etch stop layer is formed to cover the memory cell and liner the sidewall spacers and bottom electrode sidewalls, wherein the etch stop layer is formed to be doped with a dopant to reduce charge accumulation at the interface between the etch stop layer and the sidewall spacers. See, for example... Figure 16A , Figure 16B and Figure 17 .

[0134] At 2420, the etch stop layer is patterned to remove it from the peripheral area. See example. Figure 18 .

[0135] At position 2422, the interconnect structure is completed above and around the memory cell. See, for example... Figures 19-23 .

[0136] Although Figure 24 The block diagram 2400 herein illustrates and describes a series of actions or events; however, it should be understood that the order of these actions or events shown should not be interpreted as limiting. For example, some actions may occur in a different order, and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all actions shown are required to implement one or more aspects or embodiments described herein, and one or more actions depicted herein may be performed in one or more separate actions and / or phases.

[0137] refer to Figures 25-27 Provided Figures 10-15 , Figure 16A , Figure 16B and Figures 17-23 A series of cross-sectional views 2500-2700 of some first alternative embodiments of the method, wherein the etch stop layer 104 is divided into a doped etch stop layer 104a and an undoped etch stop layer 104b. For example, the first alternative embodiments can be performed to form having Figure 4A The IC chip of the embodiment of the etch stop layer 104.

[0138] like Figure 25 As shown in the cross-sectional diagram 2500, the execution regarding... Figures 10-15 The described action. Furthermore, a doped etch stop layer 104a is formed to cover the memory cell 102 and the second via dielectric layer 506, and also lining a common sidewall formed by the sidewall spacer 108, the bottom electrode 110, and the bottom electrode barrier 502. The doped etch stop layer 104a is doped to reduce charge accumulation at the interface 106 between the doped etch stop layer 104a and the sidewall spacer 108. The doped etch stop layer 104a is as described regarding... Figure 17 The etch stop layer 104 is doped as described for the etch stop layer 104. In some embodiments, the doped etch stop layer 104a is as described for the etch stop layer 104. Figure 16A , Figure 16B and Figure 17 It is formed as described. For example, the doped etch stop layer 104a can be formed as described above. Figure 16A and Figure 16B As described, it is deposited as undoped, and then can be as about Figure 17 Doping is performed via plasma processing as described. In other embodiments, the doped etch stop layer 104a may be deposited as doped.

[0139] like Figure 26As shown in cross-sectional view 2600, an undoped etch stop layer 104b is deposited to cover and liner the doped etch stop layer 104a. This deposition can be performed, for example, by ALD or some other suitable deposition process.

[0140] The undoped etch stop layer 104b can be, for example, about Figure 16A and Figure 16B The described etch stop layer 104. In some embodiments, the percentage of metal atoms in the undoped etch stop layer 104b is less than about 40% or some other suitable value, while the percentage of metal atoms in the doped etch stop layer 104a is greater than about 40% or some other suitable value. In some embodiments, the doping concentration of the doped etch stop layer 104a is three times or more the concentration of any impurities in the undoped etch stop layer 104b. In some embodiments, the undoped etch stop layer 104b is made of the same material as the doped etch stop layer 104a, except for the dopant in the doped etch stop layer 104a.

[0141] like Figure 27 As shown in the cross-sectional diagram 2700, the execution regarding... Figures 18-23 The described actions complete the interconnect structure 714 on and around the memory cells. Furthermore, in performing actions related to... Figure 20 During the patterning process described, the etchant used for patterning may have a lower etch rate on the undoped etch stop layer 104b than on the doped etch stop layer 104a, thereby the undoped etch stop layer 104b can provide enhanced protection for the memory cell 102.

[0142] Although the reference method describes Figures 25-27 However, it should be understood that Figures 25-27 The structure shown is not limited to this method, but can be used independently of it. Although Figures 25-27 Described as a series of actions, however it should be understood that the order of the actions may be changed in other embodiments. Although Figures 25-27 A specific set of actions is shown and described, but some actions shown and / or described may be omitted in other embodiments. Furthermore, actions not shown and / or described may be included in other embodiments.

[0143] refer to Figures 28-30 Provided Figures 10-15 , Figure 16A , Figure 16B and Figures 17-23 A series of cross-sectional views 2800-3000 of some second alternative embodiments of the method, wherein the sidewall spacer 108 is doped to reduce charge accumulation at the interface 106 with the etch stop layer 104. For example, the second alternative embodiments can be performed to form having Figure 4BThe IC chip of the embodiment of the sidewall spacer 108.

[0144] like Figure 28 As shown in the cross-sectional diagram 2800, the execution regarding... Figures 10-13 The described action. Furthermore, the sidewall spacer layer 108l is deposited as undoped. The sidewall spacer layer 108l can be, for example, about... Figure 14 The as described, and / or may be deposited, for example, by ALD and / or some other suitable deposition process.

[0145] like Figure 29 As shown in cross-sectional view 2900, a plasma processing technique is performed on the sidewall spacer layer 108l to dope (schematically shown by black dots) the sidewall spacer layer 108l. As will be seen below, this doping can reduce charge accumulation at the interface between the sidewall spacer layer 108l and the subsequently formed etch stop layer.

[0146] When positive charges accumulate in the sidewall spacer layer 108l at the interface, the sidewall spacer layer 108l may be doped with a donor dopant. The donor dopant may be, or include, for example, fluorine, chlorine, bromine, sulfur, some other suitable donor dopant, or any combination thereof. When negative charges accumulate in the sidewall spacer layer 108l at the interface, the sidewall spacer layer 108l may be doped with an acceptor dopant. Plasma treatment may, for example, include generating a dopant-containing plasma 2902 and exposing the sidewall spacer layer 108l to the plasma 2902. However, other suitable processes are also feasible.

[0147] In some embodiments, after doping is completed, the sidewall spacer layer 108l is or includes nitrogen-doped silicon oxide, sulfur-doped silicon nitride, carbon-doped silicon nitride, carbon-doped silicon phosphide, fluorine-doped silicon oxide, chlorine-doped silicon oxide, some other suitable doping material, or any combination thereof.

[0148] Although the sidewall spacer layer 108l is described as being deposited undoped and then doped via plasma processing, the sidewall spacer layer 108l can alternatively be deposited as doped. In other words, the sidewall spacer layer 108l can be doped simultaneously with the deposition of a dopant configured to mitigate charge accumulation as described above. For example, such deposition can be performed by CVD and / or some other suitable deposition process. By depositing the sidewall spacer layer 108l as doped, [the following can be omitted]. Figure 29 Plasma treatment.

[0149] like Figure 30 As shown in the cross-sectional view 3000, the above-described procedure regarding... Figure 15 , Figure 16A , Figure 16B and Figures 17-23 The described action, besides being able to be performed or not performed. Figure 17 Plasma treatment. Thus, the etch stop layer 104 can be doped or undoped. Because the sidewall spacer 108 is doped, Figure 16A and Figure 16B Electric dipoles are not formed or are formed to a minimum. For example, doping can make the electronegativity of the sidewall spacer 108 closer to that of the etch stop layer 104 to minimize electric dipoles.

[0150] Although the reference method describes Figures 28-30 However, it should be understood that Figures 28-30 The structure shown is not limited to this method, but can be used independently of it. Although Figures 28-30 Described as a series of actions, however it should be understood that the order of the actions may be changed in other embodiments. Although Figures 28-30 A specific set of actions is shown and described, but some actions shown and / or described may be omitted in other embodiments. Furthermore, actions not shown and / or described may be included in other embodiments.

[0151] refer to Figures 31-33 Provided Figures 10-15 , Figure 16A , Figure 16B and Figures 17-23 A series of cross-sectional views 3100-3300 of some third alternative embodiments of the method, wherein the sidewall spacer 108 includes individually doped sidewall spacers 108a and individually undoped sidewall spacers 108b. For example, the third alternative embodiments can be performed to form having Figure 4C The IC chip of the embodiment of the sidewall spacer 108.

[0152] like Figure 31 As shown in the cross-sectional diagram 3100, the execution regarding... Figures 10-13 The described action. Furthermore, an undoped sidewall spacer layer 108lb is deposited to cover the memory cell 102 and the second via dielectric layer 506, and also liner the common sidewall formed by the hard mask 1204, the top electrode 114, and the data storage element 112. The undoped sidewall spacer layer 108lb can be, for example, about... Figure 14 The described sidewall spacer layer 108l, and / or may be deposited, for example, by ALD and / or some other suitable deposition process.

[0153] like Figure 32As shown in cross-sectional view 3200, a doped sidewall spacer layer 108a is formed on top of an undoped sidewall spacer layer 108lb to reduce charge accumulation at the interface between the doped sidewall spacer layer 108a and the subsequently formed etch stop layer. In the case of positive charge accumulation at the interface in the doped sidewall spacer layer 108a, the doped sidewall spacer layer 108a may be doped with a donor dopant. In the case of negative charge accumulation at the interface in the doped sidewall spacer layer 108a, the doped sidewall spacer layer 108a may be doped with an acceptor dopant.

[0154] In some embodiments, the doped sidewall spacer layer 108a is as described regarding Figure 28 and Figure 29 The sidewall spacer layer 108l is formed as described above. For example, the doped sidewall spacer layer 108la can be formed as described above. Figure 28 As described, it is deposited as undoped, and then can be as about Figure 29 Doping is performed via plasma processing as described. In other embodiments, the doped sidewall spacer layer 108a is deposited as doped. This deposition can be performed, for example, by CVD and / or some other suitable deposition method.

[0155] like Figure 33 As shown in the cross-sectional view 3300, the execution regarding Figure 15 , Figure 16A , Figure 16B and Figures 17-23 The described action, besides being able to be performed or not performed. Figure 17 Plasma treatment is performed. Thus, the etch stop layer 104 can be doped or undoped. By performing these actions, individual doped sidewall spacers 108a and individual undoped sidewall spacers 108b are formed on the sidewalls of the data storage element 112. The doped sidewall spacer 108a is formed from a doped sidewall spacer layer 108a and directly contacts the etch stop layer 104. The undoped sidewall spacer layer 108b is formed from an undoped sidewall spacer layer 108lb. Because the doped sidewall spacer 108a is doped, the figure... Figure 16A and Figure 16B Electric dipoles are not formed or are formed to a minimum. For example, doping can make the electronegativity of the doped sidewall spacer 108a closer to that of the etch stop layer 104 to minimize electric dipoles.

[0156] Although the reference method describes Figures 31-33 However, it should be understood that Figures 31-33 The structure shown is not limited to this method, but can be used independently of it. Although Figures 31-33Described as a series of actions, however it should be understood that the order of the actions may be changed in other embodiments. Although Figures 31-33 A specific set of actions is shown and described, but some actions shown and / or described may be omitted in other embodiments. Furthermore, actions not shown and / or described may be included in other embodiments.

[0157] In some embodiments, this disclosure provides an IC chip, comprising: a bottom electrode; a data storage element superimposed on the bottom electrode; a top electrode superimposed on the data storage element; a sidewall spacer superimposed on the bottom electrode on a common sidewall formed by the data storage element and the top electrode; and an etch stop layer lining the sidewall spacer; wherein the sidewall spacer and the etch stop layer are in direct contact at an interface and form an electric dipole at the interface, and wherein the sidewall spacer and / or the etch stop layer are doped to reduce charge accumulation at the interface. In some embodiments, the negative charge of the electric dipole accumulates in the etch stop layer, wherein the etch stop layer is doped with an acceptor dopant. In some embodiments, the negative charge of the electric dipole accumulates in the etch stop layer, wherein the sidewall spacer is doped with a donor dopant. In some embodiments, the negative charge of the electric dipole accumulates in the etch stop layer, wherein the sidewall spacer is doped with a donor dopant, and wherein the etch stop layer is doped with an acceptor dopant. In some embodiments, the etch stop layer has a higher oxygen areal density than the sidewall spacer. In some embodiments, the electronegativity of the etch stop layer is lower than that of the sidewall spacer. In some embodiments, the positive charge of the electric dipole accumulates in the etch stop layer, wherein the etch stop layer is doped with a donor dopant and / or the sidewall spacers are doped with acceptor dopant. In some embodiments, the sidewall spacers comprise an undoped spacer layer and a doped spacer layer, wherein the doped spacer layer is located between and in direct contact with the undoped spacer layer and the etch stop layer. In some embodiments, the etch stop layer comprises an undoped etch stop layer and a doped etch stop layer, wherein the doped etch stop layer is located between and in direct contact with the sidewall spacers and the undoped etch stop layer.

[0158] In some embodiments, this disclosure provides another IC chip, comprising: a bottom electrode; an MTJ element overlying the bottom electrode; a top electrode overlying the MTJ element; a sidewall spacer overlying the bottom electrode on the sidewall of the MTJ element; and an etch stop layer lining the sidewall spacer; wherein the etch stop layer is doped with an acceptor dopant and / or the sidewall spacer is doped with a donor dopant. In some embodiments, the etch stop layer is doped with an acceptor dopant, and the sidewall spacer is undoped. In some embodiments, the sidewall spacer is doped with a donor dopant, and the etch stop layer is undoped. In some embodiments, the etch stop layer and the sidewall spacer are in direct contact at an interface, wherein the etch stop layer and the sidewall spacer have an electric dipole in which negative charge accumulates in the etch stop layer at the interface. In some embodiments, the sidewall spacer comprises silicon nitride, wherein the etch stop layer comprises aluminum oxide. In some embodiments, the IC chip further comprises: a via overlying and directly contacting the top electrode, wherein the via and the etch stop layer have separate surfaces that are opposite to and in direct contact with each other.

[0159] In some embodiments, this disclosure provides a method comprising: forming a data storage element and a top electrode stacked on a bottom electrode layer, wherein the data storage element is between the top electrode and the bottom electrode layer; forming a sidewall spacer on a first common sidewall formed by the data storage element and the top electrode; performing a first etch on the bottom electrode layer with the sidewall spacer in place to form a bottom electrode located below the data storage element; forming an etch stop layer covering the top electrode and lining a second common sidewall formed by the sidewall spacer and the bottom electrode; forming a via extending through the etch stop layer to the top electrode; and wherein forming the sidewall spacer includes doping the sidewall spacer, and / or wherein forming the etch stop layer includes doping the etch stop layer to reduce charge accumulation at an electric dipole between the etch stop layer and the sidewall spacer. In some embodiments, forming the etch stop layer includes: depositing the etch stop layer while doping the etch stop layer with an acceptor dopant. In some embodiments, forming the etch stop layer includes: depositing the etch stop layer and subsequently plasma-treating the etch stop layer to dope the etch stop layer with an acceptor dopant. In some embodiments, the etch stop layer comprises a metal oxide, wherein the percentage of metal atoms in the etch stop layer is less than 40% before plasma treatment and greater than 40% after plasma treatment. In some embodiments, the method further comprises: depositing an IMD layer covering the etch stop layer; performing a second etch on the IMD layer to form a via opening over a top electrode, wherein the second etch stops on the etch stop layer; performing a third etch to extend the via opening to the top electrode; wherein the via is formed to fill the via opening, and wherein the second etch is performed using an etchant with an etch rate to the IMD layer that is about 20 times or more greater than the etch rate to the etch stop layer.

[0160] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

[0161] Example 1. An integrated circuit (IC) chip, comprising:

[0162] Bottom electrode;

[0163] Data storage element, covering the bottom electrode;

[0164] The top electrode covers the data storage element;

[0165] A sidewall spacer, covering the bottom electrode on a common sidewall formed by the data storage element and the top electrode; and

[0166] An etch stop layer is applied to the sidewall spacer.

[0167] The sidewall spacer and the etch stop layer are in direct contact at the interface and form an electric dipole at the interface, and the sidewall spacer and / or the etch stop layer are doped to reduce charge accumulation at the interface.

[0168] Example 2. The IC chip according to Example 1, wherein the negative charge of the electric dipole accumulates in the etch stop layer, and wherein the etch stop layer is doped with an acceptor dopant.

[0169] Example 3. The IC chip according to Example 1, wherein the negative charge of the electric dipole accumulates in the etch stop layer, and wherein the sidewall spacer is doped with a donor dopant.

[0170] Example 4. The IC chip according to Example 1, wherein the negative charge of the electric dipole accumulates in the etch stop layer, wherein the sidewall spacers are doped with donor dopant, and wherein the etch stop layer is doped with acceptor dopant.

[0171] Example 5. The IC chip according to Example 1, wherein the etch stop layer has a higher oxygen areal density than the sidewall spacers.

[0172] Example 6. The IC chip according to Example 1, wherein the electronegativity of the etch stop layer is less than the electronegativity of the sidewall spacer.

[0173] Example 7. The IC chip according to Example 1, wherein the positive charge of the electric dipole accumulates in the etch stop layer, and wherein the etch stop layer is doped with a donor dopant and / or the sidewall spacer is doped with an acceptor dopant.

[0174] Example 8. The IC chip according to Example 1, wherein the sidewall spacer includes an undoped spacer layer and a doped spacer layer, and wherein the doped spacer layer is located between the undoped spacer layer and the etch stop layer and directly contacts the undoped spacer layer and the etch stop layer.

[0175] Example 9. The IC chip according to Example 1, wherein the etch stop layer comprises an undoped etch stop layer and a doped etch stop layer, and wherein the doped etch stop layer is located between the sidewall spacer and the undoped etch stop layer and directly contacts the sidewall spacer and the undoped etch stop layer.

[0176] Example 10. An integrated circuit (IC) chip, comprising:

[0177] Bottom electrode;

[0178] A magnetic tunnel junction (MTJ) element is superimposed on the bottom electrode;

[0179] The top electrode is covered over the MTJ element;

[0180] Sidewall spacers, covering the bottom electrode on the sidewall of the MTJ element; and

[0181] An etch stop layer is applied to the sidewall spacer.

[0182] The etch stop layer is doped with an acceptor dopant and / or the sidewall spacer is doped with a donor dopant.

[0183] Example 11. The IC chip according to Example 10, wherein the etch stop layer is doped with the acceptor dopant and the sidewall spacers are not doped.

[0184] Example 12. The IC chip according to Example 10, wherein the sidewall spacers are doped with the donor dopant and the etch stop layer is not doped.

[0185] Example 13. An IC chip according to Example 10, wherein the etch stop layer and the sidewall spacer are in direct contact at an interface, and wherein the etch stop layer and the sidewall spacer have an electric dipole in which negative charge accumulates at the interface in the etch stop layer.

[0186] Example 14. The IC chip according to Example 10, wherein the sidewall spacer comprises silicon nitride, and wherein the etch stop layer comprises aluminum oxide.

[0187] Example 15. The IC chip according to Example 10 further includes:

[0188] A via is overlaid on and in direct contact with the top electrode, wherein the via and the etch stop layer have separate surfaces that are opposite to each other and in direct contact.

[0189] Example 16. A method comprising:

[0190] A data storage element and a top electrode are formed stacked on a bottom electrode layer, wherein the data storage element is located between the top electrode and the bottom electrode layer;

[0191] A sidewall spacer is formed on the first common sidewall formed by the data storage element and the top electrode;

[0192] With the sidewall spacer in place, a first etching is performed on the bottom electrode layer to form a bottom electrode located below the data storage element;

[0193] An etch stop layer is formed covering the top electrode and lining the second common sidewall formed by the sidewall spacer and the bottom electrode;

[0194] Forming a via extending through the etch stop layer to the top electrode; and

[0195] Wherein, forming the sidewall spacer includes doping the sidewall spacer, and / or wherein forming the etch stop layer includes doping the etch stop layer to reduce charge accumulation at the electric dipole between the etch stop layer and the sidewall spacer.

[0196] Example 17. The method of Example 16, wherein forming the etch stop layer comprises: depositing the etch stop layer while doping the etch stop layer with an acceptor dopant.

[0197] Example 18. The method of Example 16, wherein forming the etch stop layer comprises: depositing the etch stop layer, and subsequently subjecting the etch stop layer to plasma treatment to dope the etch stop layer with an acceptor dopant.

[0198] Example 19. The method of Example 18, wherein the etch stop layer comprises a metal oxide, and wherein the percentage of metal atoms in the etch stop layer is less than 40% before the plasma treatment and greater than 40% after the plasma treatment.

[0199] Example 20. The method according to Example 16 further includes:

[0200] Deposit an intermetallic dielectric (IMD) layer covering the etch stop layer;

[0201] A second etching is performed on the IMD layer to form a via opening over the top electrode, wherein the second etching stops on the etch stop layer;

[0202] Perform a third etching to extend the via opening to the top electrode;

[0203] The via is formed to fill the via opening, and the second etching is performed using an etchant whose etching rate on the IMD layer is about 20 times or more than the etching rate on the etch stop layer.

Claims

1. An integrated circuit (IC) chip, comprising: Bottom electrode; A data storage element is covered by the bottom electrode, wherein the data storage element is a magnetic tunnel junction (MTJ) element; The top electrode covers the data storage element; A sidewall spacer, covering the bottom electrode on a common sidewall formed by the data storage element and the top electrode; and An etch stop layer is applied to the sidewall spacer; The sidewall spacer and the etch stop layer are in direct contact at the interface and form an electric dipole at the interface, and the sidewall spacer and / or the etch stop layer are doped to reduce charge accumulation at the interface.

2. The IC chip according to claim 1, wherein, The negative charge of the electric dipole accumulates in the etch stop layer, wherein the etch stop layer is doped with an acceptor dopant.

3. The IC chip according to claim 1, wherein, The negative charge of the electric dipole accumulates in the etch stop layer, and the sidewall spacer is doped with a donor dopant.

4. The IC chip according to claim 1, wherein, The negative charge of the electric dipole accumulates in the etch stop layer, wherein the sidewall spacers are doped with donor dopant, and wherein the etch stop layer is doped with acceptor dopant.

5. The IC chip according to claim 1, wherein, The etch stop layer has a higher oxygen areal density than the sidewall spacer.

6. The IC chip according to claim 1, wherein, The electronegativity of the etch stop layer is less than that of the sidewall spacer.

7. The IC chip according to claim 1, wherein, The positive charge of the electric dipole accumulates in the etch stop layer, wherein the etch stop layer is doped with a donor dopant and / or the sidewall spacer is doped with an acceptor dopant.

8. The IC chip according to claim 1, wherein, The sidewall spacer includes an undoped spacer layer and a doped spacer layer, wherein the doped spacer layer is located between the undoped spacer layer and the etch stop layer and directly contacts the undoped spacer layer and the etch stop layer.

9. The IC chip according to claim 1, wherein, The etch stop layer includes an undoped etch stop layer and a doped etch stop layer, wherein the doped etch stop layer is located between the sidewall spacer and the undoped etch stop layer and directly contacts the sidewall spacer and the undoped etch stop layer.

10. An integrated circuit (IC) chip, comprising: Bottom electrode; A magnetic tunnel junction (MTJ) element, covered by the bottom electrode; The top electrode is covered over the MTJ element; A sidewall spacer is placed on the sidewall of the MTJ element, covering the bottom electrode. as well as An etch stop layer is applied to the sidewall spacer; The sidewall spacer and the etch stop layer are in direct contact at the interface and form an electric dipole at the interface. The etch stop layer is doped with an acceptor dopant and / or the sidewall spacer is doped with a donor dopant to reduce charge accumulation at the interface.

11. The IC chip according to claim 10, wherein, The etch stop layer is doped with the acceptor dopant, and the sidewall spacers are not doped.

12. The IC chip according to claim 10, wherein, The sidewall spacers are doped with the donor dopant, and the etch stop layer is not doped.

13. The IC chip according to claim 10, wherein, The negative charge in the electric dipole accumulates at the interface in the etch stop layer.

14. The IC chip according to claim 10, wherein, The sidewall spacer comprises silicon nitride, and the etch stop layer comprises aluminum oxide.

15. The IC chip according to claim 10, further comprising: A via is overlaid on and in direct contact with the top electrode, wherein the via and the etch stop layer have separate surfaces that are opposite to each other and in direct contact.

16. A method for forming an integrated circuit (IC) chip, comprising: A data storage element and a top electrode are formed stacked on a bottom electrode layer, wherein the data storage element is between the top electrode and the bottom electrode layer, and wherein the data storage element is a magnetic tunnel junction (MTJ) element. A sidewall spacer is formed on the first common sidewall formed by the data storage element and the top electrode; With the sidewall spacer in place, a first etching is performed on the bottom electrode layer to form a bottom electrode located below the data storage element; An etch stop layer is formed covering the top electrode and lining the second common sidewall formed by the sidewall spacer and the bottom electrode; Forming a via extending through the etch stop layer to the top electrode; and Wherein, forming the sidewall spacer includes doping the sidewall spacer, and / or wherein forming the etch stop layer includes doping the etch stop layer to reduce charge accumulation at the electric dipole between the etch stop layer and the sidewall spacer.

17. The method of claim 16, wherein, Forming the etch stop layer includes: depositing the etch stop layer while simultaneously doping the etch stop layer with an acceptor dopant.

18. The method of claim 16, wherein, Forming the etch stop layer includes: depositing the etch stop layer, and subsequently subjecting the etch stop layer to plasma treatment to dope the etch stop layer with an acceptor dopant.

19. The method of claim 18, wherein, The etch stop layer comprises a metal oxide, wherein the percentage of metal atoms in the etch stop layer is less than 40% before the plasma treatment and greater than 40% after the plasma treatment.

20. The method of claim 16, further comprising: Deposit an intermetallic dielectric (IMD) layer covering the etch stop layer; A second etching is performed on the IMD layer to form a via opening over the top electrode, wherein the second etching stops on the etch stop layer; Perform a third etching to extend the via opening to the top electrode; The via is formed to fill the via opening, and the second etching is performed using an etchant whose etching rate on the IMD layer is 20 times or more than the etching rate on the etch stop layer.

Images