Display panel and display device comprising a display panel

Abstract

The present application provides a display panel and a display device. The display panel includes: a substrate including a corner display area including a strip-shaped portion between cut portions; and a corner pixel in the strip-shaped portion and a corner pixel circuit driving the corner pixel, wherein each corner pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, and each corner pixel circuit includes a first pixel circuit driving the first sub-pixel, a second pixel circuit driving the second sub-pixel, and a third pixel circuit driving the third sub-pixel, and a first pixel circuit, a second pixel circuit, and a third pixel circuit included in an n-th corner pixel circuit in a first direction being a length direction of the strip-shaped portion are arranged differently from the first pixel circuit, the second pixel circuit, and the third pixel circuit in an (n+1)-th corner pixel circuit.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2021-0043498, filed on April 2, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] One or more embodiments relate to a display panel and a display device including the display panel, and more specifically, to a display panel having an extended display area for displaying images on side and corner areas and a display device including the display panel. Background Technology

[0004] Display devices with various shapes have been developed, such as curved displays, foldable displays, and rollable displays. In these devices, the display area has been increased and the non-display area reduced, and various methods have been used to design the shape of the display device. Summary of the Invention

[0005] One or more embodiments include a display panel having an extended display area to display images in side and corner areas, and a display device including the display panel.

[0006] According to an embodiment, a display panel includes: a substrate including a main display area and a corner display area, wherein the corner display area extends from a corner of the main display area and includes a strip-shaped portion between cut portions; a main pixel located on the substrate in the main display area; a main pixel circuit located on the substrate in the main display area, wherein the main pixel circuit drives the main pixel; a plurality of corner pixels located on the substrate in the strip-shaped portion; and a plurality of corner pixel circuits located on the substrate in the strip-shaped portion, wherein the plurality of corner pixel circuits drive the plurality of corner pixels. In such an embodiment, each corner pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, and each corner pixel circuit includes a first pixel circuit driving the first sub-pixel, a second pixel circuit driving the second sub-pixel, and a third pixel circuit driving the third sub-pixel, and the arrangement of the first pixel circuit, the second pixel circuit, and the third pixel circuit in the nth corner pixel circuit in a first direction that is the length direction of the strip-shaped portion is different from the arrangement of the first pixel circuit, the second pixel circuit, and the third pixel circuit in the (n+1)th corner pixel circuit in the first direction, where n is a positive integer.

[0007] In an embodiment, the first pixel circuit and the third pixel circuit may be arranged alternately in a first column, the first column extending in a first direction, and the second pixel circuit is arranged in a second column adjacent to the first column.

[0008] In an embodiment, the first pixel circuit of the nth corner pixel circuit may overlap with the first sub-pixel, and the first pixel circuit of the (n+1)th corner pixel circuit may overlap with the third sub-pixel.

[0009] In an embodiment, the arrangement of the main pixels may be different from the arrangement of the corner pixels.

[0010] In this embodiment, the main pixels can be arranged in a Pentile pixel arrangement structure, and the corner pixels can be arranged in an S-strip structure.

[0011] In one embodiment, multiple corner pixel circuits may be located in the central portion of the strip portion, and signal lines extending in the first direction may be located at the edges of the strip portion.

[0012] In an embodiment, the signal lines can transmit scan signals, and some signal lines can be connected to the nth corner pixel circuit and the (n+1)th corner pixel circuit.

[0013] In an embodiment, the corner data lines that transmit data signals to multiple corner pixel circuits may overlap with the multiple corner pixel circuits and may extend in a first direction.

[0014] In an embodiment, the corner display area may include a first corner display area and a second corner display area, the strip portion may be in the first corner display area, and the scanning drive circuit may be in the second corner display area.

[0015] In an embodiment, corner pixels in the second corner display area may at least partially overlap with the scan driving circuit.

[0016] According to an embodiment, a display device includes: a display panel including a main display area and a corner display area, wherein the corner display areas extend from the corners of the main display area and are curved with a preset radius of curvature; and a cover window covering the display panel and having a shape corresponding to the shape of the display panel. In such an embodiment, the corner display area includes a strip-shaped portion between cut portions, the strip-shaped portion including a plurality of corner pixels and a plurality of corner pixel circuits driving the plurality of corner pixels, each corner pixel including a first sub-pixel, a second sub-pixel, and a third sub-pixel, and each corner pixel circuit including a first pixel circuit driving the first sub-pixel, a second pixel circuit driving the second sub-pixel, and a third pixel circuit driving the third sub-pixel, and the arrangement of the first pixel circuit, the second pixel circuit, and the third pixel circuit in the nth corner pixel circuit in a first direction that is the length direction of the strip-shaped portion is different from the arrangement of the first pixel circuit, the second pixel circuit, and the third pixel circuit in the (n+1)th corner pixel circuit in the first direction, where n is a positive integer.

[0017] In an embodiment, the first pixel circuit and the third pixel circuit may be arranged alternately in a first column, the first column extending in a first direction, and the second pixel circuit may be arranged in a second column adjacent to the first column.

[0018] In an embodiment, the first pixel circuit of the nth corner pixel circuit may overlap with the first sub-pixel, and the first pixel circuit of the (n+1)th corner pixel circuit may overlap with the third sub-pixel.

[0019] In an embodiment, the main display area may include main pixels and main pixel circuitry that drives the main pixels, and the arrangement of the main pixels may differ from the arrangement of the corner pixels.

[0020] In this embodiment, the main pixels can be arranged in a Pentile pixel arrangement structure, and the corner pixels can be arranged in an S-strip structure.

[0021] In one embodiment, multiple corner pixel circuits may be located in the central portion of the strip portion, and signal lines extending in the first direction may be located at the edges of the strip portion.

[0022] In an embodiment, the signal lines can transmit scan signals, and some signal lines can be connected to the nth corner pixel circuit and the (n+1)th corner pixel circuit.

[0023] In an embodiment, the corner data lines that transmit data signals to multiple corner pixel circuits may overlap with the multiple corner pixel circuits and may extend in a first direction.

[0024] In an embodiment, the corner display area may include a first corner display area and a second corner display area, the strip portion may be in the first corner display area, and the scanning drive circuit may be in the second corner display area.

[0025] In an embodiment, corner pixels in the second corner display area may at least partially overlap with the scan driving circuit. Attached Figure Description

[0026] The above and other features of certain embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0027] Figure 1 This is a perspective view of a display device according to an embodiment;

[0028] Figure 2 It is along Figure 1 A cross-sectional view of the display device taken by line I-I';

[0029] Figure 3A yes Figure 1 A plan view of the display panel in the unfolded state of the display device;

[0030] Figure 3B yes Figure 3A A magnified view of the circled area;

[0031] Figure 4 It is along Figure 3B A cross-sectional view of the display panel taken by line II-II';

[0032] Figure 5 It is along Figure 3A A cross-sectional view of the display panel taken by line III-III';

[0033] Figure 6 This is a diagram illustrating a pixel arrangement structure that can be applied to the main display area according to an embodiment;

[0034] Figure 7 This is a diagram illustrating a pixel arrangement structure applicable to a corner display area according to an embodiment;

[0035] Figure 8A and Figure 8B It is an equivalent circuit diagram of a pixel circuit for driving sub-pixels according to one or more embodiments;

[0036] Figure 9A This is a plan view showing a portion of the display panel according to an embodiment;

[0037] Figure 9B yes Figure 9A A magnified view of the circled area;

[0038] Figure 10 This is a diagram illustrating the pixel arrangement structure, pixel circuit arrangement structure, and some signal lines in the main display area according to an embodiment;

[0039] Figure 11A This is a diagram illustrating the pixel arrangement structure in the corner display area according to an embodiment;

[0040] Figure 11B and Figure 11C This is a diagram illustrating the pixel circuit arrangement structure and some signal lines in the corner display area according to an embodiment;

[0041] Figure 12A and Figure 12B This is a diagram illustrating the arrangement relationship between pixels and pixel circuits in a corner display area according to an embodiment;

[0042] Figure 13 It is along Figure 12B A cross-sectional view of the display panel taken by line IV-IV';

[0043] Figure 14A It is along Figure 9A A cross-sectional view of the display panel taken by line F-F';

[0044] Figure 14B yes Figure 14A Enlarged view of the dam section; and

[0045] Figure 15 It is along Figure 9A The cross-sectional view of the display panel is taken by line H-H'. Detailed Implementation

[0046] In the following description, the invention will now be described more fully with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals throughout refer to the same elements.

[0047] Because this disclosure allows for various modifications and numerous embodiments, specific embodiments will be shown in the accompanying drawings and described in detail in the written description. Reference is made to the accompanying drawings, which illustrate one or more embodiments, to obtain a full understanding of their advantages and the objectives achieved through implementation. However, embodiments may take different forms and should not be construed as limited to the description set forth herein.

[0048] It will be understood that when an element is referred to as being "on" another element, the element may be directly on the other element, or there may be an intermediary element between the element and the other element. Conversely, when an element is referred to as being "directly on" another element, there is no intermediary element.

[0049] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings herein, “first element,” “first component,” “first area,” “first layer,” or “first part” discussed below may be referred to as “second element,” “second component,” “second area,” “second layer,” or “second part.”

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, “a,” “an,” “the,” and “at least one” do not indicate a limitation on quantity but are intended to include both the singular and plural forms. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element.” “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms “comprising” and / or “covering” or “including” and / or “containing” indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0051] For ease of illustration, the dimensions of the components in the accompanying drawings may be exaggerated. In other words, since the dimensions and thicknesses of the components in the accompanying drawings are arbitrarily shown for ease of illustration, the following embodiments are not limited thereto.

[0052] The x, y, and z directions are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x, y, and z directions can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0053] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), the terms "approximately" or "about" as used herein include the stated values ​​and are intended to refer to a range of acceptable deviations for a particular value as determined by one of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0054] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms such as those defined in a general dictionary shall be interpreted as having a meaning consistent with their context in the relevant field and their meaning in this disclosure, and shall not be interpreted in an idealized or overly formalized sense.

[0055] The embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. Thus, variations in the shape of the figures will be expected due to factors such as manufacturing techniques and / or tolerances. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes of the areas shown herein, but will include deviations in shape, for example, due to manufacturing processes. For instance, areas shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to show precise shapes of the areas, nor are they intended to limit the scope of the claims.

[0056] In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0057] Figure 1 This is a perspective view of display device 1 according to an embodiment.

[0058] refer to Figure 1 The embodiment of display device 1 is a device for displaying video images or still images, and for example, it may include not only portable electronic devices such as mobile phones, smartphones, tablet personal computers (“PCs”), smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (“PMPs”), navigation devices, ultra-mobile PCs (“UMPCs”), etc., but also various devices for displaying images such as televisions, laptops, monitors, billboards, Internet of Things (“IoT”) devices, etc.

[0059] In an embodiment, such as Figure 1 As shown, the display device 1 may include a main display area MDA, a side display area SDA, and a corner display area CDA.

[0060] The main display area (MDA) is a region defined on the front surface portion of the display device 1, and may be flat rather than curved. The main display area (MDA) may have a rectangular shape comprising a short side in the x-direction and a long side in the y-direction. However, one or more embodiments are not limited thereto. Alternatively, the main display area (MDA) may have one of various other polygonal shapes instead of a rectangular shape, and may have, for example, a polygonal shape in which the corners where the short and long sides intersect may be rounded.

[0061] The side display area SDA may include a first side display area SDA1, a second side display area SDA2, a third side display area SDA3, and a fourth side display area SDA4.

[0062] The first side display area SDA1 may be an area extending from the first side of the main display area MDA and curved with a certain curvature. The first side display area SDA1 may extend from the lower side of the main display area MDA. The first side display area SDA1 may be arranged (or set) on the lower surface of the display device 1.

[0063] The second side display area SDA2 can be an area extending from the second side of the main display area MDA and curved at a certain curvature. The second side display area SDA2 can extend from the right side of the main display area MDA. The second side display area SDA2 can be arranged on the right side surface of the display device 1.

[0064] The third-side display area SDA3 can be an area extending from the third side of the main display area MDA and curved with a certain curvature. The third-side display area SDA3 can extend from the left side of the main display area MDA. The third-side display area SDA3 can be arranged on the left surface of the display device 1.

[0065] The fourth side display area SDA4 can be an area extending from the fourth side of the main display area MDA and curved at a certain curvature. The fourth side display area SDA4 can extend from the top side of the main display area MDA. The fourth side display area SDA4 can be arranged on the top surface of the display device 1.

[0066] The corner display area CDA can extend from the corner of the main display area MDA and can be curved at a certain curvature. The corner display area CDA can be arranged between the first side display area SDA1 to the fourth side display area SDA4. In one embodiment, for example, multiple corner display areas CDA can each be arranged between the first side display area SDA1 and the second side display area SDA2, between the first side display area SDA1 and the third side display area SDA3, between the second side display area SDA2 and the fourth side display area SDA4, or between the third side display area SDA3 and the fourth side display area SDA4.

[0067] Display device 1 can provide an image using a main pixel PXm arranged in the main display area MDA, a side pixel PXs arranged in the side display area SDA, and a corner pixel PXc arranged in the corner display area CDA.

[0068] In an embodiment, the image displayed on the corner display area CDA and / or the side display area SDA may be an auxiliary image and may have a lower resolution compared to the image displayed on the main display area MDA. In such an embodiment, the number of corner pixels PXc per unit area in the corner display area CDA may be less than the number of main pixels PXm per unit area in the main display area MDA. In an embodiment, the resolution of the side display area SDA may be equal to or less than the resolution of the main display area MDA.

[0069] Figure 2 It is along Figure 1 The cross-sectional view of display device 1 taken by line I-I'.

[0070] refer to Figure 2 An embodiment of the display device 1 may include a display panel 10 and a cover window 20 disposed on the display panel 10.

[0071] Covering window 20 can cover and protect display panel 10. Covering window 20 may include a transparent material. Covering window 20 may include, for example, glass or plastic. In embodiments where covering window 20 includes plastic, covering window 20 may be flexible.

[0072] The shape of the cover window 20 corresponds to the shape of the display device 1. In one embodiment, for example, the display device 1 includes a side display area SDA and a corner display area CDA, the cover window 20 may also include a side surface portion corresponding to the side display area SDA and a corner portion corresponding to the corner display area CDA. In embodiments, the side surface portion and the corner portion of the cover window 20 may be curved, and the side surface portion and the corner portion may each have a constant curvature or a variable curvature.

[0073] The display panel 10 may be located below the cover window 20. The cover window 20 and the display panel 10 may be coupled to each other via an adhesive member 30. The adhesive member 30 may include an optically clear adhesive (“OCA”) film or an optically clear resin (“OCR”) film.

[0074] Figure 3A yes Figure 1 A plan view of the display panel 10 in the display device 1 in its unfolded state, and Figure 3B yes Figure 3A An enlarged view of the circled part.

[0075] refer to Figure 3A Various components of the display panel 10 are mounted on the substrate 100. The substrate 100 may include a main display area MDA, a side display area SDA, a corner display area CDA, and a peripheral area PA.

[0076] The main display area (MDA) comprises multiple main pixels (PXm), and the main image can be displayed through these main pixels. Each main pixel (PXm) can include a group of sub-pixels. Each sub-pixel can emit red, green, blue, or white light.

[0077] The side display area SDA can be located above, below, to the left, and to the right of the main display area MDA. Side pixels PXs are located in the side display area SDA and can display side images. The side image can form a single overall image together with the main image, or it can be a separate image independent of the main image.

[0078] The corner display area (CDA) can be located at the corner extending from the main display area (MDA). The corner display area (CDA) can be located between two side display areas (SDAs). Multiple corner pixels (PXc) are located in the corner display area (CDA), and the corner image can be displayed. The corner image can form a single overall image together with the main image and the side images, or it can be a separate image independent of the main image.

[0079] In an embodiment, such as Figure 3B As shown, the corner display area CDA may include a first corner display area CDA1 and a second corner display area CDA2. The first corner display area CDA1 is located at the edge of the substrate 100 or further from the edge than the second corner display area CDA2, and the second corner display area CDA2 may be located between the first corner display area CDA1 and the main display area MDA.

[0080] In addition to the corner pixel PXc, the first scan driving circuit SDRV1 can be located in the second corner display area CDA2. The first scan driving circuit SDRV1 can provide scan signals for driving the corner pixel PXc in the corner display area CDA. In such an embodiment, the first scan driving circuit SDRV1 can provide scan signals for driving the main pixel PXm in the main display area MDA or the side pixel PXs in the side display area SDA. In an embodiment, the first scan driving circuit SDRV1 can be connected to the pixel circuits for driving the corner pixel PXc and the pixel circuits for driving the main pixel PXm, and can provide the same scan signals for both. In such an embodiment, the scan line SL connected to the first scan driving circuit SDRV1 can extend from the opposite side of the first scan driving circuit SDRV1 to the main display area MDA and the corner display area CDA.

[0081] The peripheral area PA can be located on the outside of the side display area SDA. The second scan drive circuit SDRV2 and the terminal portion (or pad area) PDA can be located within the peripheral area PA.

[0082] The second scan drive circuit SDRV2 can provide scan signals for driving the main pixel PXm and the side pixels PXs. The second scan drive circuit SDRV2 can be located on the right side of the second side display area SDA2 and / or on the left side of the third side display area SDA3, and can be connected to the scan line SL extending in the x direction.

[0083] The terminal portion of the PDA can be located on the underside of the first side display area SDA1. The terminal portion of the PDA can be exposed to connect to the display circuit board FPCB without being covered by an insulating layer. The display driver 32 can be located on the display circuit board FPCB.

[0084] The display driver 32 can generate control signals that will be transmitted to the first scan drive circuit SDRV1 and the second scan drive circuit SDRV2. In such an embodiment, the display driver 32 can generate data signals. The data signals can be transmitted to pixels PXm, PXs, and PXc via fan-out wiring FW and data lines DLm and DLc connected to the fan-out wiring FW. The main data line DLm can extend in the y-direction and can be connected to the pixel circuitry for driving the main pixel PXm. The corner data line DLc can be bent in the main display area MDA and extend to the corner display area CDA. The corner data line DLc can be connected to the pixel circuitry for driving the corner pixel PXc.

[0085] Figure 4 It is along Figure 3BThe cross-sectional view of the display panel 10 taken by line II-II'.

[0086] refer to Figure 4 The embodiment of the display panel 10 includes a corner display area CDA and a main display area MDA, and the corner display area CDA may include a first corner display area CDA1 and a second corner display area CDA2. The display panel 10 may include a substrate 100 and a display layer DISL, a touch screen layer TSL and an optical functional layer OFL on the substrate 100.

[0087] The display layer DISL may include: a circuit layer containing thin-film transistors TFTm, TFTc, and TFTd; light-emitting elements EDm and EDc as display elements; and a thin-film encapsulation layer TFEL. Insulating layers IL and IL' may be between the substrate 100 and the display layer DISL, or may be within the display layer DISL.

[0088] The substrate 100 may include insulating materials such as glass, quartz, and polymer resins. The substrate 100 may include a rigid substrate or a flexible substrate that is bendable, foldable, and rollable.

[0089] The main pixel circuit PCm and the main light-emitting element EDm connected to the main pixel circuit PCm can be located in the main display area MDA of the display panel 10. The main pixel circuit PCm may include a thin-film transistor TFTm and can control the light emission from the main light-emitting element EDm.

[0090] The corner pixel circuit PCc and the corner light-emitting element EDc connected to the corner pixel circuit PCc can be located in the first corner display area CDA1 and the second corner display area CDA2 of the display panel 10. The corner pixel circuit PCc can include a thin-film transistor TFTc and can control the light emission from the corner light-emitting element EDc.

[0091] In an embodiment, the first scan driving circuit SDRV1 may also be located in the second corner display area CDA2. The first scan driving circuit SDRV1 may include a thin-film transistor TFTd and may provide a scan signal to the corner pixel circuit PCc in the corner display area CDA. The corner light-emitting elements EDc in the first corner display area CDA1 and the second corner display area CDA2 may have the same pixel arrangement. Due to the consistent pixel arrangement in the corner light-emitting elements EDc, the corner light-emitting elements EDc in the second corner display area CDA2 may overlap with the first scan driving circuit SDRV1.

[0092] In this embodiment, the corner display area CDA is an auxiliary display area, and the resolution of the corner display area CDA can be less than the resolution of the main display area MDA. In such an embodiment, the number of corner light-emitting elements EDc per unit area in the corner display area CDA can be less than the number of main light-emitting elements EDm per unit area in the main display area MDA.

[0093] The corner light-emitting element EDc in the corner display area CDA can be larger than the main light-emitting element EDm in the main display area MDA. In one embodiment, for example, the emitting area of ​​the corner light-emitting element EDc can be larger than the emitting area of ​​the main light-emitting element EDm in the main display area MDA. Therefore, the corner display area CDA with lower resolution can provide the same or similar brightness as the main display area MDA.

[0094] The main light-emitting element EDm and the corner light-emitting elements EDc, which serve as display elements, can be covered by a thin-film encapsulation layer TFEL. In an embodiment, as shown... Figure 4 As shown, the thin-film encapsulation layer TFEL may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In an embodiment, the thin-film encapsulation layer TFEL may include a first inorganic encapsulation layer 131, a second inorganic encapsulation layer 133, and an organic encapsulation layer 132 between the first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 133.

[0095] The first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 133 may each comprise materials selected from silicon oxide (SiO2) and silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y Aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO) x The organic encapsulation layer 132 may comprise at least one inorganic insulating material, such as ZnO or ZnO2, and may be formed by a chemical vapor deposition (“CVD”) method. The organic encapsulation layer 132 may comprise a polymer-based material. For example, the polymer-based material may comprise at least one selected from silicone-based resins, acrylic-based resins, epoxy-based resins, polyimides, and polyethylene.

[0096] A touch screen layer (TSL) can obtain coordinate information corresponding to external inputs (e.g., touch events). A TSL may include touch electrodes and touch lines connected to the touch electrodes. The TSL can sense external inputs based on self-capacitance or mutual capacitance methods.

[0097] In one embodiment, the touch screen layer TSL can be provided on the thin-film encapsulation layer TFEL, for example, directly on the thin-film encapsulation layer TFEL. Alternatively, the touch screen layer TSL can be formed separately on the touch substrate and then coupled to the thin-film encapsulation layer TFEL via an adhesive layer such as an optically clear adhesive (“OCA”). In another embodiment, the touch screen layer TSL can be directly on the thin-film encapsulation layer TFEL, and no adhesive layer may be provided between the touch screen layer TSL and the thin-film encapsulation layer TFEL.

[0098] The optical functional layer (OFL) may include an anti-reflective layer. The anti-reflective layer reduces the reflectivity of light (external light) incident from the outside into the display device 1. In one embodiment, the optical functional layer (OFL) may include a polarizing film. In another embodiment, the optical functional layer (OFL) may include a filter plate comprising a black matrix and a color filter.

[0099] Display panel 10 may be a light-emitting display panel including light-emitting elements. In one embodiment, for example, display panel 10 may include an organic light-emitting display panel using organic light-emitting diodes as light-emitting elements, a micro-LED display panel using micro-LEDs as light-emitting elements, a quantum dot organic light-emitting display panel using quantum dots and organic light-emitting diodes, or an inorganic light-emitting display panel using inorganic semiconductors as light-emitting elements. In the following description, for ease of description, embodiments of display panel 10 including organic light-emitting display panels will be described in detail, but are not limited thereto.

[0100] Figure 5 It is along Figure 3A The cross-sectional view of the display panel 10 taken by line III-III'.

[0101] refer to Figure 5 The main pixel circuit PCm, including thin-film transistors (TFTs) and storage capacitors (Cst), and the organic light-emitting diode (OLED) as a display element connected to the main pixel circuit PCm, can be located in the main display area (MDA). The emission region of the OLED can form or define a main sub-pixel SPXm.

[0102] The structure of the multiple stacked components in the display panel 10 will be described below.

[0103] The substrate 100 may include insulating materials such as glass, quartz, and polymer resins. The substrate 100 may be a rigid substrate or a flexible substrate that is bendable, foldable, and rollable. In embodiments, the substrate 100 may have a structure in which organic and inorganic layers are stacked alternately.

[0104] A buffer layer 111 is disposed on a substrate 100 to reduce or block the penetration of impurities, moisture, or external air from the lower portion of the substrate 100 and to provide a flat surface on the substrate 100. The buffer layer 111 may comprise inorganic, organic, or inorganic-organic composite materials such as oxide or nitride materials, and may have a single-layer or multi-layer structure in which each layer comprises both inorganic and organic materials. A barrier layer (not shown) may be further provided between the substrate 100 and the buffer layer 111 to prevent the penetration of external air. In embodiments, the buffer layer 111 may comprise silicon oxide (SiO2) or silicon nitride (SiN). x ).

[0105] A thin-film transistor (TFT) can be mounted on a buffer layer 111. The TFT includes a first semiconductor layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The TFT is connected to an organic light-emitting diode (OLED) to drive the OLED.

[0106] The first semiconductor layer A1 is on the buffer layer 111 and may include polycrystalline silicon. In an alternative embodiment, the first semiconductor layer A1 may include amorphous silicon. In another alternative embodiment, the first semiconductor layer A1 may include an oxide selected from at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The first semiconductor layer A1 may include a channel region and impurity-doped source and drain regions.

[0107] The first gate insulating layer 112 may cover the first semiconductor layer A1. The first gate insulating layer 112 may include materials such as silicon oxide (SiO2) and silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y Aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO) x The first gate insulating layer 112 may have a single-layer structure or a multi-layer structure in which each layer comprises an inorganic insulating material.

[0108] The first gate electrode G1 is located on the first gate insulating layer 112 and overlaps with the first semiconductor layer A1. The first gate electrode G1 may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a single-layer structure or a multi-layer structure. In one embodiment, for example, the first gate electrode G1 may have a single layer including Mo.

[0109] The second gate insulating layer 113 may cover the first gate electrode G1. The second gate insulating layer 113 may include materials such as silicon oxide (SiO2) and silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y Aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO) x The second gate insulating layer 113 may have a single-layer structure or a multi-layer structure in which each layer comprises an inorganic insulating material.

[0110] The upper electrode CE2 of the storage capacitor Cst may be on the second gate insulating layer 113. The upper electrode CE2 of the storage capacitor Cst may overlap with the first gate electrode G1 below it. The first gate electrode G1 and the upper electrode CE2, which overlap each other and have the second gate insulating layer 113 between them, may constitute or jointly define the storage capacitor Cst. The first gate electrode G1 may be the lower electrode CE1 of the storage capacitor Cst.

[0111] The upper electrode CE2 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu) formed in a single-layer or multi-layer structure.

[0112] Interlayer insulating layer 115 may cover the upper electrode CE2. Interlayer insulating layer 115 may include materials such as silicon oxide (SiO2) and silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y Aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO) x The interlayer insulation layer 115 may be a single-layer structure or a multi-layer structure in which each layer comprises an inorganic insulating material.

[0113] The source electrode S1 and drain electrode D1 may be located on the interlayer insulating layer 115. The source electrode S1 and drain electrode D1 may comprise a conductive material containing molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer structure or a multilayer structure in which each layer comprises at least one of the aforementioned conductive materials. In one embodiment, for example, the source electrode S1 and drain electrode D1 may each have a multilayer structure in which each layer comprises a Ti / Al / Ti layer.

[0114] The first organic insulating layer 116 may be on the source electrode S1 and the drain electrode D1. For example, the first organic insulating layer 116 may include photosensitive polyimide, polyimide, polycarbonate (“PC”), general polymers such as benzocyclobutene (“BCB”), hexamethyldisiloxane (“HMDSO”), polymethyl methacrylate (“PMMA”) or polystyrene (“PS”), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluoropolymers, p-xylyl polymers, or vinyl alcohol polymers.

[0115] Alternatively, the first organic insulating layer 116 may comprise a siloxane-based organic material. The siloxane-based organic material may comprise hexamethyldisiloxane, octamethyltrisiloxane, decamethyltetrasiloxane, dodecylpentasiloxane, or polydimethylsiloxane.

[0116] The connecting electrodes CM and various lines WL (e.g., drive voltage lines or data lines) can be highly integrated on the first organic insulating layer 116.

[0117] The second organic insulating layer 117 can be applied over the first organic insulating layer 116 to cover the connecting electrode CM and the line WL. The second organic insulating layer 117 can have a flat upper surface, allowing the pixel electrode 121 disposed on the second organic insulating layer 117 to be planarized. The second organic insulating layer 117 can comprise a siloxane-based organic material with high light transmittance and flatness. The siloxane-based organic material can include hexamethyldisiloxane, octamethyltrisiloxane, decamethyltetrasiloxane, dodecylpentasiloxane, or polydimethylsiloxane.

[0118] Alternatively, the second organic insulating layer 117 may include photosensitive polyimide, polyimide, general-purpose polymer (BCB, HMDSO, PMMA or PS), polymer derivatives having phenolic groups, acrylic polymer, imide polymer, aryl ether polymer, amide polymer, fluoropolymer, p-xylyl polymer or vinyl alcohol polymer.

[0119] The organic light-emitting diode (OLED) can be located on the second organic insulating layer 117. The pixel electrode 121 of the OLED can be connected to the main pixel circuit PCm via the connection electrode CM on the first organic insulating layer 116.

[0120] Pixel electrode 121 may include a conductive oxide such as indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide, or aluminum zinc oxide (“AZO”). Pixel electrode 121 may include a reflective layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. In one embodiment, for example, pixel electrode 121 may have a structure comprising a film including ITO, IZO, ZnO, or In2O3 on / below the aforementioned reflective layer. In such an embodiment, pixel electrode 121 may include a stacked structure of ITO / Ag / ITO.

[0121] A pixel defining layer 118 may be applied over a second organic insulating layer 117 to cover the edge portion of the pixel electrode 121, and a first opening OP1 is defined by the pixel defining layer 118 to expose the central portion of the pixel electrode 121. The size and shape of the emission region (i.e., the principal sub-pixel SPXm) of the organic light-emitting diode OLED are defined by the first opening OP1.

[0122] The pixel defining layer 118 increases the distance between the edge of the pixel electrode 121 and the opposing electrode 123 on the pixel electrode 121 to prevent arcing at the edge of the pixel electrode 121. The pixel defining layer 118 may include organic insulating materials such as polyimide, polyamide, acrylic resin, BCB, HMDSO and phenolic resin, and may be formed by spin coating.

[0123] The first emitting layer 122b is located in the first opening OP1 of the pixel defining layer 118, corresponding to the pixel electrode 121. The first emitting layer 122b may comprise a polymer material or a low molecular weight material, and may emit red, green, blue, or white light.

[0124] The organic functional layer 122e may be on and / or below the first emitter layer 122b. The organic functional layer 122e may include the first functional layer 122a and / or the second functional layer 122c. Alternatively, the first functional layer 122a or the second functional layer 122c may be omitted.

[0125] The first functional layer 122a may be below the first emitting layer 122b. The first functional layer 122a may have a single-layer structure or a multi-layer structure in which each layer comprises an organic material. The first functional layer 122a may include a hole transport layer (“HTL”) having a single-layer structure. Alternatively, the first functional layer 122a may include a hole injection layer (“HIL”) and the HTL. The first functional layer 122a may be integrally or commonly formed to correspond to an organic light-emitting diode (OLED) included in the main display area MDA.

[0126] The second functional layer 122c may be on the first emitting layer 122b. The second functional layer 122c may have a single-layer structure or a multi-layer structure in which each layer comprises an organic material. The second functional layer 122c may include an electron transport layer (“ETL”) and / or an electron injection layer (“EIL”). The second functional layer 122c may be integrally or commonly formed to correspond to an organic light-emitting diode (OLED) included in the main display area MDA.

[0127] The counter electrode 123 is located on the second functional layer 122c. The counter electrode 123 may comprise a conductive material having a low work function. In one embodiment, for example, the counter electrode 123 may comprise a (semi-)transparent layer containing a material such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Alternatively, the counter electrode 123 may also comprise a layer containing ITO, IZO, ZnO, or In2O3 on top of a (semi-)transparent layer containing the aforementioned materials. The counter electrode 123 may be integrally or commonly formed to correspond to an organic light-emitting diode (OLED) included in the main display area MDA.

[0128] The layers from pixel electrode 121 to opposite electrode 123 in the main display area MDA can constitute an organic light-emitting diode (OLED).

[0129] An upper layer 150 comprising organic material may be provided on the counter electrode 123. The upper layer 150 may be provided to protect the counter electrode 123 and improve light extraction efficiency. The upper layer 150 may comprise an organic material having a refractive index higher than that of the counter electrode 123. Alternatively, the upper layer 150 may comprise a stack of layers with different refractive indices. In one embodiment, for example, the upper layer 150 may comprise a high refractive index layer / a low refractive index layer / a high refractive index layer. The high refractive index layer may have a refractive index of approximately 1.7 or greater, and the low refractive index layer may have a refractive index of approximately 1.3 or less.

[0130] The upper layer 150 may additionally include lithium fluoride (LiF). Alternatively, the upper layer 150 may additionally include materials such as silicon oxide (SiO2) and silicon nitride (SiN). x Inorganic insulating materials.

[0131] The thin-film encapsulation layer TFEL can be placed on the upper layer 150. The thin-film encapsulation layer TFEL can prevent external moisture or impurities from penetrating into the organic light-emitting diode OLED.

[0132] The thin-film encapsulation layer TFEL may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In an embodiment, such as... Figure 5As shown, the thin-film encapsulation layer TFEL may include a first inorganic encapsulation layer 131, an organic encapsulation layer 132, and a second inorganic encapsulation layer 133 stacked thereon. In alternative embodiments, the stacking order and number of the organic and inorganic encapsulation layers may vary.

[0133] The first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 133 may each comprise materials selected from silicon oxide (SiO2) and silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y Aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO) x The organic encapsulation layer 131 may be one or more inorganic insulating materials, such as ZnO or ZnO2, and may be formed by chemical vapor deposition (“CVD”) or similar methods. The organic encapsulation layer 132 may include a polymer-based material. For example, the polymer-based material may include at least one selected from silicone-based resins, acrylic-based resins, epoxy-based resins, polyimide, and polyethylene. The first inorganic encapsulation layer 131, the organic encapsulation layer 132, and the second inorganic encapsulation layer 133 may be integrally provided to cover the main display area MDA.

[0134] Figure 5 An embodiment of a stacked structure for the main display area MDA is shown, but the stacked structure can also be applied to the side display area SDA and the corner display area CDA.

[0135] Figure 6 This is a diagram illustrating a pixel arrangement structure that can be applied to the main display area MDA according to an embodiment.

[0136] refer to Figure 6 Multiple master subpixels SPXm can be present in the main display area MDA. In this document, a subpixel is the smallest unit used to implement an image and indicates a light-emitting area. A master pixel PXm can include a set of master subpixels SPXm. A master pixel PXm can include a first subpixel SPr, a second subpixel SPg, and a third subpixel SPb that emit light of different colors from each other. The first subpixel SPr, the second subpixel SPg, and the third subpixel SPb can emit red light, green light, and blue light, respectively. In an embodiment, a master pixel PXm can include one first subpixel SPr, two second subpixels SPg, and one third subpixel SPb.

[0137] In an embodiment, such as Figure 6 As shown, the primary sub-pixels SPXm in the main display area MDA can be arranged in a Pentile structure.

[0138] In the first row 1N, multiple first sub-pixels SPr and multiple third sub-pixels SPb are provided alternately, and in the adjacent second row 2N, multiple second sub-pixels SPg are spaced apart from each other. In the adjacent third row 3N, multiple third sub-pixels SPb and multiple first sub-pixels SPr are provided alternately, and in the adjacent fourth row 4N, multiple second sub-pixels SPg are spaced apart from each other. Furthermore, the above arrangement is repeated up to the Nth row. In such an embodiment, the third sub-pixels SPb and the first sub-pixels SPr may be larger than the second sub-pixels SPg.

[0139] Multiple first sub-pixels SPr and multiple third sub-pixels SPb in the first row 1N are arranged to intersect with multiple second sub-pixels SPg in the second row 2N. Therefore, multiple first sub-pixels SPr and multiple third sub-pixels SPb are alternately arranged in the first column 1M, multiple second sub-pixels SPg are arranged in the adjacent second column 2M with a certain distance between them, multiple third sub-pixels SPb and multiple first sub-pixels SPr are alternately arranged in the adjacent third column 3M, and multiple second sub-pixels SPg are arranged in the adjacent fourth column 4M with a certain distance between them. In this embodiment, the above arrangement of pixels is repeated up to the Mth column.

[0140] In such an embodiment, the first sub-pixel SPr is arranged at the first and third vertices facing each other within the vertices of the virtual square VS centered on the center of the second sub-pixel SPg, and the third sub-pixel SPb can be arranged at the remaining vertices (i.e., the second and fourth vertices) of the virtual square VS centered on the center of the second sub-pixel SPg. Here, the virtual square VS can be modified in various ways, such as a rectangle, a rhombus, etc.

[0141] This pixel arrangement structure is called a Pentile matrix structure or Pentile structure. High resolution can be achieved with a small number of pixels through rendering, where the color of a pixel is represented by the colors of its neighboring pixels that share the same pixel.

[0142] Figure 6 The illustration shows a plurality of principal sub-pixels SPXm arranged in a Pentile matrix structure, but one or more embodiments are not limited thereto. In an alternative embodiment, for example, the plurality of principal sub-pixels SPXm may be arranged in at least one of various structures (e.g., strip structure, mosaic arrangement structure, delta arrangement structure, etc.).

[0143] Figure 7 This is a diagram illustrating a pixel arrangement structure that can be applied to a corner display area CDA according to an embodiment.

[0144] refer to Figure 7 Multiple corner sub-pixels SPXc can be located in the corner display area CDA. A corner pixel PXc can include a group of corner sub-pixels SPXc. A corner pixel PXc can include a first sub-pixel SPr, a second sub-pixel SPg, and a third sub-pixel SPb that emit light of different colors. The first sub-pixel SPr, the second sub-pixel SPg, and the third sub-pixel SPb can emit red light, green light, and blue light, respectively. In an embodiment, a corner pixel PXc can include three corner sub-pixels SPXc, such as a first sub-pixel SPr, a second sub-pixel SPg, and a third sub-pixel SPb.

[0145] In an embodiment, in the first row 1J, the first sub-pixel SPr and the third sub-pixel SPb can be arranged alternately, and in the adjacent second row 2J, the second sub-pixel SPg can be arranged.

[0146] In such an embodiment, the second sub-pixel SPg can be arranged throughout the entire first column 1I and the second column 2I. In such an embodiment, the second sub-pixel SPg can be provided as a rectangular shape with its long side in the x' direction.

[0147] The length of the second sub-pixel SPg in the x' direction can be equal to or greater than the sum of the lengths of the first sub-pixel SPr and the third sub-pixel SPb in the x' direction. Therefore, the size of the second sub-pixel SPg can be larger than the sizes of the first sub-pixel SPr and the third sub-pixel SPb. This arrangement is called an S-strip structure.

[0148] In the corner display area CDA, basic units U can be repeatedly arranged in the x' and y' directions. Each basic unit U includes a predetermined number of corner pixels PXc and a non-pixel area NPA in which no pixels are provided. In an embodiment, as shown... Figure 7 As shown, the basic unit U can have a rectangular shape including a corner pixel PXc and a non-pixel region NPA surrounding the corner pixel PXc. The basic unit U is obtained by dividing a repeating shape and does not represent a break in the element.

[0149] In the main display area MDA, a corresponding unit U' with the same area as the basic unit U can be provided. In such an embodiment, the number of main sub-pixels SPXm included in the corresponding unit U' can be greater than the number of corner sub-pixels SPXc included in the basic unit U. In such an embodiment, the number of corner sub-pixels SPXc included in the basic unit U can be 3, and the number of main sub-pixels SPXm included in the corresponding unit U' can be 32.

[0150] In such an embodiment, the area occupied by a corner pixel PXc of the basic unit U can be approximately 1 / 4 of the basic unit U. In an embodiment, as... Figure 7 As shown, the basic unit U includes only one corner pixel PXc, but is not limited to this. In alternative embodiments, the basic unit U may include two or more corner pixels PXc. The number or arrangement type of corner sub-pixels SPXc included in the corner pixel PXc can be modified differently based on the resolution of the corner display area CDA. In such embodiments, the area of ​​the corner sub-pixels SPXc included in the corner pixel PXc can be modified differently.

[0151] Figure 8A and Figure 8B It is an equivalent circuit diagram of the pixel circuit for driving sub-pixels SPXm and SPXc according to one or more embodiments.

[0152] refer to Figure 8A In this embodiment, the pixel circuit PC can be connected to the light-emitting element ED to achieve light emission from the sub-pixels. The pixel circuit PC includes a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. The switching thin-film transistor T2 is connected to the scan line SL and the data line DL, and transmits the data signal Dm input through the data line DL to the driving thin-film transistor T1 in response to the scan signal Sn input through the scan line SL.

[0153] The storage capacitor Cst is connected to the switching thin-film transistor T2 and the drive voltage line PL, and stores a voltage corresponding to the difference between the voltage transmitted from the switching thin-film transistor T2 and the drive voltage ELVDD supplied to the drive voltage line PL.

[0154] The driving thin-film transistor T1 is connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL to the light-emitting element ED in response to the voltage value stored in the storage capacitor Cst. The light-emitting element ED can emit light with a predetermined brightness corresponding to the driving current.

[0155] Figure 8A An embodiment of a pixel circuit PC is shown, comprising two thin-film transistors T1 and T2 and a single storage capacitor Cst, but one or more embodiments are not limited thereto.

[0156] refer to Figure 8B In an alternative embodiment, the pixel circuit PC may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, and a second initialization thin-film transistor T7.

[0157] In such an embodiment, such as Figure 8B As shown, each pixel circuit PC includes signal lines SL, SL-1, SL+1, EL, DL, an initialization voltage line VL, and a drive voltage line PL; however, one or more embodiments are not limited thereto. In alternative embodiments, at least one of the signal lines SL, SL-1, SL+1, EL, and DL, and / or the initialization voltage line VL, may be shared by adjacent pixel circuits. Specifically, the signal lines SL, SL-1, SL+1, EL, and DL include scan lines SL, SL-1, and SL+1, an emission control line EL, and a data line DL.

[0158] The drain electrode of the driving thin-film transistor T1 can be electrically connected to the light-emitting element ED via the emitter control thin-film transistor T6. The driving thin-film transistor T1 receives the data signal Dm in response to the switching operation of the switching thin-film transistor T2 to supply driving current to the light-emitting element ED.

[0159] The gate electrode of the switching thin-film transistor T2 is connected to the scan line SL, and the source electrode of the switching thin-film transistor T2 is connected to the data line DL. The drain electrode of the switching thin-film transistor T2 is connected to the source electrode of the driving thin-film transistor T1, and can also be connected to the driving voltage line PL via the operation control thin-film transistor T5.

[0160] The switching thin-film transistor T2 is turned on according to the scan signal Sn received through the scan line SL, and performs a switching operation to transmit the data signal Dm transmitted through the data line DL to the source electrode of the driving thin-film transistor T1.

[0161] The gate electrode of the compensation thin-film transistor T3 can be connected to the scan line SL. The source electrode of the compensation thin-film transistor T3 is connected to the drain electrode of the driving thin-film transistor T1, and can also be connected to the pixel electrode of the light-emitting element ED via the emission control thin-film transistor T6. The drain electrode of the compensation thin-film transistor T3 can be connected together with the source electrode of the first initialization thin-film transistor T4 and the gate electrode of the driving thin-film transistor T1 to one electrode of the storage capacitor Cst. The compensation thin-film transistor T3 is turned on in response to the scan signal Sn transmitted through the scan line SL, and connects the gate electrode and drain electrode of the driving thin-film transistor T1 to each other for diode connection of the driving thin-film transistor T1.

[0162] The gate electrode of the first initialization thin-film transistor T4 can be connected to the previous scan line SL-1. The drain electrode of the first initialization thin-film transistor T4 can be connected to the initialization voltage line VL. The source electrode of the first initialization thin-film transistor T4, together with the drain electrode of the compensation thin-film transistor T3 and the gate electrode of the driving thin-film transistor T1, can be connected to one electrode of the storage capacitor Cst. The first initialization thin-film transistor T4 is turned on in response to the scan signal Sn-1 transmitted through the previous scan line SL-1 to transmit the initialization voltage Vint to the gate electrode of the driving thin-film transistor T1 and perform an initialization operation to initialize the voltage at the gate electrode of the driving thin-film transistor T1.

[0163] The gate electrode of the operation control thin-film transistor T5 can be connected to the emitter control line EL. The source electrode of the operation control thin-film transistor T5 can be connected to the drive voltage line PL. The drain electrode of the operation control thin-film transistor T5 is connected to the source electrode of the driving thin-film transistor T1 and the drain electrode of the switching thin-film transistor T2.

[0164] The gate electrode of the emission control thin-film transistor T6 can be connected to the emission control line EL. The source electrode of the emission control thin-film transistor T6 can be connected to the drain electrode of the driving thin-film transistor T1 and the source electrode of the compensation thin-film transistor T3. The drain electrode of the emission control thin-film transistor T6 can be electrically connected to the pixel electrode of the light-emitting element ED. The operation control thin-film transistor T5 and the emission control thin-film transistor T6 are simultaneously turned on in response to the emission control signal En transmitted through the emission control line EL to transmit the driving voltage ELVDD to the light-emitting element ED, and the driving current flows through the light-emitting element ED.

[0165] The gate electrode of the second initialization thin-film transistor T7 can be connected to the subsequent scan line SL+1. The source electrode of the second initialization thin-film transistor T7 can be connected to the pixel electrode of the light-emitting element ED. The drain electrode of the second initialization thin-film transistor T7 can be connected to the initialization voltage line VL. The second initialization thin-film transistor T7 is turned on in response to the subsequent scan signal Sn+1 transmitted through the subsequent scan line SL+1 to initialize the pixel electrode of the light-emitting element ED.

[0166] Figure 8B An embodiment is shown in which the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 are respectively connected to the previous scan line SL-1 and the subsequent scan line SL+1, but one or more embodiments are not limited thereto. In another alternative embodiment, the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 may both be connected to the previous scan line SL-1 to operate in response to the previous scan signal Sn-1.

[0167] The other electrode of the storage capacitor Cst can be connected to the drive voltage line PL. One electrode of the storage capacitor Cst can also be connected to the gate electrode of the driving thin-film transistor T1, the drain electrode of the compensation thin-film transistor T3, and the source electrode of the first initialization thin-film transistor T4.

[0168] The opposite electrode (e.g., the cathode) of the light-emitting element ED can receive a power supply from a common voltage ELVSS. The light-emitting element ED emits light after receiving a drive current from the driving thin-film transistor T1.

[0169] Pixel circuit PC is not limited to reference Figure 8A and Figure 8B The number of thin-film transistors and storage capacitors and the circuit design are shown, and the number and circuit design can be modified differently.

[0170] The pixel circuit PC used to drive the main sub-pixel SPXm and the corner sub-pixel SPXc can have the same structure as each other or different structures. In one embodiment, for example, the pixel circuit PC used to drive the main sub-pixel SPXm and the corner sub-pixel SPXc may include Figure 8B The pixel circuit PC shown is illustrated. In an alternative embodiment, the pixel circuit PC for driving the primary sub-pixel SPXm may include... Figure 8B The pixel circuit PC shown, and the pixel circuit PC used to drive the corner sub-pixel SPXc, may include Figure 8A The pixel circuit PC shown.

[0171] Figure 9A This is a plan view showing a portion of the display panel 10 according to an embodiment, and Figure 9B yes Figure 9A An enlarged view of the circled portion. In detail, the corner display area CDA of the display panel 10 is enlarged, and the flat state of the display panel 10 is shown.

[0172] refer to Figure 9A and Figure 9B An embodiment of the display panel 10 may include a plurality of strip-shaped portions STPs arranged in a corner display area CDA, and a plurality of cut portions V between the plurality of strip-shaped portions STPs. The plurality of cut portions V between the plurality of strip-shaped portions STPs may be formed by cutting a substrate 100. The plurality of cut portions V may be defined to pass through the display panel 10.

[0173] The end portions of multiple strip-shaped segments STP can be spaced apart from each other, and a certain gap gp exists between the end portions of the multiple strip-shaped segments STP. Due to the gap gp, empty spaces are formed between the multiple strip-shaped segments STP, and the empty spaces can each correspond to multiple cut portions V. The gap gp between the multiple strip-shaped segments STP can be variable. In one embodiment, for example, as... Figure 9B As shown, the gap gp between the plurality of strip-shaped portions STP can widen as it moves away from the main display area MDA toward the corner display area CDA. In an alternative embodiment, for example, the gap gp between the plurality of strip-shaped portions STP may not be variable, but rather uniform. In such an embodiment, the plurality of strip-shaped portions STP may be arranged radially or may be parallel to each other.

[0174] Multiple strip-shaped sections (STPs) may be connected to each other in portions adjacent to the main display area (MDA). The multiple strip-shaped sections (STPs) may extend from the main display area (MDA). The extension length of each of the multiple strip-shaped sections (STPs) may be different from each other. The extension length of the multiple strip-shaped sections (STPs) may vary according to the distance between each of the multiple strip-shaped sections (STPs) and the center of the corner display area (CDA). In one embodiment, for example, among the multiple strip-shaped sections (STPs), the strip-shaped section (STP) at the center portion may have a longer extension length toward the corner display area (CDA) than the other strip-shaped sections (STPs). As the multiple strip-shaped sections (STPs) move further away from the center of the corner display area (CDA), the extension length of the multiple strip-shaped sections (STPs) may decrease.

[0175] In an embodiment, each cut portion V may be defined to pass through the front and lower surfaces of the display panel 10. Each cut portion V can improve the flexibility of the display panel 10. In such an embodiment, when an external force (e.g., a force that bends, folds, or pulls the display panel 10) is applied to the display panel 10, the shape of the cut portion V can be changed to reduce the stress generated due to the deformation of the display panel 10, and thus, the durability of the display panel 10 can be improved.

[0176] When an external force is applied to the display panel 10, the area or shape of the cut portion V can be changed, and the position of the strip portion STP can also be changed. In one embodiment, for example, when a force is applied to the edge of the display panel 10 and the corner between the edges, the gap gp between the plurality of strip portions STP decreases. Therefore, the area of ​​the cut portion V can be reduced, and two adjacent strip portions STP can contact each other.

[0177] In this embodiment, when an external force is applied to the display panel 10, the gap gp between the plurality of strip-shaped portions STPs and the area of ​​the cutting portion V are changed, but the shape of the plurality of strip-shaped portions STPs remains unchanged. Therefore, even when an external force is applied to the display panel 10, the shape of the plurality of strip-shaped portions STPs on which pixel circuits, display elements, etc. are disposed remains unchanged. Thus, the pixel circuits, display elements, etc. on the plurality of strip-shaped portions STPs can be protected.

[0178] In such an embodiment, without altering the shape of the multiple strip-shaped portions STP, the corner pixels PXc can be located within the curved corner display area CDA in the display panel 10. In this embodiment, the display area for implementing the image can extend from the main display area MDA and the side display area SDA to the corner display area CDA. The corner pixels PXc on the strip-shaped portions STP can be spaced apart from each other in one direction.

[0179] Figure 10 This is a diagram illustrating the pixel arrangement structure, pixel circuit arrangement structure, and some signal lines in the main display area MDA according to an embodiment.

[0180] refer to Figure 10 The main sub-pixel SPXm is located in the main display area MDA of the display panel 10, and each main sub-pixel SPXm can realize color based on the driving of the main pixel circuit PCm. The main sub-pixel SPXm may include a first sub-pixel SPr, a second sub-pixel SPg, and a third sub-pixel SPb that emit light of different colors, and as referred to above. Figure 6 As described, the principal sub-pixels SPXm can be arranged in a Pentile structure.

[0181] The main pixel circuit PCm may include a first pixel circuit PCr, a second pixel circuit PCg, and a third pixel circuit PCb for driving the first sub-pixel SPr, the second sub-pixel SPg, and the third sub-pixel SPb, respectively.

[0182] In one embodiment, the main pixel circuit PCm can be arranged in a matrix in both the x and y directions. In such an embodiment, the first pixel circuit PCr and the third pixel circuit PCb are arranged alternately in the y direction, and the second pixel circuit PCg can be arranged in a column in the y direction.

[0183] The main data line DLm, configured to transmit data signals to the main pixel circuit PCm, can overlap with the central portion of the main pixel circuit PCm and can extend in the y direction.

[0184] Figure 11A This is a diagram illustrating the pixel arrangement structure in the corner display area CDA according to an embodiment, and Figure 11Band Figure 11C This is a diagram illustrating the pixel circuit arrangement and some signal lines in the corner display area CDA according to an embodiment. In detail, Figure 11A and Figure 11B The corner pixel PXc and corner pixel circuit PCc in the strip portion STP of the corner display area CDA are shown.

[0185] refer to Figure 11A and Figure 11B An embodiment of the display panel 10 may include a main display area MDA and a corner display area CDA. The corner display area CDA includes strip portions STP that extend from the main display area MDA, and cut portions V are arranged between multiple strip portions STP.

[0186] The strip-shaped portion STP can extend from the main display area MDA in a first direction. The first direction can vary depending on the position of the strip-shaped portion STP. The first direction can represent any direction between the x and y directions. The first direction can represent the direction of the long side of the strip-shaped portion STP. Furthermore, a second direction intersecting the first direction can represent the direction of the short side of the strip-shaped portion STP.

[0187] refer to Figure 11A In a strip-shaped portion STP, corner pixels PXc can be spaced apart from each other in a first direction, and there is a first distance d1 between corner pixels PXc. The arrangement of corner pixels PXc can be set considering a second distance d2 from corner pixels PXc in adjacent strip-shaped portions STP. In one embodiment, for example, the first distance d1 can be set as a value obtained by subtracting the width w1 of the cut portion in the second direction from the second distance d2. Therefore, corner pixels PXc can be uniformly arranged in the corner display area CDA.

[0188] The corner pixel PXc can include a first sub-pixel SPr, a second sub-pixel SPg, and a third sub-pixel SPb. The first sub-pixel SPr, the second sub-pixel SPg, and the third sub-pixel SPb can represent a red pixel, a green pixel, and a blue pixel, respectively. (Refer to the above.) Figure 7 As described, the first sub-pixel SPr, the second sub-pixel SPg, and the third sub-pixel SPb can be arranged in an S-strip structure.

[0189] In a strip-shaped portion STP, the sub-pixels in the nth corner pixel PXc in the first direction and the sub-pixels in the (n+1)th corner pixel PXc in the first direction can be arranged in the same way. Therefore, the first sub-pixel SPr included in a strip-shaped portion STP can be arranged in a column in the first direction. In such an embodiment, the third sub-pixel SPb included in a strip-shaped portion STP can be arranged in a column in the first direction (here, n is a positive integer).

[0190] refer to Figure 11B The corner pixel circuits PCc are spaced apart from each other in a strip-shaped section STP. The corner pixel circuits PCc may include a first pixel circuit PCr, a second pixel circuit PCg, and a third pixel circuit PCb. The first pixel circuit PCr can drive a first sub-pixel SPr, the second pixel circuit PCg can drive a second sub-pixel SPg, and the third pixel circuit PCb can drive a third sub-pixel SPb.

[0191] In an embodiment, the pixel circuits included in the nth corner pixel circuit PCc and the pixel circuits included in the (n+1)th corner pixel circuit PCc in the first direction of a strip-shaped portion STP can be arranged differently.

[0192] The pixel circuit included in the nth corner pixel circuit PCc may include a first pixel circuit PCr, a second pixel circuit PCg, and a third pixel circuit PCb arranged sequentially in the second direction, and the pixel circuit included in the (n+1)th corner pixel circuit PCc may include a third pixel circuit PCb, a second pixel circuit PCg, and a first pixel circuit PCr arranged sequentially in the second direction.

[0193] In such an embodiment, the first pixel circuit PCr and the third pixel circuit PCb in a strip-shaped portion STP can be arranged alternately along a first column C1 extending in a first direction. In a second column C2 adjacent to the first column C1, the second pixel circuit PCg can be arranged in a single column. In a third column C3 adjacent to the second column C2, the third pixel circuit PCb and the first pixel circuit PCr can be arranged alternately.

[0194] Therefore, the pixel circuits can be arranged in the same order as the pixel circuits in the main display area MDA. In embodiments where the pixel arrangement structure of the main display area MDA is a Pentile structure, the main pixel circuits included in the main display area MDA can be arranged such that the first and third sub-pixels of the main pixel (in the y-direction) are along the main data line DLm (see...). Figure 3A The first pixel circuit that drives the first sub-pixel and the third pixel circuit that drives the third sub-pixel can be arranged alternately.

[0195] In one embodiment, the pixel circuits in the strip portion STP are arranged in the same order as the pixel circuits in the main display area MDA. Simultaneously, the signals provided to the main display area MDA can also be applied to the corner display area CDA. In this embodiment, no additional signal lines need to be provided in the corner display area CDA. Because no additional signal lines are arranged in this embodiment, the width of the strip portion STP can be optimized.

[0196] The corner pixel circuit PCc is arranged from the center of the strip portion STP in a first direction, and the first signal line GW0 to the fifth signal line GW4, configured to transmit scan signals, can be arranged at the edge of the strip portion STP. The signal lines GW0 to GW4 can extend in a second direction.

[0197] The first signal line GW0 is configured to transmit a first scan signal and can be connected to the previous scan line SL-1 of the nth corner pixel circuit PCc. The second signal line GW1 is configured to transmit a second scan signal and can be connected to the scan line SL of the nth corner pixel circuit PCc. The previous scan line SL-1 and the scan line SL can extend in a second direction.

[0198] The second signal line GW1 is configured to transmit the second scan signal and can be connected to the previous scan line SL-1 of the (n+1)th corner pixel circuit PCc. The third signal line GW2 is configured to transmit the third scan signal and can be connected to the scan line SL of the (n+1)th corner pixel circuit PCc.

[0199] In such an embodiment, the second signal line GW1 can be shared by the nth corner pixel circuit PCc and the (n+1)th corner pixel circuit PCc.

[0200] The third signal line GW2 is configured to transmit the third scan signal and can be connected to the previous scan line SL-1 of the (n+2)th corner pixel circuit PCc. The fourth signal line GW3 is configured to transmit the fourth scan signal and can be connected to the scan line SL of the (n+2)th corner pixel circuit PCc.

[0201] The fourth signal line GW3 is configured to transmit the fourth scan signal and can be connected to the previous scan line SL-1 of the (n+3)th corner pixel circuit PCc. The fifth signal line GW4 is configured to transmit the fifth scan signal and can be connected to the scan line SL of the (n+4)th corner pixel circuit PCc.

[0202] In such an embodiment, the third signal line GW2 can be shared by the (n+1)th corner pixel circuit PCc and the (n+2)th corner pixel circuit PCc, and the fourth signal line GW3 can be shared by the (n+2)th corner pixel circuit PCc and the (n+3)th corner pixel circuit PCc.

[0203] Each of the first signal lines GW0 to the fifth signal line GW4 can be connected via bridging cabling BWL0 to BWL4 to a signal line arranged in an adjacent strip section STP. Bridging cabling BWL0 to BWL4 can extend in a second direction.

[0204] In such an embodiment, the corner data line DLc, configured to transmit data signals to the pixel circuitry in the corner display area CDA, may overlap with the center portion of the pixel circuitry. The corner data line DLc may extend along the length direction (first direction) of the strip portion STP. The corner data line DLc may extend in the same direction as the scan line configured to transmit scan signals.

[0205] In an embodiment, such as Figure 11B As shown, the bridging cabling BWL0 to BWL4 connects lines arranged on the right side of the strip portion STP or lines arranged on the left side of the strip portion STP, but one or more embodiments are not limited thereto.

[0206] In an alternative embodiment, for example, such as Figure 11C As shown, bridging cabling BWL0 to BWL4 can be designed to connect adjacent lines in each of the strip sections STP.

[0207] refer to Figure 11C In this embodiment, the first signal line GW0, the second signal line GW1, and the third signal line GW2 are arranged on the left side of the first strip portion STP1, and the fourth signal line GW3 and the fifth signal line GW4 can be arranged on the right side of the first strip portion STP1.

[0208] The first signal line GW0, the second signal line GW1, and the third signal line GW2 can be located on the right side of the second strip portion STP2, and the fourth signal line GW3 and the fifth signal line GW4 can be located on the left side of the second strip portion STP2.

[0209] In such an embodiment, the fourth signal line GW3 and the fifth signal line GW4 of the first strip portion STP1 are adjacent to the fourth signal line GW3 and the fifth signal line GW4 of the second strip portion STP2, and therefore, the fourth bridging wiring BWL3 and the fifth bridging wiring BWL4 can have reduced lengths.

[0210] Figure 12A and Figure 12B This is a diagram illustrating the arrangement of pixels and pixel circuits in the corner display area CDA according to an embodiment. In detail, Figure 12A The arrangement relationship between the nth corner pixel PXc and the corner pixel circuit PCc is shown, and Figure 12B The arrangement relationship between the (n+1)th corner pixel PXc and the corner pixel circuit PCc is shown.

[0211] refer to Figure 12A In the nth corner pixel circuit PCc, the first pixel circuit PCr, the second pixel circuit PCg, and the third pixel circuit PCb are provided sequentially in the second direction.

[0212] The first sub-pixel SPr may overlap with the first pixel circuit PCr. The display element implementing the first sub-pixel SPr may be connected to the first pixel circuit PCr via the first connection electrode CM1.

[0213] The second sub-pixel SPg can overlap with the first pixel circuit PCr, the second pixel circuit PCg, and the third pixel circuit PCb. The display element implementing the second sub-pixel SPg can be connected to the second pixel circuit PCg via the second connecting electrode CM2.

[0214] The third sub-pixel SPb can overlap with the third pixel circuit PCb. The display element implementing the third sub-pixel SPb can be connected to the third pixel circuit PCb via the third connection electrode CM3.

[0215] refer to Figure 12B In the (n+1)th corner pixel circuit PCc, the third pixel circuit PCb, the second pixel circuit PCg, and the first pixel circuit PCr are provided sequentially in the second direction.

[0216] The first sub-pixel SPr may overlap with the third pixel circuit PCb. The display element implementing the first sub-pixel SPr may be connected to the first pixel circuit PCr via a first connecting electrode CM1'. The first connecting electrode CM1' may extend across the upper part of the second pixel circuit PCg. The first connecting electrode CM1' may overlap with the first pixel circuit PCr, the second pixel circuit PCg, and the third pixel circuit PCb.

[0217] The second sub-pixel SPg can overlap with the first pixel circuit PCr, the second pixel circuit PCg, and the third pixel circuit PCb. The display element implementing the second sub-pixel SPg can be connected to the second pixel circuit PCg via the second connecting electrode CM2.

[0218] The third sub-pixel SPb may overlap with the first pixel circuit PCr. The display element implementing the third sub-pixel SPb may be connected to the first pixel circuit PCr via a third connecting electrode CM3'. The third connecting electrode CM3' may extend across the upper part of the second pixel circuit PCg. The third connecting electrode CM3' may overlap with the first pixel circuit PCr, the second pixel circuit PCg, and the third pixel circuit PCb.

[0219] Figure 13 It is along Figure 12B A cross-sectional view of the display panel 10 taken by line IV-IV'. Figure 13 In, with Figure 5 The same or similar reference numerals in the accompanying drawings indicate the same or similar elements, and any repeated detailed descriptions will be omitted or simplified.

[0220] refer to Figure 13 An embodiment of the display panel 10 may include a substrate 100, a first pixel circuit PCr, a second pixel circuit PCg and a third pixel circuit PCb on the substrate 100, and an organic light-emitting diode (OLED) included in sub-pixels SPg and SPb.

[0221] In a portion of the corner display area CDA, the first pixel circuit PCr may overlap with or not overlap with the third sub-pixel SPb. In such an embodiment, the third pixel circuit PCb may not overlap with the third sub-pixel SPb. Therefore, the third pixel circuit PCb may be connected to the organic light-emitting diode (OLED) included in the third sub-pixel SPb via the third connection electrode CM3'.

[0222] The third connecting electrode CM3' is located on the first organic insulating layer 116, and one end of the third connecting electrode CM3' can be connected to the third pixel circuit PCb via a contact hole defined in the first organic insulating layer 116. The other end of the third connecting electrode CM3' can be connected to the pixel electrode 121 of the organic light-emitting diode OLED included in the third sub-pixel SPb. A second organic insulating layer 117 is located between the third connecting electrode CM3' and the pixel electrode 121, and the pixel electrode 121 can be connected to the third connecting electrode CM3' via a contact hole defined in the second organic insulating layer 117. The third connecting electrode CM3' can overlap with the second pixel circuit PCg.

[0223] Figure 14A It is along Figure 9A The cross-sectional view of the display panel 10 taken by line F-F'. Figure 14B yes Figure 14A Enlarged view of the dam section DP. Figure 15 It is along Figure 9AA cross-sectional view of the display panel 10 taken by line H-H'. Figures 14A to 15 In, with Figure 5 The same or similar reference numerals in the accompanying drawings denote the same or similar elements, and therefore any repeated detailed descriptions will be omitted or simplified.

[0224] refer to Figure 14A and Figure 14B An embodiment of the display panel 10 may include a first corner display area CDA1 and a second corner display area CDA2. A corner thin-film transistor (TFTc) and a first corner organic light-emitting diode (OLED) 1 may be located in the first corner display area CDA1, and a second corner organic light-emitting diode (OLED) 2 may be located in the second corner display area CDA2. The corner TFTc and the first corner OLED 1 form sub-pixels in the first corner display area CDA1, and the second corner OLED 2 forms sub-pixels in the second corner display area CDA2.

[0225] A second corner organic light-emitting diode OLED2 can be located near the edge of the second corner display area CDA2 and can face the first corner organic light-emitting diode OLED1.

[0226] The connecting line CL can be on the base 100 where the first corner display area CDA1 and the second corner display area CDA2 are arranged. The connecting line CL may include a lower connecting line LCL, a first connecting line CL1, and a second connecting line CL2.

[0227] In one embodiment, the lower connection line LCL may be located between the first gate insulating layer 112 and the second gate insulating layer 113. In an alternative embodiment, the lower connection line LCL may be located between the second gate insulating layer 113 and the interlayer insulating layer 115. In such an embodiment, the lower connection line LCL may include... Figure 5 The first gate electrode G1 and the upper electrode CE2 shown are made of the same material. In another alternative embodiment, the lower connection line LCL may be located between the buffer layer 111 and the first gate insulating layer 112. In such an embodiment, the lower connection line LCL may include materials similar to those used in the first gate insulating layer 112. Figure 5 The first semiconductor layer A1 is made of the same material.

[0228] The lower connection line LCL can connect from the second corner display area CDA2 to the first corner display area CDA1. The lower connection line LCL can be a signal line for providing electrical signals to the first corner organic light-emitting diode OLED1, or it can be a power line for providing power.

[0229] The first connection line CL1 may be on the interlayer insulating layer 115, and the first organic insulating layer 116 may be on the first connection line CL1. The first organic insulating layer 116 may be separated into a first corner insulating layer 116C1 and a second corner insulating layer 116C2 based on the second hole HL2. The first corner insulating layer 116C1 may cover the corner thin-film transistor TFTc, and the second corner insulating layer 116C2 may cover the driving circuit thin-film transistor TFTd. In an embodiment, the first connection line CL1 may be partially exposed between the first corner insulating layer 116C1 and the second corner insulating layer 116C2.

[0230] The second connecting line CL2, the second connecting electrode CML2, and the third connecting electrode CML3 may be on the first organic insulating layer 116. The second connecting electrode CML2 may be on the first corner insulating layer 116C1. In an embodiment, the third connecting electrode CML3 may be a part of the second connecting line CL2.

[0231] The third connecting electrode CML3 can be on the second corner insulating layer 116C2. In an embodiment, the third connecting electrode CML3 can be connected to the first connecting line CL1. In such an embodiment, the third connecting electrode CML3 can extend from the second corner insulating layer 116C2 to the first corner insulating layer 116C1 and can cover the side surfaces of the second corner insulating layer 116C2 and the first corner insulating layer 116C1. In such an embodiment, the third connecting electrode CML3 can be connected to the first connecting line CL1 exposed between the first corner insulating layer 116C1 and the second corner insulating layer 116C2. Therefore, the first connecting line CL1 and the third connecting electrode CML3 can prevent external moisture from penetrating into the first corner organic light-emitting diode OLED1 or the second corner organic light-emitting diode OLED2.

[0232] The lower inorganic patterned layer LPVX can be on the second connecting line CL2 and the third connecting electrode CML3. In an embodiment, multiple lower inorganic patterned layers LPVX can be on the second connecting line CL2 and / or the third connecting electrode CML3, and the multiple lower inorganic patterned layers LPVX can be spaced apart from each other on the second connecting line CL2 and / or the third connecting electrode CML3. In an embodiment, one of the multiple lower inorganic patterned layers LPVX can cover the side surface of the second corner insulating layer 116C2 and the side surface of the first corner insulating layer 116C1 that face each other.

[0233] The second organic insulating layer 117 may cover the second connecting line CL2, the second connecting electrode CML2, and the third connecting electrode CML3. In such an embodiment, the second organic insulating layer 117 may cover the edge of the lower inorganic patterned layer LPVX.

[0234] Multiple apertures HL may be defined within a second organic insulating layer 117 to expose a portion of the underlying inorganic patterned layer LPVX. The second organic insulating layer 117 may include multiple apertures HL. In an embodiment, apertures HL may include a first aperture HL1, a second aperture HL2, a third aperture HL3, a fourth aperture HL4, and a fifth aperture HL5. The first aperture HL1 and the fourth aperture HL4 may overlap with a first corner display area CDA1. The third aperture HL3 and the fifth aperture HL5 may overlap with a second corner display area CDA2. The second aperture HL2 may be located between the third aperture HL3 and the fourth aperture HL4.

[0235] The aperture HL in the second organic insulating layer 117 can be formed by an etching process. If the lower inorganic patterning layer LPVX is omitted, the second connection line CL2 may be over-etched due to the etching process. In this case, the resistance of the second connection line CL2 may increase. In this embodiment, the lower inorganic patterning layer LPVX is provided on the second connection line CL2 to overlap with the aperture HL in the second organic insulating layer 117, thereby preventing over-etching of the second connection line CL2.

[0236] The corner inorganic pattern layer CPVX and the upper inorganic pattern layer UPVX can be on the second organic insulating layer 117. The corner inorganic pattern layer CPVX can overlap with the first corner display area CDA1. The upper inorganic pattern layer UPVX can overlap with the second corner display area CDA2. The upper inorganic pattern layer UPVX can extend between the first corner display area CDA1 and the main display area.

[0237] The corner inorganic pattern layer CPVX may include a first corner inorganic pattern layer CPVX1 and a second corner inorganic pattern layer CPVX2. In an embodiment, the first corner inorganic pattern layer CPVX1 may be located between the first corner organic light-emitting diode (OLED) 1 and the second organic insulating layer 117. The first corner inorganic pattern layer CPVX1 may be located between the pixel electrode of the first corner OLED 1 and the second organic insulating layer 117. On the second organic insulating layer 117, the second corner inorganic pattern layer CPVX2 may be spaced apart from the first corner inorganic pattern layer CPVX1, and an aperture HL is located between the second corner inorganic pattern layer CPVX2 and the first corner inorganic pattern layer CPVX1. In one embodiment, for example, the second corner inorganic pattern layer CPVX2 may be spaced apart from the first corner inorganic pattern layer CPVX1, and a first aperture HL1 is located between the second corner inorganic pattern layer CPVX2 and the first corner inorganic pattern layer CPVX1.

[0238] In an embodiment, the second corner inorganic pattern layer CPVX2 may include an outer inorganic pattern layer CPVX2-1 and an inner inorganic pattern layer CPVX2-2. The outer inorganic pattern layer CPVX2-1 and the inner inorganic pattern layer CPVX2-2 may be spaced apart from each other. The outer inorganic pattern layer CPVX2-1 may be further away from the first corner organic light-emitting diode OLED1 than the inner inorganic pattern layer CPVX2-2. In an embodiment, the outer inorganic pattern layer CPVX2-1 may overlap with the first dam portion DP1. The inner inorganic pattern layer CPVX2-2 may overlap with the first auxiliary dam portion ADP1.

[0239] The corner inorganic patterned layer CPVX and the upper inorganic patterned layer UPVX may each include a protruding tip PT projecting toward the center of the aperture HL. The center direction of the aperture HL may represent the direction from the inner surface of the second organic insulating layer 117 defining the aperture HL to the central axis of the aperture HL. Therefore, the lower surface of the protruding tip PT may be exposed in the aperture HL. In such an embodiment, the aperture HL of the second organic insulating layer 117 may have an undercut structure.

[0240] In one embodiment, the upper inorganic patterned layer UPVX and the inner inorganic patterned layer CPVX2-2 may each include a protruding tip PT projecting toward the center of the first hole HL1. In another embodiment, the inner inorganic patterned layer CPVX2-2 and the outer inorganic patterned layer CPVX2-1 may each have a protruding tip PT projecting toward the center of the fourth hole HL4. In such an embodiment, the hole HL of the second organic insulating layer 117 may have an undercut structure. At least one of the lower surface CPVXLS of the corner inorganic patterned layer CPVX and the lower surface UPVXLS of the upper inorganic patterned layer UPVX may overlap with the hole HL of the second organic insulating layer 117.

[0241] The dam portion DP may protrude from the upper surface of the upper inorganic patterned layer UPVX in the thickness direction of the substrate 100. The dam portion DP may include a first dam portion DP1 and a second dam portion DP2 spaced apart from each other. The dam portion DP and the aperture HL may be provided alternately.

[0242] The first corner organic pattern layer 118c1 may be on the corner inorganic pattern layer CPVX. The first corner organic pattern layer 118c1 may include the same material as the pixel defining layer 118. The first corner organic pattern layer 118c1 may be formed simultaneously with the pixel defining layer 118 in the same process.

[0243] The first corner organic pattern layer 118c1 may include a first sub-organic pattern layer 118a and a third sub-organic pattern layer 118c spaced apart from each other. The first sub-organic pattern layer 118a may be on the outer inorganic pattern layer CPVX2-1. The third sub-organic pattern layer 118c may be on the inner inorganic pattern layer CPVX2-2.

[0244] The second corner organic pattern layer 118c2 can be on the upper inorganic pattern layer UPVX. The second corner organic pattern layer 118c2 can include the same material as the pixel defining layer 118. The second corner organic pattern layer 118c2 can be formed simultaneously with the pixel defining layer 118 in the same process.

[0245] The second corner organic pattern layer 118c2 may include a second sub-organic pattern layer 118b and a fourth sub-organic pattern layer 118d spaced apart from each other. The second sub-organic pattern layer 118b and the fourth sub-organic pattern layer 118d may be on the upper inorganic pattern layer UPVX.

[0246] The first upper organic pattern layer 119a may be on the first sub-organic pattern layer 118a. The first sub-organic pattern layer 118a and the first upper organic pattern layer 119a may form or jointly define the first dam portion DP1.

[0247] The second upper organic pattern layer 119b may be on the second sub-organic pattern layer 118b. The second sub-organic pattern layer 118b and the second upper organic pattern layer 119b may form or jointly define the second dam portion DP2.

[0248] The first functional layer 122a, the second functional layer 122c, and the opposing electrode 123 on the corner inorganic patterned layer CPVX and the upper inorganic patterned layer UPVX can be disconnected by an aperture HL and a pair of protruding tips PT. In such an embodiment, the first functional layer pattern 122Pa, the second functional layer pattern 122Pc, and the opposing electrode pattern 123P can be within the aperture HL. In an embodiment, at least one of the lower surface CPVXLS of the corner inorganic patterned layer CPVX overlapping with the aperture HL and the lower surface UPVXLS of the upper inorganic patterned layer UPVX overlapping with the aperture HL may not be in contact with the first functional layer 122a, the second functional layer 122c, and the opposing electrode 123.

[0249] The first auxiliary dam portion ADP1 can be located between the first corner organic light-emitting diode OLED1 and the first dam portion DP1. The first auxiliary dam portion ADP1 can be located between the first hole HL1 and the fourth hole HL4. The first auxiliary dam portion ADP1 may include a third sub-organic patterning layer 118c. The second auxiliary dam portion ADP2 can be located between the second corner organic light-emitting diode OLED2 and the second dam portion DP2. The second auxiliary dam portion ADP2 can be located between the third hole HL3 and the fifth hole HL5. The second auxiliary dam portion ADP2 may include a fourth sub-organic patterning layer 118d.

[0250] In one embodiment, the thickness of the dam portion DP can be greater than the thickness of the first auxiliary dam portion ADP1. In such an embodiment, the thickness of the dam portion DP can be greater than the thickness of the second auxiliary dam portion ADP2. In one embodiment, for example, the first dam portion DP1 includes a first sub-organic patterned layer 118a and a first upper organic patterned layer 119a, while the first auxiliary dam portion ADP1 includes a third sub-organic patterned layer 118c. Therefore, the first dam portion DP1 and the first auxiliary dam portion ADP1 can have different thicknesses. The thickness of the first dam portion DP1 can correspond to the distance from the upper surface of the outer inorganic patterned layer CPVX2-1 to the upper surface of the first upper organic patterned layer 119a. The thickness of the first auxiliary dam portion ADP1 can correspond to the distance from the upper surface of the inner inorganic patterned layer CPVX2-2 to the upper surface of the third sub-organic patterned layer 118c.

[0251] In one embodiment, the distance from the upper surface of the substrate 100 to the upper surface of the first upper organic patterning layer 119a can be greater than the distance from the upper surface of the substrate 100 to the upper surface of the third sub-organic patterning layer 118c. In another embodiment, the distance from the upper surface of the substrate 100 to the upper surface of the second upper organic patterning layer 119b can be greater than the distance from the upper surface of the substrate 100 to the upper surface of the fourth sub-organic patterning layer 118d.

[0252] In this embodiment, the first auxiliary dam portion ADP1 and the second auxiliary dam portion ADP2 are located between the organic light-emitting diode (OLED) and the dam portion DP. In such an embodiment, the thickness of the first auxiliary dam portion ADP1 and the thickness of the second auxiliary dam portion ADP2 are less than the thickness of the dam portion DP, such that the first auxiliary dam portion ADP1 and the second auxiliary dam portion ADP2 do not contact the mask. Therefore, the first inorganic encapsulation layer 131 can be located on the flat upper surface of the first auxiliary dam portion ADP1 and the upper surface of the second auxiliary dam portion ADP2. This delays the time it takes for external air or moisture to reach the OLED and enhances the barrier properties of the first inorganic encapsulation layer 131.

[0253] In an embodiment, the first auxiliary dam section ADP1 and the second auxiliary dam section ADP2 may each have the same thickness as the dam section DP.

[0254] The thin-film encapsulation layer TFEL can cover the first corner organic light-emitting diode OLED1 and the second corner organic light-emitting diode OLED2. The thin-film encapsulation layer TFEL may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 14A and Figure 14B An embodiment of a thin-film encapsulation layer TFEL is shown, comprising a first inorganic encapsulation layer 131, an organic encapsulation layer 132, and a second inorganic encapsulation layer 133.

[0255] The thin-film encapsulation layer TFEL can extend from the first corner organic light-emitting diode OLED1 to the first dam portion DP1. Additionally, the thin-film encapsulation layer TFEL can extend from the second corner organic light-emitting diode OLED2 to the second dam portion DP2.

[0256] The first inorganic encapsulation layer 131 can completely and continuously cover the first corner display area CDA1 and the second corner display area CDA2. In such an embodiment, the first inorganic encapsulation layer 131 can be completely and continuously arranged throughout the entire first hole HL1, the first auxiliary dam portion ADP1, the fourth hole HL4, the first dam portion DP1, the second hole HL2, the second dam portion DP2, the third hole HL3, the second auxiliary dam portion ADP2, and the fifth hole HL5. In such an embodiment, the first inorganic encapsulation layer 131 can cover the first functional layer pattern 122Pa, the second functional layer pattern 122Pc, and the relative electrode pattern 123P arranged in the hole HL.

[0257] The first inorganic encapsulation layer 131 may contact the upper inorganic patterned layer UPVX and the corner inorganic patterned layer CPVX. In such an embodiment, the first inorganic encapsulation layer 131 may contact the protruding tips of the upper inorganic patterned layer UPVX and the protruding tips of the corner inorganic patterned layer CPVX. The first inorganic encapsulation layer 131 may contact the lower surface UPVXLS of the upper inorganic patterned layer UPVX that overlaps with the hole HL in the second organic insulating layer 117 and the lower surface CPVXLS of the corner inorganic patterned layer CPVX that overlaps with the hole HL in the second organic insulating layer 117.

[0258] The organic encapsulation layer 132 can be disconnected by the dam portion DP. In one embodiment, for example, the organic encapsulation layer 132 can extend from the first corner organic light-emitting diode OLED1 to the first dam portion DP1 and can overlap with the first aperture HL1 and / or the fourth aperture HL4. In such an embodiment, the organic encapsulation layer 132 can extend from the second corner organic light-emitting diode OLED2 to the second dam portion DP2 and can overlap with the third aperture HL3 and / or the fifth aperture HL5. In such an embodiment, the organic encapsulation layer 132 can be controlled by the first dam portion DP1 and the second dam portion DP2. In such an embodiment, the second aperture HL2 can be spaced apart from the organic encapsulation layer 132.

[0259] The second inorganic encapsulation layer 133 can completely and continuously cover the first corner display area CDA1 and the second corner display area CDA2, just like the first inorganic encapsulation layer 131. In an embodiment, the second inorganic encapsulation layer 133 can contact the first inorganic encapsulation layer 131 on the first dam portion DP1 and the second dam portion DP2. In such an embodiment, the second inorganic encapsulation layer 133 can contact the first inorganic encapsulation layer 131 in the second hole HL2. Therefore, the organic encapsulation layer 132 can be disconnected by the dam portion DP.

[0260] refer to Figure 15 The corner thin-film transistor TFTc, the first corner organic light-emitting diode OLED1, and the thin-film encapsulation layer TFEL can be in each of the first strip portion STP1 and the second strip portion STP2.

[0261] The first hole HL1 and the fourth hole HL4 can overlap with the first strip portion STP1 and the second strip portion STP2, respectively. The first auxiliary dam portion ADP1 can be between the first hole HL1 and the fourth hole HL4, and the first dam portion DP1 can be between the fourth hole HL4 and the cutting portion V (or the sixth hole HL6).

[0262] In the first corner display area CDA1, the first strip portion STP1 and the second strip portion STP2 can be spaced apart from each other, and the cut portion V is between the first strip portion STP1 and the second strip portion STP2. The inorganic insulating layer IIL, the first organic insulating layer 116, the second organic insulating layer 117 and the thin film encapsulation layer TFEL can be disconnected based on the cut portion V.

[0263] In embodiments of the present invention, as described above, the display panel and display device include corner display areas to extend the area for displaying images.

[0264] In such embodiments of the display panel and display device, the pixel circuits in the corner display areas can be optimally arranged, and therefore, the number of lines in the corner display areas can be reduced while ensuring space.

[0265] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

[0266] Although the invention has been specifically shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A display panel, wherein, The display panel includes: The substrate includes a main display area and a corner display area, wherein the corner display area extends from the corner of the main display area and includes a strip-shaped portion between cut portions; The main pixel is located in the main display area on the substrate; A main pixel circuit is located on the substrate in the main display area, wherein the main pixel circuit drives the main pixel; Multiple corner pixels, located on the substrate within the strip-shaped portion; and Multiple corner pixel circuits are located on the substrate within the strip-shaped portion, wherein the multiple corner pixel circuits drive the multiple corner pixels. in, Each corner pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. Each of the corner pixel circuits includes a first pixel circuit for driving the first sub-pixel, a second pixel circuit for driving the second sub-pixel, and a third pixel circuit for driving the third sub-pixel. The arrangement of the first pixel circuit, the second pixel circuit, and the third pixel circuit in the nth corner pixel circuit in the first direction, which is the length direction of the strip portion, is different from the arrangement of the first pixel circuit, the second pixel circuit, and the third pixel circuit in the (n+1)th corner pixel circuit in the first direction, where n is a positive integer.

2. The display panel according to claim 1, wherein, The first pixel circuit and the third pixel circuit are alternately arranged in a first column, which extends in the first direction, and The second pixel circuit is arranged in a second column adjacent to the first column.

3. The display panel according to claim 1, wherein, The first pixel circuit of the nth corner pixel circuit overlaps with the first sub-pixel, and The first pixel circuit of the (n+1)th corner pixel circuit overlaps with the third sub-pixel.

4. The display panel according to claim 1, wherein, The arrangement of the main pixels is different from the arrangement of the corner pixels.

5. The display panel according to claim 4, wherein, The main pixels are arranged in a Pentile pixel arrangement structure, and The corner pixels are arranged in an S-shaped structure.

6. The display panel according to claim 1, wherein, The plurality of corner pixel circuits are located in the central portion of the strip-shaped portion, and The signal line extending in the first direction is at the edge of the strip portion.

7. The display panel according to claim 6, wherein, The signal line transmits the scanning signal, and Some of the signal lines are connected to the nth corner pixel circuit and the (n+1)th corner pixel circuit.

8. The display panel according to claim 6, wherein, The corner data lines that transmit data signals to the plurality of corner pixel circuits overlap with the plurality of corner pixel circuits and extend in the first direction.

9. The display panel according to claim 1, wherein, The corner display area includes a first corner display area and a second corner display area. The strip-shaped portion is in the first corner display area, and The scanning drive circuit is located in the second corner display area.

10. The display panel according to claim 9, wherein, The corner pixels in the second corner display area at least partially overlap with the scanning drive circuit.

11. A display device, wherein, The display device includes: A display panel includes a main display area and corner display areas, wherein the corner display areas extend from the corners of the main display area and are curved with a preset radius of curvature; and A cover window that covers the display panel and has a shape corresponding to the shape of the display panel. The corner display area includes strip-shaped portions between the cut sections. The strip-shaped portion includes multiple corner pixels and multiple corner pixel circuits that drive the multiple corner pixels. Each corner pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. Each of the corner pixel circuits includes a first pixel circuit for driving the first sub-pixel, a second pixel circuit for driving the second sub-pixel, and a third pixel circuit for driving the third sub-pixel. The arrangement of the first pixel circuit, the second pixel circuit, and the third pixel circuit in the nth corner pixel circuit in the first direction, which is the length direction of the strip portion, is different from the arrangement of the first pixel circuit, the second pixel circuit, and the third pixel circuit in the (n+1)th corner pixel circuit in the first direction, where n is a positive integer.

12. The display device according to claim 11, wherein, The first pixel circuit and the third pixel circuit are alternately arranged in a first column, which extends in the first direction, and The second pixel circuit is arranged in a second column adjacent to the first column.

13. The display device according to claim 11, wherein, The first pixel circuit of the nth corner pixel circuit overlaps with the first sub-pixel, and The first pixel circuit of the (n+1)th corner pixel circuit overlaps with the third sub-pixel.

14. The display device according to claim 11, wherein, The main display area includes main pixels and main pixel circuitry that drives the main pixels, and The arrangement of the main pixels is different from the arrangement of the corner pixels.

15. The display device according to claim 14, wherein, The main pixels are arranged in a Pentile pixel arrangement structure, and The corner pixels are arranged in an S-shaped structure.

16. The display device according to claim 11, wherein, The plurality of corner pixel circuits are located in the central portion of the strip-shaped portion, and The signal line extending in the first direction is at the edge of the strip portion.

17. The display device according to claim 16, wherein, The signal line transmits the scanning signal, and Some of the signal lines are connected to the nth corner pixel circuit and the (n+1)th corner pixel circuit.

18. The display device according to claim 16, wherein, The corner data lines that transmit data signals to the plurality of corner pixel circuits overlap with the plurality of corner pixel circuits and extend in the first direction.

19. The display device according to claim 11, wherein, The corner display area includes a first corner display area and a second corner display area. The strip-shaped portion is in the first corner display area, and The scanning drive circuit is located in the second corner display area.

20. The display device according to claim 19, wherein, The corner pixels in the second corner display area at least partially overlap with the scanning drive circuit.

Images