Metal oxide semiconductor field effect transistor structure

Abstract

The present invention provides a novel metal oxide semiconductor field effect transistor (MOSFET) structure with a controllable channel length by forming a lightly doped drain without using ion implantation. The MOSFET structure includes a semiconductor wafer substrate having a semiconductor surface, a gate structure over the semiconductor surface, a channel region under the semiconductor surface, and a first conductive region electrically coupled to the channel region. The first conductive region includes a lightly doped drain region that is independent of the semiconductor wafer substrate.

Description

Technical Field

[0001] This invention relates to a metal-oxide-semiconductor field-effect transistor (MOSFET) structure, and more particularly to a MOSFET structure having a precisely defined source / drain boundary edge to the edge of the effective channel region to reduce leakage current. Background Technology

[0002] Figure 1 This displays the most widely used and advanced FinFET (FIN-structure Field-Effect Transistor) in today's integrated circuits (ICs). The transistor gate structure 10, using conductive materials (e.g., metals, polysilicon, or polycide) on an insulator (e.g., oxide, oxide / nitride, or some high-k dielectric), is formed on a three-dimensional (3D) silicon surface. The sidewalls of the 3D silicon surface are isolated from other transistors using insulating materials (e.g., oxide, oxide / nitride, or other dielectrics). Taking an NMOS transistor as an example, the source region 11 and drain region 12 are formed by ion implantation combined with thermal annealing to implant a high concentration of n-type dopant into a p-type substrate (or p-type well), resulting in two separate n+ / p junction regions. Furthermore, to reduce impact ionization and hot carrier injection before the heavily doped n+ / p junction, a lightly doped drain (LDD) region 13 is typically formed before the heavily doped n+ source / drain region using ion implantation followed by thermal annealing. However, this ion implantation and thermal annealing technique often causes the LDD region 13 to penetrate into a portion of the 3D active region beneath the gate structure, such as... Figure 1 As shown. Therefore, the effective channel between LDD regions 13 is inevitably shortened.

[0003] On the other hand, advancements in process technology continue to progress rapidly by shrinking the geometry of devices in both horizontal and vertical dimensions (e.g., reducing the minimum feature size, known as Lambda(λ), from 28 nm to 5 nm or 3 nm). However, this reduction in the geometry of FinFETs introduces or exacerbates numerous problems:

[0004] (1) Reducing the gate / channel length will exacerbate the short channel effect (SCE). That is, when the n+ source region in the NMOS gets closer and closer to the n+ drain region, the leakage current associated with the transistor channel will increase even when the transistor is in turn-off mode (called sub-threshold leakage current).

[0005] (2) Due to the additional damage caused by lattice defects resulting from ion implantation (such as holes and vacant traps of electrons), leakage current is generated in the peripheral and bottom regions, which are more difficult to repair. All junction formation processes are becoming increasingly difficult to control. For example, junction formation processes are used to form LDD structures in substrates / well regions and n+ source / drain structures in p-type substrates.

[0006] (3) Furthermore, since the ion implantation process for forming LDD structures (or n+ / p junctions in NMOS or p+ / n junctions in PMOS) is similar to bombardment, so that ions are inserted directly down to the substrate from the top of the silicon surface, and because the dopant concentration distribution is uneven, it is difficult to create a uniform material interface with low defects from the source and drain regions to the channel and substrate-body regions by descending vertically from the top surface with higher dopant concentration to the junction with lower dopant concentration.

[0007] (4) As device size shrinks, aligning the LDD junction edge with the gate structure edge using only conventional self-alignment methods formed by the gate, spacer, and ion implantation becomes increasingly difficult. Furthermore, the thermal annealing process for removing ion implantation damage must rely on high-temperature processing techniques, such as rapid thermal annealing using various energy sources or other thermal processes. One problem arising from this is that gate-induced drain leakage (GIDL) is difficult to control, regardless of whether it should be minimized to reduce leakage current; another problem is the difficulty in controlling the effective channel length, thus making it difficult to minimize SCE. Summary of the Invention

[0008] This invention provides a novel metal-oxide-semiconductor field-effect transistor (MOSFET) structure (e.g., a FinFET), which can be implemented as an inverter, NAND gate, NOR gate, SRAM, cross-coupled amplifier, and various circuit configurations. The novel MOSFET or FinFET structure significantly improves upon or even solves at least one of the aforementioned problems, particularly minimizing leakage current, improving channel conduction efficiency and control, optimizing the function of the source and drain regions, and achieving near-physical integrity for channel regions with seamless crystalline lattice matchup. In particular, the novel transistor or FinFET structure precisely defines the boundary edge between the source / drain regions to the edge of the effective channel region.

[0009] According to one aspect of the present invention, the MOSFET structure includes a semiconductor wafer substrate having a semiconductor surface, a gate structure above the semiconductor surface, a channel region below the semiconductor surface, and a first conductive region electrically coupled to the channel region. Specifically, the first conductive region includes a lightly doped drain region independent of the semiconductor wafer substrate.

[0010] According to one aspect of the invention, the lightly doped drain region is adjacent to the channel region.

[0011] According to another aspect of the invention, the boundary position between the lightly doped drain region and the channel region is controllable.

[0012] According to another aspect of the invention, the boundary between the lightly doped drain region and the channel region is aligned or substantially aligned with the edge of the gate structure.

[0013] According to another object of the present invention, a metal-oxide-semiconductor field-effect transistor structure includes a first trench formed below the semiconductor surface, wherein the first trench accommodates a lightly doped drain region.

[0014] According to another aspect of the invention, the lightly doped drain region is an L-shaped lightly doped drain, which includes a side lightly doped drain region covering the sidewall of the first trench and a bottom lightly doped drain region covering the bottom wall of the first trench.

[0015] According to another aspect of the invention, the side-lightly doped drain region is adjacent to the channel region, and the first conductive region further includes a heavily doped semiconductor region adjacent to the side-lightly doped drain region and the bottom lightly doped drain region.

[0016] According to another aspect of the invention, the heavily doped semiconductor region is shielded on the semiconductor wafer substrate.

[0017] According to another aspect of the invention, the sidewalls of the first trench are aligned or substantially aligned with the edge of the gate structure.

[0018] According to another aspect of the invention, the channel region has a fin structure, and the vertical depth of the channel region is substantially the same as the vertical depth of the side lightly doped drain region.

[0019] According to another aspect of the present invention, the L-shaped lightly doped drain is formed by selective epitaxial growth or atomic layer deposition, the channel region is a fin structure, and the side lightly doped drain region is in contact with the first facet of the fin structure.

[0020] According to another aspect of the invention, the L-shaped lightly doped drain is formed without ion implantation, the channel region is a fin structure, and the side lightly doped drain region is in contact with the first facet of the fin structure.

[0021] These and other objects of the invention will undoubtedly become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments illustrated in the various accompanying drawings. Attached Figure Description

[0022] Figure 1 A schematic diagram of a traditional finned transistor is shown.

[0023] Figure 2A The diagram shows a cross-sectional view of a partial NMOS fin transistor structure, illustrating the stage after several processing steps to achieve a substrate with a body region, a shallow trench isolation (STI) region, and a gate structure.

[0024] Figure 2B The drawing has coverage Figure 2A A cross-sectional view of a portion of the NMOS fin transistor structure with thermal oxide layers on the sidewalls and bottom wall of the temporary trench.

[0025] Figure 2C Drawn in Figure 2B A cross-sectional view of the NMOS fin transistor structure after the thermal oxide layer is etched away to expose the final trench.

[0026] Figure 2D The diagram illustrates the formation of LDD regions to cover the area using selective epitaxial growth (SEG) technology. Figure 2C A cross-sectional view of the sidewalls and bottom wall of the final trench of the NMOS fin transistor structure.

[0027] Figure 3 A cross-sectional view of an NMOS fin transistor structure according to the present invention is shown.

[0028] Figure 4 Drawing based on Figure 3 A schematic diagram of some doping concentration profiles of different drain regions marked with dicing lines. Detailed Implementation

[0029] The key properties of the present invention are illustrated by using an NMOS transistor or FINFET fabricated in a p-type substrate (or p-type well) as an example. Of course, the present invention can also be implemented in a PMOS transistor or FINFET. Figure 2A A cross-sectional view of a portion of the NMOS fin transistor structure is shown after several processing steps, representing a stage where a substrate 40 with an NMOS FINFET body region (or 3D active region), an STI (shallow trench isolation) region 50, and a gate structure 20 is presented. Figure 2A As shown, a gate structure 20, including a gate dielectric layer 21, a gate conductive layer 22 (e.g., a gate metal), and a gate capping layer 23, is formed on the horizontal or pristine surface (or the top of the 3D active region) of a semiconductor substrate. A spacer 30, including an oxide layer and a nitride layer (not shown), is formed to cover the sidewalls of the gate structure 20. Temporary source trenches and temporary drain trenches are formed in the body region (or 3D active region) of the substrate 40 and below the horizontal silicon surface (HSS) based on the edges of the spacer 30. In one embodiment, the edges of the source (or drain) temporary trenches are aligned or substantially aligned with the edges of the spacer 30, such as... Figure 2A As shown. The temporary source trench (or temporary drain trench) has sidewalls with a crystalline orientation (110) facing the transistor body region of the substrate and a bottom wall with a crystalline orientation (100).

[0030] like Figure 2B As shown, based on a thermal oxidation process, an oxide-V layer is formed through the vertical sidewalls (with a sharp lattice orientation (110)) of the transistor body region, and an oxide-B layer is formed on top of the bottom walls of the temporary source and drain trenches. The diagram is shown in... Figure 2BThe thicknesses of the oxide-V and oxide-B layers are shown for illustrative purposes only, and their geometry is not proportional to the dimensions of the STI 50 shown in these figures. For example, the thicknesses of the oxide-V and oxide-B layers are approximately 2–5 nm, but the vertical height of the STI layer can be approximately 200–300 nm. However, it is important to design a thermal oxidation process that allows for very precise control of the oxide-V thickness at precisely controlled thermal oxidation temperatures, times, and growth rates. Since thermal oxidation on a well-defined silicon surface should result in 40% of the oxide-V thickness being removed from the thickness of the silicon surface exposed in the vertical walls of the transistor body region at the lattice orientation (110), the remaining 60% of the oxide-V thickness is considered as an addition outside the vertical walls of the transistor body, such as… Figure 2B As shown. Because the thickness of oxide-V is controlled very precisely based on the thermal oxidation process, the edges of oxide-V can be controlled, for example, the edges of oxide-V can be aligned with or substantially aligned with the edges of the gate structure.

[0031] The oxide-V layer and oxide-B layer can then be etched away to form the final source trench and final drain trench. Since the edges of the oxide-V layer are well-controlled and aligned (or substantially aligned) with the edges of the gate structure, the edges of the final source trench (or final drain trench) will also be controllable and aligned (or substantially aligned) with the edges of the gate structure, such as... Figure 2C As shown. Of course, the vertical thickness of the final source trench (or final drain trench) is also controllable. Similarly, the final source trench (or final drain trench) has sidewalls in the lattice direction (110) of the transistor body region facing the substrate, and a bottom wall in the lattice direction (100).

[0032] Subsequently, a lightly doped drain (LDD) layer is formed to cover the sidewalls and bottomwalls of the final source trench (or final drain trench), such as... Figure 2D As shown. Specifically, the lightly doped drain (LDD) can be an L-type LDD. The lightly doped drain (LDD) includes a side LDD adjacent to the body region or silicon surface of the vertically exposed transistor in a uniform lattice direction (110), and a bottom LDD adjacent to the body region or silicon surface of the horizontally exposed transistor in a uniform lattice direction (100). In one embodiment, the thickness of the L-type LDD or the side LDD is adjustable, and the sidewalls of the side LDD can be aligned with the sidewalls of the spacer 30, such as... Figure 2D As shown. Furthermore, in another embodiment, the vertical boundary of the vertically exposed silicon surface has a suitable recess thickness opposite to the edge of the gate structure. The vertically exposed silicon surface is substantially aligned with the gate structure.

[0033] Furthermore, the side LDD and bottom LDD can be formed based on selective epitaxial growth (SEG) technology to grow silicon from a vertically exposed silicon surface with an ordered lattice orientation (110) and a horizontally exposed silicon surface with an ordered lattice orientation (110), respectively. The oxide-V layer and oxide-B layer are not very thick (e.g., 2–5 nm), so it can be said that most of the side LDD is grown from the vertically exposed silicon surface with a lattice orientation (110) crystal structure, and most of the bottom LDD is grown from the bottom exposed silicon surface with a lattice orientation (100) crystal structure.

[0034] exist Figure 3 In the middle, a heavily N+ doped region is then formed based on the side LDD and bottom LDD using SEG technology. That is, the heavily N+ doped region is completely shielded from the P-type well or silicon substrate by the side LDD and bottom LDD. Alternatively, it can be said that... Figure 3 As shown, the heavily doped N+ region is surrounded by the side LDD, the bottom LDD, and the STI, and shielded by an N-type well or a silicon substrate. In this embodiment, the source region (or drain region) is a composite region containing the heavily doped N+ region, the side LDD, and the bottom LDD.

[0035] It should be mentioned that no ion implantation process, which can only be formed from the top silicon down to the source / drain regions, is performed here, nor is a thermal annealing process, which makes it difficult to define and control the junction boundary, performed. In conventional transistor structures, the LDD region is formed by implanting ions into the semiconductor substrate, and this LDD region formed by the ion implantation process is still part of the silicon substrate. However, it should be noted that the side LDD and bottom LDD of this invention are independent of the silicon substrate and are not part of the silicon substrate. This invention can more precisely define the boundary edge of the source / drain to the edge of the effective channel region, and this boundary can be well aligned with the edge of the gate structure to minimize SCE, GIDL, and junction leakage current. Furthermore, since the side LDD covers most of the sidewalls of the final source trench (or final drain trench) and seamlessly adheres to the vertically exposed silicon surface of the FinFET, the effective vertical depth of the channel region of the FinFET can be considered to be substantially the same as the vertical depth of the sidewalls of the final source or drain trench.

[0036] The source, lightly doped drain (LDD), and heavily N+ doped regions can be formed based on other suitable techniques, such as atomic layer deposition (ALD) or selective growth of ALD-SALD, to grow silicon from the exposed bulk region of the transistor or from a silicon surface used as a seed to form a new well-organized lattice.

[0037] This case achieves several new results: (1) A well-defined crystalline silicon structure between the effective channel length and the newly formed lattice orientation (110) LDD region results in a tight, seamless full coverage of the fin structure, which is perfectly integrated with the interface of the fin structure with the newly laterally grown lattice orientation (110) source / drain region; In addition, in the so-called fin structure or tri-gate structure, the effective channel conduction region surrounded by the gate dielectric is tightly connected through the LDD region of the composite source / drain region, just like a horizontal conduction extension, which can precisely control the size of the transistor width / depth (as with the tri-gate shape), making the on-current flow more uniform than that of a conventional tri-gate transistor; (2) The formed LDD region and heavily doped region can be grown in situ with phosphorus / arsenic atoms of NMOS or boron atoms of PMOS. Using this in-situ doped silicon growth technique, the source / drain can be designed into an LDD structure with controllable lateral spacing, and then converted into a heavily doped region of the composite source / drain region; (3) Since ion implantation is not required to form the LDD, thermal annealing is not required to reduce defects. Once defects are generated, they are difficult to completely eliminate even through annealing. Therefore, when no additional defects are generated, any unpredictable leakage current sources should be significantly reduced. Therefore, it is expected that this laterally grown LDD region with a precisely controllable SEG lattice orientation (110) should produce a better high-quality / high-efficiency energy / drain to channel conduction mechanism. Subcritical leakage current should be reduced. Because the conduction mechanism from the channel through the LDD to the heavily doped region of the composite source / drain region can be designed as a whole (even including some stress-channel-mobility-enhancement techniques by inserting foreign atoms / ions to uniformly enter the source / drain region), it can have a synergistic effect that enhances the conduction efficiency, and the channel conduction efficiency should be enhanced; (4) Another great advantage is that, since the vertical boundary between the gate-edge and the lattice direction (110) LDD region formed by lateral growth can be well defined based on the controllability of thermal oxidation, the GIDL effect should be reduced compared with the traditional method of using LDD implantation as the alignment of the gate edge and the LDD.

[0038] In summary, since the LDD regions formed by the lateral growth of the source / drain regions grow directly outward from the crystal planes of the transistor channel and body regions, their interfaces are seamlessly formed with the same lattice orientation (110), allowing the device width / depth of the top horizontal edge and two vertical edges of the fin structure to be precisely controlled to maximize uniformity. Furthermore, except for the bottom LDD, the planes of the side LDD regions are grown horizontally outward from both the transistor channel and body during SEG using in-situ doping technology, eliminating the need for ion implantation processes (which can only be formed downward from the top silicon in the source / drain regions) and thermal annealing processes (which would make the junction boundary difficult to define and control). This invention can more precisely define the boundary edge of the source / drain to the edge of the effective channel region, and this boundary can be well aligned with the gate edge to minimize SCE, GIDL, and junction leakage current.

[0039] Furthermore, in this invention, the horizontal SEG formation from LDD to the heavily doped region even includes various non-silicon dopants, such as germanium or carbon atoms, to increase stress and enhance channel mobility. In the SEG / ALD formation of the source / drain region according to this invention, the doping concentration profile is controllable or adjustable. Figure 4 Displayed based on Figure 3 The diagram shows the doping concentration profiles of different drain regions marked with cut lines, where the X-axis represents the distance measured from the edge of the MOSFET's gate structure (or a predetermined edge close to the gate structure edge), and the Y-axis represents the doping concentration. In conventional MOSFET structures, due to the formation of n-LDD regions through ion implantation, the n-LDD regions horizontally penetrate into certain regions beneath the gate structure. Figure 4 (The dashed line in the diagram), and the penetration portion of the n-LDD region inevitably shortens the effective channel length. On the other hand, according to the present invention, since the n-LDD region is formed directly from the vertical surface of the transistor body through SEG or ALD processes, the n-LDD region will not penetrate below the gate structure (the dashed line in the diagram). Figure 4 (The dashed and solid lines in the diagram) do not correspondingly shorten the effective channel length. Furthermore, the doping concentration profile gradually increases from the edge of the gate structure to the drain region, for example, from 10 in the n-LDD region. 19 Increase to 10 in the heavily doped region 20 ( Figure 4 (The gradually changing solid line in the middle), or from 10 in the n-LDD region 19 A sudden change to 10 in the heavily doped region 20 ( Figure 4 (The dashed line changes abruptly in the middle). Similarly, the same applies to PMOS.

[0040] Those skilled in the art will readily observe that many modifications and alterations can be made to the apparatus and method while retaining the teachings of the invention. Therefore, the foregoing disclosure should be construed as being limited only by the definition of the appended claims.

Claims

1. A metal-oxide-semiconductor field-effect transistor structure, characterized in that, The metal-oxide-semiconductor field-effect transistor structure includes: A semiconductor wafer substrate having a semiconductor surface; A gate structure is located above the surface of the semiconductor; A channel region is located below the surface of the semiconductor; A first conductive region, surrounded by a shallow trench isolation region, and electrically coupled to the channel region; and A first trench is formed below the semiconductor surface, extending from one edge of the channel region to one edge of the shallow trench isolation region, the edge of the channel region and the edge of the shallow trench isolation region being opposite to each other, the first trench including a first edge and a second edge, the first edge being aligned with the edge of the channel region, the second edge being aligned with the edge of the shallow trench isolation region relative to the first edge, the first edge being aligned with or substantially aligned with the edge of the gate structure, the semiconductor surface being flush with the top of the first trench, the horizontal bottom wall of the first trench being lower than the upper surface of the shallow trench isolation region, the first edge of the first trench having a first lattice direction (110), and the horizontal bottom wall of the first trench having a second lattice direction (100); The first conductive region includes a lightly doped drain region and a heavily doped semiconductor region. The lightly doped drain region and the heavily doped semiconductor region have the same conductivity type. The lightly doped drain region extends laterally from the first lattice direction (110) of the first edge of the first trench and extends upward from the second lattice direction (100) of the horizontal bottom wall. The heavily doped semiconductor region extends laterally from the lightly doped drain region at least. The lightly doped drain region is formed by selective epitaxial growth.

2. The metal-oxide-semiconductor field-effect transistor structure as described in claim 1, characterized in that, The lightly doped drain region is adjacent to the channel region.

3. The metal-oxide-semiconductor field-effect transistor structure as described in claim 1, characterized in that, The lightly doped drain region is an L-shaped lightly doped drain, which includes a side lightly doped drain region covering one side wall of the first trench and a bottom lightly doped drain region covering the bottom wall of the first trench.

4. The metal-oxide-semiconductor field-effect transistor structure as described in claim 3, characterized in that, The side-lightly doped drain region is adjacent to the channel region, and the heavily doped semiconductor region is adjacent to the side-lightly doped drain region and the bottom lightly doped drain region.

5. The metal-oxide-semiconductor field-effect transistor structure as described in claim 4, characterized in that, The heavily doped semiconductor region is shielded by the semiconductor wafer substrate.

6. The metal-oxide-semiconductor field-effect transistor structure as described in claim 3, characterized in that, The channel region has a fin-like structure, and the vertical depth of the channel region is substantially the same as the vertical depth of the side lightly doped drain region.

7. The metal-oxide-semiconductor field-effect transistor structure as described in claim 3, characterized in that, The channel region is a fin structure, and the lightly doped drain region on the side is in contact with the first facet of the fin structure.

8. The metal-oxide-semiconductor field-effect transistor structure as described in claim 3, characterized in that, The L-shaped lightly doped drain is formed without ion implantation, the channel region is a fin structure, and the side lightly doped drain region is in contact with the first facet of the fin structure.

Images