Multi-gate transistors, devices having multi-gate transistors, and methods for forming multi-gate transistors

Abstract

Multi-gate transistors, devices containing such multi-gate transistors, and methods of forming such multi-gate transistors can facilitate voltage in gated integrated circuit devices. Such multi-gate transistors may include an active region having a first conductivity type; a first source / drain region located within the active region and having a second conductivity type different from the first conductivity type; a second source / drain region located within the active region and having the second conductivity type; and a plurality of control gates adjacent to the active region between the first and second source / drain regions, wherein each of the plurality of control gates includes a corresponding plurality of control gate portions, and wherein for a particular control gate among the plurality of control gates, each of its corresponding plurality of control gate portions is adjacent to the active region in a corresponding plane among a plurality of different planes.

Description

Technical Field

[0001] This disclosure generally relates to integrated circuits, and specifically, in one or more embodiments, to multi-gate transistors, devices including multi-gate transistors, and methods of forming multi-gate transistors. Background Technology

[0002] Memory (e.g., memory devices) is typically provided as internal semiconductor integrated circuit devices in computers or other electronic devices. Many different types of memory exist, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

[0003] Flash memory has become a ubiquitous source of non-volatile memory for a wide range of electronic applications. Flash memory typically uses single-transistor memory cells that allow for high memory density, high reliability, and low power consumption. The data state (e.g., data value) of each memory cell is determined by changes in the threshold voltage (Vt) of the memory cell, through programming (often referred to as writing) via charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase transitions or polarization). Common applications of flash memory and other non-volatile memories include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, game consoles, electrical appliances, vehicles, wireless devices, mobile phones, and removable memory modules, and the applications of non-volatile memory continue to expand.

[0004] NAND flash memory is a common type of flash memory device and is therefore referred to as the logical form by which the basic memory cell configuration is arranged. Typically, an array of memory cells for NAND flash memory is arranged such that the control gates of each memory cell in a row of the array are connected together to form an access line, such as a word line. A column of the array contains a string (often referred to as a NAND string) of memory cells connected in series between a pair of select gates (e.g., a source select transistor and a drain select transistor). Each source select transistor may be connected to a source, and each drain select transistor may be connected to a data line, such as a column bit line. Variations of more than one select gate are known to be used between the memory cell string and the source and / or between the memory cell string and the data line.

[0005] In memory devices, access to memory cells (e.g., programmable memory cells) typically utilizes high voltage levels, exceeding 20V, delivered to the control gates of those memory cells. Gate-leveling of such voltage levels often relies on transistors with high breakdown voltages, such as field-effect transistors (FETs). These transistors typically use a relatively large footprint and often require an overdrive voltage to be applied to their control gates to pass through the full voltage level of the voltage node. Summary of the Invention

[0006] In one aspect, this disclosure provides a multi-gate transistor comprising: an active region having a first conductivity type; a first source / drain region located in the active region and having a second conductivity type different from the first conductivity type; a second source / drain region located in the active region and having the second conductivity type; and a plurality of control gates adjacent to the active region between the first source / drain region and the second source / drain region; wherein each of the plurality of control gates includes a corresponding plurality of control gate portions; and wherein for a particular control gate among the plurality of control gates, each of its corresponding plurality of control gate portions is adjacent to the active region in a corresponding plane among a plurality of different planes.

[0007] In another aspect, this disclosure provides a memory comprising: a memory cell array; a plurality of access lines, wherein each of the plurality of access lines is commonly connected to a control gate of a corresponding plurality of memory cells of the memory cell array; and a driver circuit system comprising a plurality of transistors, wherein each of the plurality of transistors is connected to a corresponding access line of the plurality of access lines; wherein a particular transistor of the plurality of transistors comprises: an active region having a first conductivity type; a first source / drain region located in the active region and having a second conductivity type different from the first conductivity type; a second source / drain region located in the active region and having the second conductivity type; and a plurality of control gates adjacent to the active region between the first source / drain region and the second source / drain region; wherein each of the plurality of control gates comprises a corresponding plurality of control gate portions; wherein for a particular control gate of the plurality of control gates, each of its corresponding plurality of control gate portions is adjacent to the active region in a corresponding plane of a plurality of different planes; and wherein the second source / drain region of the particular transistor is connected to the corresponding access line of the particular transistor.

[0008] In another aspect, this disclosure provides a method for forming a multi-gate transistor, comprising: forming a semiconductor material having a first conductivity type covered by a first dielectric material; patterning the semiconductor material to form an active region; forming a first source / drain region having a second conductivity type different from the first conductivity type in the active region; and forming a second source / drain region having the second conductivity type in the active region; forming a second dielectric material covering the active region and the first dielectric material; forming a first conductive via in the second dielectric material that contacts the first source / drain region; and in the... A second conductive via is formed in the second dielectric material to contact the second source / drain region; a plurality of third conductive vias are formed in the second dielectric material; a conductive material is formed covering the first conductive via, the second conductive via, the plurality of third conductive vias, and the second dielectric material, wherein the conductive material contacts the first conductive via, the second conductive via, and the plurality of third conductive vias; and the second conductive material is patterned to form a plurality of upper control gate portions, a first contact to the first source / drain region, and a second contact to the second source / drain region.

[0009] In another aspect, this disclosure provides a method for forming a multi-gate transistor, comprising: forming a first conductive material covered by a first dielectric material; patterning the first conductive material to form a plurality of lower control gate portions; forming a second dielectric material covering the plurality of lower control gate portions and the first dielectric material; forming a semiconductor material having a first conductivity type covered by the second dielectric material; patterning the semiconductor material to form an active region covering the plurality of lower control gate portions; forming a first source / drain region having a second conductivity type different from the first conductivity type in the active region; and forming a second source / drain region having the second conductivity type in the active region, wherein each lower control gate of the plurality of lower control gate portions... A portion is laterally located between the first source / drain region and the second source / drain region; a third dielectric material is formed covering the active region and the second dielectric material; a first conductive via is formed in the third dielectric material that contacts the first source / drain region; a second conductive via is formed in the third dielectric material that contacts the second source / drain region; a second conductive material is formed covering the first conductive via, the second conductive via, and the third dielectric material, wherein the second conductive material contacts both the first and second conductive vias; and the second conductive material is patterned to form a plurality of upper control gate portions, a first contact to the first source / drain region, and a second contact to the second source / drain region. Attached Figure Description

[0010] Figure 1 A simplified block diagram of a memory that communicates with a processor as part of an electronic system according to an embodiment.

[0011] Figures 2A to 2C For reference purposes Figure 1 A partial schematic diagram of the memory cell array in the described type of memory.

[0012] Figure 3A For reference purposes Figure 1 A schematic diagram of the memory cell array and the string driver portion of a memory device of the described type.

[0013] Figure 3B For reference purposes Figure 1 A partial schematic diagram of an instance of a string driver in a memory of the described type.

[0014] Figure 3C For reference purposes Figure 1 A partial schematic diagram of another instance of a string driver in a memory of the described type.

[0015] Figure 4 This is a plan view of a multi-gate transistor according to an embodiment.

[0016] Figures 5A to 12D According to the embodiments, at various manufacturing stages Figure 4 A cross-sectional view of a transistor.

[0017] Figure 13 According to another embodiment Figure 4 A cross-sectional view of a transistor.

[0018] Figure 14 According to yet another embodiment Figure 4 A cross-sectional view of a transistor.

[0019] Figures 15A to 15E According to various embodiments Figure 4 A cross-sectional view of a transistor.

[0020] Figure 16 A conceptual depiction of the connection of a portion of a string driver connected to access lines of a plurality of memory cell blocks, according to an embodiment, is provided.

[0021] Figure 17 This is a perspective view of a transistor according to an embodiment. Detailed Implementation

[0022] In the following detailed description, reference is made to the accompanying drawings, which form part of this document and illustrate particular embodiments by way of illustration. In the drawings, the same reference numerals pervade several views depicting generally similar components. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be construed as limiting.

[0023] As used herein, the term "semiconductor" may refer to, for example, a material layer, a wafer, or a substrate, and includes any basic semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon layers supported by a substrate semiconductor structure, and other semiconductor structures well known to those skilled in the art. Furthermore, when referring to the semiconductor in the following description, regions / junctions may have been formed in the substrate semiconductor structure using prior processing steps, and the term semiconductor may include an underlying material containing such regions / junctions.

[0024] As used herein, the term "conductive" and its various related forms (e.g., conduct, conductively, conducting, conduction, conductivity, etc.) means conductive unless otherwise apparent from the context. Similarly, as used herein, the term "connecting" and its various related forms (e.g., connect, connected, connection, etc.) means an electrical connection via a conductive path unless otherwise apparent from the context.

[0025] This paper recognizes that even if values ​​are intended to be equal, the variability and accuracy of industrial processing and operation can lead to differences from their expected values. These variability and accuracy will typically depend on the technology used in the manufacture and operation of integrated circuit devices. Therefore, if values ​​are intended to be equal, then those values ​​are considered equal regardless of their resulting values.

[0026] Various embodiments can facilitate high breakdown voltage transistors, such as field-effect transistors (FETs), by using multiple gates along the active region providing the channel region of the transistor. While transistors of various embodiments can be used in all types of integrated circuit devices utilizing transistors, this document will specifically refer to devices containing memory cells, some of which are generally referred to as memory devices or simply memory.

[0027] Figure 1This is a simplified block diagram of a first device (in the form of a memory (e.g., a memory device) 100) that communicates with a second device (in the form of a processor 130) as part of a third device (in the form of an electronic system) according to an embodiment. Examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile phones, and so on. The processor 130, for example, a controller external to the memory device 100, may be a memory controller or other external host device.

[0028] Memory device 100 includes an array 104 of memory cells that can be logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access lines (collectively referred to as word lines), while memory cells in logical columns are typically selectively connected to the same data lines (collectively referred to as bit lines). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1 (Not shown in the text) It can be programmed to one of at least two target data states.

[0029] Row decoding circuitry 108 and column decoding circuitry 110 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 100 also includes input / output (I / O) control circuitry 112 to manage inputs of commands, addresses, and data to memory device 100 and outputs of data and status information from memory device 100. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 110 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and control logic 116 to latch incoming commands.

[0030] A controller (e.g., control logic 116 within memory device 100) controls access to memory cell array 104 in response to a command and may generate status information for external processor 130, i.e., control logic 116 is configured to perform access operations (e.g., sensing operations [which may include read and check operations], programming operations, and / or erase operations) on memory cell array 104. Control logic 116 communicates with row decoding circuitry 108 and column decoding circuitry 110 to control row decoding circuitry 108 and column decoding circuitry 110 in response to an address. Control logic 116 may include an instruction register 128, which may represent computer-available memory for storing computer-readable instructions. In some embodiments, instruction register 128 may represent firmware. Alternatively, instruction register 128 may represent a set of memory cells of memory cell array 104, such as a reserved block of memory cells.

[0031] Control logic 116 may also communicate with cache register 118. Cache register 118, guided by control logic 116, latches incoming or outgoing data to temporarily store data while memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 118 to data register 120 to be transferred to memory cell array 104; then, new data can be latched from I / O control circuitry 112 into cache 118. During read operations, data can be transferred from cache register 118 to I / O control circuitry 112 to be output to external processor 130; then, new data can be transferred from data register 120 to cache register 118. Cache register 118 and / or data register 120 may form a page buffer of memory device 100 (e.g., may form a portion thereof). The page buffer may further include sensing devices ( Figure 1 (Not shown) to sense the data status of the memory cells in the memory cell array 104, for example by sensing the status of the data lines connected to the memory cells. The status register 122 can communicate with the I / O control circuitry system 112, and the control logic 116 latches the status information for output to the processor 130.

[0032] The memory device 100 receives control signals from the processor 130 via control link 132 at control logic 116. These control signals may include chip enable (CE#), command latch enable (CLE), address latch enable (ALE), write enable (WE#), read enable (RE#), and write protection (WP#). Depending on the nature of the memory device 100, additional or alternative control signals (not shown) may be received via control link 132. The memory device 100 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the processor 130 via multiplexed input / output (I / O) bus 134 and outputs data to the processor 130 via I / O bus 134.

[0033] For example, commands can be received at the input / output (I / O) control circuitry 112 via I / O pins [7:0] of the I / O bus 134, and then written to the command register 124. Addresses can be received at the input / output (I / O) control circuitry 112 via I / O pins [7:0] of the I / O bus 134, and then written to the address register 114. Data can be received at the input / output (I / O) control circuitry 112 via I / O pins [7:0] for 8-bit devices or I / O pins [15:0] for 16-bit devices, and then written to the cache register 118. The data can then be written to the data register 120 to program the memory cell array 104. In another embodiment, the cache register 118 can be omitted, and data can be written directly to the data register 120. Data can also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. Although references are made to the I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that provide electrical connections to the memory device 100 via external devices (e.g., processor 130).

[0034] Those skilled in the art will understand that additional circuitry and signals can be provided, and Figure 1 The memory device 100 has been simplified. It should be recognized that it may not be necessary to include a reference... Figure 1 The various block components described are functionally isolated to distinguish components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device can be adapted to perform... Figure 1 The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1 The functionality of a single block component.

[0035] Additionally, while specific I / O pins are described according to common conventions for receiving and outputting various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0036] Figure 2A For reference Figure 1 A schematic diagram of a portion of a memory cell array 200A (such as a "NAND" memory array) that serves as a part of a memory cell array 104 in the described type of memory. The memory array 200A includes access lines (e.g., word lines) 2020 to 202... N and data lines (e.g., bit lines) 2040 to 204 M Word line 202 can be connected in a many-to-one relationship. Figure 2A Global access lines (e.g., global word lines) not shown in the diagram. In some embodiments, the memory array 200A may be formed on a semiconductor, which may be conductively doped to have a conductivity type, such as p-type conductivity, for example to form a p-well, or n-type conductivity, for example to form an n-well.

[0037] The memory array 200A can be arranged in rows (each row corresponds to access line 202) and columns (each column corresponds to data line 204). Each column can contain a series of serially connected memory cells (e.g., non-volatile memory cells), such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be concatenated (e.g., selectively concatenated) to a command source (SRC) 216 and may contain memory cells 2080 to 208. N Source 216 may represent a voltage node of memory cell 208 that is typically selectively connected to multiple NAND strings 206. Memory cell 208 may represent a non-volatile memory cell used for storing data. Memory cells 2080 to 208 N It may include memory cells intended for storing data, and may further include other memory cells not intended for storing data, such as virtual memory cells. Virtual memory cells are typically not accessible to the user of the memory, and are instead typically incorporated into the serially connected memory cells to achieve well-known operational advantages.

[0038] Each NAND string 206 memory cell 208 may be connected in series with the select gate 210 (e.g., a field-effect transistor) (e.g., select gates 2100 to 210). M One of them (e.g., it may be a source-select transistor, commonly referred to as a select-gate source) and select-gate 212 (e.g., a field-effect transistor) (e.g., select-gate 2120 to 212). MBetween one of them (for example, it could be a drain-select transistor, often referred to as the select gate drain). Select gate 2100 to 210 M They can be connected together to select line 214, such as source select line (SGS), and select gates 2120 to 212. M They can be connected together to select line 215, such as drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can use a structure similar to (e.g., the same) as memory cell 208. Select gates 210 and 212 can represent multiple select gates connected in series, wherein each series select gate is configured to receive the same or independent control signal.

[0039] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to the memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to the memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to the select line 214.

[0040] The drain of each select gate 212 can be connected to the data line 204 of the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the data line 2040 of the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding data line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0041] Figure 2A The memory array in the array can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, the NAND string 206, and the data line 204 extend in a generally parallel plane. Alternatively, Figure 2A The memory array in the array can be a three-dimensional memory array, for example, in which the NAND string 206 can extend substantially perpendicular to the plane containing the common source 216 and the plane containing the data line 204, the data line being substantially parallel to the plane containing the common source 216.

[0042] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, or other structure configured to store charge) that determines the data state of the memory cell (e.g., by a change in a threshold voltage); and a control gate 236, as shown in [the original text]. Figure 2A As shown in the diagram. The data storage structure 234 may include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may further have defined source / drain (e.g., source) 230 and defined source / drain (e.g., drain) 232. The memory cell 208 connects its control gate 236 to (and in some cases forms) access line 202.

[0043] Columns of memory cells 208 may be NAND strings 206 or multiple NAND strings 206 selectively connected to a given data line 204. Rows of memory cells 208 may be memory cells 208 commonly connected to a given access line 202. Rows of memory cells 208 may, but need not, contain all memory cells 208 commonly connected to a given access line 202. Rows of memory cells 208 may typically be divided into one or more physical page groups of memory cells 208, and physical pages of memory cells 208 typically contain every other memory cell 208 commonly connected to a given access line 202. For example, typically connected to access line 202 N Furthermore, memory cells 208 selectively connected to even-numbered data lines 204 (e.g., data lines 2040, 2042, 2044, etc.) can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), and memory cells 208 are typically connected to access lines 202. N And selectively connecting to odd-numbered data lines 204 (e.g., data lines 2041, 2043, 2045, etc.) can be another physical page of memory cell 208 (e.g., odd-numbered memory cell). Although in Figure 2A Data lines 2043 to 2045 are not explicitly depicted in the figure, but it is evident from the figure that data lines 204 of the memory cell array 200A can extend from data line 2040 to data line 2045. M Sequential numbering. Other groups of memory cells 208 commonly connected to a given access line 202 may also define physical pages of memory cells 208. For some memory devices, all memory cells commonly connected to a given access line may be considered physical pages of the memory cell. A portion of the physical page of a memory cell (e.g., the upper or lower page of the memory cell) that is read during a single read operation or programmed during a single programmable operation (in some embodiments, it may still be an entire row) may be considered a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to access lines 2020 to 202.N All memory cells (e.g., all NAND strings 206 share a common access line 202). Unless explicitly distinguished, references to memory cell pages herein refer to the memory cells of logical pages of memory cells.

[0044] Despite combining the discussion of NAND flash memory Figure 2A Examples are provided, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS or other data storage structures configured to store charge) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0045] Figure 2B For reference Figure 1 Another schematic diagram of a portion of memory cell array 200B, which serves as a portion of memory cell array 104 in a memory of the type described. Figure 2B Elements with the same number in the middle correspond to, for example, those about Figure 2A The description provided. Figure 2B Additional details are provided for an example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B may incorporate a vertical structure that may include semiconductor pillars, portions of which may serve as channel regions for the memory cells of the NAND strings 206. Each of the NAND strings 206 may be selectively connected to data lines 2040 to 2046 via a select transistor 212 (e.g., a drain select transistor, collectively referred to as select gate drain) M And connected to a common source 216 via a select transistor 210 (e.g., which may be a source select transistor, collectively referred to as the select gate source). Multiple NAND strings 206 can be selectively connected to the same data line 204. This can be achieved by connecting select lines 2150 to 215... K A bias voltage is applied to selectively activate specific selection transistors 212, each located between the NAND string 206 and the data line 204, connecting a subset of the NAND string 206 to its corresponding data line 204. Selection transistors 210 can be activated by biasing selection line 214. Each access line 202 can be connected to multiple rows of memory cells in the memory array 200B. Rows of memory cells interconnected via specific access lines 202 can be collectively referred to as layers.

[0046] A three-dimensional NAND memory array 200B may be formed above a peripheral circuit system 226. The peripheral circuit system 226 may represent various circuit systems for accessing the memory array 200B. The peripheral circuit system 226 may include complementary circuit elements. For example, the peripheral circuit system 226 may include both n-channel and p-channel transistors formed on the same semiconductor substrate, commonly referred to as CMOS or complementary metal-oxide-semiconductor (CMOS) technology. Although CMOS typically no longer uses a strictly metal-oxide-semiconductor structure due to advancements in integrated circuit fabrication and design, the name CMOS remains unchanged for convenience.

[0047] Figure 2C For reference Figure 1 Another schematic diagram of a portion of a memory cell array 200C, which serves as a portion of a memory cell array 104, in a memory of the type described. Figure 2C Elements with the same number in the middle correspond to, for example, those about Figure 2A The provided description indicates that the memory cell array 200C may include a series-connected string of memory cells (e.g., a NAND string) 206, access (e.g., word) lines 202, data (e.g., bit) lines 204, select lines 214 (e.g., source select lines), select lines 215 (e.g., drain select lines), and sources 216, as shown in... Figure 2A As depicted in the diagram. For example, a portion of memory cell array 200A may be a portion of memory cell array 200C. Figure 2C The diagram depicts grouping the NAND string 206 into memory cell blocks 250, such as memory cell blocks 2500 to 250. L Memory cell block 250 may be a group of memory cells 208 that can be erased together in a single erase operation, sometimes referred to as an erase block. Each memory cell block 250 may contain those NAND strings 206 typically associated with a single select line 215 (e.g., select line 2150). The source 216 of memory cell block 2500 may be associated with memory cell block 250. L The source 216 is the same as the source. For example, each memory cell block 2500 to 250 L They can be selectively connected to source 216. Access lines 202 and select lines 214 and 215 of a memory cell block 250 can be connected to memory cell blocks 2500 to 2500 respectively. L Access lines 202 and select lines 214 and 215 of any other memory cell block are not directly connected.

[0048] Data cable 2040 to 204 MIt can be connected (e.g., selectively connected) to buffer portion 240, which may be a portion of the data buffer of the memory. Buffer portion 240 may correspond to a memory plane (e.g., memory cell blocks 2500 to 250). L The buffer portion 240 may include sensing means for sensing data values ​​indicated on the corresponding data lines 204. Figure 2C (Not shown in the image).

[0049] Although Figure 2C Each memory cell block 250 may depict only one select line 215 per memory cell block 250, but the memory cell block 250 may contain those NAND strings 206 that are typically associated with more than one select line 215. For example, the select line 2150 of the memory cell block 2500 may correspond to Figure 2B The selection line 2150 of the memory array 200B, and Figure 2C The memory cell blocks of the memory array 200C can further include... Figure 2B Selection line 2151 to 215 K The associated NAND strings 206. In such a memory cell block 250 having NAND strings 206 associated with multiple select lines 215, those NAND strings 206 typically associated with a single select line 215 may be referred to as memory cell sub-blocks. Each such memory cell sub-block may be selectively connected to buffer portion 240 in response to its respective select line 215.

[0050] Figure 3A For reference purposes Figure 1 A schematic diagram of a portion of the memory cell array and serial driver in a memory device of the described type, depicting a many-to-one relationship between local access lines (e.g., word line 202) and global access lines (e.g., global word line 302).

[0051] As in Figure 3A As depicted, multiple memory blocks 250 may selectively connect their local access lines (e.g., word lines 202) to multiple global access lines (e.g., global word lines 302). Although Figure 3A Only memory blocks 2500 and 250 are depicted. L (Block 0 and Block L), but other memory blocks 250 can have their word lines 202 connected together to the global word line 302 in a similar manner. Similarly, although Figure 3A Only four word lines 202 are depicted, but memory block 250 may contain fewer or more word lines 202.

[0052] To facilitate memory access operations to specific memory blocks 250 typically coupled to a given group of global word lines 302, each memory block 250 may have a corresponding block select transistor 354 in a one-to-one relationship with its word line 202. The control gates of the block select transistors 354 of a given memory block 250 may be co-coupled to the corresponding block select line 356. (See reference...) Figure 4 The discussion focuses on block selection line 356 (e.g., block selection lines 3560 to 356). L Each of these can represent multiple independent conductors, each of which is connected to the corresponding control gate of a multi-gate transistor.

[0053] For memory block 2500, word line 202 00 Transistor 354 can be selected via block. 00 Selectively connect to global word line 3020, word line 202 10 Transistor 354 can be selected via block. 10 Selectively connected to global word line 3021, word line 202 20 Transistor 354 can be selected via block. 20 Selectively connected to global word line 3022, and word line 202 30 Transistor 354 can be selected via block. 30 Selectively connected to global word line 3023, while block select transistor 354 00 Up to 354 30 In response to the control signal received on block select line 3560. For memory block 250 L , character line 202 0L Transistor 354 can be selected via block. 0L Selectively connected to global word line 302 L , character line 202 1L Transistor 354 can be selected via block. 1L Selectively connected to global word line 3021, word line 202 2L Transistor 354 can be selected via block. 2L Selectively connected to global word line 3022, and word line 202 3L Transistor 354 can be selected via block. 3L Selectively connected to global word line 3023, while block select transistor 354 0L Up to 354 3L In response to block selection line 356 L The control signals received are from the upper part. The block selection transistor 354 used for memory cell block 250 can be collectively referred to as a serial driver, or simply a driver circuit system.

[0054] Figure 3B For reference purposes Figure 1A partial schematic diagram of an instance of a string driver in a memory of the described type. Figure 3B The string driver section describes a transistor, for example, block select transistor 354. YX In response to control signal nodes, such as block select line 356 X And connected to the voltage node (e.g., global word line 302) Y (configured to supply voltage level) and load node (e.g., local word line 202) YX (configured to receive the voltage level). For example, block select transistor 354 YX Can represent block select transistor 354 10 The block select transistor has a local word line 202 connected to the block select line 3560 and to the global word line 3021 and the memory cell block 2500. 10 The control gate between. Block select transistor 356 YX This can be a high-voltage junction-gate field-effect transistor or a JFET. (See reference...) Figure 4 The discussion focuses on block selection line 356. X It can represent multiple independent conductors.

[0055] Figure 3C For reference purposes Figure 1 A partial schematic diagram of another instance of a string driver in a memory of the described type. Figure 3C The string driver section depicts two transistors, for example, block select transistor 354. YX and block select transistor 354 Y(X+1) Block select transistor 354 YX In response to control signal nodes, such as block select line 356 X And connected to the voltage node (e.g., global word line 302) Y (configured to supply voltage level) and load node (e.g., local word line 202) YX (configured to receive the voltage level). For example, block select transistor 354 YX Can represent block select transistor 354 10 The block select transistor has a local word line 202 connected to the block select line 3560 and to the global word line 3021 and the memory cell block 2500. 10 The control gate between them.

[0056] Block select transistor 354 Y(X+1) In response to control signal nodes, such as block select line 356 X+1 And connected to the voltage node (e.g., global word line 302) Y(configured to supply voltage level) and load node (e.g., local word line 202) Y(X+1) (configured to receive the voltage level). For example, block select transistor 354 Y(X+1) Can represent block select transistor 354 1L The block select transistor has a connection to the block select line 356. L And connected to global word line 3021 and memory cell block 250 L 202 partial character lines 1L The control gate between. Block select transistor 356 YX and 356 Y(X+1) Each can be a high-voltage JFET. See reference... Figure 4 The discussion focuses on block selection line 356. X and 356 X+1 Each can represent multiple independent conductors.

[0057] Figure 4 This is a plan view of transistors 4540 and 4541 according to an embodiment. Figure 4 Transistors can be made from, for example Figure 3C The diagram depicted in the image is used to represent this. Figure 4 In this transistor, transistors 454 (e.g., transistors 4540 and 4541) each include an active region 460 of semiconductor (e.g., active regions 4600 and 4601, respectively). Each transistor may be formed at a corresponding first contact 4660 or 4661 (e.g., for connection to a corresponding voltage node, such as a global access line) and a corresponding second contact 4680 or 4681 (e.g., for connection to a corresponding load node, such as a local access line). Such transistors are responsive to conductors 464 (e.g., conductors 4640 to 464). G The conductor 464 receives a control signal and may be connected to (and form) at least a portion of the control gate of one or more transistors. The conductors 464 may be independent of each other. For example, each conductor 464 may be configured to receive a control signal, such as an applied voltage level, independent of the control signal of each remaining conductor 464. Commonly, conductors 4640 to 464... G Block select line 356 can be represented. Active regions 4600 and 4601 can extend to a second pair of adjacent transistors sharing first contacts 4660 and 4661. Figure 4 (not fully depicted in the text), for example, by conductor 464 corresponding to the second pair of adjacent transistors. 0′ As shown by the dashed lines, the second pair of adjacent transistors is a mirror image of transistors 4540 and 4541.

[0058] Figures 5A to 12D For various stages of production according to the embodiments Figure 4A cross-sectional view of a transistor. Figure 5A , 6A 7A, 8A, 9A, 10A, 11A and 12A are along Figure 4 The cross section cut by line AA in the diagram. Figure 5B , 6B 7B, 8B, 9B, 10B, 11B, and 12B are along... Figure 4 The cross-section cut by line BB in the middle. Figure 5C , 6C 7C, 8C, 9C, 10C, 11C, and 12C are along... Figure 4 The cross section cut by line CC in the diagram. Figure 5D , 6D 7D, 8D, 9D, 10D, 11D, and 12D are along... Figure 4 The cross section cut by line DD in the diagram.

[0059] Although Figure 5A , 6A The cross-sections of transistors 7A, 8A, 9A, 10A, 11A, and 12A depict portions of transistor 4540 from one side, but these figures can be further applied to the corresponding cross-sections on the other side of transistor 4540, or either side of transistor 4541, since the two transistors can have similar, for example, identical structures, and can be symmetrical on either side of their active region 460. Although Figure 5B , 6B The cross-sections of 7B, 8B, 9B, 10B, 11B, and 12B depict portions of transistor 4540, but these figures can be further applied to the corresponding cross-sections of transistor 4541, since the two transistors can have similar, for example, identical structures. Although Figure 5C , 6C The cross-sections at 7C, 8C, 9C, 10C, 11C, and 12C depict portions of transistors 4540 and 4541 containing conductor 4640, but these figures are further applicable to portions containing residual conductors 4641 to 464. G The corresponding cross-sections of either transistor 4540 or 4541, because such portions of the two transistors can have similar (e.g., identical) structures. Although Figure 5D , 6D Cross sections 7D, 8D, 9D, 10D, 11D, and 12D depict portions of transistors 4540 and 4541 containing first contacts 4660 and 4661, respectively. However, these figures can be further applied to corresponding cross sections of transistors 4540 and 4541 containing second contacts 4680 and 4681, respectively, since such portions of the two transistors may have similar (e.g., identical) structures.

[0060] exist Figures 5A to 5DIn this process, dielectric 572 may be formed as an overlay on substrate 570 (e.g., on it). Substrate 570 may include silicon, such as monocrystalline silicon, or other semiconductor materials. Semiconductor 570 may have a conductivity type, such as p-type conductivity. For some embodiments where its transistors will be formed as part of the peripheral circuit system, substrate 570 may be located on... Figure 2B Below the peripheral circuit system 226. Alternatively, for some embodiments where the transistors will be formed on the memory array, the substrate 570 may contain... Figure 2B The memory array is 200B.

[0061] The dielectric 572 may be formed of one or more dielectric materials. For example, the dielectric 572 may include oxides (e.g., silicon dioxide), constitute or substantially constitute thereof, and / or may include high-k dielectric materials, constitute or substantially constitute thereof, such as aluminum oxide (Al₂O₃). x ), hafnium oxide (HfO) x ), Hafnium aluminum oxide (HfAlO) x ), Hafnium silicate oxide (HfSiO) x ), Lanthanum oxide (LaO) x ), tantalum oxide (TaO) x Zirconium oxide (ZrO) x ), zirconium aluminum oxide (ZrAlO) x ) or yttrium oxide (Y2O3) and any other dielectric material.

[0062] Conductor 574 may be formed as an overlying dielectric 572 (e.g., on said dielectric). Conductor 574 may be formed of one or more conductive materials. Conductor 574 may include conductive doped polycrystalline silicon, be composed of or substantially composed of it, and / or may include metals (e.g., refractory metals) or metal-containing materials (e.g., refractory metal silicides or metal nitrides, such as refractory metal nitrides) and any other conductive materials, be composed of or substantially composed of it. As an example, conductor 574 may contain tungsten or aluminum. In one embodiment where transistors are formed below the memory array, conductor 574 may contain tungsten. In another embodiment where transistors are formed above the memory array, conductor 574 may contain aluminum. Generally, conductive materials (e.g., metals) with a lower formation thermal budget are preferred when a memory cell array has been formed therein. Such conductive materials may have a lower formation thermal budget compared to conductive materials (e.g., metals) formed below the memory cell array.

[0063] exist Figures 6A to 6DIn this configuration, conductor 574 may be patterned to define a first portion of each control gate of the future transistor. For example, conductor 574 may be patterned to define the lower control gate portions 4620 to 462 of the future transistor. G The first control gate portion is defined as the control gate. Future transistors may contain G+1 lower control gate portions. The variable G may represent an integer value greater than or equal to 1. In some embodiments, the variable G may represent an integer greater than or equal to 5. The value of the variable G may be determined in response to the breakdown characteristics of the control gate corresponding to the finished transistor. For example, if the breakdown voltage between adjacent control gates is X volts and the expected maximum Vds is Y volts, then the variable G may be chosen as an integer value equal to or greater than Y / X.

[0064] Patterning conductor 574 may include forming a patterned mask (not depicted) that is formed to overlay (e.g., on) conductor 574 to expose areas of conductor 574 for removal. The mask may represent a mask formed using an optical lithography process. Optical lithography is commonly used in integrated circuit manufacturing to define desired patterns. In an optical lithography process, a photoresist layer may be formed on the surface of a device in the process. The photoresist layer may contain a photosensitive polymer whose removability changes upon exposure to light or other electromagnetic radiation. To define the pattern, the photoresist layer may be selectively exposed to radiation and then developed to expose portions of the underlying layer. In a positive resist system, portions of the photoresist layer exposed to radiation are dissolved by light, and the optical lithography mask is designed to block radiation from those portions of the photoresist layer that remain after development. In a negative resist system, portions of the photoresist layer exposed to radiation are photopolymerized, and the optical lithography mask is designed to block radiation from those portions of the photoresist layer that will be removed by development.

[0065] The exposed area of ​​conductor 574 can be removed, for example, anisotropically, to define the lower control gate portions 4620 to 462. G For example, reactive ion etching can be used to remove portions of conductor 574 that are not covered by the patterned mask. The mask can then be removed, for example, by ashing or otherwise removing the photoresist material.

[0066] exist Figures 7A to 7D In this process, for example, by forming additional dielectric material, the dielectric 572 can be extended, the dielectric material covering the lower control gate portions 4620 to 462. G (For example, on it) and overlaid Figures 6A to 6D The dielectric 572 (e.g., on it). As in Figures 7A to 7DAs depicted, a semiconductor material 576 can then be formed, on which a dielectric 572 is coated (e.g., thereon). The semiconductor material 576 may include silicon (e.g., monocrystalline silicon, amorphous silicon, or polycrystalline silicon) or other semiconductor materials (e.g., silicon-germanium (SiGe)). Other semiconductor materials may include indium zinc oxide (commonly referred to as InZnO or InZO), zinc oxide (ZnO), indium gallium zinc oxide (commonly referred to as InGaZnO or IGZO), molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten disulfide (WS2), tungsten diselenide (WSe2), graphene, carbon nanotubes, etc. The semiconductor material 576 may have a first conductivity type, such as p-type conductivity. Conductive doping may be performed on the semiconductor material 576 during or after formation. To produce p-type conductivity, the dopant material may contain boron (B) ions or another p-type impurity. For example, semiconductor material 576 can be conductively doped during formation by adding diborane (B2H6) to the reaction gas of the CVD process that forms semiconductor material 576, so as to mix sufficient boron into semiconductor material 576 to achieve the desired threshold voltage of future transistors. For example, undoped to 2E18 / cm 3 The dopant concentration. As an alternative example, the semiconductor material 576 can be conductively doped after formation by implanting one or more dopant materials into the semiconductor material 576. As is well known in the art, such implantation typically involves accelerating the direction of ions toward the surface of the semiconductor material 576. To produce n-type conductivity, the dopant material may contain ions of arsenic (As), antimony (Sb), phosphorus (P), or other n-type impurities.

[0067] exist Figures 8A to 8D In this process, the conductive doped semiconductor material 576 can be patterned to define active regions 4600 and 4601. The patterning of the conductive doped semiconductor material 576 can be similar to that of the reference [reference material]. Figures 6A to 6D The method described herein shall be implemented in such a manner. A first source / drain region 578 (e.g., a source region) and a second source / drain region 580 (e.g., a drain region) may be formed in each of the active regions 4600 and 4601 and may have a second conductivity type, which differs from the first conductivity type. For example, if the first conductivity type is p-type conductivity, the second conductivity type may be n-type conductivity.

[0068] The source / drain regions 578 and 580 may include conductive doped portions of the active regions 4600 and 4601. For example, the first source / drain region 578 and the second source / drain region 580 can be formed by implanting one or more dopants into the active region 460. To generate n-type conductivity, the dopants may include ions of arsenic (As), antimony (Sb), phosphorus (P), or another n-type impurity. The doping level of the first source / drain region 578 and the second source / drain region 580 may be higher than the doping level of their active region 460. As an example, the doping level of the first source / drain region 578 and the second source / drain region 580 may be 2E18-1E21 / cm². 3 Although the first source / drain region 578 and the second source / drain region 580 are depicted as extending into the active regions 4600 and 4601, they are smaller than their thickness, for example, as measured from the top surface to the bottom surface of the active region 460. Figure 8B and 8D As shown, in some embodiments, the first source / drain region 578 and the second source / drain region 580 may extend over the entire thickness of the active regions 4600 and 4601.

[0069] exist Figures 9A to 9D In the middle, dielectric 582 can be formed as an overlay Figures 8A to 8D The structure (e.g., thereon). Dielectric 582 may be formed of one or more dielectric materials, such as those discussed with reference to dielectric 572.

[0070] exist Figures 10A to 10D In this process, a conductive via 463 can be formed in dielectric 582 to connect with the lower control gate portions 4620 to 462. G Contact. One or more conductive vias 463 may contact each lower control gate portion 462. Conductive vias 586 may be further formed in the dielectric 582 simultaneously with conductive vias 463 to contact the first source / drain region 578 and the second source / drain region 580. For example, openings may be formed in the dielectric 582 to individually expose the first source / drain region 578, the second source / drain region 580, or the lower control gate portions 4620 to 462. G The portion of the via 463 and 586 may then be filled or lined with a conductive material. In one embodiment, conductive vias 463 and 586 may each contain conductive-doped polysilicon, such as n-type conductive-doped polysilicon, but other conductive materials may or may be used alternatively. As an example, the doping level of conductive vias 463 and 586 may be 2E18-1E21 / cm². 3 The conductive via 463 can form the second and third control gate portions of the control gate of a future transistor, such as the side control gate portion, and may be referred to as such.

[0071] exist Figures 11A to 11D In this embodiment, conductor 588 may be formed as an overlying dielectric 582 (e.g., on which). Conductor 588 may be formed of one or more conductive materials. Conductor 588 may comprise, consist of, or be substantially composed of conductive doped polycrystalline silicon, and / or may comprise metals (e.g., refractory metals) or metal-containing materials (e.g., refractory metal silicides or metal nitrides, such as refractory metal nitrides) and any other conductive materials, comprised of, or substantially composed of. As an example, conductor 588 may contain tungsten or aluminum. In one embodiment in which transistors are formed below the memory array, conductor 588 may comprise tungsten. In another embodiment in which transistors are formed above the memory array, conductor 588 may comprise aluminum. Generally, in cases where a memory cell array has been formed, conductive materials (e.g., metals) with a lower formation thermal budget are preferred. Such conductive materials may have a lower formation thermal budget compared to conductive materials (e.g., metals) formed below the memory cell array.

[0072] exist Figures 12A to 12D In this configuration, conductor 588 can be patterned to define a fourth portion of each control gate of the transistor. For example, conductor 588 can be patterned to define conductors or upper control gate portions, 4640 to 464 of the transistor. G And the first contacts 4660 to 4661 and the second contacts 4680 to 4681. The patterning of conductor 588 can be performed, for example, in a manner described with reference to the patterning of conductor 574.

[0073] Figures 12A to 12D The transistors are depicted, each having multiple independent control gates surrounding an active region 460 (e.g., a lower surface, a side surface, and a top surface). Commonly, a lower control gate portion 462 adjacent to the active region 460, a corresponding side control gate portion 463 adjacent to the active region 460, and a corresponding upper control gate portion 464 adjacent to the active region define a transistor 454 containing the active region 460 (e.g., Figure 12A Control gate 465 00 up to 465 G0 A control gate 465 is provided. As an example, a lower control gate portion 4620 adjacent to the bottom surface of the active region 4600, a side control gate portion 463 adjacent to the left and right surfaces of the active region 4600, and an upper control gate portion 4640 adjacent to the top surface of the active region 4600 can collectively define the control gate 465 of the transistor 4540. 00For each control gate 465, its lower control gate portion 462 may be in a plane parallel to the plane containing its upper control gate portion 464, and its side control gate portion 463 may be in different planes, each orthogonal to the planes of the lower control gate portion 462 and the upper control gate portion 464.

[0074] In one embodiment, the length of the control gate (e.g., as in...) Figure 12A The distance (measured from left to right) can be 0.15 μm, where the spacing between adjacent control gates is 0.05 μm. The control gate can be spaced 0.04 μm from the surface of the active region 460, for example, through a dielectric material. In some embodiments, the lower portion of the control gate can be spaced from the lower surface of the active region 460 by a greater distance than the side and upper surfaces. For example, the lower portion of the control gate can be spaced 0.14 μm from the lower surface of the active region 460. The active region 460 can have a cross-section of 0.07 μm × 0.07 μm. Although specific examples of dimensions are provided, such dimensions are not required and other dimensions may be used in response to desired operating characteristics or in response to advancements in the ability to reliably define smaller device sizes.

[0075] As in Figure 12B As depicted, the distance (e.g., lateral distance) d1 between the first source / drain region 578 and the nearest control gate (e.g., a control gate having a lower control gate portion 4620 and an upper control gate portion 4640) may differ from the distance between the second source / drain region 580 and the nearest control gate (e.g., a control gate having a lower control gate portion 4620 and an upper control gate portion 4640). G and the upper control gate portion 464 G The distance (e.g., lateral distance) d2 between the control gates of transistor 4540. Specifically, for example, due to the expected voltage drop across transistor 4540, it is desirable to have different active region lengths between the source and drain sides of transistor 4540 and their nearest control gates. For example, considering the expected voltage level of the voltage node is higher than the voltage level of the load node, the distance d1 may be greater than the distance d2.

[0076] Figures 12A to 12D In some embodiments, the upper control gate portion 464 and its corresponding lower control gate portion 462 may be connected to the same signal line of the block select line 356. Alternatively, the signal line of the block select line 356 may be connected to a specific control gate portion of the control gate, such as the upper control gate portion 464 or the lower control gate portion 462, and each remaining control gate portion of the control gate may be connected to the signal line only through its connection to a specific control gate portion.

[0077] Although reference Figures 5A to 12DThe depicted embodiment illustrates three conductive vias 463 extending from the lower control gate portion 462 to the upper control gate portion 464 on both sides of the active region 460. However, alternative embodiments may utilize more or fewer conductive vias 463 to connect the lower control gate portion 462 to the corresponding upper control gate portion 464. The conductive vias 463 may contact a significant portion of the length of each lower control gate portion 462 and upper control gate portion 464, as shown in... Figure 12A Measured from left to right. Furthermore, although the reference... Figures 5A to 12D The depicted embodiment shows a plurality of conductive vias 463 extending from the lower control gate portion 462 to the upper control gate portion 464 on both sides of the active region 460, but alternative embodiments may utilize a single conductive via 463' on each side of the active region to connect the lower control gate portion 462 to the corresponding upper control gate portion 464. Figure 13 According to yet another embodiment along Figure 4 The line AA is intercepted Figure 4 A cross-sectional view of the transistor, wherein the conductive via 463' extends across most of the length of the lower control gate portion 462 and the upper control gate portion 464, as shown in... Figure 13 Measured from left to right. In some embodiments, the conductive via 463' may extend the full length of the lower control gate portion 462 or the upper control gate portion 464, and in further embodiments, it may extend beyond the full length of the lower control gate portion 462 or the upper control gate portion 464. Although Figure 13 The cross-section depicts one side of transistor 4540, but this cross-section can also be applied to the other side of transistor 4540, or to both sides of transistor 4541.

[0078] Additionally, although reference Figures 5A to 12D The depicted embodiment illustrates a lower control gate portion 462 extending between adjacent transistors, for example, as in Figure 12C As depicted, it extends between transistors 4540 and 4541, but in alternative embodiments, the lower control gate portion 462 adjacent to the transistor may be separated. Figure 14 For along Figure 4 The line CC is intercepted according to yet another embodiment Figure 4 A cross-sectional view of a transistor. Figure 14 The image depicts transistor 4540 having a lower control gate portion 462 similar to that of transistor 4541. 01 Separate lower control gate portion 462 00 Examples. See reference. Figures 6A to 6D As discussed, such a separate lower control gate portion 462 can be defined during the patterning of conductor 574. Although Figure 14The cross-section depicts the lower control gate portion 462 00 and 462 01 However, this cross-section can be applied equally to any of the lower control gate portions 462, as they can all have similar (e.g., identical) structures.

[0079] Furthermore, despite reference Figures 5A to 12D The depicted embodiments depict an active region 460 surrounded by control gate portions 462, 463 and 464, for example having control gate portions adjacent to the surface of the active region 460 in four planes. Various embodiments may only partially surround the active region 460, for example having control gate portions adjacent to the surface of the active region 460 in fewer than four planes. Figures 15A to 15E According to various embodiments Figure 4 A cross-sectional view of the transistor, showing a control gate portion adjacent to the surface of the active region 460 in fewer than four planes. Figures 15A to 15E The directional terms used in the description will be from the perspective of the observer of the graph.

[0080] exist Figure 15A In this embodiment, transistor 454 has a control gate portion in two planes adjacent to the surfaces (e.g., top and side surfaces) of each of the active regions 460. For example, for each active region 460, the upper control gate portion 4640 is adjacent to the upper surface of the active region 460 extending in a plane (e.g., a horizontal plane) above the active region 460; and the corresponding side control gate portion 463 is adjacent to the side surface of the active region 460 extending in a plane (e.g., a vertical plane), and adjacent to the side surfaces of the active regions 460 (e.g., the right side surface of active region 4600 and the left side surface of active region 4601). Note that such embodiments having a side control gate portion 463 on one side of the active region 460 may alternatively be on the same side of each active region 460. For example, the side control gate portion 463 may be adjacent to the right side of each active region 4600 and 4601, or adjacent to the left side of each active region 4600 and 4601. Furthermore, for different control gates, the embodiments may stagger the placement of the control gate portions 463 on different sides. For example, as in Figure 15A As depicted, the side control gate portion 463 may be adjacent to the right side surface of the active region 4600 of the upper control gate portion 4640, and the side control gate portion 463 may be adjacent to the left side surface of the active region 4600 of the upper control gate portion 4641.

[0081] exist Figure 15B In the reference transistor 454, there is a similarity to the reference transistor. Figure 15A The control gate portion is adjacent to the surface (e.g., top surface and side surface) of each active region 460 in two planes similar to the plane discussed. However, although Figure 15AThe side control gate portion 463 is depicted to extend beyond the entire thickness of the active region 460, for example, as measured from the top surface to the bottom surface of the active region 460. Figure 15B The side control gate portion 463 is depicted as extending along the entire thickness of the active region 460.

[0082] exist Figure 15C In this configuration, transistor 454 has a control gate portion adjacent to the surface (e.g., top surface and two side surfaces) of each of the three planes of the active region 460. Figure 15A Similarly, the side control gate portion 463 may extend the entire thickness of the active region 460, which may include extending beyond the bottom surface of the active region 460 as depicted, or extending less than the referenced... Figure 15B The entire thickness of the active region 460 discussed.

[0083] exist Figure 15D In this transistor, transistor 454 has a control gate portion that is adjacent to the surface (e.g., top surface, a side surface, and bottom surface) of each active region 460 in three planes. For example, for each active region 460, the upper control gate portion 4640 is adjacent to the upper surface of the active region 460 extending in a plane (e.g., a horizontal plane) above the active region 460; the corresponding side control gate portion 463 is adjacent to the side surface of the active region 460 extending in a plane (e.g., a vertical plane), and adjacent to the side surfaces of the active region 460 (e.g., the left side surface of active region 4600 and the right side surface of active region 4601); and the lower control gate portion 462... 00 and 462 01 It is adjacent to the lower surface of the active region 460, which extends in a plane (e.g., a horizontal plane) below the active region 460. Although Figure 15D The embodiments depict lower control gate portions 462 of different active regions 460 separated from each other, but the lower control gate portions can utilize, for example... Figure 12C The single conductor depicted. Although not mandatory, such embodiments using a single conductor for the lower control gate portion 462 may connect both the lower control gate portion 462 and the upper control gate portion 464 to the same signal line of the block select line 356. Alternatively, such embodiments may connect the signal line of the block select line 356 to only one of the upper control gate portion 464 and the lower control gate portion 462.

[0084] exist Figure 15E In the transistor 454, the control gate portion is adjacent to the surface (e.g., top surface and bottom surface) of each active region 460 in the two planes. Figure 15EAn embodiment uses a single conductor for the lower control gate portion 462. For example, for each active region 460, the upper control gate portion 4640 is adjacent to the upper surface of the active region 460 extending in a plane (e.g., a horizontal plane) above the active region 460; and the lower control gate portion 4620 is adjacent to the lower surface of the active region 460 extending in a plane (e.g., a horizontal plane) below the active region 460. The upper control gate portion 4640 and the lower control gate portion 4620 may be commonly connected to signal lines 15560 of the block select line 356. As indicated, each remaining signal line 15561 to 1556 of the block select line 356... G They can be similarly connected together to the corresponding pair of upper control gate portions 464 and lower control gate portions 462.

[0085] Figure 16 A conceptual depiction illustrates the connection of a portion of a string driver circuitry system connected to access lines of multiple memory cell blocks according to an embodiment. For example, the first string driver 16950 may have transistors ( Figure 16 (Examples are provided below), the transistors correspond to conductors 464 respectively. 00 Up to 464 G0 And connected to the first contact 466 (e.g., the first contact 466) X 466 X+1 and 466 X+2 ) and the corresponding second contact 468 (e.g., second contact 468) X0 468 (X+1)0 and 468 (X+2)0 Between, and the second string driver 16951 may have transistors ( Figure 16 (Not listed in the text), the transistors correspond to conductors 464 respectively. 01 Up to 464 G1 And connected to the first contact 466 (e.g., the first contact 466) X 466 X+1 and 466 X+2 ) and the corresponding second contact 468 (e.g., second contact 468) X1 468 (X+1)1 and 468 (X+2)1 Between. For example, the transistors of string drivers 16950 and 16951 can correspond to Figure 4 and 12A Transistor 454 as depicted in 12D.

[0086] The second contact 468 of the first string driver 16950 X0 468 (X+1)0 and 468 (X+2)0 Word lines 202 that can be connected to memory cell block 2500 respectively X0202 (X+1)0 and 202 (X+2)0 . Word line 202 X0 202 (X+1)0 and 202 (X+2)0 It may only represent a portion of the word lines of memory cell block 2500. For example, memory cell block 2500 may contain N+1 word lines 202, for example... Figure 2A As depicted, and the word line 202 of memory cell block 2500 X0 202 (X+1)0 and 202 (X+2)0 They can correspond to respectively Figure 2A 202 X 202 X+1 and 202 X+2 .

[0087] The second contact 468 of the second string driver 16951 X1 468 (X+1)1 and 468 (X+2)1 Word lines 202 that can be connected to memory cell block 2501 respectively X1 202 (X+1)1 and 202 (X+2)1 . Word line 202 X1 202 (X+1)1 and 202 (X+2)1 It may only represent a portion of the word lines of memory cell block 2501. For example, memory cell block 2501 may contain N+1 word lines 202, for example... Figure 2A As depicted, and the word line 202 of memory cell block 2501 X1 202 (X+1)1 and 202 (X+2)1 They can correspond to respectively Figure 2A 202 X 202 X+1 and 202 X+2 .

[0088] Serial drivers 16950 and 16951 can be Figure 2C This is part of the peripheral circuit system 226. For example, a string driver 16950 may be formed on word line 202 of memory cell block 2500. X0 202 (X+1)0 and 202 (X+2)0 Below (e.g., at least partially below). For example, a string driver 16951 may be formed on word line 202 of memory cell block 2501. X1 202 (X+1)1 and 202 (X+2)1Below (e.g., at least partially below). Alternatively, the string driver 16950 may be formed on word line 202 of memory cell block 2500. X0 202 (X+1)0 and 202 (X+2)0 Above (e.g., at least partially above), and the string driver 16951 may be formed on word line 202 of memory cell block 2501. X1 202 (X+1)1 and 202 (X+2)1 Above (e.g., at least partially above it).

[0089] To activate the string driver 1695, or any of its corresponding transistors, for example Figure 4 Transistor 4540 can apply a reference potential (e.g., ground, 0V, or Vss) to conductors 4640 to 464 G Each of them, because the transistor can be a normally open transistor, regardless of whether the active region 460 has p-type or n-type conductivity.

[0090] To deactivate the string driver 1695, or any of its corresponding transistors, for example Figure 4 The transistor 4540 can apply one or more positive voltage levels (e.g., for a p-type active region) or can apply one or more negative voltage levels of sufficient magnitude (e.g., for an n-type active region) to conductors 4640 to 464. G One or more of them. In some embodiments, the voltage level applied to conductor 4640 has a voltage level greater than or equal to that applied to the remaining conductors 4641 to 4642. G The corresponding magnitude of the voltage level. In another embodiment, applied to conductor 464 Q The voltage level has a value greater than or equal to that applied to the remaining conductors 464 Q+1 Up to 464 G The voltage level is of the corresponding order of magnitude, and for each value of Q, the relationship 0 <= Q <= G-1 is satisfied. In a further embodiment, the voltage applied to conductor 464... Q The voltage level and the voltage applied to conductor 464 Q+1 The voltage difference between the voltage levels is less than or equal to the voltage applied to conductor 464. Q+1 The voltage level and the voltage applied to conductor 464 Q+2 The voltage difference between the voltage levels satisfies the relationship 0 <= Q <= G-2 for each value of Q.

[0091] As deactivation Figure 4An example of a transistor of the type depicted herein, wherein G = 8, wherein a first contact 466 is configured to receive 30V, and wherein a second contact 468 is at 0V, conductor 4640 is configured to receive 30V, conductor 4641 is configured to receive 30V, conductor 4642 is configured to receive 28V, conductor 4643 is configured to receive 25V, conductor 4644 is configured to receive 20V, conductor 4645 is configured to receive 15V, conductor 4646 is configured to receive 10V, conductor 4647 is configured to receive 5V, and conductor 4648 is configured to receive 0V.

[0092] Figure 17 This is a perspective view of transistor 454 according to an embodiment. Figure 17 Elements with the same number in the middle correspond to, for example, those about Figures 5A to 12D The description provided. Figure 17 In the embodiment, variable G equals 4, such that Figure 17 The transistor 454 contains five control gates 4650 to 4654. Figure 17 An embodiment is further depicted that extends the entire thickness of the active region 460 by the first source / drain region 578 and the second source / drain region 580.

[0093] in conclusion

[0094] While specific embodiments have been illustrated and described herein, those skilled in the art will understand that any arrangement calculated to achieve the same purpose may replace the specific embodiments shown. Many modifications to the embodiments will be apparent to those skilled in the art. Therefore, this application is intended to cover any alterations or variations to the embodiments.

Claims

1. A multi-gate transistor, comprising: The active region has the first type of conductivity; A first source / drain region, which is located in the active region and has a second conductivity type different from the first conductivity type; A second source / drain region, located in the active region and having the second conductivity type; and Multiple control gates are located adjacent to the active region between the first source / drain region and the second source / drain region; Each of the plurality of control gates includes a corresponding plurality of control gate portions; and For a particular control gate among the plurality of control gates, each of the corresponding plurality of control gate portions is adjacent to the active region in a corresponding plane among a plurality of different planes.

2. The multi-gate transistor of claim 1, wherein each of the plurality of control gates is independent of each of the remaining control gates of the plurality of control gates.

3. The multi-gate transistor of claim 1, wherein the respective plurality of control gate portions of the particular control gate include a conductive first control gate portion in a first plane among the plurality of different planes and a conductive second control gate portion in a second plane among the plurality of different planes.

4. The multi-gate transistor of claim 3, wherein the conductive second control gate portion comprises a conductive material different from the conductive first control gate portion.

5. The multi-gate transistor of claim 3, wherein the second plane is in an orientation selected from the group consisting of being orthogonal to the first plane and parallel to the first plane.

6. The multi-gate transistor of claim 3, wherein the respective plurality of control gate portions of the particular control gate further includes a conductive third control gate portion in a third plane among the plurality of different planes.

7. The multi-gate transistor of claim 6, wherein the second plane is orthogonal to the first plane, and wherein the third plane is parallel to the first plane.

8. The multi-gate transistor of claim 6, wherein the respective plurality of control gate portions of the particular control gate further includes a conductive fourth control gate portion in a fourth plane parallel to the first plane and the second plane among the plurality of different planes.

9. The multi-gate transistor according to claim 1, wherein the first conductivity type is p-type conductivity and the second conductivity type is n-type conductivity.

10. The multi-gate transistor of claim 1, wherein the first source / drain region and the second source / drain region have a dopant concentration greater than the dopant concentration of the active region.

11. The multi-gate transistor of claim 10, wherein the active region has an undoped 2E18 / cm² region. 3 The dopant concentration.

12. The multi-gate transistor of claim 11, wherein the first source / drain region and the second source / drain region each have a density of 2E18-1E21 / cm. 3 The dopant concentration.

13. A memory comprising: Memory cell array; Multiple access lines, wherein each of the multiple access lines is commonly connected to the control gate of a corresponding plurality of memory cells in the memory cell array; and A driver circuit system comprising a plurality of transistors, wherein each of the plurality of transistors is connected to a corresponding access line of a plurality of access lines; The specific transistors among the plurality of transistors include: The active region has the first type of conductivity; A first source / drain region, which is located in the active region and has a second conductivity type different from the first conductivity type; A second source / drain region, located in the active region and having the second conductivity type; and Multiple control gates are located adjacent to the active region between the first source / drain region and the second source / drain region; Each of the plurality of control gates includes a corresponding plurality of control gate portions; Wherein, for a specific control gate among the plurality of control gates, each of its corresponding plurality of control gate portions is adjacent to the active region in a corresponding plane among a plurality of different planes; and The second source / drain region of the particular transistor is connected to the corresponding access line of the particular transistor.

14. The memory of claim 13, wherein the lateral distance between the first source / drain region and the control gate closest to the first source / drain region among the plurality of control gates is greater than the lateral distance between the second source / drain region and the control gate closest to the second source / drain region among the plurality of control gates.

15. The memory of claim 13, wherein for a particular control gate among the plurality of control gates, each of the respective plurality of control gate portions is adjacent to the active region in a respective plane among the plurality of different planes.

16. The memory of claim 15, wherein each of the respective plurality of control gate portions for different control gates is located in the same plane among the plurality of different planes as a corresponding control gate portion of the respective plurality of control gate portions for the particular control gate.

17. The memory of claim 13, wherein the different transistors of the plurality of transistors comprise: A third source / drain region, located in the active region and having the second conductivity type; and A second plurality of control gates surround the active region between the first source / drain region and the third source / drain region; The third source / drain regions of the different transistors are connected to the corresponding access lines of the different transistors.

18. The memory of claim 13, wherein the active region is a first active region, the plurality of control gates are a first plurality of control gates, the plurality of different planes are a first plurality of different planes, and the different transistors among the plurality of transistors include: The second active region has the first conductivity type; The third source / drain region is located in the second active region and has the second conductivity type; A fourth source / drain region, which is located in the second active region and has the second conductivity type; and The second plurality of control gates are adjacent to the second active region between the third source / drain region and the fourth source / drain region; Each of the second plurality of control gates includes a corresponding plurality of control gate portions; and Wherein, for a particular control gate among the second plurality of control gates, each of its respective plurality of control gate portions is adjacent to the active region in a corresponding plane among the second plurality of different planes; The fourth source / drain regions of the different transistors are connected to the corresponding access lines of the different transistors; and Each of the first plurality of control gates is connected to a corresponding control gate in the second plurality of control gates.

19. The memory of claim 18, wherein a particular control gate in the first plurality of control gates is connected to its respective control gate in the second plurality of control gates using two conductors formed on opposite sides of the first active region.

20. The memory of claim 18, wherein a particular control gate in the first plurality of control gates is connected to its corresponding control gate in the second plurality of control gates via only a single conductor.

21. The memory of claim 13, wherein the particular control gate of the plurality of control gates comprises a conductive lower control gate portion, two conductive side control gate portions, and a conductive upper control gate portion.

22. The memory of claim 21, wherein the conductive lower control gate portion comprises a first metal, wherein the conductive side control gate portion comprises conductive doped polysilicon, and wherein the conductive upper control gate portion comprises a second metal.

23. The memory of claim 22, wherein the first metal and the second metal are the same metal.

24. The memory of claim 21, wherein each conductive side control gate portion includes a plurality of conductive vias that are in contact with the conductive lower control gate portion and the conductive upper control gate portion.

25. The memory of claim 21, wherein each conductive side control gate portion includes a single conductive via that contacts the conductive lower control gate portion and the conductive upper control gate portion.

26. The memory of claim 25, wherein the single conductive via for one of the conductive side control gate portions is in contact with a substantial length of the conductive lower control gate portion and a substantial length of the conductive upper control gate portion.

27. The memory of claim 26, wherein the single conductive via for one of the conductive side control gate portions contacts the entire length of the conductive lower control gate portion and the entire length of the conductive upper control gate portion.

28. A method of forming a multi-gate transistor, comprising: A semiconductor material having a first conductivity type is formed by forming a first dielectric material overlying it; Patterning the semiconductor material to form an active region; A first source / drain region having a second conductivity type different from the first conductivity type is formed in the active region, and a second source / drain region having the second conductivity type is formed in the active region; A second dielectric material is formed that covers the active region and is also covered by the first dielectric material; A first conductive via is formed in the second dielectric material to contact the first source / drain region; A second conductive via is formed in the second dielectric material to contact the second source / drain region; Multiple third conductive vias are formed in the second dielectric material; A conductive material is formed covering the first conductive via, the second conductive via, the plurality of third conductive vias, and the second dielectric material, wherein the conductive material is in contact with the first conductive via, the second conductive via, and the plurality of third conductive vias; and The conductive material is patterned to form a plurality of upper control gate portions, a first contact to the first source / drain region, and a second contact to the second source / drain region.

29. The method of claim 28, wherein forming the semiconductor material having the first conductivity type comprises forming p-type polycrystalline silicon.

30. The method of claim 29, wherein forming the first source / drain region having the second conductivity type in the active region, and forming the second source / drain region having the second conductivity type in the active region comprises using an n-type dopant material to conductively dope the p-type polysilicon.

31. The method of claim 28, wherein prior to forming the semiconductor material, the method further comprises: A second conductive material is formed by covering a third dielectric material; The second conductive material is patterned to form a plurality of lower control gate portions; and The first dielectric material is formed covering the plurality of lower control gate portions and the third dielectric material; Each of the plurality of lower control gate portions is configured to be laterally located between the subsequently formed first source / drain region and the subsequently formed second source / drain region; Each of the plurality of third conductive vias is subsequently formed to contact a corresponding lower control gate portion of the plurality of lower control gate portions; and Each of the plurality of third conductive vias is subsequently configured such that each of the plurality of lower control gate portions will contact at least one of the plurality of third conductive vias.

32. A method for forming a multi-gate transistor, comprising: A first conductive material is formed by covering the first dielectric material; The first conductive material is patterned to form a plurality of lower control gate portions; A second dielectric material is formed that covers the plurality of lower control gate portions and is also covered by the first dielectric material; A semiconductor material having a first conductivity type is formed by covering the second dielectric material; The semiconductor material is patterned to form an active region covering the plurality of lower control gate portions; A first source / drain region having a second conductivity type different from the first conductivity type is formed in the active region, and a second source / drain region having the second conductivity type is formed in the active region, wherein each of the plurality of lower control gate portions is laterally located between the first source / drain region and the second source / drain region; A third dielectric material is formed that covers the active region and is also covered by the second dielectric material; A first conductive via is formed in the third dielectric material to contact the first source / drain region; A second conductive via is formed in the third dielectric material to contact the second source / drain region; A second conductive material is formed covering the first conductive via, the second conductive via, and the third dielectric material, wherein the second conductive material is in contact with the first conductive via and the second conductive via; and The second conductive material is patterned to form a plurality of upper control gate portions, a first contact to the first source / drain region, and a second contact to the second source / drain region.

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