Comparator and method for stabilizing an output signal thereof

Abstract

The application discloses a comparator and a method for stabilizing an output signal of the comparator. The comparator comprises a comparator unit, a sampling circuit, a driving circuit and a feedback control circuit. The sampling circuit is configured to collect an input signal and convert the input signal into a sampling current signal and output the sampling current signal. The driving circuit is configured to output one or more driving signals based on the sampling current signal. The feedback control circuit is configured to determine whether to feed a comparison signal to an input end of the comparator unit in a positive direction based on the driving signal, so as to latch the comparison signal. The comparator can capture a rapid and large amplitude change of the input signal in time, latch and hold a previous output, end the latching and holding when a working state of the circuit is fully re-established and a correct output can be output, so that the comparator does not occur error flip when dealing with a rapid and large amplitude signal, and always maintains a correct output.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a comparator and a method for stabilizing its output signal. Background Technology

[0002] Comparators typically support an input common-mode range from 0V to VDD-1.5V. In some applications, rapid input changes occur, such as a sudden shift from a relatively low voltage to a relatively high voltage or vice versa. The internal circuitry may struggle to capture and accurately follow these rapid changes, potentially causing disruptions to its operating point and resulting in erroneous output signal flips. This is especially true for high-voltage comparators, where the input common-mode voltage can exceed 30V, resulting in a very wide input voltage range. Such erroneous output flips due to rapid input changes are even more likely to occur.

[0003] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a comparator and a method for stabilizing its output signal, which can latch and hold the previous output when the common-mode voltage signal in the input signal changes rapidly and significantly.

[0005] To achieve the above objectives, embodiments of the present invention provide a comparator, including: a first MOS transistor, a second MOS transistor, a comparator unit, a sampling circuit, a driving circuit, and a feedback control circuit.

[0006] The first MOSFET and the second MOSFET form an input transistor pair, which is used to receive input signals. The first and second input terminals of the comparator unit are connected to the output terminals of the input transistor pair, and the output terminal of the comparator unit outputs a comparison signal. The sampling circuit is used to acquire the input signal and output a sampling current signal based on the input signal. The driving circuit is used to receive the sampling current signal and output one or more driving signals based on the sampling current signal. The feedback control circuit is connected to the output and input terminals of the comparator unit and the driving circuit. The feedback control circuit determines whether to positively feed the comparison signal back to the input terminal of the comparator unit based on the driving signal to latch the comparison signal.

[0007] In one or more embodiments of the present invention, the driving circuit includes a current providing unit for providing a reference current, the driving circuit compares the sampled current signal with the corresponding reference current, and outputs a driving signal according to the comparison result.

[0008] In one or more embodiments of the present invention, there are multiple current providing units to provide multiple different reference currents, and the driving circuit compares the sampled current signal with the corresponding reference current and outputs multiple driving signals according to the comparison result.

[0009] In one or more embodiments of the present invention, the driving circuit further includes a delay unit for delaying the output of the driving signal.

[0010] In one or more embodiments of the present invention, there are multiple current providing units, and at least one current providing unit is used to provide a first reference current, at least one current providing unit is used to provide a second reference current, and the delay unit is used to delay the output of a drive signal generated based on the comparison result of at least one first reference current and the corresponding sampled current signal and / or delay the output of a drive signal generated based on the comparison result of at least one second reference current and the corresponding sampled current signal.

[0011] In one or more embodiments of the present invention, the sampling circuit includes a third MOS transistor, a fourth MOS transistor, and a second power supply unit. The sources of the third MOS transistor and the fourth MOS transistor are connected and connected to the first terminal of the second power supply unit. The second terminal of the second power supply unit is connected to the power supply voltage. The gates of the third MOS transistor and the fourth MOS transistor are used to acquire input signals. The drains of the third MOS transistor and the fourth MOS transistor are connected to the driving circuit.

[0012] In one or more embodiments of the present invention, the driving circuit includes a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, a first current supply unit, and a second current supply unit;

[0013] The gate and drain of the fifth MOS transistor are shorted and connected to the output terminal of the sampling circuit. The source of the fifth MOS transistor is connected to ground. The fifth, sixth, and seventh MOS transistors are connected via a common gate. The drain of the sixth MOS transistor is connected to the first terminal of the first current supply unit and the feedback control circuit. The second terminal of the first current supply unit is connected to the power supply voltage. The source of the sixth MOS transistor is connected to ground. The drain of the seventh MOS transistor is connected to the first terminal of the second current supply unit and the feedback control circuit. The second terminal of the second current supply unit is connected to the power supply voltage. The source of the seventh MOS transistor is connected to ground.

[0014] In one or more embodiments of the present invention, the driving circuit further includes a twenty-fifth MOS transistor, a twenty-sixth MOS transistor, a third current supply unit, a fourth current supply unit, a first delay unit, and a second delay unit;

[0015] The 25th, 26th, and 5th MOSFETs are connected via a common gate. The first terminal of the third current supply unit is connected to the power supply voltage. The second terminal of the third current supply unit is connected to the first terminal of the first delay unit and the drain of the 25th MOSFET. The first terminal of the fourth current supply unit is connected to the power supply voltage. The second terminal of the fourth current supply unit is connected to the first terminal of the second delay unit and the drain of the 26th MOSFET. The sources of the 25th and 26th MOSFETs are connected to ground. The second terminals of the first and second delay units are connected to the feedback control circuit. The first and third current supply units are used to provide a first reference current, and the second and fourth current supply units are used to provide a second reference current. The width-to-length ratio of the 6th MOSFET is equal to that of the 25th MOSFET, and the width-to-length ratio of the 7th MOSFET is equal to that of the 26th MOSFET.

[0016] In one or more embodiments of the present invention, the first current providing unit is a first resistor or a third current source, the second current providing unit is a second resistor or a fourth current source, or the first current providing unit and the second current providing unit are connected to form a current mirror.

[0017] In one or more embodiments of the present invention, the first current providing unit is a first resistor or a third current source, the second current providing unit is a second resistor or a fourth current source, the third current providing unit is a third resistor or a sixth current source, the fourth current providing unit is a fourth resistor or a seventh current source, or two or more of the first current providing unit, the second current providing unit, the third current providing unit and the fourth current providing unit are connected together to form a current mirror.

[0018] In one or more embodiments of the present invention, the drain of the seventh MOS transistor or the drain of the sixth MOS transistor is connected to the feedback control circuit through a first inverter.

[0019] In one or more embodiments of the present invention, the drain of the seventh MOS transistor or the drain of the sixth MOS transistor is connected to the feedback control circuit through a first inverter, and the drain of the twenty-fifth MOS transistor or the twenty-sixth MOS transistor is connected to the feedback control circuit through a second inverter.

[0020] In one or more embodiments of the present invention, the feedback control circuit includes an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, and a third inverter;

[0021] The sources of the eighth and ninth MOS transistors are connected, the drains of the tenth and eleventh MOS transistors are connected and simultaneously connected to the source of the ninth MOS transistor, the sources of the tenth and eleventh MOS transistors are connected and connected to ground, and the output terminal of the third inverter is connected to the gate of the ninth MOS transistor.

[0022] The gate of the tenth MOS transistor forms the first input terminal of the feedback control circuit, and the gate of the eleventh MOS transistor forms the second input terminal of the feedback control circuit. The first and second input terminals are connected to the driving circuit. The gate of the eighth MOS transistor and the input terminal of the third inverter form the third input terminal of the feedback control circuit. The third input terminal is connected to the output terminal of the comparator unit. The drain of the eighth MOS transistor forms the first output terminal of the feedback control circuit, and the drain of the ninth MOS transistor forms the second output terminal of the feedback control circuit. The first and second output terminals are respectively connected to the first and second input terminals of the comparator unit.

[0023] In one or more embodiments of the present invention, the feedback control circuit further includes a twelfth MOS transistor or a twelfth MOS transistor and a thirteenth MOS transistor;

[0024] If the feedback control circuit includes a twelfth MOSFET, the drain of the twelfth MOSFET is connected to the source of the eighth MOSFET, and the source of the twelfth MOSFET is connected to the drain of the tenth MOSFET; or

[0025] The drain of the twelfth MOS transistor is connected to the source of the tenth MOS transistor, and the source of the twelfth MOS transistor is connected to ground.

[0026] If the feedback control circuit includes a twelfth MOS transistor and a thirteenth MOS transistor, the source of the twelfth MOS transistor is connected to the drain of the eighth MOS transistor, the source of the thirteenth MOS transistor is connected to the drain of the ninth MOS transistor, the sources of the eighth MOS transistor and the ninth MOS transistor are connected, the drains of the tenth MOS transistor and the eleventh MOS transistor are connected and simultaneously connected to the source of the ninth MOS transistor, the sources of the tenth MOS transistor and the eleventh MOS transistor are connected and connected to ground, and the output terminal of the third inverter is connected to the gate of the ninth MOS transistor;

[0027] The gate of the tenth MOS transistor forms the first input terminal of the feedback control circuit, the gate of the eleventh MOS transistor forms the second input terminal of the feedback control circuit, the gate of the eighth MOS transistor and the input terminal of the third inverter form the third input terminal of the feedback control circuit, the drain of the twelfth MOS transistor forms the first output terminal of the feedback control circuit, and the drain of the thirteenth MOS transistor forms the second output terminal of the feedback control circuit.

[0028] In one or more embodiments of the present invention, the feedback control circuit includes an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, and a third inverter;

[0029] The sources of the eighth and ninth MOS transistors are connected to ground. The drains of the tenth and eleventh MOS transistors are connected. The sources of the tenth and eleventh MOS transistors are connected and connected to the drain of the eighth MOS transistor. The drains of the fourteenth and fifteenth MOS transistors are connected. The sources of the fourteenth and fifteenth MOS transistors are connected and connected to the drain of the ninth MOS transistor. The gates of the eleventh and fourteenth MOS transistors are connected. The output of the third inverter is connected to the gate of the ninth MOS transistor.

[0030] The gates of the tenth and fifteenth MOS transistors form the first input terminal of the feedback control circuit, and the gates of the eleventh and fourteenth MOS transistors form the second input terminal of the feedback control circuit. The first and second input terminals are connected to the driving circuit. The gate of the eighth MOS transistor and the input terminal of the third inverter form the third input terminal of the feedback control circuit. The third input terminal is connected to the output terminal of the comparator unit. The drains of the tenth and eleventh MOS transistors form the first output terminal of the feedback control circuit, and the drains of the fourteenth and fifteenth MOS transistors form the second output terminal of the feedback control circuit. The first and second output terminals are respectively connected to the first and second input terminals of the comparator unit.

[0031] In one or more embodiments of the present invention, the feedback control circuit further includes a sixteenth MOS transistor or a sixteenth MOS transistor and a seventeenth MOS transistor;

[0032] If the feedback control circuit further includes a sixteenth MOS transistor, the drain of the sixteenth MOS transistor is connected to the source of the ninth MOS transistor, and the source of the sixteenth MOS transistor is connected to ground;

[0033] If the feedback control circuit further includes a sixteenth MOSFET and a seventeenth MOSFET, the drain of the sixteenth MOSFET is connected to the source of the tenth MOSFET, the source of the sixteenth MOSFET is connected to the drain of the eighth MOSFET, the drain of the seventeenth MOSFET is connected to the source of the fourteenth MOSFET, and the source of the seventeenth MOSFET is connected to the drain of the ninth MOSFET; or

[0034] The source of the sixteenth MOS transistor is connected to the drain of the tenth MOS transistor, the source of the seventeenth MOS transistor is connected to the drain of the fourteenth MOS transistor, the drain of the sixteenth MOS transistor forms the first output terminal of the feedback control circuit, and the drain of the seventeenth MOS transistor forms the second output terminal of the feedback control circuit.

[0035] In one or more embodiments of the present invention, if the feedback control circuit further includes a sixteenth MOS transistor, a plurality of transistor pairs are connected in series between the drain of the sixteenth MOS transistor and the source of the ninth MOS transistor and the eighth MOS transistor, the transistor pairs including an eighteenth MOS transistor and a nineteenth MOS transistor, the drains of the eighteenth MOS transistor and the nineteenth MOS transistor are connected and connected to the source of the ninth MOS transistor, and the sources of the eighteenth MOS transistor and the nineteenth MOS transistor are connected and connected to the drain of the sixteenth MOS transistor.

[0036] In one or more embodiments of the present invention, the feedback control circuit includes an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twenty-seventh MOS transistor, a twenty-eighth MOS transistor, and a third inverter;

[0037] The sources of the eighth and ninth MOS transistors are connected, the drains of the tenth, eleventh, twenty-seventh, and twenty-eighth MOS transistors are connected and simultaneously connected to the source of the ninth MOS transistor, the sources of the tenth, eleventh, twenty-seventh, and twenty-eighth MOS transistors are connected and connected to ground, and the output terminal of the third inverter is connected to the gate of the ninth MOS transistor.

[0038] The gate of the tenth MOS transistor forms the first input terminal of the feedback control circuit, the gate of the eleventh MOS transistor forms the second input terminal of the feedback control circuit, the gate of the twenty-seventh MOS transistor forms the third input terminal of the feedback control circuit, and the gate of the twenty-eighth MOS transistor forms the fourth input terminal of the feedback control circuit. The first, second, third, and fourth input terminals are connected to the driving circuit. The gate of the eighth MOS transistor and the input terminal of the third inverter form the fifth input terminal of the feedback control circuit. The fifth input terminal is connected to the output terminal of the comparator unit. The drain of the eighth MOS transistor forms the first output terminal of the feedback control circuit, and the drain of the ninth MOS transistor forms the second output terminal of the feedback control circuit. The first and second output terminals are respectively connected to the first and second input terminals of the comparator unit.

[0039] In one or more embodiments of the present invention, the comparator further includes a twentieth MOS transistor, a twenty-first MOS transistor, a twenty-second MOS transistor, a twenty-third MOS transistor, a twenty-fourth MOS transistor, and a fifth current source;

[0040] The source of the twentieth MOSFET is connected to the sources of the third and fourth MOSFETs. The gate and drain of the twentieth MOSFET are connected and connected to the source of the twentieth MOSFET. The gate and drain of the twentieth MOSFET are connected and connected to the first terminal of the fifth current source. The second terminal of the fifth current source is grounded. The source of the twentieth MOSFET is connected to the drain of the third MOSFET. The drain of the twentieth MOSFET is connected to the driving circuit. The gates of the twentieth, twentieth, twentieth, and twenty-fourth MOSFETs are connected. The source of the twentieth MOSFET is connected to the drain of the first MOSFET. The source of the twenty-fourth MOSFET is connected to the drain of the second MOSFET. The drains of the twentieth and twenty-fourth MOSFETs are respectively connected to the first and second input terminals of the comparator unit.

[0041] In one or more embodiments of the present invention, the comparator further includes a differential amplifier, wherein the first input terminal and the second input terminal of the differential amplifier are respectively connected to the drains of the first MOS transistor and the second MOS transistor, the first output terminal and the second output terminal of the differential amplifier are respectively connected to the first input terminal and the second input terminal of the comparator unit, and the first input terminal and the second input terminal of the differential amplifier, or the first output terminal and the second output terminal of the differential amplifier, or the drains of the first MOS transistor and the second MOS transistor are connected to a feedback control circuit.

[0042] This invention also discloses a method for stabilizing a comparator output signal, comprising:

[0043] The input signal is acquired by a sampling circuit and a sampled current signal is output based on the input signal.

[0044] The driving circuit captures the sampled current signal and outputs one or more driving signals.

[0045] The drive signal is received through the feedback control circuit. When the common-mode voltage signal in the input signal changes abruptly, causing the drive signal to change, the comparison signal output by the comparator unit is positively fed back to the input of the comparator unit to latch the comparison signal.

[0046] In one or more embodiments of the present invention, the sampled current signal is compared with the corresponding reference current by a driving circuit, and one or more driving signals are output according to the comparison result.

[0047] In one or more embodiments of the present invention, a driving circuit captures the sampled current signal and outputs one or more driving signals after a delay.

[0048] In one or more embodiments of the present invention, the reference current includes a first reference current and a second reference current. When the sampled current signal is less than the first reference current or the sampled current is greater than the second reference current, the output drive signal triggers the comparison signal output by the comparator unit to be positively fed back to the input terminal of the comparator unit, so as to latch the comparison signal.

[0049] Compared with the prior art, the comparator and its output signal stabilization method according to this embodiment capture the rapid and large-amplitude changes of the common-mode voltage signal of the input signal in a timely manner through the sampling circuit and convert the changes of the common-mode voltage signal into changes of the sampling current signal. The driving circuit receives the sampling current signal and outputs one or more driving signals based on the sampling current signal. The feedback control circuit starts working after receiving the driving signal and determines whether to feed the comparison signal output by the comparator unit positively back to the input terminal of the comparator unit based on the driving signal to latch and hold the previous output of the comparator unit. When the working state of the internal circuit of the comparator is fully re-established and the comparator unit can output correctly, the latching and holding ends. Thus, the comparator will not make erroneous flips when dealing with the rapid and large swing of the common-mode voltage signal of the input signal and can always maintain the correct output. Attached Figure Description

[0050] Figure 1 This is a first circuit schematic diagram of a comparator according to Embodiment 1 of the present invention.

[0051] Figure 2 This is a second circuit schematic diagram of the comparator according to Embodiment 1 of the present invention.

[0052] Figure 3 This is a circuit diagram of the feedback control circuit according to Embodiment 1 of the present invention.

[0053] Figure 4 This is a schematic diagram of the third circuit of the comparator according to Embodiment 1 of the present invention.

[0054] Figure 5 This is a method for stabilizing the comparator output signal according to Embodiment 1 of the present invention.

[0055] Figure 6 This is a circuit diagram of the feedback control circuit according to Embodiment 2 of the present invention.

[0056] Figure 7 This is a circuit diagram of the feedback control circuit according to Embodiment 3 of the present invention.

[0057] Figure 8 This is a circuit diagram of the feedback control circuit according to Embodiment 4 of the present invention.

[0058] Figure 9This is a circuit diagram of the feedback control circuit according to Embodiment 5 of the present invention.

[0059] Figure 10 This is a first circuit diagram of the feedback control circuit according to Embodiment Six of the present invention.

[0060] Figure 11 This is a second circuit schematic diagram of the feedback control circuit according to Embodiment Six of the present invention.

[0061] Figure 12 This is a circuit diagram of the feedback control circuit according to Embodiment Seven of the present invention.

[0062] Figure 13 This is a circuit diagram of the feedback control circuit according to Embodiment 8 of the present invention.

[0063] Figure 14 This is a circuit diagram of the driving circuit according to Embodiment Nine of the present invention.

[0064] Figure 15 This is another circuit schematic diagram of the driving circuit according to Embodiment Nine of the present invention.

[0065] Figure 16 This is a circuit diagram of the feedback control circuit according to Embodiment Nine of the present invention. Detailed Implementation

[0066] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0067] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0068] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected to" or "connected to" another element, or when an element / circuit is said to be "connected" between two nodes, it may be directly coupled to or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between them.

[0069] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0070] Example 1

[0071] like Figure 1 As shown, a comparator includes: a first MOSFET M1, a second MOSFET M2, a first power supply unit 11, a comparator unit CMP, a sampling circuit 20, a driving circuit 30, and a feedback control circuit 40.

[0072] Specifically, the first MOSFET M1 and the second MOSFET M2 form an input transistor pair to receive input signals IN+ and IN-, and the first power supply unit 11 is a first constant current source ib1. The gates of the first MOSFET M1 and the second MOSFET M2 are used to receive input signals IN+ and IN-, respectively. The first terminal of the first constant current source ib1 is connected to the source of the first MOSFET M1 and the second MOSFET M2, and the second terminal of the first constant current source ib1 is connected to the power supply voltage VDD.

[0073] The first and second input terminals of the comparator unit CMP are connected to the output terminals of the input transistor pair, and the output terminal of the comparator unit CMP outputs a comparison signal OP. In this embodiment, the first input terminal of the comparator unit CMP is a positive input terminal, and the second input terminal of the comparator unit CMP is a negative input terminal. The drains of the first MOSFET M1 and the second MOSFET M2 are the output terminals of the input transistor pair. The drain of the first MOSFET M1 is connected to the second input terminal of the comparator unit CMP, and the drain of the second MOSFET M2 is connected to the first input terminal of the comparator unit CMP. In other embodiments, the first input terminal of the comparator unit CMP can be a negative input terminal, and the second input terminal of the comparator unit CMP can be a positive input terminal.

[0074] like Figure 1 As shown, the sampling circuit 20 is used to acquire the input signals IN+ and IN-, and output the sampled current signal based on the input signals IN+ and IN-.

[0075] Specifically, the sampling circuit 20 includes a third MOSFET M3, a fourth MOSFET M4, and a second power supply unit 21. In this embodiment, the second power supply unit 21 is a second constant current source ib2. The sources of the third MOSFET M3 and the fourth MOSFET M4 are connected and connected to the first terminal of the second constant current source ib2, and the second terminal of the second constant current source ib2 is connected to the power supply voltage VDD. The gates of the third MOSFET M3 and the fourth MOSFET M4 are used to acquire the input signals IN+ and IN-, and the drains of the third MOSFET M3 and the fourth MOSFET M4 are connected to the driving circuit 30. After the gates of the third MOSFET M3 and the fourth MOSFET M4 acquire the input signals IN+ and IN-, the sampling current signal is output through the drains of the third MOSFET M3 and the fourth MOSFET M4. In other embodiments, the first power supply unit 11 and the second power supply unit 21 can also both be MOSFETs, and the two MOSFETs are combined to form a current mirror.

[0076] like Figure 1 As shown, the driving circuit 30 is used to receive the sampled current signal and output one or more driving signals based on the sampled current signal.

[0077] The driving circuit 30 includes a current providing unit, which provides a reference current. The driving circuit 30 compares the sampled current signal with the corresponding reference current and outputs a driving signal based on the comparison result. When there are multiple current providing units, multiple different reference currents can be provided. In this embodiment, two current providing units are provided: a first current providing unit 31 and a second current providing unit 32. The driving circuit 30 compares the sampled current signal with the corresponding reference current and outputs multiple driving signals based on the comparison result.

[0078] Specifically, the driving circuit 30 includes a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, a first current supply unit 31, and a second current supply unit 32.

[0079] The gate and drain of the fifth MOSFET M5 are shorted and connected to the drains of the third MOSFET M3 and the fourth MOSFET M4. The source of the fifth MOSFET M5 is connected to ground. The fifth MOSFET M5, the sixth MOSFET M6, and the seventh MOSFET M7 are connected in a common-gate configuration. The drain of the sixth MOSFET M6 is connected to the first terminal of the first current supply unit 31 and the first input terminal B1 of the feedback control circuit 40. The second terminal of the first current supply unit 31 is connected to the power supply voltage VDD. The source of the sixth MOSFET M6 is connected to ground. The drain of the seventh MOSFET M7 is connected to the first terminal of the second current supply unit 32 and the second input terminal B2 of the feedback control circuit 40. The second terminal of the second current supply unit 32 is connected to the power supply voltage VDD. The source of the seventh MOSFET M7 is connected to ground.

[0080] In this embodiment, the first current providing unit 31 is the third current source ib3, and the second current providing unit 32 is the fourth current source ib4. The third current source ib3 and the fourth current source ib4 respectively provide corresponding reference currents. The fifth MOSFET M5, the sixth MOSFET M6, and the seventh MOSFET M7 form a current mirror. The ratio of the current flowing through the sixth MOSFET M6 to the current flowing through the fifth MOSFET M5 can be adjusted by adjusting the width-to-length ratio of the fifth MOSFET M5 and the sixth MOSFET M6. Similarly, the ratio of the current flowing through the seventh MOSFET M7 to the current flowing through the fifth MOSFET M5 can be adjusted by adjusting the width-to-length ratio of the fifth MOSFET M5 and the seventh MOSFET M7. When the comparator is operating normally, the reference current provided by the third current source ib3 is generally set to be less than the reference current provided by the fourth current source ib4, and the current flowing through the sixth MOSFET M6 is greater than the reference current provided by the third current source ib3, while the current flowing through the seventh MOSFET M7 is less than the reference current provided by the fourth current source ib4. In other embodiments, the magnitude relationship between the reference currents provided by the third current source ib3 and the fourth current source ib4, and their respective relationships with the currents flowing through the sixth MOS transistor M6 and the seventh MOS transistor M7, can be changed.

[0081] The drain of the seventh MOSFET M7 is connected to the second input terminal B2 of the feedback control circuit 40 via the first inverter INV1, or the drain of the sixth MOSFET M6 is connected to the first input terminal B1 of the feedback control circuit 40 via the first inverter INV1. The first inverter INV1 inverts the output level signals from the drains of either the seventh MOSFET M7 or the sixth MOSFET M6, thus unifying the output level signals from the drains of the seventh MOSFET M7 and the sixth MOSFET M6. In this embodiment, the drain of the seventh MOSFET M7 is connected to the input terminal of the first inverter INV1, and the output terminal of the first inverter INV1 is connected to the second input terminal B2 of the feedback control circuit 40. This ensures that the feedback control circuit 40 operates when both its first input terminal B1 and second input terminal B2 receive a high-level signal. In other embodiments, the first inverter INV1 can be omitted.

[0082] like Figure 2As shown, the first current providing unit 31 can also be a first resistor R1, and the second current providing unit 32 can also be a second resistor R2. Alternatively, in other embodiments, the first current providing unit 31 can be a first resistor R1, and the second current providing unit 32 can be a fourth current source ib4; or the first current providing unit 31 can be a third current source ib3, and the second current providing unit 32 can be a second resistor R2. Furthermore, the first current providing unit 31 and the second current providing unit 32 can be connected to form a current mirror, meaning that both the first current providing unit 31 and the second current providing unit 32 are MOSFETs.

[0083] If the first current providing unit 31 is the first resistor R1, when the current through the first resistor R1 decreases, the drain of the sixth MOSFET M6 outputs a high-level signal; if the second current providing unit 32 is the second resistor R2, when the current through the second resistor R2 increases, the drain of the seventh MOSFET M7 outputs a low-level signal. If the first current providing unit 31 and the second current providing unit 32 form a current mirror, the principle of current comparison and signal output is the same as when the first current providing unit 31 is the third current source ib3 and the second current providing unit 32 is the fourth current source ib4.

[0084] like Figure 1 As shown, the feedback control circuit 40 is connected to the output and input terminals of the comparator unit CMP and the drive circuit 30. The feedback control circuit 40 determines whether to positively feed the comparison signal OP to the front end of the comparator unit CMP based on the drive signal, so as to latch the comparison signal OP.

[0085] like Figure 3 As shown, specifically, the feedback control circuit 40 includes an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, an eleventh MOSFET M11, and a third inverter INV3.

[0086] The sources of the eighth MOSFET M8 and the ninth MOSFET M9 are connected. The drains of the tenth MOSFET M10 and the eleventh MOSFET M11 are connected and simultaneously connected to the sources of the ninth MOSFET M9 and the eighth MOSFET M8. The sources of the tenth MOSFET M10 and the eleventh MOSFET M11 are connected and connected to ground. The output of the third inverter INV3 is connected to the gate of the ninth MOSFET M9.

[0087] The gate of the tenth MOSFET M10 forms the first input terminal B1 of the feedback control circuit 40, and the gate of the eleventh MOSFET M11 forms the second input terminal B2 of the feedback control circuit 40. In this embodiment, the first input terminal B1 is connected to the drain of the sixth MOSFET M6, and the second input terminal B2 is connected to the drain of the seventh MOSFET M7 through the first inverter INV1.

[0088] The gate of the eighth MOSFET M8 and the input of the third inverter INV3 form the third input A1 of the feedback control circuit 40. The third input A1 is connected to the output of the comparator unit CMP.

[0089] The drain of the eighth MOSFET M8 forms the first output terminal Q1 of the feedback control circuit 40, and the drain of the ninth MOSFET M9 forms the second output terminal Q2 of the feedback control circuit 40. The first output terminal Q1 is connected to the second input terminal of the comparator unit CMP, and the second output terminal Q2 is connected to the first input terminal of the comparator unit CMP.

[0090] In other embodiments, buffers can be added to the first input terminal B1, the second input terminal B2, the third input terminal A1, the first output terminal Q1, and the second output terminal Q2.

[0091] In addition, such as Figure 4 As shown, the comparator in this embodiment further includes a twentieth MOSFET M20, a twenty-first MOSFET M21, a twenty-second MOSFET M22, a twenty-third MOSFET M23, a twenty-fourth MOSFET M24, and a fifth current source ib5. The twentieth MOSFET M20, twenty-first MOSFET M21, twenty-second MOSFET M22, twenty-third MOSFET M23, twenty-fourth MOSFET M24, and the fifth current source ib5 form a level shifting circuit. This level shifting circuit is used to clamp the source-drain voltages of the first MOSFET M1, the second MOSFET M2, the third MOSFET M3, and the fourth MOSFET M4. In this embodiment, the twenty-second MOSFET M22, the twenty-third MOSFET M23, and the twenty-fourth MOSFET M24 are high-voltage transistors.

[0092] Specifically, the source of the twentieth MOSFET M20 is connected to the sources of the third MOSFET M3 and the fourth MOSFET M4. The gate and drain of the twentieth MOSFET M20 are connected and also connected to the source of the twenty-first MOSFET M21. The gate and drain of the twenty-first MOSFET M21 are connected and also connected to the first terminal of the fifth current source ib5. The second terminal of the fifth current source ib5 is grounded. The source of the twenty-second MOSFET M22 is connected to the drain of the third MOSFET M3. The drain of the twenty-second MOSFET M22 is connected to the drain of the fifth MOSFET M5 in the drive circuit 30. The gates of the 21st MOSFET M21, the 22nd MOSFET M22, the 23rd MOSFET M23, and the 24th MOSFET M24 are connected. The source of the 23rd MOSFET M23 is connected to the drain of the 1st MOSFET M1. The source of the 24th MOSFET M24 is connected to the drain of the 2nd MOSFET M2. The drain of the 23rd MOSFET M23 is connected to the second input terminal of the comparator unit CMP. The drain of the 24th MOSFET M24 is connected to the first input terminal of the comparator unit CMP.

[0093] like Figure 4 As shown, the comparator in this embodiment also includes a differential amplifier AMP. The first and second input terminals of the differential amplifier AMP are connected to the drains of the first MOSFET M1 and the second MOSFET M2, respectively. The first and second output terminals of the differential amplifier AMP are connected to the first and second input terminals of the comparator unit CMP, respectively. In this embodiment, the first input terminal of the differential amplifier AMP is a positive input terminal, and the second input terminal is a negative input terminal; the first output terminal of the differential amplifier AMP is a positive output terminal, and the second output terminal is a negative output terminal. In other embodiments, the first input terminal of the differential amplifier AMP is a negative input terminal, the second input terminal is a positive input terminal, the first output terminal is a negative output terminal, and the second output terminal is a positive output terminal.

[0094] The first input terminal of the differential amplifier AMP is connected to the drain of the twenty-fourth MOSFET M24, and the second input terminal of the differential amplifier AMP is connected to the drain of the twenty-third MOSFET M23. The first output terminal of the differential amplifier AMP is connected to the first input terminal of the comparator unit CMP, and the second output terminal of the differential amplifier AMP is connected to the second input terminal of the comparator unit CMP.

[0095] In this embodiment, the first output terminal Q1 of the feedback control circuit 40 is connected to the second output terminal of the differential amplifier AMP and the second input terminal of the comparator unit CMP, and the second output terminal Q2 of the feedback control circuit 40 is connected to the first output terminal of the differential amplifier AMP and the first input terminal of the comparator unit CMP. In other embodiments, the first output terminal Q1 of the feedback control circuit 40 is connected to the second input terminal of the differential amplifier AMP, and the second output terminal Q2 of the feedback control circuit 40 is connected to the first input terminal of the differential amplifier AMP. Alternatively, in other embodiments, the first output terminal Q1 of the feedback control circuit 40 is connected to the drain of the first MOSFET M1, and the second output terminal Q2 of the feedback control circuit 40 is connected to the drain of the second MOSFET M2.

[0096] In this embodiment, the first MOSFET M1, the second MOSFET M2, the third MOSFET M3, the fourth MOSFET M4, the twentieth MOSFET M20, the twenty-first MOSFET M21, the twenty-second MOSFET M22, the twenty-third MOSFET M23, and the twenty-fourth MOSFET M24 are all P-channel MOSFETs. The fifth MOSFET M5, the sixth MOSFET M6, the seventh MOSFET M7, the eighth MOSFET M8, the ninth MOSFET M9, the tenth MOSFET M10, and the eleventh MOSFET M11 are all N-channel MOSFETs. In other embodiments, the P-channel and N-channel MOSFETs can be interchanged, or PNP or NPN transistors can be used instead.

[0097] In summary, the working principle of this invention is as follows:

[0098] When the common-mode voltage signal in the input signals IN+ and IN- changes rapidly from low to high, the current on the fifth MOSFET M5 will decrease. At this time, the current on the sixth MOSFET M6 will decrease to less than the reference current provided by the third current source ib3. The drain voltage of the sixth MOSFET M6 will be pulled up to a high level signal. At this time, the drive signal is a high level signal, and the first input terminal B1 of the feedback control circuit 40 receives the high level signal.

[0099] When the common-mode voltage signal in the input signals IN+ and IN- changes rapidly from high to low, the current on the fifth MOSFET M5 will increase. At this time, the current on the seventh MOSFET will increase to a level greater than the reference current provided by the fourth current source ib4. The drain voltage of the seventh MOSFET will be pulled down to a low level signal. The drive signal at this time is a low level signal. The low level signal is converted into a high level signal by the first inverter INV1 and input to the second input terminal B2 of the feedback control circuit 40.

[0100] The feedback control circuit 40 starts operating upon receiving a high-level drive signal, positively feeding back the comparison signal OP output by the comparator unit CMP to the input of the comparator unit CMP, thereby latching the output comparison signal OP. It should be noted that the feedback control circuit 40 can also positively feed back the comparison signal OP to any differential node at the front end of the comparator CMP, such as the input of the differential amplifier AMP or the drain of the first MOSFET M1 and the second MOSFET M2. Therefore, when the common-mode voltage signal in the input signals IN+ and IN- exhibits a large swing, the output will remain unchanged until internal stabilization is achieved. After this, the feedback control circuit 40 stops operating, and the comparator unit CMP performs normal comparison output.

[0101] Combination Figure 4 and Figure 5 As shown, the present invention also discloses a method for stabilizing a comparator output signal, comprising:

[0102] S1. The sampling circuit 20 acquires the input signals IN+ and IN- and outputs the sampled current signal based on the input signals IN+ and IN-.

[0103] S2. The driving circuit 30 captures the sampled current signal and outputs one or more driving signals based on the sampled current signal.

[0104] In this embodiment, the driving circuit 30 compares the sampled current signal with the corresponding reference current and outputs one or more driving signals based on the comparison result. If a sudden change occurs in the common-mode voltage signal in the input signals IN+ and IN-, it will cause a change in the sampled current signal. The driving circuit 30 captures the changed sampled current signal and compares it with the corresponding reference current, outputting the corresponding driving signal based on the comparison result. The common-mode voltage signal in the input signal is the lower voltage or average voltage in the differential input signal.

[0105] In other embodiments, the sampling current signal can be captured by the driving circuit and one or more driving signals can be output with a delay.

[0106] In this embodiment, the reference current includes a first reference current and a second reference current. If the common-mode voltage signal in the input signals IN+ and IN- changes abruptly, causing the sampled current signal to be less than the first reference current or greater than the second reference current, the drive signals output respectively will trigger the comparison signal output by the comparator unit CMP to be positively fed back to the input terminal of the comparator unit CMP, so as to latch the comparison signal.

[0107] In other embodiments, the driving circuit 30 can be pulled up to output a high-level signal or pulled down to output a low-level signal (e.g., by setting pull-up resistors and pull-down resistors). When the sampled current signal changes, the internal current of the driving circuit 30 changes, so that the driving signal becomes a high-level signal or a low-level signal due to the pull-up or pull-down.

[0108] S3. The drive signal is received through the feedback control circuit 40. When the common-mode voltage signal in the input signals IN+ and IN- changes abruptly, causing the drive signal to change, the comparison signal output by the comparator unit CMP is positively fed back to the input terminal of the comparator unit CMP to latch the comparison signal.

[0109] Example 2

[0110] like Figure 6As shown, based on Embodiment 1, the feedback control circuit 40 in this embodiment further includes a twelfth MOSFET M12. The twelfth MOSFET M12 is an N-channel MOSFET. In other embodiments, the twelfth MOSFET M12 can also be a P-channel MOSFET, or replaced by a PNP or NPN transistor. The twelfth MOSFET M12 is connected between the sources of the eighth MOSFET M8 and the ninth MOSFET M9 and the drains of the tenth MOSFET M10 and the eleventh MOSFET M11. The gate of the twelfth MOSFET M12 forms the control terminal C1 for receiving control signals.

[0111] Specifically, the drain of the twelfth MOSFET M12 is connected to the source of the eighth MOSFET M8 and the ninth MOSFET M9, and the source of the twelfth MOSFET M12 is connected to the drain of the tenth MOSFET M10 and the eleventh MOSFET M11.

[0112] The bias current is provided by the twelfth MOSFET M12. When the feedback control circuit 40 is not working, there is no current in the twelfth MOSFET M12. When the feedback control circuit 40 is working, the maximum current in the feedback control circuit 40 is limited by the twelfth MOSFET M12.

[0113] Example 3

[0114] like Figure 7 As shown, based on Embodiment 1, the feedback control circuit 40 in this embodiment further includes a twelfth MOSFET M12. The twelfth MOSFET M12 is an N-channel MOSFET. In other embodiments, the twelfth MOSFET M12 can also be a P-channel MOSFET, or replaced by a PNP or NPN transistor. The twelfth MOSFET M12 is connected between the source of the tenth MOSFET M10 and the eleventh MOSFET M11 and ground. The gate of the twelfth MOSFET M12 forms the control terminal C1 for receiving control signals.

[0115] Specifically, the drain of the twelfth MOSFET M12 is connected to the source of the tenth MOSFET M10 and the eleventh MOSFET M11, and the source of the twelfth MOSFET M12 is connected to ground.

[0116] Example 4

[0117] like Figure 8As shown, based on Embodiment 1, the feedback control circuit 40 in this embodiment further includes a twelfth MOSFET M12 and a thirteenth MOSFET M13. The twelfth MOSFET M12 and the thirteenth MOSFET M13 are N-channel MOSFETs. In other embodiments, the twelfth MOSFET M12 and the thirteenth MOSFET M13 can also be P-channel MOSFETs or replaced with PNP or NPN transistors. In this case, the gates of the twelfth MOSFET M12 and the thirteenth MOSFET M13 form the control terminal C1 for receiving control signals.

[0118] Bias current is provided by the twelfth MOSFET M12 and the thirteenth MOSFET M13. When the feedback control circuit 40 is not working, there is no current in the twelfth MOSFET M12 and the thirteenth MOSFET M13. When the feedback control circuit 40 is working, the maximum current in the feedback control circuit 40 is limited by the twelfth MOSFET M12 and the thirteenth MOSFET M13.

[0119] The source of the twelfth MOSFET M12 is connected to the drain of the eighth MOSFET M8, and the source of the thirteenth MOSFET M13 is connected to the drain of the ninth MOSFET M9. The sources of the eighth MOSFET M8 and the ninth MOSFET M9 are connected. The drains of the tenth MOSFET M10 and the eleventh MOSFET M11 are connected and simultaneously connected to the sources of the eighth MOSFET M8 and the ninth MOSFET M9. The sources of the tenth MOSFET M10 and the eleventh MOSFET M11 are connected and grounded. The output of the third inverter INV3 is connected to the gate of the ninth MOSFET M9.

[0120] At this time, the gate of the tenth MOSFET M10 forms the first input terminal B1 of the feedback control circuit 40, and the gate of the eleventh MOSFET M11 forms the second input terminal B2 of the feedback control circuit 40. The gate of the eighth MOSFET M8 and the input terminal of the third inverter INV3 form the third input terminal A1 of the feedback control circuit 40. The drain of the twelfth MOSFET M12 forms the first output terminal Q1 of the feedback control circuit 40, and the drain of the thirteenth MOSFET M13 forms the second output terminal Q2 of the feedback control circuit 40.

[0121] Example 5

[0122] like Figure 9As shown, in this embodiment, the feedback control circuit 40 includes an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, an eleventh MOSFET M11, a fourteenth MOSFET M14, a fifteenth MOSFET M15, and a third inverter INV3. The eighth MOSFET M8, ninth MOSFET M9, tenth MOSFET M10, eleventh MOSFET M11, fourteenth MOSFET M14, and fifteenth MOSFET M15 are N-channel MOSFETs. In other embodiments, the eighth MOSFET M8, ninth MOSFET M9, tenth MOSFET M10, eleventh MOSFET M11, fourteenth MOSFET M14, and fifteenth MOSFET M15 can also be P-channel MOSFETs or replaced with PNP or NPN transistors.

[0123] The sources of the eighth MOSFET M8 and the ninth MOSFET M9 are connected to ground. The drains of the tenth MOSFET M10 and the eleventh MOSFET M11 are connected, and their sources are connected to the drain of the eighth MOSFET M8. The drains of the fourteenth MOSFET M14 and the fifteenth MOSFET M15 are connected, and their sources are connected to the drain of the ninth MOSFET M9. The gates of the eleventh MOSFET M11 and the fourteenth MOSFET M14 are connected. The output of the third inverter INV3 is connected to the gate of the ninth MOSFET M9.

[0124] At this time, the gates of the tenth MOSFET M10 and the fifteenth MOSFET M15 form the first input terminal B1 of the feedback control circuit 40, and the gates of the eleventh MOSFET M11 and the fourteenth MOSFET M14 form the second input terminal B2 of the feedback control circuit 40. The gate of the eighth MOSFET M8 and the input terminal of the third inverter INV3 form the third input terminal A1 of the feedback control circuit 40. The drains of the tenth MOSFET M10 and the eleventh MOSFET M11 form the first output terminal Q1 of the feedback control circuit 40, and the drains of the fourteenth MOSFET M14 and the fifteenth MOSFET M15 form the second output terminal Q2 of the feedback control circuit 40.

[0125] Example 6

[0126] like Figure 10As shown, based on Embodiment 5, the feedback control circuit 40 in this embodiment further includes a sixteenth MOSFET M16. The sixteenth MOSFET M16 is an N-channel MOSFET. In other embodiments, the sixteenth MOSFET M16 can also be a P-channel MOSFET, or replaced by a PNP or NPN transistor. The drain of the sixteenth MOSFET M16 is connected to the source of the ninth MOSFET M9, and the source of the sixteenth MOSFET M16 is connected to ground. The gate of the sixteenth MOSFET M16 forms the control terminal C1 for receiving control signals.

[0127] In addition, such as Figure 11 As shown, several transistor pairs can be connected in series between the sources of the eighth MOSFET M8 and the ninth MOSFET M9 and the drain of the sixteenth MOSFET M16. These transistor pairs include the eighteenth MOSFET M18 and the nineteenth MOSFET M19. The drains of the eighteenth MOSFET M18 and the nineteenth MOSFET M19 are connected to the sources of the eighth MOSFET M8 and the ninth MOSFET M9. The sources of the eighteenth MOSFET M18 and the nineteenth MOSFET M19 are connected to the drain of the sixteenth MOSFET M16. The gate of the eighteenth MOSFET M18 can serve as the first input terminal B1 of the feedback control circuit 40, and the gate of the nineteenth MOSFET M19 can serve as the second input terminal B2 of the feedback control circuit 40.

[0128] The number of transistor pairs formed by connecting the eighteenth MOSFET M18 and the nineteenth MOSFET M19 is not specifically limited, and can be increased or decreased as needed between the source of the eighth MOSFET M8 and the ninth MOSFET M9 and the drain of the sixteenth MOSFET M16.

[0129] Example 7

[0130] like Figure 12 As shown, based on Embodiment 5, the feedback control circuit 40 in this embodiment further includes a sixteenth MOSFET M16 and a seventeenth MOSFET M17. The sixteenth MOSFET M16 and the seventeenth MOSFET M17 are N-channel MOSFETs. In other embodiments, the sixteenth MOSFET M16 and the seventeenth MOSFET M17 can also be P-channel MOSFETs or replaced with PNP or NPN transistors.

[0131] The drain of the sixteenth MOSFET M16 is connected to the source of the tenth MOSFET M10 and the eleventh MOSFET M11, and the source of the sixteenth MOSFET M16 is connected to the drain of the eighth MOSFET M8. The drain of the seventeenth MOSFET M17 is connected to the source of the fourteenth MOSFET M14 and the fifteenth MOSFET M15, and the source of the seventeenth MOSFET M17 is connected to the drain of the ninth MOSFET M9. The gates of the sixteenth MOSFET M16 and the seventeenth MOSFET M17 form the control terminal C1 for receiving control signals.

[0132] Example 8

[0133] like Figure 13 As shown, based on Embodiment 5, the feedback control circuit 40 in this embodiment further includes a sixteenth MOSFET M16 and a seventeenth MOSFET M17. The sixteenth MOSFET M16 and the seventeenth MOSFET M17 are N-channel MOSFETs. In other embodiments, the sixteenth MOSFET M16 and the seventeenth MOSFET M17 can also be P-channel MOSFETs or replaced with PNP or NPN transistors.

[0134] The source of the sixteenth MOSFET M16 is connected to the drains of the tenth MOSFET M10 and the eleventh MOSFET M11, and the source of the seventeenth MOSFET M17 is connected to the drains of the fourteenth MOSFET M14 and the fifteenth MOSFET M15. At this time, the drain of the sixteenth MOSFET M16 forms the first output terminal Q1 of the feedback control circuit 40, and the drain of the seventeenth MOSFET M17 forms the second output terminal Q2 of the feedback control circuit 40. The gates of the sixteenth MOSFET M16 and the seventeenth MOSFET M17 form the control terminal C1 for receiving control signals.

[0135] Example 9

[0136] like Figure 14 and Figure 15 As shown, based on Embodiment 1, the driving circuit 30 in this embodiment further includes a delay unit, a 25th MOSFET M25, a 26th MOSFET M26, a third current supply unit 33, a fourth current supply unit 34, and a second inverter INV2. The driving circuit 30 captures the sampled current signal and outputs one or more driving signals after a delay. The delay unit can be constructed using several inverters, transmission gates, buffers, or RC low-pass filters, etc. Two delay units are provided: a first delay unit 35 and a second delay unit 36. In other embodiments, the number of delay units, the 25th MOSFET M25, the 26th MOSFET M26, the third current supply unit 33, and the fourth current supply unit 34 can be increased or decreased as needed.

[0137] Similar to Embodiment 1, in this embodiment, the third current providing unit 33 can be a third resistor R3 or a sixth current source ib6, and the fourth current providing unit 34 can be a fourth resistor R4 or a seventh current source ib7. In other embodiments, two or more of the first current providing unit 31, the second current providing unit 32, the third current providing unit 33, and the fourth current providing unit 34 can be connected to form a current mirror.

[0138] Specifically, the 25th MOSFET M25, the 26th MOSFET M26, the 6th MOSFET M6, the 7th MOSFET M7, and the 5th MOSFET M5 are connected in a common-gate configuration. The first terminal of the third current supply unit 33 is connected to the power supply voltage VDD, and the second terminal of the third current supply unit 33 is connected to the first terminal of the first delay unit 35 and the drain of the 25th MOSFET M25. The second terminal of the first delay unit 35 is connected to the third input terminal B3 of the feedback control circuit 40. The first terminal of the fourth current supply unit 34 is connected to the power supply voltage VDD, and the second terminal of the fourth current supply unit 34 is connected to the first terminal of the second delay unit 36 ​​and the drain of the 26th MOSFET M26. The sources of the 25th MOSFET M25 and the 26th MOSFET M26 are connected to ground, and the second terminal of the second delay unit 36 ​​is connected to the fourth input terminal B4 of the feedback control circuit 40.

[0139] In this embodiment, the first current providing unit 31 and the third current providing unit 33 are respectively used to provide the first reference current i1, and the second current providing unit 32 and the fourth current providing unit 34 are respectively used to provide the second reference current i2. In other embodiments, the number of current providing units providing the first reference current i1 and the second reference current i2 can be selected as needed.

[0140] The width-to-length ratio of the sixth MOSFET M6 is equal to that of the twenty-fifth MOSFET M25, and the width-to-length ratio of the seventh MOSFET M7 is equal to that of the twenty-sixth MOSFET M26. That is, the current flowing through the sixth MOSFET M6 is equal to the current flowing through the twenty-fifth MOSFET M25, and the current flowing through the seventh MOSFET M7 is equal to the current flowing through the twenty-sixth MOSFET M26.

[0141] In summary, the current comparison method on the branch where the first current supply unit 31 and the sixth MOS transistor M6 are located is the same as the current comparison method on the branch where the third current supply unit 33 and the twenty-fifth MOS transistor M25 are located, and the current comparison method on the branch where the second current supply unit 32 and the seventh MOS transistor M7 are located is the same as the current comparison method on the branch where the fourth current supply unit 34 and the twenty-sixth MOS transistor M26 are located.

[0142] The number of branches corresponding to the first current supply unit 31 and the sixth MOSFET M6, the third current supply unit 33 and the twenty-fifth MOSFET M25, the second current supply unit 32 and the seventh MOSFET M7, and the fourth current supply unit 34 and the twenty-sixth MOSFET M26 can be selected as needed. The number of delay units can also be increased or decreased based on the number of branches containing the third current supply unit 33 and the twenty-fifth MOSFET M25, and the number of branches containing the fourth current supply unit 34 and the twenty-sixth MOSFET M26.

[0143] In this embodiment, the second terminal of the second delay unit 36 ​​is connected to the input terminal of the second inverter INV2, and the output terminal of the second inverter INV2 is connected to the fourth input terminal B4 of the feedback control circuit 40. The function of the second inverter INV2 is the same as that of the first inverter INV1 in Embodiment 1, that is, both ensure that the feedback control circuit 40 starts working when the input drive signals are both high-level or low-level signals. In other embodiments, the first inverter INV1 and the second inverter INV2 can also be removed.

[0144] like Figure 16 As shown, due to the addition of delay units and other circuit structures, the structure of the feedback control circuit 40 in this embodiment has also been adjusted accordingly. The feedback control circuit 40 includes an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, an eleventh MOSFET M11, a twenty-seventh MOSFET M27, a twenty-eighth MOSFET M28, and a third inverter INV3.

[0145] The sources of the eighth MOSFET M8 and the ninth MOSFET M9 are connected. The drains of the tenth MOSFET M10, the eleventh MOSFET M11, the twenty-seventh MOSFET M27, and the twenty-eighth MOSFET M28 are connected and simultaneously connected to the source of the ninth MOSFET M9. The sources of the tenth MOSFET M10, the eleventh MOSFET M11, the twenty-seventh MOSFET M27, and the twenty-eighth MOSFET M28 are connected and grounded. The output of the third inverter INV3 is connected to the gate of the ninth MOSFET M9.

[0146] The gate of the tenth MOSFET M10 forms the first input terminal B1 of the feedback control circuit 40, the gate of the eleventh MOSFET M11 forms the second input terminal B2 of the feedback control circuit 40, the gate of the twenty-seventh MOSFET M27 forms the third input terminal B3 of the feedback control circuit 40, and the gate of the twenty-eighth MOSFET M28 forms the fourth input terminal B4 of the feedback control circuit 40. The first input terminal B1, the second input terminal B2, the third input terminal B3 and the fourth input terminal B4 are connected to the drive circuit 30.

[0147] The gate of the eighth MOSFET M8 and the input of the third inverter INV3 form the fifth input terminal A1 of the feedback control circuit 40, which is connected to the output of the comparator unit CMP. The drain of the eighth MOSFET M8 forms the first output terminal Q1 of the feedback control circuit 40, and the drain of the ninth MOSFET M9 forms the second output terminal Q2 of the feedback control circuit 40. The first output terminal Q1 and the second output terminal Q2 are connected to the first and second input terminals of the comparator unit CMP, respectively.

[0148] From Embodiment 1, we can understand the generation method of the drive signal for the first input terminal B1 of the input feedback control circuit 40, and the generation method of the drive signal for the second input terminal B2 of the input feedback control circuit 40. In this embodiment, the drive signal for the third input terminal B3 of the input feedback control circuit 40 is the same as the drive signal for the first input terminal B1 of the input feedback control circuit 40. The drive signal for the fourth input terminal B4 of the input feedback control circuit 40 is the same as the drive signal for the second input terminal B2 of the input feedback control circuit 40.

[0149] By setting the first delay unit 35 and the second delay unit 36, the drive signal input to the third input terminal B3 of the feedback control circuit 40 is delayed after a drive signal is input to the first input terminal B1; and the drive signal input to the fourth input terminal B4 of the feedback control circuit 40 is delayed after a drive signal is input to the second input terminal B2. That is, after the corresponding drive signal is input to the first input terminal B1 or the second input terminal B2 of the feedback control circuit 40, the feedback control circuit 10 should stop working, but because there is still a corresponding drive signal delayed input to the third input terminal B3 or the fourth input terminal B4 of the feedback control circuit 40, the feedback control circuit 40 can be turned on for a longer time, providing more sufficient setup time for the establishment of the internal operating point of the comparator of the present invention.

[0150] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A comparator, characterized in that, include: A first MOSFET and a second MOSFET form an input transistor pair, which is used to receive input signals. A comparator unit, wherein the first input terminal and the second input terminal of the comparator unit are connected to the output terminal of the input transistor pair, and the output terminal of the comparator unit outputs a comparison signal; A sampling circuit is used to acquire the input signal and output a sampled current signal based on the input signal; A driving circuit, connected to a sampling circuit, is used to receive the sampled current signal and output one or more driving signals based on the sampled current signal. The sampling circuit includes a third MOS transistor and a fourth MOS transistor. The gates of the third MOS transistor and the fourth MOS transistor are used to acquire the input signal. The drains of the third MOS transistor and the fourth MOS transistor are connected to the driving circuit. The driving circuit includes a current providing unit for providing a reference current. The driving circuit compares the sampled current signal with the corresponding reference current and outputs a driving signal based on the comparison result. as well as The feedback control circuit is connected to the output and input terminals of the comparator unit and the drive circuit. The feedback control circuit determines whether to positively feed the comparison signal to the input terminal of the comparator unit based on the drive signal to latch the comparison signal. When the common-mode voltage signal in the input signal changes abruptly from high to low or from low to high, causing the sampling current signal to decrease or increase, the feedback control circuit operates based on the drive signal control and positively feeds the comparison signal to the input terminal of the comparator unit.

2. The comparator as claimed in claim 1, characterized in that, The current providing unit is multiple, so as to provide multiple different reference currents. The driving circuit compares the sampled current signal with the corresponding reference current and outputs multiple driving signals according to the comparison result.

3. The comparator as claimed in claim 1, characterized in that, The driving circuit also includes a delay unit for delaying the output of the driving signal.

4. The comparator as described in claim 3, characterized in that, The current providing unit is multiple, and at least one of the current providing units is used to provide a first reference current, at least one of the current providing units is used to provide a second reference current, and the delay unit is used to delay the output of a drive signal generated based on the comparison result of at least one first reference current and the corresponding sampled current signal and / or delay the output of a drive signal generated based on the comparison result of at least one second reference current and the corresponding sampled current signal.

5. The comparator as claimed in claim 1, characterized in that, The sampling circuit includes a second power supply unit. The sources of the third and fourth MOS transistors are connected and connected to the first terminal of the second power supply unit. The second terminal of the second power supply unit is connected to the power supply voltage.

6. The comparator as claimed in claim 1, characterized in that, The driving circuit includes a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, a first current supply unit, and a second current supply unit; The gate and drain of the fifth MOS transistor are shorted and connected to the output terminal of the sampling circuit. The source of the fifth MOS transistor is connected to ground. The fifth, sixth, and seventh MOS transistors are connected via a common gate. The drain of the sixth MOS transistor is connected to the first terminal of the first current supply unit and the feedback control circuit. The second terminal of the first current supply unit is connected to the power supply voltage. The source of the sixth MOS transistor is connected to ground. The drain of the seventh MOS transistor is connected to the first terminal of the second current supply unit and the feedback control circuit. The second terminal of the second current supply unit is connected to the power supply voltage. The source of the seventh MOS transistor is connected to ground.

7. The comparator as claimed in claim 6, characterized in that, The driving circuit also includes a 25th MOS transistor, a 26th MOS transistor, a third current supply unit, a fourth current supply unit, a first delay unit, and a second delay unit; The 25th, 26th, and 5th MOSFETs are connected via a common gate. The first terminal of the third current supply unit is connected to the power supply voltage. The second terminal of the third current supply unit is connected to the first terminal of the first delay unit and the drain of the 25th MOSFET. The first terminal of the fourth current supply unit is connected to the power supply voltage. The second terminal of the fourth current supply unit is connected to the first terminal of the second delay unit and the drain of the 26th MOSFET. The sources of the 25th and 26th MOSFETs are connected to ground. The second terminals of the first and second delay units are connected to the feedback control circuit. The first and third current supply units are used to provide a first reference current, and the second and fourth current supply units are used to provide a second reference current. The width-to-length ratio of the 6th MOSFET is equal to that of the 25th MOSFET, and the width-to-length ratio of the 7th MOSFET is equal to that of the 26th MOSFET.

8. The comparator as claimed in claim 6, characterized in that, The first current providing unit is a first resistor or a third current source, the second current providing unit is a second resistor or a fourth current source, or the first current providing unit and the second current providing unit are connected to form a current mirror.

9. The comparator as claimed in claim 7, characterized in that, The first current providing unit is a first resistor or a third current source, the second current providing unit is a second resistor or a fourth current source, the third current providing unit is a third resistor or a sixth current source, and the fourth current providing unit is a fourth resistor or a seventh current source. Alternatively, two or more of the first current providing unit, the second current providing unit, the third current providing unit, and the fourth current providing unit may be connected together to form a current mirror.

10. The comparator as claimed in claim 6, characterized in that, The drain of the seventh MOS transistor or the drain of the sixth MOS transistor is connected to the feedback control circuit through the first inverter.

11. The comparator as claimed in claim 7, characterized in that, The drain of the seventh MOS transistor or the drain of the sixth MOS transistor is connected to the feedback control circuit through the first inverter, and the drain of the twenty-fifth MOS transistor or the twenty-sixth MOS transistor is connected to the feedback control circuit through the second inverter.

12. The comparator as claimed in claim 1, characterized in that, The feedback control circuit includes an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, and a third inverter; The sources of the eighth and ninth MOS transistors are connected, the drains of the tenth and eleventh MOS transistors are connected and simultaneously connected to the source of the ninth MOS transistor, the sources of the tenth and eleventh MOS transistors are connected and connected to ground, and the output terminal of the third inverter is connected to the gate of the ninth MOS transistor. The gate of the tenth MOS transistor forms the first input terminal of the feedback control circuit, and the gate of the eleventh MOS transistor forms the second input terminal of the feedback control circuit. The first and second input terminals are connected to the driving circuit. The gate of the eighth MOS transistor and the input terminal of the third inverter form the third input terminal of the feedback control circuit. The third input terminal is connected to the output terminal of the comparator unit. The drain of the eighth MOS transistor forms the first output terminal of the feedback control circuit, and the drain of the ninth MOS transistor forms the second output terminal of the feedback control circuit. The first and second output terminals are respectively connected to the first and second input terminals of the comparator unit.

13. The comparator as claimed in claim 12, characterized in that, The feedback control circuit further includes a twelfth MOSFET or a twelfth MOSFET and a thirteenth MOSFET; If the feedback control circuit includes a twelfth MOSFET, the drain of the twelfth MOSFET is connected to the source of the eighth MOSFET, and the source of the twelfth MOSFET is connected to the drain of the tenth MOSFET; or The drain of the twelfth MOS transistor is connected to the source of the tenth MOS transistor, and the source of the twelfth MOS transistor is connected to ground. If the feedback control circuit includes a twelfth MOS transistor and a thirteenth MOS transistor, the source of the twelfth MOS transistor is connected to the drain of the eighth MOS transistor, the source of the thirteenth MOS transistor is connected to the drain of the ninth MOS transistor, the sources of the eighth MOS transistor and the ninth MOS transistor are connected, the drains of the tenth MOS transistor and the eleventh MOS transistor are connected and simultaneously connected to the source of the ninth MOS transistor, the sources of the tenth MOS transistor and the eleventh MOS transistor are connected and connected to ground, and the output terminal of the third inverter is connected to the gate of the ninth MOS transistor; The gate of the tenth MOS transistor forms the first input terminal of the feedback control circuit, the gate of the eleventh MOS transistor forms the second input terminal of the feedback control circuit, the gate of the eighth MOS transistor and the input terminal of the third inverter form the third input terminal of the feedback control circuit, the drain of the twelfth MOS transistor forms the first output terminal of the feedback control circuit, and the drain of the thirteenth MOS transistor forms the second output terminal of the feedback control circuit.

14. The comparator as claimed in claim 1, characterized in that, The feedback control circuit includes an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, a fourteenth MOSFET, a fifteenth MOSFET, and a third inverter; The sources of the eighth and ninth MOS transistors are connected to ground. The drains of the tenth and eleventh MOS transistors are connected. The sources of the tenth and eleventh MOS transistors are connected and connected to the drain of the eighth MOS transistor. The drains of the fourteenth and fifteenth MOS transistors are connected. The sources of the fourteenth and fifteenth MOS transistors are connected and connected to the drain of the ninth MOS transistor. The gates of the eleventh and fourteenth MOS transistors are connected. The output of the third inverter is connected to the gate of the ninth MOS transistor. The gates of the tenth and fifteenth MOS transistors form the first input terminal of the feedback control circuit, and the gates of the eleventh and fourteenth MOS transistors form the second input terminal of the feedback control circuit. The first and second input terminals are connected to the driving circuit. The gate of the eighth MOS transistor and the input terminal of the third inverter form the third input terminal of the feedback control circuit. The third input terminal is connected to the output terminal of the comparator unit. The drains of the tenth and eleventh MOS transistors form the first output terminal of the feedback control circuit, and the drains of the fourteenth and fifteenth MOS transistors form the second output terminal of the feedback control circuit. The first and second output terminals are respectively connected to the first and second input terminals of the comparator unit.

15. The comparator as claimed in claim 14, characterized in that, The feedback control circuit further includes a sixteenth MOSFET or a sixteenth MOSFET and a seventeenth MOSFET; If the feedback control circuit further includes a sixteenth MOS transistor, the drain of the sixteenth MOS transistor is connected to the source of the ninth MOS transistor, and the source of the sixteenth MOS transistor is connected to ground; If the feedback control circuit further includes a sixteenth MOS transistor and a seventeenth MOS transistor, the drain of the sixteenth MOS transistor is connected to the source of the tenth MOS transistor, the source of the sixteenth MOS transistor is connected to the drain of the eighth MOS transistor, the drain of the seventeenth MOS transistor is connected to the source of the fourteenth MOS transistor, and the source of the seventeenth MOS transistor is connected to the drain of the ninth MOS transistor. or The source of the sixteenth MOS transistor is connected to the drain of the tenth MOS transistor, the source of the seventeenth MOS transistor is connected to the drain of the fourteenth MOS transistor, the drain of the sixteenth MOS transistor forms the first output terminal of the feedback control circuit, and the drain of the seventeenth MOS transistor forms the second output terminal of the feedback control circuit.

16. The comparator as claimed in claim 15, characterized in that, If the feedback control circuit further includes a sixteenth MOS transistor, a plurality of transistor pairs are connected in series between the drain of the sixteenth MOS transistor and the source of the ninth MOS transistor and the eighth MOS transistor. The transistor pairs include an eighteenth MOS transistor and a nineteenth MOS transistor. The drains of the eighteenth MOS transistor and the nineteenth MOS transistor are connected and connected to the source of the ninth MOS transistor. The sources of the eighteenth MOS transistor and the nineteenth MOS transistor are connected and connected to the drain of the sixteenth MOS transistor.

17. The comparator as claimed in claim 3, characterized in that, The feedback control circuit includes an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, a twenty-seventh MOSFET, a twenty-eighth MOSFET, and a third inverter; The sources of the eighth and ninth MOS transistors are connected, the drains of the tenth, eleventh, twenty-seventh, and twenty-eighth MOS transistors are connected and simultaneously connected to the source of the ninth MOS transistor, the sources of the tenth, eleventh, twenty-seventh, and twenty-eighth MOS transistors are connected and connected to ground, and the output terminal of the third inverter is connected to the gate of the ninth MOS transistor. The gate of the tenth MOS transistor forms the first input terminal of the feedback control circuit, the gate of the eleventh MOS transistor forms the second input terminal of the feedback control circuit, the gate of the twenty-seventh MOS transistor forms the third input terminal of the feedback control circuit, and the gate of the twenty-eighth MOS transistor forms the fourth input terminal of the feedback control circuit. The first, second, third, and fourth input terminals are connected to the driving circuit. The gate of the eighth MOS transistor and the input terminal of the third inverter form the fifth input terminal of the feedback control circuit. The fifth input terminal is connected to the output terminal of the comparator unit. The drain of the eighth MOS transistor forms the first output terminal of the feedback control circuit, and the drain of the ninth MOS transistor forms the second output terminal of the feedback control circuit. The first and second output terminals are respectively connected to the first and second input terminals of the comparator unit.

18. The comparator as claimed in claim 5, characterized in that, The comparator also includes a twentieth MOSFET, a twenty-first MOSFET, a twenty-second MOSFET, a twenty-third MOSFET, a twenty-fourth MOSFET, and a fifth current source; The source of the twentieth MOSFET is connected to the sources of the third and fourth MOSFETs. The gate and drain of the twentieth MOSFET are connected and connected to the source of the twentieth MOSFET. The gate and drain of the twentieth MOSFET are connected and connected to the first terminal of the fifth current source. The second terminal of the fifth current source is grounded. The source of the twentieth MOSFET is connected to the drain of the third MOSFET. The drain of the twentieth MOSFET is connected to the driving circuit. The gates of the twentieth, twentieth, twentieth, and twenty-fourth MOSFETs are connected. The source of the twentieth MOSFET is connected to the drain of the first MOSFET. The source of the twenty-fourth MOSFET is connected to the drain of the second MOSFET. The drains of the twentieth and twenty-fourth MOSFETs are respectively connected to the first and second input terminals of the comparator unit.

19. The comparator as claimed in claim 1, characterized in that, The comparator further includes a differential amplifier, the first input terminal and the second input terminal of the differential amplifier are respectively connected to the drains of the first MOSFET and the second MOSFET, the first output terminal and the second output terminal of the differential amplifier are respectively connected to the first input terminal and the second input terminal of the comparator unit, and the first input terminal and the second input terminal of the differential amplifier, or the first output terminal and the second output terminal of the differential amplifier, or the drains of the first MOSFET and the second MOSFET are connected to a feedback control circuit.

20. A method for stabilizing a comparator output signal, characterized in that, Based on the comparator as described in any one of claims 1 to 19, the stabilization method includes: The input signal is acquired by a sampling circuit and a sampled current signal is output based on the input signal. The driving circuit captures the sampled current signal and outputs one or more driving signals. The drive signal is received through the feedback control circuit. When the common-mode voltage signal in the input signal changes abruptly, causing the drive signal to change, the comparison signal output by the comparator unit is positively fed back to the input of the comparator unit to latch the comparison signal.

21. The method for stabilizing the comparator output signal as described in claim 20, characterized in that, The driving circuit compares the sampled current signal with the corresponding reference current and outputs one or more driving signals based on the comparison result.

22. The method for stabilizing the comparator output signal as described in claim 20, characterized in that, The driving circuit captures the sampled current signal and outputs one or more driving signals after a delay.

23. The method for stabilizing the comparator output signal as described in claim 21, characterized in that, The reference current includes a first reference current and a second reference current. When the sampled current signal is less than the first reference current or the sampled current is greater than the second reference current, the output drive signal triggers the comparison signal output by the comparator unit to be positively fed back to the input of the comparator unit in order to latch the comparison signal.

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