Common mode sampling circuit

Abstract

The application discloses a common-mode sampling circuit, which comprises a first differential input stage and a second differential input stage, a differential transistor pair in the first differential input stage is realized by a normal threshold process, a differential transistor pair in the second differential input stage is realized by a negative threshold process, when the common-mode voltage of a first input signal and a second input signal is large, the first differential input stage is in a working state, when the common-mode voltage of the first input signal and the second input signal is small, the second differential input stage is in the working state, so that sampling of the full common-mode range of the input signal can be realized.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to a common-mode sampling circuit. Background Technology

[0002] Figure 1 A schematic circuit diagram of a common-mode sampling circuit according to the prior art is shown. The common-mode sampling circuit 100 samples the common-mode voltage of a first input signal Inn and a second input signal Inp, and converts this common-mode voltage into a current for output. To achieve voltage sampling across the entire common-mode range, the existing common-mode sampling circuit 100 generally employs complementary input pairs of NMOS and PMOS input transistors connected in parallel. For example... Figure 1 As shown, PMOS transistors Mp1 and Mp2 constitute the first input stage, and NMOS transistors Mn1 and Mn2 constitute the second input stage. The current source Ip is connected in series with the first input stage between the positive power supply terminal Vdd and the common-mode output terminal Outp. The second input stage and the current source In are connected in series between the common-mode output terminal Outn and the negative power supply terminal Vss.

[0003] The common-mode sampling circuit 100 operates in three phases: when the common-mode voltage of the first input signal Inn and the second input signal Inp is close to the negative power supply Vss, NMOS transistors Mn1 and Mn2 are turned off, and PMOS transistors Mp1 and Mp2 are turned on, and the PMOS input transistor pair is in the sampling phase; when the common-mode voltage of the first input signal Inn and the second input signal Inp is close to the positive power supply Vdd, PMOS transistors Mp1 and Mp2 are turned off, and NMOS transistors Mn1 and Mn2 are turned on, and the NMOS input transistor pair is in the sampling phase; when the common-mode voltage of the first input signal Inn and the second input signal Inp is in the intermediate phase, both the PMOS input transistor pair and the NMOS input transistor pair are in the sampling phase.

[0004] First, the common-mode sampling circuit 100 requires two current sources, Ip and In, resulting in high power consumption and making it unsuitable for power-sensitive circuits. Furthermore, the gain of the common-mode sampling circuit 100 differs across its three operating ranges, causing the gain, bandwidth, and compensation of subsequent circuits to not change linearly, thus reducing circuit stability. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a common-mode sampling circuit that, while meeting the sampling requirements of the full common-mode range, only requires one current source, which can greatly reduce the power consumption of the circuit and is beneficial for application in power-sensitive circuits.

[0006] According to an embodiment of the present invention, a common-mode sampling circuit is provided for sampling the common-mode voltage of a first input signal and a second input signal, comprising: a first differential input stage connected in series with a first switch between a common-mode output terminal and a third node; and a second differential input stage connected in series with a second switch between the common-mode output terminal and the third node, wherein a first turn-on threshold of the differential transistor pair in the first differential input stage is greater than a second turn-on threshold of the second differential transistor pair; when the common-mode voltage of the first input signal and the second input signal is greater than the first turn-on threshold, the first switch is turned on, the second switch is turned off, and the first differential input stage is in an operating state; when the common-mode voltage of the first input signal and the second input signal is less than the first turn-on threshold but greater than the second turn-on threshold, the second switch is turned on, and the second differential input stage is in an operating state.

[0007] Optionally, the differential transistor pairs in the second differential input stage are implemented using a negative threshold process.

[0008] Optionally, the common-mode sampling circuit further includes a current source connected between the third node and the negative power supply terminal, used to provide bias current for the first differential input stage and the second differential input stage.

[0009] Optionally, the common-mode sampling circuit further includes a constant voltage bias circuit, connected to the control terminals of the first switch and the second switch, for providing a constant voltage bias to the first switch and the second switch.

[0010] Optionally, the first differential input stage includes a first transistor and a second transistor, wherein the first terminals of the first transistor and the second transistor are connected to the common-mode output terminal, the control terminal of the first transistor receives the first input signal, the control terminal of the second transistor receives the second input signal, and the second terminals of the first transistor and the second transistor are connected to the first terminal of the first switch at a first node.

[0011] Optionally, the second differential input stage includes a third transistor and a fourth transistor, wherein the first terminals of the third transistor and the fourth transistor are connected to the common-mode output terminal, the control terminal of the third transistor receives the first input signal, the control terminal of the fourth transistor receives the second input signal, and the second terminals of the third transistor and the fourth transistor are connected to the first terminal of the second switch at the second node.

[0012] Optionally, the constant voltage bias circuit includes a first constant voltage source and a second constant voltage source. The first constant voltage source is connected to the control terminal of the first switch. The second terminal of the first constant voltage source is connected to the first terminal of the second constant voltage source. The second terminal of the second constant voltage source is connected to the negative power supply terminal. The intermediate node between the first constant voltage source and the second constant voltage source is connected to the control terminal of the second switch.

[0013] Optionally, the first transistor, the second transistor, the third transistor, and the fourth transistor are all NMOS transistors.

[0014] Optionally, the first switch and the second switch are selected from one of electromechanical switches, metal-oxide-semiconductor field-effect transistors, complementary metal-oxide-semiconductor transistors, or bipolar transistors.

[0015] The common-mode sampling circuit provided in this embodiment of the invention includes a first differential input stage and a second differential input stage. The differential transistor pairs in the first differential input stage are implemented using a normal threshold process, and the differential transistor pairs in the second differential input stage are implemented using a negative threshold process. When the common-mode voltage of the first input signal and the second input signal is large, the first differential input stage is in the working state; when the common-mode voltage of the first input signal and the second input signal is small, the second differential input stage is in the working state, thereby enabling sampling of the entire common-mode range of the input signal.

[0016] Furthermore, the differential transistor pairs in the first differential input stage and the differential transistor pairs in the second differential input stage are implemented using transistors of the same conductivity type. Therefore, only one current source is needed to provide the bias current, which helps to reduce the overall power consumption of the circuit and is beneficial for application in power-sensitive circuits.

[0017] Furthermore, the differential transistor pairs in the second differential input stage only experience leakage and gain reduction at high temperatures. By cooperating with the normal transistor pairs in the first differential input stage, the gain reduction phenomenon can be achieved only in a very small area, ensuring that the gain, bandwidth, and compensation of subsequent circuits change linearly, which can meet the needs of specific circuits. Attached Figure Description

[0018] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings.

[0019] Figure 1 A schematic circuit diagram of a common-mode sampling circuit according to the prior art is shown;

[0020] Figure 2 A schematic circuit diagram of a common-mode sampling circuit according to an embodiment of the present invention is shown. Detailed Implementation

[0021] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown in the drawings.

[0022] Many specific details of the invention, such as the structure, materials, dimensions, processing methods, and techniques of the components, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0023] It should be understood that, in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by an electrical or electromagnetic link. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to the other element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0024] In this application, the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal, and a control terminal. When the MOSFET is in the on state, current flows from the first terminal to the second terminal. The first terminal, second terminal, and control terminal of the PMOS transistor are the source, drain, and gate, respectively, and the first terminal, second terminal, and control terminal of the NMOS transistor are the drain, source, and gate, respectively.

[0025] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0026] Figure 2 A schematic circuit diagram of a common-mode sampling circuit according to an embodiment of the present invention is shown. Figure 2 As shown, the common-mode sampling circuit 200 includes a first differential input stage 210, a second differential input stage 220, a constant voltage bias circuit 230, a first switch SW1, a second switch SW2, and a current source In.

[0027] The first differential input stage 210 includes NMOS transistors Mn1 and Mn2, each having a first turn-on threshold. NMOS transistors Mn1 and Mn2 form a differential transistor pair, with the first terminals of Mn1 and Mn2 connected to the common-mode output terminal Outn, and the substrates of Mn1 and Mn2 connected to their second terminals. The control terminals of Mn1 and Mn2 are used to receive the first input signal Inn and the second input signal Inp, respectively.

[0028] The second differential input stage 220 includes NMOS transistors Mv1 and Mv2, each having a second turn-on threshold. NMOS transistors Mv1 and Mv2 form a differential transistor pair, with the first terminals of Mv1 and Mv2 connected to the common-mode output terminal Outn, and the substrates of Mv1 and Mv2 connected to the second terminals. The control terminals of Mv1 and Mv2 receive a first input signal Inn and a second input signal Inp, respectively.

[0029] The first terminal of the first switch SW1 is connected to the second terminals of NMOS transistors Mn1 and Mn2 at the first node A. The second terminal of the first switch SW1 is connected to the first terminal of the current source In at the third node C. The control terminal of the first switch SW1 is connected to the constant voltage bias circuit 230. The second terminal of the current source In is connected to the negative power supply terminal Vss.

[0030] The first terminal of the second switch SW2 is connected to the second terminals of NMOS transistors Mv1 and Mv2 at the second node B. The second terminal of the second switch SW2 is connected to the third node C. The control terminal of the second switch SW2 is connected to the constant voltage bias circuit 230.

[0031] The constant voltage bias circuit 230 includes constant voltage sources V1 and V2. The first terminal of constant voltage source V1 is connected to the control terminal of the first switch SW1, the second terminal of constant voltage source V1 is connected to the first terminal of constant voltage source V2, and the second terminal of constant voltage source V2 is connected to the negative power supply terminal Vss. The intermediate node between constant voltage sources V1 and V2 is connected to the control terminal of the second switch SW2.

[0032] Furthermore, NMOS transistors Mv1 and Mv2 are implemented using a negative threshold process, which means that NMOS transistors Mv1 and Mv2 can still work normally when the gate voltage is negative.

[0033] When the common-mode voltage of the first input signal Inn and the second input signal Inp is greater than the first turn-on threshold of NMOS transistors Mn1 and Mn2, the first switch SW1 is turned on and the second switch SW2 is turned off by adjusting the voltage values ​​of constant voltage sources V1 and V2. At this time, the first differential input stage 210 is in working state, and NMOS transistors Mn1 and Mn2 are in the sampling stage. When the common-mode voltage of the first input signal Inn and the second input signal Inp is less than the first turn-on threshold of NMOS transistors Mn1 and Mn2, NMOS transistors Mn1 and Mn2 are turned off. At this time, the voltage of the third node C will gradually decrease. When the potential of the third node C decreases to the point that the gate-source voltage of the second switch SW2 is greater than the turn-on threshold of the second switch SW2, the second switch SW2 is turned on, the second differential input stage 220 is in working state, and NMOS transistors Mv1 and Mv2 are in the sampling stage, thereby completing the sampling of the entire common-mode range of the differential input signal.

[0034] Furthermore, the first switch 230 and the second switch 240 are selected from one of the following: electromechanical switches, metal-oxide-semiconductor field-effect transistors, complementary metal-oxide-semiconductor transistors, or bipolar transistors. Even further, the first switch 230 and the second switch 240 are NMOS transistors.

[0035] In summary, the common-mode sampling circuit provided in this embodiment of the invention includes a first differential input stage and a second differential input stage. The differential transistor pairs in the first differential input stage are implemented using a normal threshold process, while the differential transistor pairs in the second differential input stage are implemented using a negative threshold process. When the common-mode voltage of the first input signal and the second input signal is large, the first differential input stage is in the working state; when the common-mode voltage of the first input signal and the second input signal is small, the second differential input stage is in the working state, thereby enabling sampling of the entire common-mode range of the input signal.

[0036] Furthermore, the differential transistor pairs in the first differential input stage and the differential transistor pairs in the second differential input stage are implemented using transistors of the same conductivity type. Therefore, only one current source is needed to provide the bias current, which helps to reduce the overall power consumption of the circuit and is beneficial for application in power-sensitive circuits.

[0037] Furthermore, the differential transistor pairs in the second differential input stage only experience leakage and gain reduction at high temperatures. By cooperating with the normal transistor pairs in the first differential input stage, the gain reduction phenomenon can be achieved only in a very small area, ensuring that the gain, bandwidth, and compensation of subsequent circuits change linearly, which can meet the needs of specific circuits.

[0038] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0039] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A common-mode sampling circuit for sampling the common-mode voltage of a first input signal and a second input signal, comprising: The first differential input stage includes a first transistor and a second transistor. The first terminals of the first transistor and the second transistor are connected to the common-mode output terminal. The control terminal of the first transistor receives the first input signal, and the control terminal of the second transistor receives the second input signal. The second terminals of the first transistor and the second transistor are connected to the first terminal of the first switch at a first node, and the second terminal of the first switch is connected to a third node. The second differential input stage includes a third transistor and a fourth transistor. The first terminals of the third and fourth transistors are connected to the common-mode output terminal. The control terminal of the third transistor receives the first input signal, and the control terminal of the fourth transistor receives the second input signal. The second terminals of the third and fourth transistors are connected to the first terminal of a second switch at a second node. The second terminal of the second switch is connected to the third node. Wherein, the first turn-on threshold of the differential transistor pair in the first differential input stage is greater than the second turn-on threshold of the differential transistor pair in the second differential input stage. When the common-mode voltage of the first input signal and the second input signal is greater than the first turn-on threshold, the first switch is turned on and the second switch is turned off, and the first differential input stage is in the working state. When the common-mode voltage of the first input signal and the second input signal is less than the first turn-on threshold but greater than the second turn-on threshold, the second switch is turned on, and the second differential input stage is in the working state.

2. The common-mode sampling circuit according to claim 1, wherein, The differential transistor pairs in the second differential input stage are implemented using a negative threshold process.

3. The common-mode sampling circuit according to claim 1, wherein, Also includes: A current source, connected between the third node and the negative power supply terminal, is used to provide bias current for the first differential input stage and the second differential input stage.

4. The common-mode sampling circuit according to claim 1, wherein, It also includes a constant voltage bias circuit, which is connected to the control terminals of the first switch and the second switch, and is used to provide a constant voltage bias for the first switch and the second switch.

5. The common-mode sampling circuit according to claim 4, wherein, The constant voltage bias circuit includes a first constant voltage source and a second constant voltage source. The first constant voltage source is connected to the control terminal of the first switch, the second terminal of the first constant voltage source is connected to the first terminal of the second constant voltage source, the second terminal of the second constant voltage source is connected to the negative power supply terminal, and the intermediate node between the first constant voltage source and the second constant voltage source is connected to the control terminal of the second switch.

6. The common-mode sampling circuit according to claim 1, wherein, The first transistor, the second transistor, the third transistor, and the fourth transistor are all NMOS transistors.

7. The common-mode sampling circuit according to claim 1, wherein, The first switch and the second switch are selected from one of electromechanical switches, metal-oxide-semiconductor field-effect transistors, complementary metal-oxide-semiconductor transistors, or bipolar transistors.

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