Semiconductor structure and operating circuit

Abstract

The present application provides a semiconductor structure and an operating circuit. The semiconductor structure includes a substrate, a first well region, a second well region, a first doped region, a second doped region, a gate electrode layer, an insulating layer, a field plate and an adjustable circuit. The first well region and the second well region are formed on the substrate. The first doped region is formed in the first well region. The second doped region is formed in the second well region. The gate electrode layer is located on the substrate. The gate electrode layer, the first doped region and the second doped region constitute a transistor. The insulating layer is located on the substrate and overlaps part of the gate electrode layer. The field plate overlaps the insulating layer and the gate electrode layer. The adjustable circuit provides a first short circuit path between the field plate and the gate electrode layer, or a second short circuit path between the field plate and the first doped region. The semiconductor structure of the present application has a lower on-resistance, so that the power consumption of the semiconductor structure is lower, and the switching speed of the semiconductor structure is faster.

Description

Technical Field

[0001] This invention relates to a semiconductor structure, and more particularly to a high-voltage semiconductor device. Background Technology

[0002] High-voltage semiconductor devices utilize gate voltage to create a channel and control the current flowing between the source and drain. In traditional high-voltage semiconductor devices, the channel length of the transistor must be extended to prevent the punch-through effect between the source and drain. However, this increases the device size, leading to an increase in wafer area and raising the on-resistance (Ron) of the transistor. Summary of the Invention

[0003] An embodiment of the present invention provides a semiconductor structure including a substrate, a first well region, a second well region, a first doped region, a second doped region, a gate electrode layer, an insulating layer, a field plate, and an adjustable circuit. The substrate has a first conductivity type. The first well region is formed on the substrate and has the first conductivity type. The second well region is formed on the substrate and has a second conductivity type. The first doped region is formed in the first well region and has the second conductivity type. The second doped region is formed in the second well region and has the second conductivity type. The gate electrode layer is located on the substrate. The gate electrode layer, the first doped region, and the second doped region constitute a transistor. The insulating layer is located on the substrate and partially overlaps the gate electrode layer. The field plate overlaps the insulating layer and the gate electrode layer. The adjustable circuit is coupled to the field plate, the gate electrode layer, and the first doped region, and provides a first short-circuit path between the field plate and the gate electrode layer, or a second short-circuit path between the field plate and the first doped region.

[0004] The present invention further provides an operating circuit, including a first transistor, a first adjustable circuit, a second transistor, and a second adjustable circuit. The first transistor is formed in a first region of a substrate and includes a first field plate contact, a first gate contact, and a first source contact. The first adjustable circuit forms a first short-circuit path between the first field plate contact and the first gate contact, or forms a second short-circuit path between the first field plate contact and the first source contact. The second transistor is formed in a second region of the substrate and includes a second field plate contact, a second gate contact, and a second source contact. The second adjustable circuit forms a third short-circuit path between the second field plate contact and the second gate contact, or forms a fourth short-circuit path between the second field plate contact and the second source contact.

[0005] The present invention provides a semiconductor structure with low power consumption due to the low on-resistance of the metal-to-gate transistors. Simultaneously, the fast switching speed is achieved because the low gate charge value of the metal-to-source transistors in the semiconductor structure results in high-speed switching. Since the figure of merit (FOM) is proportional to the product of the on-resistance and the gate charge value, the substrate in this semiconductor structure exhibits a superior figure of merit. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of the semiconductor structure of the present invention.

[0007] Figure 2 This is a schematic diagram of the equivalent circuit of the semiconductor structure of the present invention.

[0008] Figure 3 This is a possible embodiment of the adjustable circuit of the present invention.

[0009] Figure 4 This is another schematic diagram of the semiconductor structure of the present invention.

[0010] Figure label:

[0011] 100, 400: Semiconductor structure

[0012] 101, 410: Substrate

[0013] 111, 112: Trap Zone

[0014] 121-123: Doped region

[0015] 140: Gate structure

[0016] 150, 170: Insulation layer

[0017] 160: Field board

[0018] 131, 132: Trench isolation materials

[0019] 141: Gate dielectric layer

[0020] 142: Gate electrode layer

[0021] GP: gap

[0022] 102, 420, 430, 440, 450: Transistors

[0023] 190: Line Layer

[0024] 191: Adjustable circuit

[0025] L1~L4: Internal wiring

[0026] E1~E5: Electrodes

[0027] 181-185: Through-hole

[0028] 210: Contact pad

[0029] 220: Control circuit

[0030] SIG: Control signal

[0031] SW1, SW2: Switching circuits

[0032] GND: Grounding voltage

[0033] T1~T4: Switches

[0034] IV1, IV2: Inverters

[0035] SV1, SV2: Inverted signals

[0036] VP: High Operating Voltage

[0037] 411~414: Area

[0038] F1~F4: Field plate contact end

[0039] S1~S4: Source contact terminals

[0040] G1~G4: Gate contact terminals

[0041] D1~D4: Drain contact terminals

[0042] B1~B4: Base contact terminals Detailed Implementation

[0043] To make the objectives, features, and advantages of this invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. This specification provides different embodiments to illustrate the technical features of different implementations of the invention. The configuration of the elements in the embodiments is for illustrative purposes only and is not intended to limit the invention. Furthermore, the repetition of some reference numerals in the embodiments is for simplification and does not imply any correlation between different embodiments.

[0044] Figure 1 This is a schematic diagram of the semiconductor structure of the present invention. As shown, the semiconductor structure 100 includes a substrate 101, well regions 111 and 112, doped regions 121 and 122, a gate structure 140, an insulating layer 150, and a field plate 160. In this embodiment, the semiconductor structure 100 is a high-voltage semiconductor structure, for example, capable of receiving voltages above 18V.

[0045] The substrate 101 may be a semiconductor substrate, such as a silicon substrate, an epitaxial III-V substrate, a silicon-germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate. Alternatively, the substrate 101 may comprise silicon, silicon germanide (SiGe), or a semiconductor material of a III-V element. In this embodiment, the substrate 101 has a first conductivity type. In other embodiments, a buried layer (BL) 120, a first well region 111, and a second well region 112 are disposed within the substrate 101.

[0046] Well regions 111 and 112 are formed in substrate 101, wherein well region 111 has a first conductivity type. Well region 112 is formed in well region 111, wherein well region 112 has a second conductivity type. The first conductivity type and the second conductivity type are different. In one embodiment, buried layer 120, for example, having the second conductivity type (e.g., P-type), is located between well region 111 and substrate 101, and its doping concentration is preferably higher than that of well region 112. In a possible embodiment, well region 111 surrounds well region 112.

[0047] A doped region 121 is formed in the well region 111 and has a second conductivity type. In this embodiment, the doping concentration of the doped region 121 is higher than that of the well region 112. In some embodiments, the semiconductor structure 100 further includes a doped region 123. The doped region 123 is formed in the well region 111 and has a first conductivity type. The doping concentration of the doped region 123 is higher than that of the well region 111. In other embodiments, a shallow trench isolation process (STI) can be used to form a trench separator 131 in the well region 111 to separate the doped regions 121 and 123. However, the doped regions 121 and 123 can also be separated in any other suitable manner, for example, a field oxide layer can be formed using conventional zone oxidation (LOCOS) to isolate the doped regions 121 and 123 in the well region 111.

[0048] A doped region 122 is formed within the well region 112 and has a second conductivity type. In this embodiment, the doping concentration of the doped region 122 is higher than that of the well region 112. In some embodiments, a trench separator 132 is formed in the well regions 112 and 111 using a shallow trench isolation process to separate the well region 111 from the doped region 122. In other embodiments, a field oxide layer can also be formed between the well region 111 and the doped region 123 using a zone oxidation method.

[0049] A gate structure 140 is located on the substrate 101 and overlaps with portions of the well regions 111 and 112. The gate structure 140 includes a gate dielectric layer 141 and a gate electrode layer 142. In this embodiment, the gate dielectric layer 141 is formed on a portion of the surface of the well regions 111 and 112. The gate dielectric layer 141 may include, for example, oxides, nitrides, oxynitrides, oxycarbide, combinations thereof, or a high-k dielectric material (high-k, dielectric constant greater than 8). Next, the gate electrode layer 142 is formed on the gate dielectric layer 141. In some embodiments, the gate electrode layer 142 includes silicon or polysilicon. The gate electrode layer 142 is preferably doped to reduce its sheet resistance. In other embodiments, the gate electrode layer 142 includes amorphous silicon. Furthermore, the surface of the gate electrode layer 142 may also have metal nitrides or metal silicides. In some embodiments, a gap GP exists between the gate structure 140 and the doped region 122. In other words, the gate structure 140 does not contact the doped region 122.

[0050] In this embodiment, gate electrode layer 142, doped regions 121 and 122 constitute a transistor 102. The present invention does not limit the type of transistor 102. In one possible embodiment, transistor 102 is a laterally diffused metal-oxide-semiconductor (LDMOS) transistor. In this example, gate electrode layer 142 serves as the gate of transistor 102, doped region 121 serves as the source of transistor 102, and doped region 122 serves as the drain of transistor 102. In other embodiments, transistor 102 further includes a doped region 123. In this example, doped region 123 serves as the bulk of transistor 102.

[0051] An insulating layer 150 is located on the substrate 101 and overlaps a portion of the gate structure 140. In this embodiment, the insulating layer 150 overlaps with and directly contacts a portion of the doped region 122, a portion of the well region 122, and a portion of the gate electrode layer 142. The material of the insulating layer 150 includes oxides, nitrides, oxynitrides, low dielectric constant materials, any other suitable insulating materials, or combinations thereof, and can be formed by the chemical vapor deposition process described above. In some embodiments, the insulating layer 150 and the gate dielectric layer 141 are formed in different processes, but this is not intended to limit the invention. In other embodiments, the insulating layer 150 and the gate dielectric layer 141 are formed in the same process (e.g., chemical vapor deposition). In this embodiment, the thickness of the insulating layer 150 is greater than the thickness of the gate dielectric layer 141.

[0052] The field plate 160 is located above the insulating layer 150 and overlaps with the doped region 122 and the gate dielectric layer 141. In this embodiment, the field plate 160 directly contacts and overlaps with the insulating layer 150. The field plate 160 is used to homogenize the distribution of the electric field. In one possible embodiment, the field plate 160 is a conductor, and its material includes metal or silicon.

[0053] In some embodiments, the semiconductor structure 100 further includes an insulating layer 170. The insulating layer 170 covers well regions 111 and 112, doped regions 121-123, trench separators 131 and 132, gate structure 140, insulating layer 150, and field plate 160. Therefore, the field plate 160 and the gate dielectric layer 141 are located within the same insulating layer. In some embodiments, insulating layers 150 and 170 are formed using different processes. For example, after forming the insulating layer 150, the field plate 160 is formed on the insulating layer 150 before the insulating layer 170 is formed.

[0054] In some embodiments, the semiconductor structure 100 further includes a circuit layer 190. The circuit layer 190 has a tunable circuit 191, interconnects L1-L3, and electrodes E1-E5. Electrode E1 is electrically connected to the doped region 122 through a through hole 181. In one possible embodiment, electrode E1 serves as the drain contact of transistor 102. Electrode E2 is electrically connected to the field plate 160 through the through hole 182. In one possible embodiment, electrode E2 serves as the field plate contact of transistor 102. Electrode E3 is electrically connected to the gate electrode layer 142 through a through hole 183. In one possible embodiment, electrode E3 serves as the gate contact of transistor 102. Electrode E4 is electrically connected to the doped region 121 through a through hole 184. In one possible embodiment, electrode E4 serves as the source contact of transistor 102. Electrode E5 is electrically connected to the doped region 123 through a through hole 185. In one possible embodiment, electrode E5 serves as the base contact of transistor 102.

[0055] In this embodiment, the adjustable circuit 191 is electrically connected to electrodes E2-E4 via interconnects L1-L3. In this example, the adjustable circuit 191 may provide a first short-circuit path between the field plate 160 and the gate electrode layer 142, or a second short-circuit path between the field plate 160 and the doped region 121. When the field plate 160 and the gate electrode layer 142 have a first short-circuit path, the potential of the field plate 160 will be the same as the potential of the gate electrode layer 142. At this time, the transistor 102 has a first on-resistance (Ron) and a first gate charge value (Qg). When the field plate 160 and the doped region 121 have a second short-circuit path, the potential of the field plate 160 will be the same as the voltage of the doped region 121. At this time, the transistor 102 has a second on-resistance and a second gate charge value. In this example, the first on-resistance is less than the second on-resistance, and the second gate charge value is less than the first gate charge value.

[0056] This invention does not limit the architecture of the adjustable circuit 191. In one possible embodiment, the adjustable circuit 191, according to a control signal (not shown), either activates a first short-circuit path between electrodes E2 and E3, or activates a second short-circuit path between electrodes E2 and E4. When the adjustable circuit 191 activates the first short-circuit path between electrodes E2 and E3, the potential of the field plate 160 is equal to the potential of the gate electrode layer 142. When the adjustable circuit 191 activates the second short-circuit path between electrodes E2 and E4, the potential of the field plate 160 is equal to the potential of the doped region 121.

[0057] In other embodiments, the circuit layer 190 further includes an interconnect L4. The interconnect L4 may be electrically connected to electrodes E4 and E5. In some embodiments, the material of the interconnects L1 to L4 may include copper, aluminum, tungsten, doped polysilicon, any other suitable conductive material, or a combination thereof.

[0058] Figure 2 This is a schematic diagram of the equivalent circuit of the semiconductor structure 100 of the present invention. As shown, the semiconductor structure 100 includes a transistor 102 and an adjustable circuit 191. The doped region 122 of the transistor 102 is electrically connected to an electrode E1 (or drain contact). In this embodiment, the electrode E1 is coupled to a contact pad 210. The contact pad 210 is used to receive a control voltage. In one possible embodiment, the control voltage is approximately 40V.

[0059] The field plate 160 of transistor 102 is electrically connected to electrode E2 (or field plate contact). Electrode E2 is coupled to adjustable circuit 191. The gate electrode layer 142 of transistor 102 is electrically connected to electrode E3 (or gate contact). Electrode E3 is coupled to a control circuit 220. The control circuit 220 provides a gate voltage to electrode E3. By controlling the potentials of electrodes E1, E3, and E4, transistor 102 can be turned on or off. The doped region 121 of transistor 102 is electrically connected to electrode E4 (or source contact). Electrode E4 receives a ground voltage GND. The doped region 123 of transistor 102 is electrically connected to electrode E5 (or base contact). Electrode E5 is coupled to electrode E4.

[0060] In this embodiment, the adjustable circuit 191 may, according to a control signal SIG, activate a first short-circuit path between electrodes E2 and E3, or activate a second short-circuit path between electrodes E2 and E4. The present invention does not limit the source of the control signal SIG. In one possible embodiment, the control signal SIG may originate from a one-time programmable (OTP) memory circuit or a multiple-time programmable (MTP) memory circuit.

[0061] Furthermore, the present invention does not limit the architecture of the adjustable circuit 191. Any circuit that can provide two different short-circuit paths according to a control signal can be used as the adjustable circuit 191. In one possible embodiment, the adjustable circuit 191 includes switching circuits SW1 and SW2. Switching circuit SW1 is coupled between electrodes E2 and E3 to form a first short-circuit path between electrodes E2 and E3. Switching circuit SW2 is coupled between electrodes E2 and E4 to provide a second short-circuit path between electrodes E2 and E4. In some embodiments, the adjustable circuit 191 does not simultaneously conduct the first and second short-circuit paths.

[0062] For example, when the control signal SIG equals a first level (e.g., high level), switch circuit SW1 is turned on, and switch circuit SW2 is turned off. In this example, because switch circuit SW1 is turned on, there is a first short-circuit path between electrodes E2 and E3. Therefore, electrodes E2 and E3 have the same potential. At this time, transistor 102 has a first on-resistance and a first gate charge value. In this example, because switch circuit SW2 is not turned on, switch circuit SW2 does not provide a second short-circuit path between electrodes E2 and E4.

[0063] When the control signal SIG equals a second level (e.g., low level), switch circuit SW1 is not turned on, and switch circuit SW2 is turned on. In this example, because switch circuit SW2 is turned on, there is a second short-circuit path between electrodes E2 and E4. Therefore, the potential of electrode E2 is equal to the potential of electrode E4, and transistor 102 has a second on-resistance and a second gate charge value. In one possible embodiment, the first on-resistance is less than the second on-resistance, and the second gate charge value is less than the first gate charge value. When there is a second short-circuit path between electrodes E2 and E4, switch circuit SW1 is not turned on. Therefore, switch circuit SW1 does not form a first short-circuit path between electrodes E2 and E3.

[0064] In this embodiment, switching circuits SW1 and SW2 receive the same control signal, but this is not intended to limit the invention. In other embodiments, switching circuits SW1 and SW2 receive different control signals. In this example, when switching circuit SW1 provides a first short-circuit path between electrodes E2 and E3, switching circuit SW2 does not provide a second short-circuit path between electrodes E2 and E4. When switching circuit SW2 provides a second short-circuit path between electrodes E2 and E4, switching circuit SW1 does not provide a first short-circuit path between electrodes E2 and E3.

[0065] Figure 3 This is a possible embodiment of the adjustable circuit of the present invention. In this embodiment, the switching circuit SW1 includes an inverter IV1, switches T1 and T2. Inverter IV1 inverts the control signal SIG to generate an inverted signal SV1. Switch T1 is coupled between electrodes E2 and E3 and receives the inverted signal SV1. Switch T2 is coupled between electrodes E2 and E3 and receives the control signal SIG. The present invention does not limit the types of switches T1 and T2. In one possible embodiment, switch T1 is an N-type transistor and switch T2 is a P-type transistor. In this example, the base of switch T1 receives a ground voltage GND, and the base of switch T2 receives a high operating voltage VP. When the control signal SIG is equal to a first level (e.g., a high level), switches T1 and T2 are not turned on. When the control signal SIG is equal to a second level (e.g., a low level), switches T1 and T2 are turned on. Therefore, the potential of electrode E2 is equal to the potential of electrode E3.

[0066] The switching circuit SW2 includes an inverter IV2, switches T3 and T4. Inverter IV2 inverts the control signal SIG to generate an inverted signal SV2. Switch T3 is coupled between electrodes E2 and E4 and receives the control signal SIG. Switch T4 is coupled between electrodes E2 and E4 and receives the inverted signal SV2. This invention does not limit the types of switches T3 and T4. In one possible embodiment, switch T3 is an N-type transistor and switch T4 is a P-type transistor. In this example, the base of switch T3 receives ground voltage GND, and the base of switch T4 receives a high operating voltage VP. When the control signal SIG equals a first level (e.g., high level), switches T3 and T4 are turned on. Therefore, the potential of electrode E2 is equal to the potential of electrode E4. When the control signal SIG equals a second level (e.g., low level), switches T3 and T4 are not turned on.

[0067] Figure 4 This is another schematic diagram of the semiconductor structure of the present invention. The semiconductor structure 400 includes a substrate 410. The substrate 410 has regions 411 to 414. The present invention does not limit the number of regions. In other embodiments, the substrate 410 is divided into more or fewer regions. In this embodiment, the structure of each of regions 411 to 414 is similar to... Figure 1 The semiconductor structure 100 shown is shown.

[0068] Each of regions 411–414 has multiple transistors. For ease of explanation, Figure 4 Only transistors 420, 430, 440, and 450 are shown. Transistors 420, 430, 440, and 450 are located in regions 411–414, respectively. In one possible embodiment, transistors 420, 430, 440, and 450 are silicon transistors (silicon MOS), such as laterally diffused metal-oxide-semiconductor transistors, or high electron mobility transistors (HEMTs), such as gallium nitride high electron mobility transistors. In this embodiment, since the structures of transistors 420, 430, 440, and 450 are the same as... Figure 1 The structure of transistor 102 is not described in detail here.

[0069] Transistor 420 is located in region 411 and has a gate contact G1, a drain contact D1, a source contact S1, a base contact B1, and a field plate contact F1. Transistor 420 operates according to the potentials of the gate contact G1, drain contact D1, and source contact S1. In some embodiments, the base contact B1 may be electrically connected to the source contact S1. In this example, a first adjustable circuit (not shown) provides a short-circuit path between the field plate contact F1 and the gate contact G1. Therefore, the field plate contact F1 is electrically connected to the gate contact G1, but this is not intended to limit the invention. In other embodiments, the first adjustable circuit may provide a short-circuit path between the field plate contact F1 and the source contact S1. In some embodiments, the first adjustable circuit may be located in region 411.

[0070] Transistor 430 is located in region 412 and has a gate contact G2, a drain contact D2, a source contact S2, a base contact B2, and a field plate contact F2. Transistor 430 operates according to the potentials of the gate contact G2, the drain contact D2, and the source contact S2. In some embodiments, the base contact B2 may be electrically connected to the source contact S2. In this example, a second adjustable circuit (not shown) provides a short-circuit path between the field plate contact F2 and the source contact S2. Therefore, the field plate contact F2 is electrically connected to the source contact S2. In this example, the gate charge required to turn on transistor 430 is less than the gate charge required to turn on transistor 420. Therefore, transistor 430 has a faster switching speed. In other embodiments, the second adjustable circuit may provide a short-circuit path between the field plate contact F2 and the gate contact G2. In some embodiments, the second adjustable circuit may be located in region 412.

[0071] Transistor 440 is located in region 413 and has a gate contact G3, a drain contact D3, a source contact S3, a base contact B3, and a field plate contact F3. Transistor 440 operates according to the potentials of the gate contact G3, drain contact D3, and source contact S3. In some embodiments, the base contact B3 may be electrically connected to the source contact S3. In this embodiment, a third adjustable circuit (not shown) provides a short-circuit path between the field plate contact F3 and the gate contact G3. Therefore, the field plate contact F3 is electrically connected to the gate contact G3. In this example, the on-resistance and gate charge of transistor 440 are similar to those of transistor 420. In one possible embodiment, the on-resistance of transistor 440 is less than that of transistor 430. Therefore, the power consumption of transistor 440 is lower than that of transistor 430. In other embodiments, the third adjustable circuit may provide a short-circuit path between the field plate contact F3 and the source contact S3. In some embodiments, the third adjustable circuit may be located in region 413.

[0072] Transistor 450 is located in region 414 and has a gate contact G4, a drain contact D4, a source contact S4, a base contact B4, and a field plate contact F4. Transistor 450 operates according to the potentials of the gate contact G4, drain contact D4, and source contact S4. In some embodiments, the base contact B4 may be electrically connected to the source contact S4. In this embodiment, a fourth adjustable circuit (not shown) provides a short-circuit path between the field plate contact F4 and the source contact S4. Therefore, the field plate contact F4 is electrically connected to the source contact S4. In this example, the on-resistance and gate charge of transistor 450 are similar to those of transistor 430. Additionally, the gate charge of transistor 450 is less than the gate charge of transistors 420 and 440. In other embodiments, the fourth adjustable circuit may provide a short-circuit path between the field plate contact F4 and the gate contact G4. The fourth adjustable circuit may be located in region 414.

[0073] exist Figure 4 In this substrate 410, since the substrate 410 is divided into regions 411 to 414, and the field plate contacts of the transistors in regions 411 and 413 are electrically connected to the gate contacts, approximately 50% of the transistors in the substrate 410 belong to a metal-to-gate (MTG) architecture. Furthermore, since the field plate contacts of the transistors in regions 412 and 414 are electrically connected to the source contacts, approximately 50% of the transistors in the substrate 410 belong to a metal-to-source (MTS) architecture.

[0074] Because metal-to-gate (MTG) transistors have lower on-resistance, they consume less power. Metal-to-source (MTS) transistors have lower gate charge, resulting in faster switching speeds. Since the figure of merit (FOM) is proportional to the product of on-resistance and gate charge, substrate 410 exhibits a superior FOM.

[0075] In other embodiments, only the field plate contacts of transistors in a single region may be electrically connected to the gate contacts. In this example, the number of transistors with the MTG architecture is approximately 25% of all transistors. In another possible embodiment, if the field plate contacts of transistors in three regions are electrically connected to the gate contacts, the number of transistors with the MTG architecture is approximately 75% of all transistors. If the field plate contacts of transistors in all regions (e.g., 411–414) are electrically connected to the gate contacts, the number of transistors with the MTG architecture is approximately 100% of all transistors. However, if the field plate contacts of transistors in regions 411–414 are not electrically connected to the gate contacts, the number of transistors with the MTG architecture is approximately 0% of all transistors. Therefore, users can adjust the number of transistors with MTG and MTS architectures according to their actual applications to optimize the quality factor and achieve higher device efficiency.

[0076] This invention does not limit the location of transistors with an MTG architecture. If the number of transistors with an MTG architecture is limited to 50%, transistors with an MTG architecture can be present in any two regions 411-414 by adjusting the aforementioned control signal SIG. In this embodiment, since the adjustable circuits (not shown) in regions 411 and 413 conduct the short-circuit path between the field plate contact F1 and the gate contact G1 and the short-circuit path between the field plate contact F3 and the gate contact G3 according to the control signal SIG, regions 411 and 413 have transistors with an MTG architecture. In other embodiments, if the adjustable circuits (not shown) in regions 411 and 412 conduct the short-circuit path between the field plate contact F1 and the gate contact G1 and the short-circuit path between the field plate contact F2 and the gate contact G2 according to the control signal SIG, then regions 411 and 412 have transistors with an MTG architecture. Similarly, if the adjustable circuits in regions 411 and 414 (not shown) conduct the short-circuit path between field plate contact F1 and gate contact G1 and the short-circuit path between field plate contact F4 and gate contact G4 according to the control signal SIG, then regions 411 and 414 have transistors with an MTG architecture. In other words, the MTG architecture or MTS architecture can be dynamically adjusted according to the different control signals SIG of the corresponding adjustable circuits.

[0077] In some embodiments, the short-circuit paths in each region are not fixed. For example, when the number of transistors in the MTG architecture is limited to 50%, the adjustable circuits (not shown) in regions 411 and 413 activate the short-circuit path between the field plate contact F1 and the gate contact G1, and the short-circuit path between the field plate contact F3 and the gate contact G3, according to the control signal SIG. However, when the number of transistors in the MTG architecture is changed to be limited to 25%, the adjustable circuit of one of regions 411 and 413 activates the short-circuit path between the field plate contact and the gate contact according to the control signal SIG. In this example, the adjustable circuit of the other region 411 and 413 may activate the short-circuit path between the field plate contact and the source contact according to the control signal SIG. In some embodiments, the adjustable circuit of the other region 411 and 413 may not activate the short-circuit path between the field plate contact and the source contact, and the short-circuit path between the field plate contact and the gate contact.

[0078] Unless otherwise defined, all terms herein (including technical and scientific terms) are as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, unless expressly stated otherwise, definitions of terms in general dictionaries should be interpreted as consistent with their meaning in the context of their respective technical fields, and not as idealized or overly formal expressions. While terms such as "first," "second," etc., may be used to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another.

[0079] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make modifications and refinements without departing from the spirit and scope of the invention. For example, the systems, apparatus, or methods described in the embodiments of the present invention can be implemented in physical embodiments using hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having a first conductivity type; A first well region is formed on the substrate and has the first conductivity type; A second well region is formed on the substrate and has a second conductivity type, which is complementary to the first conductivity type; A first doped region is formed in the first well region and has the second conductivity type; A second doped region is formed in the second well region and has the second conductivity type; A gate electrode layer is located on the substrate, wherein the gate electrode layer, the first doped region, and the second doped region constitute a transistor; An insulating layer is located on the substrate and overlaps a portion of the gate electrode layer; A plate, overlapping the insulating layer and the gate electrode layer; as well as An adjustable circuit is coupled to the field plate, the gate electrode layer and the first doped region, and is configured to selectively provide a first short-circuit path between the field plate and the gate electrode layer, or a second short-circuit path between the field plate and the first doped region, according to a control signal.

2. The semiconductor structure as described in claim 1, characterized in that, The adjustable circuit includes: A first switching circuit is coupled between the field plate and the gate electrode layer; and A second switching circuit is coupled between the field plate and the first doped region.

3. The semiconductor structure as described in claim 2, characterized in that, The first switching circuit includes: A first inverter inverts a control signal to generate a first inverted signal; A first switch, coupled between the field plate and the gate electrode layer, and receiving the first inverted signal; and A second switch is coupled between the field plate and the gate electrode layer and receives the control signal.

4. The semiconductor structure as described in claim 3, characterized in that, The second switching circuit includes: A second inverter inverts the control signal to generate a second inverted signal; A third switch, coupled between the field plate and the first doped region, and receiving the control signal; and A fourth switch is coupled between the field plate and the first doped region and receives the second inverted signal.

5. The semiconductor structure as described in claim 4, characterized in that, The first and third switches are both N-type transistors, and the second and fourth switches are both P-type transistors.

6. The semiconductor structure as described in claim 1, characterized in that, The transistor is a laterally diffused metal-oxide-semiconductor transistor.

7. An operating circuit, characterized in that, include: A first transistor is formed in a first region of a substrate and includes a first field plate contact, a first gate contact, and a first source contact. A first adjustable circuit forms a first short-circuit path between the first field plate contact terminal and the first gate contact terminal, or forms a second short-circuit path between the first field plate contact terminal and the first source contact terminal. A second transistor is formed in a second region of the substrate and includes a second field plate contact, a second gate contact, and a second source contact; and A second adjustable circuit forms a third short-circuit path between the second field plate contact terminal and the second gate contact terminal, or forms a fourth short-circuit path between the second field plate contact terminal and the second source contact terminal.

8. The operating circuit as described in claim 7, characterized in that, The first adjustable circuit includes: A first switching circuit is coupled between the first field plate contact and the first gate contact; and A second switching circuit is coupled between the first field plate contact terminal and the first source contact terminal.

9. The operating circuit as described in claim 8, characterized in that, The first switching circuit includes: A first inverter inverts a control signal to generate a first inverted signal; A first switch, coupled between the first field plate contact and the first gate contact, and receiving the first inverted signal; and A second switch is coupled between the first field plate contact terminal and the first gate contact terminal, and receives the control signal.

10. The operating circuit as described in claim 9, characterized in that, The second switching circuit includes: A second inverter inverts the control signal to generate a second inverted signal; A third switch, coupled between the first field plate contact and the first source contact, and receiving the control signal; and A fourth switch is coupled between the first field plate contact terminal and the first source contact terminal, and receives the second inverted signal.

11. The operating circuit as described in claim 10, characterized in that, The first and third switches are both N-type transistors, and the second and fourth switches are both P-type transistors.

12. The operating circuit as described in claim 7, characterized in that, The first and second transistors are silicon transistors or high electron mobility transistors.

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