Semiconductor device and signal processing method thereof

Abstract

A semiconductor device and a signal processing method thereof are provided. The signal processing method of the semiconductor device includes receiving a first digital code of a first digital signal, generating a constraint vector, performing a masking operation on the first digital code using a transmission mask based on the constraint vector, and outputting a data bus inversion (DBI) bit of the transmission mask and the first digital code that is masked.

Description

Technical Field

[0001] The present invention relates to a signal processing method and apparatus for generating optimal transition codes in an environment where data signals are transmitted and received at multiple levels. Background Technology

[0002] Data transmission and reception are achieved through point-to-point or point-to-multipoint communication channels. In data transmission and reception between a host and a storage device, the amount of data that can be transmitted at a time using pulse amplitude modulation (PAM) 2-level technology is very small. Therefore, multilevel signal transmission technology can be used to increase the communication bandwidth between different types of devices. Summary of the Invention

[0003] Embodiments of the present invention provide a signal processing method and semiconductor device that do not exhibit maximum transitions in a multi-level signaling system.

[0004] Embodiments of the present invention also provide a signal processing method and semiconductor device that ensures eye margin while minimizing delay time.

[0005] An embodiment of the present invention provides a signal processing method for a semiconductor device, the method comprising: receiving a first digital code of a first digital signal; generating a constraint vector; performing a masking operation on the first digital code using a transmit mask based on the constraint vector; and outputting the masked first digital code and the data bus inversion (DBI) bits of the transmit mask.

[0006] An embodiment of the present invention provides a semiconductor device, comprising: a processing unit that outputs a first digital code; an encoder that performs a masking operation on the first digital code based on a constraint vector using a transmission mask; and a transmission circuit that transmits the masked first digital code and the DBI bits of the transmission mask, wherein the constraint vector is based on a second digital code, the second digital code being a preceding digital code relative to the first digital code.

[0007] An embodiment of the present invention provides a semiconductor device, comprising: a receiving circuit that receives a first digital code and a DBI bit; and a decoder that performs a demasking operation on the first digital code based on the DBI bit using a receiving mask, wherein the receiving mask corresponds to a constraint vector generated based on a second digital code, the second digital code being a preceding digital code relative to the first digital code. Attached Figure Description

[0008] Figure 1A semiconductor device is shown that operates according to a signal processing method based on some embodiments of the present invention.

[0009] Figure 2 This is a signal diagram showing the signals sent and received via the data bus.

[0010] Figure 3 and Figure 4 This is a diagram illustrating a signal processing method according to some embodiments of the concept of the present invention.

[0011] Figure 5 It is shown in detail Figure 1 A diagram showing an embodiment of the encoder.

[0012] Figure 6 This is a diagram illustrating a signal processing method according to some embodiments of the concept of the present invention.

[0013] Figure 7 This is a diagram illustrating some embodiments of a mask book according to the present invention.

[0014] Figure 8 This is a diagram illustrating a signal processing method according to some embodiments of the concept of the present invention.

[0015] Figure 9 It is shown in detail Figure 1 A diagram illustrating an embodiment of the decoder.

[0016] Figure 10 It is shown in detail Figure 1 A diagram of another embodiment of the encoder shown.

[0017] Figure 11 It is shown in detail Figure 1 A diagram of another embodiment of the decoder is shown.

[0018] Figure 12a and Figure 12b Several mask books are shown, illustrating some embodiments of the inventive concept.

[0019] Figure 13 This is a diagram illustrating a signal processing method according to some embodiments of the concept of the present invention.

[0020] Figure 14 This is a diagram illustrating a signal processing method according to some embodiments of the concept of the present invention.

[0021] Figure 15 This is a diagram illustrating a signal processing method according to some embodiments of the concept of the present invention.

[0022] Figure 16This is a diagram illustrating a signal processing method according to some embodiments of the concept of the present invention.

[0023] Figure 17 This is a diagram illustrating a signal processing method according to some embodiments of the concept of the present invention.

[0024] Figure 18 It shows including Figure 1 A diagram of a memory system for a semiconductor device. Detailed Implementation

[0025] In the following description, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0026] Figure 1 A semiconductor device is shown that operates according to a signal processing method based on some embodiments of the present invention. Figure 2 This is a signal diagram showing the signals sent and received via the data bus.

[0027] Semiconductor device 10 includes a transmitting device 20 and a receiving device 30. The transmitting device 20 performs data encoding symmetrical to that of the receiving device 30 on the data to be transmitted, and the receiving device 30 performs data decoding symmetrical to that of the transmitting device 20 on the data to be received. Semiconductor device 10 can utilize a multi-level signaling transmission system to encode or decode digital signals to perform data communication. According to some embodiments of the present invention, semiconductor device 10 can use pulse amplitude modulation (PAM) to encode or decode digital signals. According to some embodiments of the present invention, semiconductor device 10 can map multiple amplitude levels to Gray-coded binary codes and perform encoding or decoding. Depending on the number of bits in the digital code, PAM can be 4-level (e.g., PAM 4, 2-bit code), 8-level (e.g., PAM 8, 3-bit code), 16-level (e.g., PAM 16, 4-bit code), etc. As an example, the signal transmitted by transmitting device 20 and the signal received by receiving device 30 can be signals encoded using pulse amplitude modulation Gray code. Figure 2 The example shown illustrates the PAM4 type transmit and receive signals according to Table 1.

[0028]

[0029] 0 0 0 0mV 1 0 1 200mV 2 1 1 400mV 3 1 0 600mV

[0030] According to some embodiments of the present invention, the transmitting device 20 and the receiving device 30 may be included in each of a first device and a second device connected via a wired network. For example, the first device may include a first semiconductor device, and the second device may include a second semiconductor device. The first semiconductor device may include a first transmitting device and a first receiving device, and the second semiconductor device may include a second transmitting device and a second receiving device.

[0031] For example, when the first device sends first data to the second device, the first transmitting device in the first semiconductor device sends the first data to the second receiving device in the second semiconductor device. Conversely, when the second device sends second data to the first device, the second transmitting device in the second semiconductor device sends the second data to the first receiving device in the first semiconductor device.

[0032] The transmitting device 20 may include a processing unit 21, an encoder 100, and a transmitting circuit 23.

[0033] Processing unit 21 generates transmission data as master data. The transmission data can be an n-bit digital signal. Encoder 100 performs encoding by mapping the n-bit transmission data to multiple multi-level signals and converting the encoded data into an m-bit digital code. Transmitting circuit 23 can output an analog signal with an amplitude level mapped to the m-bit digital code to receiving circuit 33. For example, when the digital code is 10, an analog signal with an amplitude level of 600mV can be output. In various embodiments of the present invention, n and m can be the same natural number or can be different natural numbers.

[0034] For example, such as Figure 2 As shown, when using pulse amplitude modulation types with 4 or more levels, the power of the transmitted signal increases, and crosstalk may occur on adjacent data buses, especially with signals having a wide transition range (e.g., a signal changing from a maximum voltage level of 3 to a minimum voltage level of 0, or vice versa). Furthermore, the eye diagram sclera may be insufficient due to the steepness of the voltage level transitions. Therefore, signal processing techniques with minimal delay while reducing the probability of the maximum transition can be employed to reduce crosstalk and ensure adequate eye diagram sclera.

[0035] According to some embodiments of the present invention, encoder 100 can mask the original digital signal using transmitted digital codes based on a constraint vector by employing a transmission mask. For example, the constraint vector can be a signal obtained by comparing the currently transmitted digital code (hereinafter referred to as the "current digital code") with a previously transmitted digital code (hereinafter referred to as the "previous digital code"), and indicating the location in the current digital code where the probability of occurrence of the maximum transition is high (hereinafter referred to as the location of the maximum transition code) (e.g., as will be described in detail below). Figure 6 (DQ2 and DQ3 shown).

[0036] According to some embodiments of the present invention, encoder 100 includes multiple transmission masks. Multiple transmission masks corresponding to the number of bits in the digital code can exist. For example, when the digital code is 2 bits in PAM4, four transmission masks can exist. For example, when the digital code is 3 bits in PAM8, eight transmission masks can exist.

[0037] According to some embodiments of the present invention, encoder 100 may include multiple mask books. Multiple transmit masks may be grouped and stored as a single mask book. In other words, a single mask book may include multiple transmit masks having a predetermined pattern.

[0038] For example, when encoder 100 includes a first mask book and a second mask book, the multiple transmission mask patterns included in the first mask book may be different from the multiple transmission mask patterns included in the second mask book.

[0039] According to some embodiments of the present invention, encoder 100 can select any one of a plurality of transmit masks corresponding to the constraint vector, wherein the selected transmit mask has a minimum bit count. The bit count may be the number of occurrence positions of the maximum transition code in the current digital code.

[0040] Furthermore, according to some embodiments of the present invention, encoder 100 can select any mask book from a plurality of mask books that minimizes the number of maximum transition codes, and can select any transmission mask from the selected mask book that minimizes the number of maximum transition codes.

[0041] Encoder 100 performs a masking operation on the current digital code using a selected transmit mask, and outputs the masked current digital code to transmit circuit 23. On the other hand, encoder 100 maps the mask information used for the masking operation to Data Bus Inversion (DBI) bits, and outputs the DBI bits to transmit circuit 23. Transmit circuit 23 can transmit the masked digital code (e.g., m bits) of the main data and the DBI bits of the mask information to receiving device 30.

[0042] The receiving device 30 receives the masked digital code and DBI bits.

[0043] The receiving device 30 can select a receive mask corresponding to the DBI bit. The receiving device 30 may include multiple receive masks identical to the transmit mask of the transmitting device 20. The receiving device 30 can recover the constraint vector based on the previous digital code and select any receive mask corresponding to the DBI bit and the constraint vector from among the multiple receive masks. The receiving device 30 can perform a demasking operation on the masked digital code based on the selected receive mask.

[0044] The receiving device 30 includes a receiving circuit 33, a decoder 200, and a data storage unit 31. The receiving circuit 33 can receive an analog signal with an amplitude level mapped to an m-bit digital code from the transmitting circuit 23. The decoder 200 can perform decoding to demask the m-bit digital code and convert the demasked m-bit digital code into an n-bit digital code. The data storage unit 31 can store the decoded digital code. In various embodiments of the present invention, n and m can be the same natural number or can be different natural numbers.

[0045] Figure 3 and Figure 4 This is a diagram illustrating a signal processing method according to some embodiments of the concept of the present invention.

[0046] Reference Figure 3 and Figure 4 The transmitting device 20 transmits data to the receiving device 30 in burst mode. In burst output, for example, the main data can be output in parallel via the 8-pin data bus DQ[7:0] and the DBI bits of the DBI bus. For example, Figure 4 The first burst (D11, D21, and D31 to D81) and the DBI site (D91) in Figure 3 Output at time point T1, Figure 4 The second burst (D12, D22, and D32 to D82) and the DBI site (D92) can be detected. Figure 3 Output at time point T2. Figure 4 The third burst (D13, D23, and D33 to D83) and the DBI site (D93) can be Figure 3 Output at time point T3.

[0047] For ease of explanation, in the case of PAM4 Gray encoding, it will be assumed that the data output to a single pin is a 2-bit data signal mapped to four amplitude levels.

[0048] Transmitting device 20 continuously transmits data bursts to the DBI pin via the data bus DQ[7:0] from time point T1 to time point T8. It should be noted that the digital code transmitted at time point T1 is called digital code T1, and so on. For example, based on digital codes T1 and T2, transmitting device 20 simultaneously outputs digital code T1 to the DBI pin via DQ[7:0] at time point T1 (①) and stores digital code T1 (②). Transmitting device 20 compares the digital code transmitted at time point T2 with the stored digital code T1, checks the location of the maximum transition, performs a masking operation on the digital code to be transmitted using a mask that minimizes the occurrence of the maximum transition, and outputs the mask that minimizes the occurrence of the maximum transition as digital code T2 (③). At this time, mask information is transmitted via the DBI pin so that receiving device 30 can check the mask used for transmission. Therefore, when decoding the current digital code in the receiving device 30, since only the previous digital code needs to be checked (e.g., the T1 digital code in the example above), the decoding delay can be only one unit interval (UI) (see reference). Figure 2 ,1UI).

[0049] Figure 5 It is shown in detail Figure 1 A diagram showing an embodiment of the encoder. Figure 6 This is a diagram illustrating a signal processing method according to some embodiments of the concept of the present invention. Figure 7 This is a diagram illustrating some embodiments of a mask book according to the concept of the present invention. Figure 8 This is a diagram illustrating a signal processing method according to some embodiments of the concept of the present invention. Figure 9 It is shown in detail Figure 1 A diagram illustrating an embodiment of the decoder.

[0050] Reference Figure 5 The encoder 100 may include an arithmetic unit 110, a register 120, a constraint vector calculator 130, and a mask selector 140.

[0051] The arithmetic unit 110 performs a masking operation on the current digital code R_DQ (corresponding to binary user data) output from the processing unit 21 using the selected transmission mask M, and outputs the masked current digital code R_DQ as the masked digital code E_DQ. The arithmetic unit 110 may, for example, perform an XOR operation on the current digital code R_DQ and the transmission mask M, and the masked digital code E_DQ may be the result of the XOR operation.

[0052] Register 120 stores the masked numeric code E_DQ. Register 120 stores the data used to modify the current numeric code (e.g., time point T). k The preceding digital code (e.g., time point T) to be used for masking operationsk-1 For example, in Figure 3 In the example, the T1 numeric code is stored to generate the T2 numeric code.

[0053] The constraint vector calculator 130 generates a constraint vector based on the previous digital code stored in register 120. The constraint vector may be, for example, a signal indicating the location (hereinafter, the location of the maximum transition code) where the probability of occurrence of the maximum transition is high at the current digital code by comparing the digital code to be transmitted (hereinafter referred to as the "current digital code") with the previously transmitted digital code (hereinafter referred to as the "previous digital code").

[0054] Reference Figure 6 In PAM 4 type, the signals that can be sent to a pin are 10, 11, 01, and 00, such as... Figure 2 As shown. In this case, the maximum transition occurs when the signal changes from 10 to 00 or from 00 to 10 in a given single pin. In other words, the maximum transition occurs when the voltage level changes from the maximum voltage level 3 to the minimum voltage level 0, and vice versa.

[0055] Figure 6 The items are shown in the order of output from each pin (in other words, in the order of LSB and MSB). For example, the output at pin DQ1 is output in the order of LSB 0 and MSB 1, but the actual data needs to be interpreted as "10". The following descriptions are given in the order of output.

[0056] The constraint vector calculator 130 generates a constraint vector by comparing the previously encoded data with the current data. When considering the LSB and MSB in the example shown, since data pin DQ0 changes from 00 (previously) to 01 (currently) and data pin DQ1 changes from 01 (previously) to 01 (currently), this does not correspond to a maximum transition, and in this case, the constraint vector CV can be calculated as 0.

[0057] However, in data pin DQ2, when the previous digit code is 10, if the LSB of the next digit code becomes 0, the next digit code can change to 00 or 01 depending on the MSB. Therefore, the constraint vector CV can be set to 1. In data pin DQ3, when the previous digit code is 00, if the LSB of the next digit code becomes 1, the next digit code can change to 10 or 11 depending on the MSB. Therefore, the constraint vector can be set to 1.

[0058] In other words, when receiving the LSB of the previous encoded data to the next current data input to the same data pin in a series of UI inputs, a maximum transition may or may not occur, depending on the value of the input MSB (in...). Figure 6 In the example, in the case of 10→0X in DQ2 and 00→1X in DQ3).

[0059] Therefore, the constraint vector calculator 130 can set the constraint vector CV based on the LSB of the previous digit code and the LSB of the next digit code. When calculating based on the LSB of the next digit code, the constraint vector can be set to 1 when a maximum transition is possible; and set to 0 when a maximum transition is impossible.

[0060] For example, in Gray coding of type PAM 4, the constraint vector can be calculated using the following formula 1.

[0061] CV=(LSBp^LSB0)&(~MSBp)...(1)

[0062] In Formula 1, CV is the constraint vector, LSBp is the least significant bit of the previous digit code, MSBp is the most significant bit of the previous digit code, LSB0 is the least significant bit of the current digit code, "^" is the XOR operation, "&" is the AND operation, and "~" represents the NOT operation.

[0063] The mask selector 140 can store multiple masks, select any mask based on the constraint vector CV, and output the selected mask M to the arithmetic unit 110. All masks can be sequences of mask patterns with a number of bits according to the digital code.

[0064] Reference Figure 6 and Figure 7 According to some embodiments of the present invention, when the data burst is DQ[0:3], it is assumed that the mask selector 140 includes four predetermined masks M0, M1, M2 and M3. The sequence of mask M0 can be 0000, the sequence of mask M1 can be 0101, the sequence of mask M2 can be 1010, and the sequence of mask M3 can be 1111.

[0065] Mask selector 140 can output mask information to transmitting circuit 23 via DBI pin. The DBI bit information transmitted as mask information can be the code value representing each of a plurality of masks. According to various embodiments of the present invention, the number of bits representing the code value of each mask can vary depending on the number of masks.

[0066] As an example, if there are four masks, the DBI bit information can be represented by two bits. In the example shown, for mask M0, the DBI bit information can be represented as 00; for mask M1, the DBI bit information can be represented as 01; for mask M2, the DBI bit information can be represented as 10; and for mask M3, the DBI bit information can be represented as 11. Alternatively, as another example, when there are eight masks, the DBI bit information can be represented by three bits.

[0067] Mask selector 140 can select from multiple transmit masks the mask with the smallest sum of bit counts (MT Count) calculated corresponding to the constraint vector CV and the current numeric code DQ[0:3]. In other words, the expression that minimizes the sum of bit counts (MTCount) can mean that the number of maximum transitions eliminated is the largest, and mask selector 140 can select the best transmit mask in which the maximum number of maximum transitions can be eliminated.

[0068] Reference Figure 6 , Figure 7 and Figure 8 The mask selector 140 performs a masking operation on the current numeric code DQ[0:3] and calculates the bit count with the constraint vector applied. In other words, the bit count MTCount can be calculated according to Equation 2.

[0069] MT Count=bit1count((MSB0^M)&CV)...(2)

[0070] In Formula 2, MTCount is the sum of bit counts, MSB0 is the most significant bit of the current numeric code, M is the mask, CV is the constraint vector, "^" is the XOR operation, "&" is the AND operation, "~" is the NOT operation, and bit1count() is a function that calculates and outputs the number of 1s in the binary vector of the elements input into ().

[0071] The mask selector 140 calculates the MT Count by adding the bit counts of each data pin DQ of the same UI, which is 0 for mask M0, 1 for mask M1, 1 for mask M2, and 2 for mask M3. In this case, the mask M3 with the maximum value can be selected and sent to the arithmetic unit 110, and the code value 11 can be output to the DBI pin.

[0072] Furthermore, the arithmetic unit 110 converts the MSB0 of the current digital code as in Formula 2, and outputs the converted MSB0 as a mask value. In other words, Figure 6 DQ2 00 and DQ3 10 are masked, converted, and output as follows: Figure 8The maximum transition does not occur in DQ[0:3] because the current numeric code 10 is output in DQ2 when the previous numeric code is 10, and the current numeric code 11 is output in DQ3 when the previous numeric code is 00.

[0073] Reference Figure 9 The decoder 200 may include an arithmetic unit 210, a register 220, a constraint vector calculator 230, and a mask selector 240.

[0074] The arithmetic unit 210 uses the selected receive mask M to perform a demasking operation on the masked digital code E_DQ from the receiving circuit 33, and outputs it as the demasked digital code D_DQ.

[0075] Register 220 stores the demasked numeric code D_DQ. Register 220 also stores the previous numeric code used to demask the current numeric code. For example, in... Figure 3 In the example, the decoded digital code T1 is stored to decode the digital code T2.

[0076] The constraint vector calculator 230 generates the constraint vector CV based on the previous numeric code stored in register 220. The constraint vector CV can be calculated and recovered in the same manner as the constraint vector calculator 130.

[0077] The mask selector 240 can store multiple receive masks, select any receive mask based on the constraint vector CV, and output the selected receive mask M to the arithmetic unit 210. The multiple receive masks can be a sequence having the same mask pattern as the multiple transmit masks of the transmitting device 20. The mask selector 240 can select any receive mask from the multiple receive masks based on the DBI bit received via the DBI pin, and output the selected receive mask M to the arithmetic unit 210.

[0078] Figure 10 It is shown in detail Figure 1 A diagram of another embodiment of the encoder shown. Figure 11 It is shown in detail Figure 1 A diagram of another embodiment of the decoder is shown.

[0079] Reference Figure 10 and Figure 11 The encoder 100 may also include a transmit mask selector 150. Furthermore, the decoder 200 may also include a receive mask selector 250 corresponding to the transmit mask selector 150. The transmit mask selector 150 and the receive mask selector 250 are collectively referred to as mask selectors 150 and 250.

[0080] The transmit mask selector 150 may include multiple transmit mask books. The receive mask selector 250 may include multiple receive mask books. The multiple transmit mask books and the multiple receive mask books may symmetrically include multiple masks, each mask corresponding to one DBI bit.

[0081] By including multiple mask books containing multiple masks, the semiconductor device 10 can ensure more mask sequences that minimize the probability of the occurrence of the maximum transition.

[0082] The following will be Figures 12a to 17 The text describes the operations of the mask book.

[0083] Figure 12a and Figure 12b Several mask books are shown, illustrating some embodiments of the concept according to the present invention. Figure 13 This is a diagram illustrating a signal processing method according to some embodiments of the concept of the present invention. Figure 14 This is a diagram illustrating a signal processing method according to some embodiments of the concept of the present invention. Figure 15 This is a diagram illustrating a signal processing method according to some embodiments of the concept of the present invention. Figure 16 This is a diagram illustrating a signal processing method according to some embodiments of the concept of the present invention. Figure 17 This is a diagram illustrating a signal processing method according to some embodiments of the concept of the present invention.

[0084] Reference Figure 12a and Figure 12b The send mask book selector 150 and the receive mask book selector 250 include two mask books (Mask Book 1 and Mask Book 2).

[0085] According to some embodiments of the present invention, firstly, mask book selectors 150 and 250 can select a mask book based on the constraint vector CV. Mask selectors 140 and 240 can select any mask M corresponding to the constraint vector CV from the mask book MB selected by mask book selectors 150 and 250.

[0086] When multiple mask books exist, mask book selectors 150 and 250 can select any mask book based on the pattern where the constraint vector CV is 1. Figure 12a The pattern sequence of the mask book shown is different. Figure 12bThe mask book (Mask Book 2) uses a sequence of patterns. For example, the mask patterns of masks M1 and M2 can be different from each other. Mask M1 of Mask Book 1 is used to transform the MSB of the odd-numbered pins DQ1 and DQ3 of the current numeric code, and mask M2 of Mask Book 1 is used to transform the MSB of the even-numbered pins DQ0 and DQ2 of the current numeric code. Mask M1 of Mask Book 2 is used to transform the MSB of the higher-numbered pins DQ2 and DQ3 of the current numeric code, and mask M2 of Mask Book 2 is used to transform the MSB of the lower-numbered pins DQ0 and DQ1 of the current numeric code.

[0087] Specifically, mask book selectors 150 and 250 can select the mask book based on the position of constraint vector 1 (the position where CV is 1 among all data pins). For example, if the positions where constraint vector 1 is 1 have a pattern of alternating occurrences per pin (in other words, odd-numbered pins or even-numbered pins), then the mask book can be selected. Figure 12a The mask book (Mask Book 1). For example, if the calculated constraint vector is 1 at a location with other patterns, then you can choose... Figure 12b The mask book (Mask Book 2). Then, mask selectors 140 and 150 can select any one of multiple masks from the mask book selected by mask book selectors 150 and 250 based on the constraint vector.

[0088] For example, suppose the previous numeric code and the current numeric code are as follows: Figure 13 The data is transmitted as shown. In this case, data pins DQ2 and DQ3 correspond to the cases of 10→0X and 00→1X respectively, and the constraint vector CV can be calculated as 1 based on Equation 1.

[0089] like Figure 14 and Figure 15 As shown, when using Mask Book 1, in the MSB0 of the current numeric code, when using Mask M2, since DQ2 is transmitted from 10 to 01 and DQ3 is transmitted from 00 to 11, the occurrence positions of all maximum transitions (MT Count = 0) can be eliminated.

[0090] However, as Figure 16 and Figure 17 As shown, when using Mask Book 2, in the MSB0 of the current numeric code, even if any mask is used (e.g., mask M1), since DQ2 is transmitted from 10 to 00 and DQ3 is transmitted from 00 to 11, the maximum transition occurs in DQ2 and does not eliminate the occurrence position of all maximum transitions (MT Count = 1).

[0091] Mask selectors 140 and 240 select the mask whose bit count sum is the maximum value from the selected mask book.

[0092] Figure 18 It shows including Figure 1 A diagram of a memory system for a semiconductor device.

[0093] Semiconductor device 10 may be included in memory system 1000. Specifically, memory system 1000 may include memory controller 1100 and a plurality of memory devices 1200.

[0094] The memory controller 1100 controls the operation of the memory system 1000 and controls all data exchange between the host and the storage device 1210. For example, the memory controller 1100 can control the storage device 1210 to write or read data in response to a request from the host. For example, the memory controller 1100 uses operation commands to control the operation of the storage device 1210.

[0095] According to various embodiments of the present invention, each memory device 1210 may be one of the following: phase-change random access memory (PRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FRAM) including resistive memory cells. In another embodiment of the present invention, each memory device 1210 may be dynamic random access memory (DRAM) including dynamic memory cells.

[0096] The memory controller 1100 can send commands and addresses to each of the multiple memory devices 1200 via the CA bus and CA_CLK bus according to the clock. The memory controller 1100 can send data bursts and DBI bits to each of the multiple memory devices 1200 via the DQ_CLK bus and DQ bus according to the data clock.

[0097] The memory controller 1100 may include a semiconductor device 10 as a first device, the semiconductor device 10 including both a transmitting device 20 and a receiving device 30. A plurality of memory devices 1200 (or 1210) may each include a semiconductor device 10 as a second device, the semiconductor device 10 including both a transmitting device 20 and a receiving device 30.

[0098] It should be understood that those skilled in the art will appreciate that many variations and modifications can be made to the embodiments described herein without departing from the principles of the inventive concept. Therefore, the inventive concept is not limited to the embodiments described herein.

Claims

1. A signal processing method for a semiconductor device, the method comprising: The first digital code received from the first digital signal; Generate a constraint vector, wherein the constraint vector is a signal that is based on a comparison of at least one least significant bit of the first digital code with a second digital code and indicates the position in the first digital code where the maximum transition code can occur, the second digital code being the preceding digital code relative to the first digital code; Based on the constraint vector, a masking operation is performed on the first digital code using a transmission mask; and Output the first digital code after masking and the DBI bit of the transmit mask, where DBI is the data bus inversion.

2. The signal processing method according to claim 1, wherein, The first digital code is based on Gray coding with pulse amplitude modulation at four or more levels.

3. The signal processing method according to claim 1, wherein, The transmission mask includes multiple transmission masks, the number of which corresponds to the number of bits in the first digital code.

4. The signal processing method according to claim 3, wherein, The transmission mask that performs the masking operation on the first digital code is the one among the plurality of transmission masks that maximizes the sum of the bit counts calculated corresponding to the constraint vector and the first digital code.

5. The signal processing method according to claim 4, wherein, The bit count is the number of positions in the first digital code where the maximum transition code can appear.

6. The signal processing method according to claim 3, wherein, Each of the plurality of transmission masks corresponds to a digital code that serves as the DBI bit.

7. The signal processing method according to claim 1, wherein, The transmission mask is one of a plurality of transmission masks included in the transmission mask book, and the number of the plurality of transmission masks corresponds to the number of bits of the first digital code.

8. The signal processing method according to claim 1, wherein, The semiconductor device is used as a transmitting semiconductor device, and the receiving semiconductor device communicating with the transmitting semiconductor device: receives the masked first digital code and the DBI bit; selects a receiving mask corresponding to the DBI bit; And use the selected receive mask to perform a demasking operation on the first digital code after masking.

9. The signal processing method according to claim 8, wherein, The receive mask is selected from multiple receive masks based on the DBI bit and another constraint vector generated from a third digital code, the third digital code being the preceding digital code relative to the first digital code after the masked mask.

10. A semiconductor device, comprising: Processing unit, the processing unit outputs a first digital code; An encoder that performs a masking operation on the first digital code using a transmission mask based on a constraint vector, wherein the constraint vector is a signal that is based on a comparison of at least one least significant bit of the first digital code with a second digital code and indicates the position in the first digital code where the maximum transition code can occur, the second digital code being the preceding digital code relative to the first digital code. as well as The transmitting circuit transmits the masked first digital code and the DBI bit of the transmitting mask, wherein the DBI is the data bus inversion.

11. The semiconductor device according to claim 10, wherein, The encoder includes: A register that stores the second digital code; A constraint vector calculator that generates the constraint vector based on the second digital code; A mask selector, which stores multiple transmit masks, selects and outputs the transmit mask corresponding to the constraint vector; and The arithmetic unit performs a masking operation on the first digital code using the transmit mask output from the mask selector.

12. The semiconductor device according to claim 11, wherein, The DBI bit has multiple code values ​​that correspond to the multiple transmission masks respectively.

13. The semiconductor device of claim 11, further comprising: A mask book selector stores multiple transmit mask books and selects any transmit mask book corresponding to the constraint vector.

14. The semiconductor device according to claim 13, wherein, The plurality of transmit masks includes the plurality of transmit masks, and The mask book selector selects the transmission mask book corresponding to the constraint vector from the plurality of transmission mask books, and outputs any transmission mask from the selected transmission mask book.

15. The semiconductor device according to claim 11, wherein, The transmit mask output by the mask selector is the one among the plurality of transmit masks that maximizes the sum of the bit counts calculated corresponding to the constraint vector and the first digital code.

16. A semiconductor device, comprising: The receiving circuit receives a first digital code and a DBI bit, wherein the DBI bit is the data bus inversion bit. as well as A decoder that performs a demasking operation on the first digital code based on the DBI bits using a receive mask. The receive mask corresponds to a constraint vector generated based on a second digital code, which is a preceding digital code relative to the first digital code. The constraint vector is a signal that is based on a comparison of at least one least significant bit of the first digital code with the second digital code and indicates the position in the first digital code where the maximum transition code can occur.

17. The semiconductor device according to claim 16, wherein, The decoder includes: A register that stores the second digital code; A constraint vector calculator that generates the constraint vector based on the second digital code; A mask selector, which stores multiple receive masks, selects and outputs the receive mask corresponding to the DBI bit; and The arithmetic unit performs a demasking operation on the first digital code using the received mask output from the mask selector.

18. The semiconductor device of claim 17, further comprising: A receive mask selector stores multiple receive masks and selects any receive mask corresponding to the constraint vector. The mask selector outputs the receive mask corresponding to the DBI bit in the selected receive mask book.

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