Imaging device and method of operating the same

Abstract

An imaging device and an operating method thereof are provided. The imaging device includes an image sensing circuit configured to receive an image signal from a pixel, convert the received image signal into image data, and output the image data. The imaging device includes a digital processing circuit configured to process the image data in synchronization with a digital clock. The digital processing circuit includes a digital clock generator configured to generate a digital clock. The digital clock generator is configured to disperse the digital clock in response to the image sensing circuit converting the image signal into the image data.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2021-0048135 filed on April 14, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments of the inventive concepts relate to an image forming apparatus and an operating method thereof. Background Art

[0003] Typically, an image sensor can capture a two-dimensional or three-dimensional image of an object. An image sensor can generate an image of an object using a photoelectric conversion device in response to the intensity of light reflected from the object. Recently, image sensors using complementary metal oxide semiconductors (CMOS) have been widely used. However, ordinary image sensors can cause pixel noise caused by the influence of power fluctuations. Summary of the invention

[0004] Some example embodiments of the present inventive concepts provide an image forming apparatus less affected by power fluctuation and an operating method thereof.

[0005] According to some example embodiments of the inventive concept, an imaging device may include: an image sensing circuit configured to receive an image signal from a pixel, convert the received image signal into image data, and output the image data; and a digital processing circuit configured to process the image data in synchronization with a digital clock. The digital processing circuit may include a digital clock generator configured to generate a digital clock. The digital clock generator may be configured to disperse the digital clock in response to the image sensing circuit converting the image signal into the image data.

[0006] According to some example embodiments of the inventive concept, a method of operating an imaging device may include: converting an image signal into image data based on performing a counting operation until the image signal and a ramp signal are equal; and reducing consumption of digital power using a clock dispersion scheme in response to performing the counting operation.

[0007] According to some example embodiments of the inventive concept, an imaging device includes: a pixel array having a plurality of pixels arranged in a plurality of row lines and a plurality of column lines; a row driver configured to select one of the plurality of row lines; an analog-to-digital conversion circuit configured to convert an analog signal output by the pixel array into digital data; a digital clock generator configured to generate a transmission clock for sending the digital data to an image signal processor; and

[0008] A timing controller configured to control the timing of the pixel array, the row driver, the analog-to-digital conversion circuit, and the digital clock generator. The analog-to-digital conversion circuit may include: a comparator circuit having a comparator for comparing a pixel signal output by the pixel array with a ramp signal; and a counter circuit having a counter configured to count the output of each comparator of the comparator. The digital clock generator may be configured to disperse the transmission clock in response to receiving a horizontal synchronization signal or a counter enable signal from the timing controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 are diagrams illustrating imaging devices according to some example embodiments of the inventive concept;

[0011] Figure 2 is a diagram illustrating an image sensor according to some example embodiments of the inventive concept;

[0012] Figure 3 is a diagram illustrating the timing of a digital clock of a gated clock scheme according to some example embodiments of the inventive concept;

[0013] Figure 4A and Figure 4B is a diagram illustrating a timing of a digital processing unit and a digital clock thereof implemented by a plurality of ISPs connected in series to each other according to some example embodiments of the inventive concept;

[0014] Figure 5 is a diagram illustrating a timing of a digital clock of a divided clock scheme according to some example embodiments of the inventive concept;

[0015] Fig. 6A , Figure 6B , Figure 6C and Fig.6D is a diagram illustrating a timing of a digital clock in which a digital clock is dispersedly applied to a portion of an ADC period according to some example embodiments of the inventive concept;

[0016] Figure 7 is a diagram illustrating consumption of digital current of an imaging device according to some example embodiments of the inventive concept;

[0017] Figure 8 is a diagram illustrating consumption of digital current of an imaging device according to some example embodiments of the inventive concept;

[0018] Fig.9A are diagrams illustrating imaging devices according to some example embodiments of the inventive concept, Fig. 9B is a diagram illustrating a digital processing unit implemented by a plurality of ISPs connected in parallel to each other according to some example embodiments of the inventive concept;

[0019] Fig.10 is a flowchart illustrating a method of operating an imaging device according to some example embodiments of the inventive concept;

[0020] Fig.11 is a diagram showing an electronic device having a multi-camera module; and

[0021] Fig.12 It is shown Fig.11 Illustration of a specific configuration of a camera module is shown. DETAILED DESCRIPTION

[0022] Hereinafter, some example embodiments of the inventive concept will be described as follows with reference to the accompanying drawings.

[0023] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, the element can be directly on the other element or intervening elements may also be present. Conversely, when an element is referred to as being “directly on” another element, there are no intervening elements. It will also be understood that when an element is referred to as being “on” another element, the element can be above, below, or adjacent to (e.g., horizontally adjacent to) the other element.

[0024] It will be understood that elements and / or their properties (e.g., structures, surfaces, directions, etc.) that may be referred to as "perpendicular", "parallel", "coplanar", etc. relative to other elements and / or their properties (e.g., structures, surfaces, directions, etc.) may be "perpendicular", "parallel", "coplanar", etc., or "substantially perpendicular", "substantially parallel", "substantially coplanar", etc., respectively relative to the other elements and / or their properties.

[0025] Elements and / or properties that are "substantially perpendicular" relative to other elements and / or properties (e.g., structure, surface, direction, etc.) will be understood as being "perpendicular" relative to the other elements and / or properties within the range of manufacturing tolerances and / or material tolerances, and / or having a deviation in amplitude and / or angle equal to or less than 10% (e.g., a tolerance of ±10%) from "perpendicular", etc. relative to the other elements and / or properties.

[0026] Elements and / or their properties that are "substantially parallel" relative to other elements and / or their properties (e.g., structure, surface, direction, etc.) will be understood to be "parallel" relative to the other elements and / or their properties within the range of manufacturing tolerances and / or material tolerances, and / or relative to the other elements and / or their properties having a deviation in amplitude and / or angle equal to or less than 10% from "parallel", etc. (e.g., a tolerance of ±10%).

[0027] Elements and / or their properties that are "substantially coplanar" relative to other elements and / or their properties (e.g., structure, surface, direction, etc.) will be understood to be "coplanar" relative to the other elements and / or their properties within the range of manufacturing tolerances and / or material tolerances, and / or relative to the other elements and / or their properties having a deviation in magnitude and / or angle equal to or less than 10% from "coplanarity", etc. (e.g., a tolerance of ±10%).

[0028] It will be understood that elements and / or properties stated herein may be "the same" or "equivalent" to other elements, and it will also be understood that elements and / or properties stated herein as "the same", "equal" or "equivalent" to other elements may be "the same", "equal" or "equivalent", or "substantially the same", "substantially equivalent" or "substantially equivalent" to the other elements and / or properties. Elements and / or properties that are "substantially the same", "substantially equivalent" or "substantially equivalent" to other elements and / or properties will be understood to include elements and / or properties that are the same, equal or equivalent to the other elements and / or properties within manufacturing tolerances and / or material tolerances. Elements and / or properties that are the same or substantially the same and / or equal or substantially equivalent to other elements and / or properties may be structurally equal or substantially equivalent, functionally equal or substantially equivalent, and / or compositionally equal or substantially equivalent.

[0029] It should be understood that elements and / or properties thereof described herein as being "substantially" equal and / or identical include elements and / or properties thereof having a relative difference of magnitude equal to or less than 10%. Furthermore, regardless of whether elements and / or properties thereof are modified by "substantially", it will be understood that these elements and / or properties thereof should be understood to include manufacturing or operating tolerances (e.g., ±10%) around the stated elements and / or properties thereof.

[0030] When the term "about" or "substantially" is used in connection with a numerical value in this specification, it is intended that the associated numerical value should include a tolerance of ±10% around the stated numerical value. When a range is specified, the range includes all values ​​therebetween (such as increments of 0.1%).

[0031] Figure 1 is a diagram illustrating an imaging device 10 according to some example embodiments. Figure 1, the imaging device 10 may include an image sensing unit 100 and a digital processing unit 200 .

[0032] The image sensing unit 100 (also referred to herein as an image sensing circuit, an image sensor, an image sensor circuit, etc.) may be configured to receive an image (e.g., an image signal) from one pixel and / or a plurality of pixels, to convert the received image (e.g., the received image signal) into a digital value (e.g., into image data such as image data IDATA), and to output (e.g., transmit) the converted image data IDATA to the digital processing unit 200. In addition, the image sensing unit 100 may include a timing controller 170 configured to generate timing for controlling internal components of the image sensing unit 100.

[0033] The digital processing unit 200 may be configured to receive the image data IDATA output by the image sensing unit 100, process the image data IDATA to be suitable for the human eye, and output the processed image data PDATA to an external device (e.g., a display device). In addition, the digital processing unit 200 may include and / or may be configured to implement a digital clock generator 201 and at least one image signal processor 210 (ISP). The digital processing unit (e.g., digital processing unit 200) as described herein may be interchangeably referred to as a digital processing circuit. The digital clock generator 201 may include an electronic oscillator. The digital clock generator 201 may include a resonant circuit and an amplifier.

[0034] The digital clock generator 201 may be configured to generate an optimal digital clock (DCLK) according to the analog operation of the image sensing unit 100 to control the fluctuation of the digital power that may affect the analog quality of the image sensing unit 100. For example, the digital clock generator 201 may generate a digital clock (DCLK) and / or a dispersed digital clock (DCLK) according to a specific (or alternatively, predetermined) clock timing sequence in response to a counter enable signal CNT_EN or a horizontal synchronization signal H_SYN of the timing controller 170 for performing an analog-to-digital conversion (ADC) operation of the image sensing unit 100. The specific (or alternatively, predetermined) sequence of the digital clock DCLK may control the digital power fluctuation by bypassing / gating / dividing the digital clock DCLK in the ADC operation period. The digital processing unit 200 may be configured to process the image data IDATA synchronously with the digital clock DCLK. By controlling the output of the digital clock DCLK, the pixel noise of the image sensing unit 100 may be reduced. In other words, by controlling the digital clock DCLK of the digital domain of the imaging device 10, the influence of the analog domain can be reduced.

[0035] In addition, while the image sensing unit 100 senses and outputs an image, the digital clock generator 201 may generate a digital clock (DCLK) having a plurality of clock dispersion sections (e.g., clock dispersion periods) that may be gated or divided. The starting point and the end point of each of the plurality of clock dispersion periods may be determined by user settings. For example, the digital clock generator 201 may output the digital clock DCLK in the reverse direction of the counter enable signal CNT_EN for the ADC operation of the image sensing unit 100. In some example embodiments, the clock gating period, the clock division period, or the clock division ratio between the entire starting point and the end point may be determined by user settings.

[0036] In some example embodiments, the digital clock generator 201 may disperse the digital clock DCLK in response to the image sensing unit 100 converting the image signal into the image data IDAT and / or simultaneously with the image sensing unit 100 converting the image signal into the image data IDAT. In some example embodiments, the digital clock generator 201 may output the digital clock DCLK with reference to the reference point of the horizontal period (the same reference point for determining the counter activation area of ​​the ADC operation) in response to the horizontal synchronization signal H_SYN. In some example embodiments, there may be a plurality of clock dispersion periods for controlling the dispersion of the digital clock DCLK. The position (cycle count) of the start and end of each of the plurality of clock dispersion periods may be determined by user setting. For example, each of the plurality of clock dispersion periods may start at a time earlier than the counter enable signal CNT_EN with reference to the setting area of ​​the counter enable signal CNT_EN of the ADC operation, and the end may also be determined at a time before the counter enable signal CNT_EN is cleared. In some example embodiments, the ratio between clock gating and clock division may be determined by user setting for each of the start and end of each of the plurality of clock dispersion periods.

[0037] At least one image signal processor 210 may process the image data IDATA received from the image sensing unit 100 in synchronization with the digital clock DCLK, and may output the processed data PDATA to an external entity. In some example embodiments, the image signal processor 210 may perform depth map generation, 3D modeling, panorama generation, feature point extraction, image synthesis, or image compensation (e.g., noise reduction, resolution adjustment, brightness adjustment, blurring, sharpening, or softening) on ​​the image data IDATA. In the ADC period, when the voltage value of the pixel signal is converted into a digital value, a general imaging device may cause noise elements according to the power fluctuation of the entire chip. In some exemplary embodiments, the imaging device 10 may disperse the digital clock DCLK of the digital processing unit 200 in the ADC period of the image sensing unit 100 through a gated clock scheme or a divided clock scheme, thereby reducing the influence of digital power fluctuations.

[0038] Figure 2 is a diagram illustrating an image sensing unit 100 according to some example embodiments. Figure 2 , the image sensing unit 100 may include a pixel array 110 , a row driver 120 , an analog-to-digital conversion circuit 130 , a ramp signal generator 160 , a timing controller 170 , and a buffer 180 .

[0039] The pixel array 110 may include a plurality of pixels PX arranged in a matrix form and connected to a plurality of row lines and a plurality of column lines CL. The pixels PX may be arranged according to a plurality of row lines and a plurality of column lines CL. Each of the plurality of pixels may include a light sensing device. For example, the light sensing device may include a photodiode, a phototransistor, a port gate, or a pinned photodiode. Each of the plurality of pixels may include at least one light sensing device. In some example embodiments, each of the plurality of pixels may include a plurality of light sensing devices. Each of the plurality of light sensing devices may be stacked on top of each other.

[0040] Each of the plurality of pixels may sense light using a light sensing device, and may convert the light into a pixel signal that may be an electrical signal. Each of the plurality of pixels may sense light in a specific spectral region. For example, the plurality of pixels may include a red pixel for converting light in a red spectral region into an electrical signal, a green pixel for converting light in a green spectral region into an electrical signal, and a blue pixel for converting light in a blue spectral region into an electrical signal. A color filter for transmitting light in a specific spectral region may be provided on each of the plurality of pixels.

[0041] The row driver 120 may be configured to drive the pixel array 110 in units of rows. The row driver 120 may decode a row control signal (e.g., an address signal) generated by the timing controller 170, and may select at least one of the row lines included in the pixel array 110 in response to the decoded row control signal. For example, the row driver 120 may generate a row selection signal. The row driver 120 may be understood as being configured to select one of the plurality of row lines. In addition, the pixel array 110 may output a pixel signal from a row selected by the row selection signal provided from the row driver 120. The pixel signal may include a reset signal and an image signal.

[0042] The analog-to-digital conversion circuit 130 may be configured to convert an analog pixel signal (e.g., an image signal received from a pixel PX, also referred to as an analog signal output by the pixel array 110) input from the pixel array 110 into digital data (e.g., image data IDATA) in response to an ADC enable signal ADC_EN and based on comparing the image signal with the ramp signal RAMP and performing a counting operation corresponding to the comparison result. The analog-to-digital conversion circuit 130 may include a comparator circuit 140 (CDB) and a counter circuit 150 (DBS).

[0043] The comparator circuit 140 may be configured to compare a pixel signal output by a unit pixel connected to one of the column lines CL included in the pixel array 110 (e.g., a pixel signal output by the pixel array 110) with the ramp signal RAMP. The comparator circuit 140 may include a plurality of comparators 141 arranged to correspond to each column. Each comparator 141 may be connected to the pixel array 110 and the ramp signal generator 160.

[0044] The comparator 141 (CMP) may be configured to receive a pixel signal and a ramp signal RAMP generated by the ramp signal generator 160, compare the pixel signal with the ramp signal, and output a comparison result signal to an output terminal. In addition, the comparator 141 may generate a comparison result signal to which a correlated double sampling (CDS) technique is applied. The pixel signal output by a plurality of pixels may have a deviation caused by a unique pixel characteristic of each pixel (e.g., fixed pattern noise (FPN)), or may have a deviation caused by a characteristic difference of a logic for outputting a pixel signal from a pixel PX. The correlated double sampling technique may be to calculate a reset element (or reset signal) and an image element (or image signal) for each pixel signal, and extract the difference therebetween as an effective signal element so as to compensate for the deviation between the pixel signals. The comparator 141 may output a comparison result signal to which a correlated double sampling technique is applied.

[0045] In addition, the comparator 141 may be implemented as a secondary amplifier. For example, the comparator 141 may include a first amplifier for comparing a pixel signal with a ramp signal and a second amplifier for amplifying the output of the first amplifier and outputting the amplified output. In some example embodiments, the first amplifier may operate based on a smaller amount of bias current in the auto-zero phase than in the comparison operation phase. Therefore, noise can be reduced and the input range can be increased. In some example embodiments, the second amplifier may adaptively control a current source that generates a bias current for each operation, and may generate a minimum bias current before and after the decision. Therefore, power supply fluctuations caused by the operation of the second amplifier may be prevented. In some example embodiments, the first amplifier may include a limiting circuit that connects the output terminal to a common node. The limiting circuit may prevent the voltage level of the common node from being reduced to a minimum value below which the first amplifier can operate normally, and may compensate for voltage fluctuations occurring in the output node.

[0046] In addition, the comparator circuit 140 may be configured to output a decision signal (eg, an output signal of the comparator) at different time points according to the column line groups.

[0047] The counter circuit 150 may include a plurality of counters. Each of the plurality of counters 151 (CNT) may be connected to an output terminal of the comparator 141, and may be configured to count based on the output of each comparator 141 (e.g., perform a counting operation corresponding to a result of the comparison performed by the comparator 141). The counter 151 may be configured to count the output of each of the comparators 141. The counter control signal CTCS may include a counter enable signal CNT_EN, a counter clock signal, a counter reset signal for controlling a reset operation of the plurality of counters 151, and an inversion signal for inverting an internal bit of each of the plurality of counters. The counter circuit 150 may output a comparison result signal as digital data by counting the comparison result signal according to the counter clock signal. In some example embodiments, each of the plurality of counters may be enabled by the counter enable signal CNT_EN (see Figure 1 ) to enable.

[0048] The counter 151 (CNT) may include an up / down counter or a bitwise counter. In some example embodiments, the bitwise counter may perform operations similar to those of the up / down counter. For example, the bitwise counter may perform a function of performing only up counting, and a function of inverting all bits in the counter to 1's complement when a specific signal is input. The bitwise counter may perform a reset count, and may invert and convert it to 1's complement (negative value).

[0049] The ramp signal generator 160 may be configured to generate a ramp signal (or an ADC reference voltage). The ramp signal generator 160 may operate based on a ramp control signal CTRP provided by the timing controller 170. The ramp control signal CTRP may include a ramp enable signal and a mode signal. When the ramp enable signal is enabled, the ramp signal generator 160 may generate a ramp signal RAMP having a slope determined based on the mode signal.

[0050] The timing controller 170 may be configured to control the operation or timing of the row driver 120 , the analog-to-digital conversion circuit 130 , and the ramp signal generator 160 by outputting a control signal or a clock signal to each of the row driver 120 , the analog-to-digital conversion circuit 130 , and the ramp signal generator 160 .

[0051] In some example embodiments, the timing controller 170 may transmit information about the ADC operation period of the image sensing unit 100 to the digital processing unit 200 (see Figure 1 For example, the timing controller 170 may send the ADC enable signal ADC_EN, the horizontal synchronization signal H_SYN, or the counter enable signal CNT_EN to the digital processing unit 200. The timing controller 170 may be configured to generate at least the counter enable signal CNT_EN related to the counting operation performed by the plurality of counters 151.

[0052] In addition, the timing controller 170 may generate a switching control signal provided to the comparator circuit 140 to configure the decision speed to be different according to the column line group.

[0053] The buffer 180 may be configured to temporarily store the digital data output by the analog-to-digital conversion circuit 130, and amplify and output the digital data. The buffer 180 may include a column memory block 181 (MEM) and a sense amplifier 182 (SA).

[0054] The column memory block 181 (MEM) may include a plurality of memories, each of which may temporarily store digital data output by each of the plurality of counters 151 , and may output the digital data to the sense amplifier 182 .

[0055] The sense amplifier 182 (SA) may be configured to sense and amplify the digital data output by the plurality of memories. The sense amplifier 182 may output the amplified digital data as image data IDATA.

[0056] Hereinafter, control of the dispersed digital clock (DCLK) will be described in more detail according to some example embodiments.

[0057] Figure 3is a diagram showing the timing of a digital clock DCLK of a gated clock scheme according to some example embodiments. Figure 3 As shown, the ADC enable signal ADC_EN may have a high level in the first ADC period A1 and the second ADC period A2. In the first ADC period A1, the reset voltage may be converted, and in the second ADC period A2, the pixel voltage may be converted. Therefore, the image sensing unit 100 may be configured to perform a first analog-to-digital conversion (ADC) operation corresponding to the reset voltage (e.g., in a period corresponding to the first ADC period A1), and to perform a second ADC operation corresponding to the pixel voltage (e.g., in a period corresponding to the second ADC period A2). In some example embodiments, the second ADC period A2 may be longer than the first ADC period A1.

[0058] The digital clock DCLK may be gated before / after each of the first ADC period A1 and the second ADC period A2. For example, the digital clock DCLK may include a first clock gating period G1 and a second clock gating period G2. The first clock gating period G1 may include the first ADC period A1, and the second clock gating period G2 may include the second ADC period A2. The digital clock DCLK may be normally output in periods other than the first clock gating period G1 and the second clock gating period G2. The digital clock generator 201 may be understood as being configured to gate the digital clock DCLK in the entire period or a partial period of each of the first ADC period A1 corresponding to the first ADC operation performed by the image sensing unit 100 and the second ADC period A2 corresponding to the second ADC operation performed by the image sensing unit 100.

[0059] In some example embodiments, the digital clock DCLK may be output according to a specific (or alternatively, predetermined) timing in response to the ADC enable signal ADC_EN. For example, the digital clock DCLK may determine a gating period in response to a counter enable signal for ADC operation.

[0060] like Figure 3 As shown, the image data enable signal IDATA_EN may have a high level in a specific (or alternatively, predetermined) period to indicate that the image data IDATA received from the image signal processor 210 of the digital processing unit 200 is valid. In some example embodiments, the image data enable signal IDATA_EN may be generated by the timing controller 170 (see Figure 1 ) is generated. In some example embodiments, the image data enable signal IDATA_EN may be generated in response to the ADC enable signal ADC_EN in the digital processing unit 200 (see Figure 1 ). Figure 3 During the blank period shown, the image sensing unit 100 may not perform signal reading (see Figure 1 ). The image data enable signal IDATA_EN may have a first stall period S1 and a second stall period S2. The first stall period S1 may correspond to the first clock gating period G1, and the second stall period S2 may correspond to the second clock gating period G2. In some example embodiments, in the first stall period S1 and the second stall period S2, there may be no output of the converted image data IDATA.

[0061] In some example embodiments, while the image data enable signal IDATA_EN has a high level, the processed data PDATA (see Figure 1 ) can be output to an external entity in a period other than the first stall period S1 and the second stall period S2.

[0062] The method of controlling a digital clock (DCLK) in some example embodiments may reduce digital influences in ADC operation by gating the clock in a period corresponding to ADC operation.

[0063] The converted digital data IDATA of the image sensing unit 100 may be output to a plurality of image signal processors (ISPs) connected to each other in series.

[0064] Figure 4A and Figure 4B 2 is a diagram illustrating a digital processing unit 200 implemented by a plurality of ISPs connected in series to each other and the timing of a digital clock thereof according to some example embodiments. Figure 4A , the image data IDATA may be digitally processed by four ISPs 211 to 214 (ISP1 to ISP4) connected in series to each other in synchronization with the digital clock DCLK.

[0065] exist Figure 4B, the image data enable signal IDATA_EN corresponding to each of the ISPs 211 to 214 (e.g., ISPs 211, 212, 213, and 214) may have a common first stall period S1 and a second stall period S2. In some example embodiments, each of the ISPs 211 to 214 may process received data with appropriate delays LT1 to LT3 in a period other than the first stall period S1 and the second stall period S2. To reiterate, each of the ISPs 211 to 214 may not process data processed in the first stall period S1 and the second stall period S2 corresponding to the first ADC operation and the second ADC operation, respectively. For example, the second ISP 212 may receive data processed by the first ISP 211, and may perform a specific (or alternatively, predetermined) processing operation on the received data. In some example embodiments, the image data enable signal IDATA_EN2 of the second ISP 212 may have a higher level after a first delay LT1 later than the image data enable signal IDATA_EN1 of the first ISP 211.

[0066] When a blank period in an output period for the processed data PDATA is insufficient, a divided clock scheme may be applied.

[0067] Figure 5 is a diagram illustrating the timing of a digital clock DCLK of a divided clock scheme according to some example embodiments. Figure 5 , the timing of the digital clock DCLK may have a first clock division period D1 corresponding to the first ADC period A1 and a second clock division period D2 corresponding to the second ADC period A2. In other words, the digital clock DCLK may be divided according to the first ADC period A1 and the second ADC period A2. The digital clock generator 201 may be understood as being configured to divide the digital clock DCLK in the entire period or a partial period of each of the first ADC period A1 corresponding to the first ADC operation performed by the image sensing unit 100 and the second ADC period A2 corresponding to the second ADC operation performed by the image sensing unit 100.

[0068] In some example embodiments, when determining the clock division ratio, the digital clock generator 201 may gate n-1 clocks from the start of the clock division period and may allow a single clock to be bypassed (passed). In addition, the clock may be bypassed from the end of the divided clock.

[0069] A method of controlling a digital clock (DCLK) according to some example embodiments may ensure a blank period by dividing a clock in a period corresponding to an ADC operation, and may reduce digital influence in the ADC operation.

[0070] The gated clock scheme and the divided clock scheme according to some example embodiments may be applied to only a portion of an ADC period.

[0071] Fig. 6A , Figure 6B , Figure 6C and Fig.6D is a diagram illustrating a timing of a digital clock DCLK dispersedly applied to a portion of an ADC according to some example embodiments.

[0072] Reference Fig. 6A , there may be a third clock gating period G3 corresponding to a portion of the first ADC period A1 (for example, in the stall period S3), and there may be a fourth clock gating period G4 corresponding to a portion of the second ADC period A2 (for example, in the stall period S4). For example, a period corresponding to the first 25% of the first ADC period A1 may be included in the third clock gating period G3, and a period corresponding to the first 25% of the second ADC period A2 may be included in the fourth clock gating period G4. The period corresponding to the first 25% may be a dark area that is sensitive to image quality characteristics. Therefore, as Fig. 6A As shown, the digital clock generator 201 may be configured to gate the digital clock DCLK in a partial period of each of the first ADC period A1 and the second ADC period A2 .

[0073] Reference Figure 6B , there may be a third clock division period D3 corresponding to a portion of the first ADC period A1, and there may be a fourth clock division period D4 corresponding to a portion of the second ADC period A2. For example, a period corresponding to the first 25% of the first ADC period A1 may be included in the third clock division period D3, and a period corresponding to the first 25% of the second ADC period A2 may be included in the fourth clock division period D4. Therefore, Figure 6B As shown, the digital clock generator 201 may be configured to divide the frequency of the digital clock DCLK in a partial period of each of the first ADC period A1 and the second ADC period A2.

[0074] Reference Figure 6C , there may be a fifth clock gating period G5 and a fifth clock frequency division period D5 corresponding to the first ADC period A1, and there may be a sixth clock gating period G6 and a sixth clock frequency division period D6 corresponding to the second ADC period A2. For example, the first 25% of the period corresponding to the first ADC period A1 may be the fifth clock gating period G5, and the period corresponding to the other 75% may be the fifth clock frequency division period D5. Similarly, the first 25% of the period corresponding to the second ADC period A2 may be the sixth clock gating period G6, and the period corresponding to the other 75% may be the sixth clock frequency division period D6. Figure 6C As shown, the digital clock generator 201 can be understood as being configured to enable the digital clock DCLK in a partial period (e.g., G5, G6) of each of the first ADC period A1 corresponding to the first ADC operation performed by the image sensing unit 100 and the second ADC period A2 corresponding to the second ADC operation performed by the image sensing unit 100, and to divide the digital clock DCLK in another period (e.g., D5, D6) of each of the first ADC period A1 and the second ADC period A2.

[0075] Reference Fig.6D , there may be two clock division periods G7 and D7 corresponding to the first ADC period A1, and there may be two clock division periods G8 and D8 corresponding to the second ADC period A2. For example, the first 25% period corresponding to the first ADC period A1 may be a clock division period G7 according to the first clock division ratio, and the other 75% period may be a clock division period D7 according to the second clock division ratio. The second clock division ratio may be greater than the first clock division ratio. However, some example embodiments thereof are not limited thereto.

[0076] Similarly, a period corresponding to the first 25% of the second ADC period A2 may be a clock division period G8 according to the first clock division ratio, and a period corresponding to the other 75% of the second ADC period A2 may be a clock division period D8 according to the second clock division ratio.

[0077] In some example embodiments, the ratio of the clock gating period or the clock division period is not limited to the above example.

[0078] Reference FIG. 6C to FIG. 6D In some example embodiments, the digital clock generator 201 may be configured to generate a first stall period (eg, Figure 3 and Figure 4B The image sensing unit 100 includes a second stall period (eg, S1) and a second ADC period A2 corresponding to a second ADC operation performed by the image sensing unit 100. Figure 3 and Figure 4B The digital clock DCLK is dispersed in S2). Figure 6C As shown, each of the first ADC period A1 and the second ADC period A2 can be divided into a plurality of clock dispersion periods, and in the plurality of clock dispersion periods, the digital clock DCLK can be dispersed by different schemes (for example, gating G5, G6 or dividing D5, D6). Fig.6DAs shown, each of the first ADC period A1 and the second ADC period A2 can be divided into a plurality of clock dispersion periods, and in the plurality of clock dispersion periods, the digital clock DCLK can be divided according to different clock division ratios.

[0079] Figure 7 is a diagram illustrating consumption of digital current of the imaging device 10 according to some example embodiments. Figure 7 During the horizontal period, the analog counter clock may be enabled in the first ramp period R1 and the second ramp period R2 according to the change of the ADC reference voltage. A first counting operation corresponding to the reset voltage may be performed in the first ramp period R1, and a second counting operation corresponding to the pixel voltage may be performed in the second ramp period R2.

[0080] The digital clock DCLK may be output in response to the horizontal synchronization signal H_SYN. In addition, the digital clock DCLK may not be output in response to the counter clock. For example, the digital clock DCLK may be gated in the period corresponding to the first ramp period R1 and the second ramp period R2. In some example embodiments, the consumption of the digital current consumed by the digital processing unit 200 may be significantly reduced in the ramp periods R1 and R2. Therefore, the counting operation for the ADC operation may be less affected by the digital power.

[0081] Figure 8 is a diagram illustrating consumption of digital current of the imaging device 10 according to some example embodiments. Figure 8 , the digital clock DCLK may be output in response to the horizontal synchronization signal H_SYN, and the digital clock DCLK may not be output in response to the counter clock. For example, the digital clock DCLK may be divided in the period corresponding to the first ramp period R1 and the second ramp period R2. In some example embodiments, the consumption of the digital current consumed by the digital processing unit 200 may be reduced in the ramp periods R1 and R2.

[0082] exist Figures 1 to 8 In the imaging device 10 in FIG. 1 , control of a decentralized digital clock DCLK used by the digital processing unit 200 is shown. However, some example embodiments thereof are not limited thereto. Some example embodiments may also be applied to decentralized control of a digital clock used in an image sensing unit.

[0083] Fig.9A 2 is a diagram illustrating an imaging device 20 according to some example embodiments. Fig.9A , the imaging device 20 may include an image sensing unit 100 a and a digital processing unit 300 .

[0084] The image sensing unit 100a may include a digital clock generator 101 and a timing controller 170. The image sensing unit 100a may include at least Figure 2 At least one of the pixel array 110, the row driver 120, the analog-to-digital conversion circuit 130, the ramp signal generator 160, the timing controller 170 and / or the buffer 180. The digital clock generator 101 may be configured to generate a transmission clock TCLK for sending digital data (e.g., IDATA) to an image signal processor (e.g., the image signal processor 310). The timing controller 170 may be configured to control the timing of the pixel array 110, the row driver 120, the analog-to-digital conversion circuit 130 and the digital clock generator 101. The image sensing unit 100a may synchronize the image data IDATA with the transmission clock TCLK and may output the data to the digital processing unit 300. The digital clock generator 101 may be configured to disperse the transmission clock TCLK in response to the horizontal synchronization signal H_SYN or the counter enable signal CNT_EN received from the timing controller 170. The digital clock generator 101 may be configured to gate or divide the transmission clock TCLK in response to the counter 151 being enabled. The dispersion of the transmission clock TCLK can be determined according to user settings. The transmission clock TCLK can be dispersed based on a gated clock scheme or a divided clock scheme. This dispersion can be based on a gated clock scheme or a divided clock scheme in a partial period or the entire period in which the counter 151 is enabled.

[0085] The digital clock generator 101 may generate a clock-distributed (gated / divided) transmission clock TCLK in an analog operation (eg, ADC operation) of the image sensing unit 100a. The clock-distributed transmission clock TCLK may be similar to the reference clock. Figures 1 to 8 Describes the gated clock or divided clock.

[0086] The digital processing unit 300 may include at least one image signal processor 310 (ISP). The image signal processor 310 may perform a processing operation on the received image data IDATA in synchronization with the transmission clock TCLK. A plurality of ISPs of the digital processing unit according to some example embodiments may be connected in parallel.

[0087] Fig. 9B is a diagram illustrating a digital processing unit 400 according to some example embodiments. Fig. 9B , the digital processing unit 400 may include a digital clock generator 401, a line buffer 402, a plurality of ISPs 411 to 414 (eg, ISPs 411, 412, 413, and 414), a merging module 420, and a storage module 430. Figures 1 to 8 As described above, the digital clock generator 401 may be configured to disperse the digital clock DCLK in the ADC period of the image sensing unit.

[0088] The line buffer 402 may be configured to store image data obtained from the image sensing unit in units of lines. At least a portion of the data stored in the line buffer 402 may be associated data of a plurality of photodiodes arranged according to a two-dimensional arrangement of the image sensing unit. The plurality of photodiodes may be arranged in the image sensing unit based on pixels arranged two-dimensionally along two axes perpendicular to each other. A line may be a group of pixels arranged in the image sensing unit and may correspond to a group of pixels arranged along one of the two axes. In some example embodiments, the data stored in the line buffer 402 may be divided into a plurality of slices. The plurality of divided data may be sent to a corresponding ISP via a corresponding buffer.

[0089] Each of the multiple ISPs 411 to 414 may be configured to perform digital processing operations on the data stored in the buffer in synchronization with the digital clock DCLK. The digital processing operations may include color interpolation (CI), gamma correction, edge enhancement (EE), and noise reduction (NR). The merging module 420 may be configured to merge part or all of the data output by the multiple ISPs 411 to 414. The storage module 430 may be configured to store the merged data from the merging module 420. The stored data may be frame data corresponding to the image data acquired by the image sensing unit. The application processor (AP) may process the frame data based on the application being executed. For example, the AP may generate an image file or video file in a specified format (e.g., a JPEG format or an MPEG format) based on the identified frame data.

[0090] Fig.10 is a flowchart illustrating a method of operating an image forming apparatus according to some example embodiments. Fig.10 The method shown may be performed with respect to the imaging device 10 according to any of the example embodiments. Figures 1 to 10 , the method of operating the imaging device 10 may be performed as follows.

[0091] The image sensing unit 100 may perform an analog-to-digital conversion operation (S110), which may include converting the image signal into image data (e.g., IDATA) based on (e.g., by the counter 151) performing a counting operation until the image signal and the ramp signal RAMP are equal. While performing the analog-to-digital conversion operation (e.g., simultaneously with and / or in response to performing the counting operation), the digital processing unit 200 or the image sensing unit 100 may utilize a clock dispersion scheme to reduce digital power consumption (S120). The clock dispersion scheme may be implemented as a gated clock scheme or a divided clock scheme. The clock dispersion scheme may include gating or dividing a digital clock DCLK used in the image sensing unit 100 of the imaging device 10 or the digital processing unit 200 of the imaging device 10.

[0092] In some example embodiments, the clock dispersion scheme may gate the clock or divide the clock in the entire period or a portion of the ADC period. For example, the operation of converting to image data at S110 may include forming a first analog-to-digital (ADC) operation corresponding to a reset voltage, and performing a second ADC operation corresponding to a pixel voltage, and reducing the consumption of digital power may include gating or dividing the digital clock in the entire period or a portion of a first ADC period corresponding to the first ADC operation and a second ADC period corresponding to the second ADC operation. For example, in a portion of the ADC period (for example, the approximately first 25% period of a dark region that is sensitive to image quality characteristics), the clock may be gated or a divided clock may be output. In addition, the clock may be gated in the first 25% period of the ADC period, and the divided clock may be output in the subsequent 75% period.

[0093] Reference FIG. 4A to FIG. 4B and Fig.10 , the method may include transmitting the image data IDATA to image signal processors (e.g., ISPs 211 to 214) connected in series to each other. Each of the image signal processors (e.g., ISPs 211 to 214) may not process data processed in a first stall period S1 corresponding to the first ADC operation and a second stall period S2 corresponding to the second ADC operation.

[0094] In the clock dispersion scheme used in S120, a clock gating period, a clock frequency division period, or a clock frequency division ratio is determined based on user settings.

[0095] In some example embodiments, the ADC period may be determined as a plurality of clock dispersion periods. In some example embodiments, the determined clock dispersion periods may overlap with each other. In some example embodiments, a priority may be provided to each of the periods by a user. When the periods overlap, a clock corresponding to the priority may be output. In some example embodiments, the starting point of the latter period may be the same as or before the end point of the earlier period in time.

[0096] Fig.11 is a diagram showing an electronic device having a multi-camera module. Fig.11 , the electronic device 1000 may include a camera module group 1100 , an application processor 1200 , a PMIC 1300 , and an external memory 1400 .

[0097] The camera module group 1100 may include a plurality of camera modules 1100a, 1100b, and 1100c. As used herein, camera modules are interchangeably referred to as "cameras," "camera devices," and the like. Although the accompanying drawings show some example embodiments in which three camera modules 1100a, 1100b, and 1100c are provided, some example embodiments thereof are not limited thereto. In some example embodiments, the camera module group 1100 may be modified to include only two camera modules. In addition, in some example embodiments, the camera module group 1100 may be modified to include n (n is a natural number equal to or greater than 4) camera modules.

[0098] Fig.12 It is shown Fig.11 The following description is also applicable to the other camera modules 1100a and 1100c in the example embodiments. Fig.12 , the camera module 1100 b may include a prism 1105 , an optical path folding element (OPFE) 1110 , an actuator 1130 , an image sensing device 1140 , and a storage device 1150 .

[0099] The prism 1105 may include a reflective surface 1107 of a light reflective material, and may change a path of light L incident from the outside.

[0100] In example embodiments, the prism 1105 may change the path of the light L incident in the first direction X to travel in the second direction Y perpendicular to the first direction X. In addition, the prism 1105 may rotate the reflective surface 1107 of the light reflective material in the direction A around the central axis 1106, or may rotate the central axis 1106 in the direction B to change the path of the light L incident in the first direction X to travel in the vertical second direction Y. In some example embodiments, the OPFE 1110 may also move in a third direction Z perpendicular to the first direction X, and the third direction Z is perpendicular to the second direction Y.

[0101] In some example embodiments, as shown, the maximum rotation angle of the prism 1105 in the positive (+) A direction may be 15 degrees or less, and may be greater than 15 degrees in the negative (-) A direction, but some example embodiments thereof are not limited thereto.

[0102] In an exemplary embodiment, the prism 1105 can move approximately 20 degrees in the positive (+) or negative (-) B direction, between 10 and 20 degrees, or between 15 and 20 degrees, and with respect to the moving angle, the prism 1105 can move the same angle in the positive (+) or negative (-) B direction, or can move an almost similar angle within a range of approximately 1 degree in the positive (+) or negative (-) B direction.

[0103] In example embodiments, the prism 1105 may move the reflective surface 1107 of the light reflective material in a third direction (eg, Z direction) parallel to the extension direction of the central axis 1106 .

[0104] OPFE 1110 may include, for example, optical lenses composed of m (where m is a natural number) groups. The m lenses may move in the second direction Y, and may change the optical zoom ratio of camera module 1100b. For example, when the basic optical zoom magnification of camera module 1100b is defined as Z, and the m optical lenses included in OPFE 1110 move, the optical zoom magnification of camera module 1100b may be changed to 3Z or 5Z or 7Z or higher optical zoom magnification.

[0105] The actuator 1130 may move the OPFE 1110 or the optical lens (hereinafter referred to as “optical lens”) to a specific position. For example, the actuator 1130 may adjust the position of the optical lens so that the image sensor 1142 may be disposed at the focal length of the optical lens for accurate sensing.

[0106] The image sensing device 1140 may include an image sensor 1142, a control logic 1144, and a memory 1146. The image sensor 1142 may sense an image of a sensed object using light L provided through an optical lens. The control logic 1144 may control the overall operation of the camera module 1100b. For example, the control logic 1144 may control the operation of the camera module 1100b according to a control signal provided via a control signal line CSLb.

[0107] The memory 1146 may store information required for the operation of the camera module 1100b, such as calibration data 1147. The calibration data 1147 may include information required by the camera module 1100b to generate image data using light L provided from the outside. For example, the calibration data 1147 may include information about the above-mentioned degree of rotation, information about the focal length, information about the optical axis, etc. When the camera module 1100b is implemented in the form of a multi-state camera in which the focal length changes according to the position of the optical lens, the calibration data 1147 may include a focal length value for each position (or each state) of the optical lens and information related to autofocus.

[0108] The storage device 1150 may store image data sensed via the image sensor 1142. The storage device 1150 may be provided outside the image sensing device 1140, and may be implemented to be stacked with a sensor chip included in the image sensing device 1140. In example embodiments, the storage device 1150 may be implemented as an electrically erasable programmable read-only memory (EEPROM), but some example embodiments thereof are not limited thereto.

[0109] Refer to Fig.11 and Fig.12 In example embodiments, each of the plurality of camera modules 1100a, 1100b, and 1100c may include an actuator 1130. Therefore, each of the plurality of camera modules 1100a, 1100b, and 1100c may include the same or different calibration data 1147 according to the operation of the actuator 1130 included therein.

[0110] In an example embodiment, one camera module (e.g., 1100b) among the multiple camera modules 1100a, 1100b and 1100c may be configured as a folded lens camera module including the above-mentioned prism 1105 and OPFE 1110, and the other camera modules (e.g., 1100a and 1100c) may be vertical camera modules that do not include the prism 1105 and OPFE 1110, but some example embodiments thereof are not limited thereto.

[0111] In an example embodiment, one camera module (e.g., 1100c) among the plurality of camera modules 1100a, 1100b, and 1100c may be configured as a vertical depth camera that can extract depth information using, for example, infrared (IR). In some example embodiments, the application processor 1200 may merge image data provided by the depth camera with image data provided by other camera modules (e.g., 1100a or 1100b), and may generate a 3D depth image.

[0112] In an example embodiment, at least two camera modules (e.g., 1100a and 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may have different fields of view. In some example embodiments, for example, the optical lenses of at least two camera modules (e.g., 1100a and 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may be different, but some example embodiments thereof are not limited thereto. In addition, in an example embodiment, the fields of view of the plurality of camera modules 1100a, 1100b, and 1100c may be different. In some example embodiments, the optical lenses included in the plurality of camera modules 1100a, 1100b, and 1100c may also be different, but some example embodiments thereof are not limited thereto. In an example embodiment, the plurality of camera modules 1100a, 1100b, and 1100c may be physically separated from each other. In other words, an independent image sensor 1142 may be provided in each of the plurality of camera modules 1100a, 1100b, and 1100c without dividing and using a sensing area of ​​a single image sensor 1142 by the plurality of camera modules 1100a, 1100b, and 1100c.

[0113] Return to reference Fig.11, the application processor 1200 may include an image processing device 1210, a memory controller 1220, and an internal memory 1230. The application processor 1200 may be implemented separately from the plurality of camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the plurality of camera modules 1100a, 1100b, and 1100c may be separated from each other as separate semiconductor chips.

[0114] The image processing device 1210 may include a plurality of sub-image processors 1212a, 1212b, and 1212c, an image generator 1214, and a camera module controller 1216. The image processing device 1210 may also include a plurality of sub-image processors 1212a, 1212b, and 1212c corresponding to the number of the plurality of camera modules 1100a, 1100b, and 1100c.

[0115] The image data generated by each of the camera modules 1100a, 1100b, and 1100c may be provided to the corresponding sub-image processors 1212a, 1212b, and 1212c via image signal lines ISLa, ISLb, and ISLc separated from each other. For example, the image data generated by the camera module 1100a may be provided to the sub-image processor 1212a via the image signal line ISLa, the image data generated by the camera module 1100b may be provided to the sub-image processor 1212b via the image signal line ISLb, and the image data generated by the camera module 1100c may be provided to the sub-image processor 1212c via the image signal line ISLc. Such image data transmission may be performed using, for example, a camera serial interface (CSI) based on a mobile industry processor interface (MIPI), but some example embodiments thereof are not limited thereto.

[0116] In an example embodiment, a single sub-image processor may be arranged to correspond to the plurality of camera modules. For example, as shown, the sub-image processor 1212a and the sub-image processor 1212c may be integrated into a single sub-image processor instead of being separated from each other, and the image data provided by the camera modules 1100a and 1100c may be selected by a selection device (e.g., a multiplexer) and may be provided to the integrated sub-image processor.

[0117] The image data provided to each of the sub-image processors 1212a, 1212b, and 1212c may be provided to the image generator 1214. The image generator 1214 may generate an output image using the image data provided by each of the sub-image processors 1212a, 1212b, and 1212c according to the image generation information or the mode signal. Specifically, the image generator 1214 may merge at least a portion of the image data generated by the camera modules 1100a, 1100b, and 1100c having different fields of view according to the image generation information or the mode signal. In addition, the image generator 1214 may generate an output image by selecting one of the image data generated by the camera modules 1100a, 1100b, and 1100c having different fields of view according to the image generation information or the mode signal.

[0118] In an example embodiment, the image generation information may include a zoom signal or a zoom factor. In addition, in an example embodiment, for example, the mode signal may be based on a mode selected by a user. When the image generation information is a zoom signal (zoom factor), and the camera modules 1100a, 1100b, and 1100c have different fields of view, the image generator 1214 may perform different operations according to the type of the zoom signal. For example, when the zoom signal is a first signal, the image data output by the camera module 1100a may be merged with the image data output by the camera module 1100c, and the merged image signal and the image data output by the camera module 1100b not used in the merge may be used to generate an output image. When the zoom signal is a second signal different from the first signal, the image generator 1214 may not perform image data merging, and may select one of the image data output by each camera module 1100a, 1100b, and 1100c, and may generate an output image. However, some example embodiments thereof are not limited thereto, and if necessary, the method of processing image data may be changed.

[0119] In an example embodiment, the image generator 1214 may receive a plurality of pieces of image data having different exposure times from at least one of the plurality of sub-image processors 1212a, 1212b, and 1212c, and may perform high dynamic range (HDR) processing on the plurality of pieces of image data to generate merged image data having an increased dynamic range. Figures 1 to 10 As described above, when at least one of the camera modules 1100a, 1100b, and 1100c performs an analog operation, at least one of the plurality of sub-image processors 1212a, 1212b, and 1212c may be configured to perform digital clock dispersion.

[0120] The camera module controller 1216 may provide a control signal to each of the camera modules 1100a, 1100b, and 1100c. The control signal generated by the camera module controller 1216 may be provided to the corresponding camera modules 1100a, 1100b, and 1100c via control signal lines CSLa, CSLb, and CSLc separated from each other. In addition, one (e.g., 1100b) of the plurality of camera modules 1100a, 1100b, and 1100c may be designated as a master camera according to image generation information including a zoom signal or a mode signal, and the other camera modules (e.g., 1100a and 1100c) may be designated as slave cameras. Such information may be included in the control signal and may be provided to the corresponding camera modules 1100a, 1100b, and 1100c via control signal lines CSLa, CSLb, and CSLc separated from each other.

[0121] The camera modules operating as the master camera and the slave camera may be changed according to the zoom factor or the operation mode signal. For example, when the field of view of the camera module 1100a is wider than the field of view of the camera module 1100b and the zoom factor shows a low zoom magnification, the camera module 1100b may be operated as the master camera and the camera module 1100a may be operated as the slave camera. Alternatively, when the zoom factor shows a high zoom magnification, the camera module 1100a may be operated as the master camera and the camera module 1100b may be operated as the slave camera.

[0122] In an example embodiment, the control signal provided by the camera module controller 1216 to each of the camera modules 1100a, 1100b, and 1100c may include a synchronization enable signal. For example, when the camera module 1100b is a master camera and the camera modules 1100a and 1100c are slave cameras, the camera module controller 1216 may send the synchronization enable signal to the camera module 1100b. The camera module 1100b receiving the synchronization enable signal may generate a synchronization signal based on the received synchronization enable signal, and may provide the generated synchronization signal to the camera modules 1100a and 1100c via the synchronization signal line SSL. The camera module 1100b and the camera modules 1100a and 1100c may be synchronized with the synchronization signal, and may send the image data to the application processor 1200.

[0123] In an example embodiment, the control signal provided by the camera module controller 1216 to the plurality of camera modules 1100a, 1100b and 1100c may include mode information based on the mode signal. Based on the mode information, the plurality of camera modules 1100a, 1100b and 1100c may operate in the first operation mode and the second operation mode in relation to the sensing speed.

[0124] In the first operation mode, the plurality of camera modules 1100a, 1100b, and 1100c may generate image signals at a first rate (e.g., generate image signals at a first frame rate), may encode signals at a second rate higher than the first rate (e.g., encode image signals at a second frame rate higher than the first frame rate), and may transmit the encoded image signals to the application processor 1200. In some example embodiments, the second rate may be 30 times or less than the first rate.

[0125] The application processor 1200 may store the received image signal (i.e., the encoded image signal) in the internal memory 1230 provided therein or in the external memory 1400 provided outside the application processor 1200, and thereafter, the application processor 1200 may decode the encoded image signal from the internal memory 1230 or the external memory 1400, and may display image data generated based on the decoded image signal. For example, a corresponding sub-image processor among the plurality of sub-image processors 1212a, 1212b, and 1212c of the image processing device 1210 may perform decoding, and may also perform image processing on the decoded image signal.

[0126] In the second operation mode, the plurality of camera modules 1100a, 1100b, and 1100c may generate image signals at a third rate lower than the first rate (e.g., generate image signals at a third frame rate lower than the first frame rate), and may transmit the image signals to the application processor 1200. The image signals provided to the application processor 1200 may be uncoded signals. The application processor 1200 may perform image processing on the received image signals, or may store the image signals in the internal memory 1230 or the external memory 1400.

[0127] The PMIC 1300 may supply power (e.g., power voltage) to each of the plurality of camera modules 1100a, 1100b, and 1100c. For example, the PMIC 1300 may supply a first power to the camera module 1100a via a power signal line PSLa, may supply a second power to the camera module 1100b via a power signal line PSLb, and may supply a third power to the camera module 1100c via a power signal line PSLc.

[0128] The PMIC 1300 may generate power corresponding to each of the plurality of camera modules 1100a, 1100b, and 1100c in response to a power control signal PCON from the application processor 1200, and may also adjust the level of the power. The power control signal PCON may include a power adjustment signal for each operating mode of the plurality of camera modules 1100a, 1100b, and 1100c. For example, the operating mode may include a low power mode, and in some example embodiments, the power control signal PCON may include information about a camera module operating in a low power mode and a determined power level. The levels of power provided to the plurality of camera modules 1100a, 1100b, and 1100c may be the same or different. In addition, the level of power may be changed dynamically.

[0129] As described herein, any device, electronic device, module, unit, controller, circuit, camera module, image sensor and / or some parts thereof, and / or any part thereof (including but not limited to the imaging device 10, the image sensing unit 100, the digital processing unit 200, the timing controller 170, the digital clock generator 201, the image signal processor 210, the ramp signal generator 160, the analog-to-digital conversion circuit 130, the buffer 180, the imaging device 20, the image sensing unit 100a, the digital processing unit 300, the image signal processor 310, the digital processing unit 400, the line buffer 402, the digital clock generator 401, the ISP 411 to 414, merging module 420, storage module 430, electronic device 1000, application processor 1200, image processing device 1210, image generator 1214, sub-image processors 1212a, 1212b, 1212c, camera module controller 1216, memory controller 1220, PMIC 1300, external memory 1400, internal memory 1230, image sensing device 1140, control logic 1144, image sensor 1142, etc.) may include one or more instances of the following processing circuits, may be included in one or more instances of the following processing circuits, and / or may be implemented as one or more instances of the following processing circuits: such as hardware including logic circuits; a hardware / software combination such as a processor that executes software; or a combination thereof. For example, the processing circuit may more specifically include (but not limited to) a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA) and a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), a neural network processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. In some example embodiments, the processing circuit may include a non-transitory computer-readable storage device (e.g., memory) storing an instruction program, such as a solid-state drive (SSD), and a processor (e.g., CPU) configured to execute the instruction program to implement the functions and / or methods performed by any device, electronic device, module, controller, unit, camera module, image sensor and / or some or all of its parts, and / or any part thereof according to any of the exemplary embodiments.

[0130] Any memory described herein (including but not limited to internal memory 1230, external memory 1400, memory 1146, and / or storage device 1150) may be a non-transitory computer-readable medium and may store a program of instructions. Any of the memories described herein may be a non-volatile memory (such as flash memory, phase change random access memory (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), or ferroelectric RAM (FRAM)) or a volatile memory (such as static RAM (SRAM), dynamic RAM (DRAM), or synchronous DRAM (SDRAM)).

[0131] According to the aforementioned example embodiments, when an analog operation is performed in an image sensor, an image sensor, an image device having the same, and a method of operating the image sensor may reduce fluctuations in digital power by dispersing a digital clock.

[0132] While certain example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined in the appended claims.

Claims

1. An imaging device, comprising: an image sensing circuit configured to receive an image signal from a pixel, to convert the received image signal into image data, and to output the image data; as well as a digital processing circuit configured to process the image data in synchronization with a digital clock, Wherein, the digital processing circuit comprises a digital clock generator configured to generate the digital clock, wherein the digital clock generator is configured to disperse the digital clock by gating or dividing the digital clock in response to the image sensing circuit converting the image signal into the image data during the entire period or a portion of the analog-to-digital conversion operation period, and The gating of the digital clock indicates that the digital clock is normally output in a period other than a gating period.

2. The imaging device according to claim 1, wherein: The image sensing circuit comprises: an analog-to-digital conversion circuit configured to convert a received image signal into the image data based on comparing the image signal with a ramp signal and performing a counting operation corresponding to a result of the comparison; and A timing controller is configured to generate a counter enable signal related to the counting operation.

3. The imaging device according to claim 2, wherein: The digital clock generator is configured to disperse the digital clock according to a specific timing sequence in response to the counter enable signal.

4. The imaging device according to claim 2, wherein: The digital clock generator is configured to disperse the digital clock according to a specific timing sequence in response to a horizontal synchronization signal of the timing controller.

5. The imaging device according to claim 1, wherein: The image sensing circuit is configured to perform a first analog-to-digital conversion operation corresponding to a reset voltage and to perform a second analog-to-digital conversion operation corresponding to a pixel voltage, and The digital clock generator is configured to gate the digital clock in an entire period or a partial period of each of a first analog-to-digital conversion period corresponding to the first analog-to-digital conversion operation and a second analog-to-digital conversion period corresponding to the second analog-to-digital conversion operation.

6. The imaging device according to claim 1, wherein: The image sensing circuit is configured to perform a first analog-to-digital conversion operation corresponding to a reset voltage and to perform a second analog-to-digital conversion operation corresponding to a pixel voltage, and The digital clock generator is configured to divide the frequency of the digital clock in an entire period or a partial period of each of a first analog-to-digital conversion period corresponding to the first analog-to-digital conversion operation and a second analog-to-digital conversion period corresponding to the second analog-to-digital conversion operation.

7. The imaging device according to claim 1, wherein: The image sensing circuit is configured to perform a first analog-to-digital conversion operation corresponding to a reset voltage and to perform a second analog-to-digital conversion operation corresponding to a pixel voltage, and The digital clock generator is configured as: gating the digital clock in a partial period of each of a first analog-to-digital conversion period corresponding to the first analog-to-digital conversion operation and a second analog-to-digital conversion period corresponding to the second analog-to-digital conversion operation, and The digital clock is frequency-divided in the other period of each of the first analog-to-digital conversion period and the second analog-to-digital conversion period.

8. The imaging device according to claim 1, wherein: The image sensing circuit is configured to perform a first analog-to-digital conversion operation corresponding to a reset voltage and to perform a second analog-to-digital conversion operation corresponding to a pixel voltage, The digital clock generator is configured to disperse the digital clock in a first stall period including a first analog-to-digital conversion period corresponding to the first analog-to-digital conversion operation and a second stall period including a second analog-to-digital conversion period corresponding to the second analog-to-digital conversion operation, In which, during the first stall period and the second stall period, no converted image data is output.

9. The imaging device according to claim 8, wherein: Each of the first analog-to-digital conversion period and the second analog-to-digital conversion period is frequency-divided into a plurality of clock dispersion periods, and In the plurality of clock dispersion periods, the digital clock is dispersed by different schemes.

10. The imaging device according to claim 8, wherein: Each of the first analog-to-digital conversion period and the second analog-to-digital conversion period is frequency-divided into a plurality of clock dispersion periods, and In at least two of the plurality of clock dispersion periods, the digital clock is divided according to different clock division ratios.

11. A method of operating an imaging device, the method comprising: converting the image signal into image data based on performing a counting operation until the image signal and the ramp signal are equal; as well as In response to performing the counting operation, a clock dispersion scheme is used to reduce the consumption of digital power during the entire period or a portion of the period of the analog-to-digital conversion operation. The clock dispersion scheme includes gating or frequency division of a digital clock used in an image sensing circuit or a digital processing circuit of the imaging device, and The gating of the digital clock indicates that the digital clock is normally output in a period other than a gating period.

12. The method according to claim 11, wherein: The conversion into the image data includes: performing a first analog-to-digital conversion operation corresponding to a reset voltage; and performing a second analog-to-digital conversion operation corresponding to a pixel voltage, and Reducing the consumption of the digital power includes gating or dividing the digital clock in the entire period or a part of a first analog-to-digital conversion period corresponding to the first analog-to-digital conversion operation and a second analog-to-digital conversion period corresponding to the second analog-to-digital conversion operation.

13. The method according to claim 12, further comprising: sending the image data to a plurality of image signal processors connected in series to each other, wherein each of the plurality of image signal processors does not process data processed in a first stall period corresponding to the first analog-to-digital conversion operation and a second stall period corresponding to the second analog-to-digital conversion operation, In which, during the first stall period and the second stall period, no converted image data is output.

14. The method according to claim 11, wherein: In the clock dispersion scheme, a clock gating period, a clock division period, or a clock division ratio is determined based on a user setting.

15. An imaging device comprising: A pixel array having a plurality of pixels arranged in a plurality of row lines and a plurality of column lines; a row driver configured to select one row line of the plurality of row lines; an analog-to-digital conversion circuit configured to convert an analog signal output by the pixel array into digital data; a digital clock generator configured to generate a transmission clock for sending the digital data to an image signal processor; as well as a timing controller configured to control the timing of the pixel array, the row driver, the analog-to-digital conversion circuit and the digital clock generator, The analog-to-digital conversion circuit includes: a comparator circuit having a comparator for comparing a pixel signal output by the pixel array with a ramp signal; and a counter circuit having a counter configured to count the output of each of the comparators. wherein the digital clock generator is configured to disperse the transmission clock by gating or dividing the digital clock in response to receiving a horizontal synchronization signal or a counter enable signal from the timing controller during a portion of the period or the entire period during which the counter is enabled, and The gating of the digital clock indicates that the digital clock is normally output in a period other than a gating period.

16. The imaging device according to claim 15, wherein: The digital clock generator is configured to gate or divide the transmission clock in response to the counter being enabled.

17. The imaging device according to claim 15, wherein: The dispersion of the transmission clock is determined according to user settings.

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