On-demand memory allocation

Abstract

This invention discloses techniques for dynamically allocating and mapping dedicated memory for a request circuit (210). The disclosed circuit (220) can receive a dedicated address and translate it into a virtual address (MMU (230) can then translate the virtual address into a physical address to actually access the memory element (240)). In some embodiments, the dedicated memory allocation circuit (220) is configured to generate page table information before it has been established and to map dedicated memory pages for requests. In various embodiments, this can advantageously allow dynamic dedicated memory allocation, for example, to efficiently allocate memory for graphics shaders with different types of workloads. The disclosed caching techniques for page table information can improve performance relative to conventional techniques. Furthermore, the disclosed embodiments can facilitate memory consolidation across devices such as graphics processors.

Description

Background Technology Technical Field

[0002] This disclosure relates in general to computer memory management, and more specifically to techniques for allocating dedicated memory on demand.

[0003] Related technical descriptions

[0004] Processors such as graphics processing units (GPUs) can use various types of memory space. For example, shared memory space can be used to share data processed by multiple processor blocks, while other blocks such as shader processors can use dedicated memory space during operation. Attached Figure Description

[0005] Figure 1A This is an illustration showing an overview of exemplary graphics processing operations according to some implementation schemes.

[0006] Figure 1B This is a block diagram illustrating exemplary graphical units according to some implementation schemes.

[0007] Figure 2 This is a block diagram illustrating an exemplary device with dedicated memory allocator circuitry according to some embodiments.

[0008] Figure 3 This is a block diagram illustrating a more detailed system with memory allocator circuitry and a cache for page table information according to some embodiments.

[0009] Figure 4 This is a diagram illustrating an exemplary page table hierarchy structure according to some implementation schemes.

[0010] Figure 5 This is a flowchart illustrating an exemplary method for creating page table entries and mapping pages in response to a request, according to some implementation schemes.

[0011] Figure 6 This is a flowchart illustrating a more general method for processing access requests, including addresses in a dedicated memory space, according to some implementation schemes.

[0012] Figure 7 This is a block diagram illustrating an exemplary computing device according to some implementation schemes.

[0013] Figure 8 This is a block diagram illustrating an exemplary computer-readable medium for storing circuit design information according to some embodiments.

[0014] This specification includes references to various embodiments to indicate that this disclosure is not intended to refer to a particular specific embodiment, but rather to a range of embodiments falling within the spirit of this disclosure, including the appended claims. Specific features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

[0015] Within this disclosure, different entities (which may be referred to differently as “cells,” “circuits,” other components, etc.) may be described or claimed to be “configured to” perform one or more tasks or operations. This expression—an [entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing, such as an electronic circuit). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be said to be “configured to” perform a task even if the structure is not currently being operated. “A programmable shader processor configured to execute shader programs” is intended to cover, for example, a circuit that performs this function during operation, even if the circuit in question is not currently in use (e.g., the circuit is not connected to a power source). Therefore, an entity described or stated as “configured to” perform a task refers to a physical thing used to perform that task, such as a device, circuit, memory storing executable program instructions, etc. This phrase is not used herein to refer to intangible things.

[0016] The term "configured as" is not intended to mean "configurable as". For example, an unprogrammed FPGA is not considered "configured as" to perform a particular function, although it may be "configurable as" to perform that function. After proper programming, the FPGA can then be configured to perform that function.

[0017] The formulation structure in the appended claims is "configured" to perform one or more tasks explicitly intended for the claim elements. No Referring to 35 USC §112(f). Therefore, none of the claims in this application are intended to be interpreted as having a means-plus-function element. If the applicant wishes to invoke 112(f) during the application process, it will use the structure "means for [performing a function]" to formulate the elements of the claims.

[0018] As used herein, the term "based on" is used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors may influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on another factor such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0019] Furthermore, as used herein, the terms “first,” “second,” “third,” etc., do not necessarily imply an order of elements (e.g., chronological order). For example, references to a “first” graphic operation and a “second” graphic operation do not imply an order of graphic operations, and there is a lack of additional language to restrict the temporal relationship between these operations. In short, references such as “first,” “second,” etc., are used as designations to facilitate reference in the specification and appended claims. Detailed Implementation

[0020] Overview of Graphics Processing

[0021] See Figure 1A The diagram illustrates a flowchart of an exemplary processing flow 100 for processing graphics data. In some embodiments, the transformation and lighting step 110 may involve processing lighting information of vertices received from the application based on defined light source positions, reflectivity, etc., assembling vertices into polygons (e.g., triangles), and / or converting polygons to the correct size and orientation based on their position in three-dimensional space. The clipping step 115 may involve discarding polygons or vertices outside the visible area. The rasterization step 120 may involve defining fragments within each polygon and assigning initial color values ​​to each fragment, for example, based on the texture coordinates of the polygon vertices. Fragments may specify the properties of the pixels they overlap, but the actual pixel properties may be determined based on combining multiple fragments (e.g., in a frame buffer) and / or ignoring one or more fragments (e.g., if they are covered by other objects). The shading step 130 may involve altering pixel components based on lighting, shadows, bump mapping, translucency, etc. Shaded pixels may be assembled in frame buffer 135. Modern GPUs typically include programmable shaders that allow application developers to customize shading and other processing steps. Therefore, in various embodiments, Figure 1A The exemplary components can be executed in various sequences, in parallel, or omitted. Additional processing steps can also be implemented.

[0022] See now Figure 1BA simplified block diagram of an exemplary graphics unit 150 according to some embodiments is shown. In the exemplary embodiments, the graphics unit 150 includes a programmable shader 160, a vertex pipe 185, a fragment pipe 175, a texture processing unit (TPU) 165, an image writing unit 170, and a memory interface 180. In some embodiments, the graphics unit 150 is configured to use the programmable shader 160 to process both vertex data and fragment data, and the programmable shader may be configured to process the graphics data in parallel using multiple execution pipelines or instances.

[0023] In the illustrated embodiment, vertex tube 185 may include various fixed-function hardware configured to process vertex data. Vertex tube 185 may be configured to communicate with programmable shader 160 to coordinate vertex processing. In the illustrated embodiment, vertex tube 185 is configured to send processed data to fragment tube 175 and / or programmable shader 160 for further processing.

[0024] In the illustrated embodiment, fragment tube 175 may include various fixed-function hardware configured to process pixel data. Fragment tube 175 may be configured to communicate with programmable shader 160 to coordinate fragment processing. Fragment tube 175 may be configured to perform rasterization on polygons from vertex tube 185 and / or programmable shader 160 to generate fragment data. Vertex tube 185 and / or fragment tube 175 may be coupled to memory interface 180 (coupling not shown) to access graphics data.

[0025] In the illustrated embodiment, programmable shader 160 is configured to receive vertex data from vertex tube 185 and fragment data from fragment tube 175 and / or TPU 165. Programmable shader 160 may be configured to perform vertex processing tasks on the vertex data, which may include various transformations and / or adjustments to the vertex data. In the illustrated embodiment, programmable shader 160 is also configured to perform fragment processing tasks on pixel data, such as texturing and shading processing. Programmable shader 160 may include multiple execution pipelines for parallel processing of data.

[0026] In the illustrated implementation, TPU 165 is configured to schedule fragment processing tasks from programmable shader 160. In some implementations, TPU 165 is configured to prefetch texture data and assign initial colors to fragments for further processing by programmable shader 160 (e.g., via memory interface 180). TPU 165 may be configured to provide fragment components, for example, in normalized integer or floating-point format. In some implementations, TPU 165 is configured to provide fragments in a 2x2 format, grouped into sets of four (“fragment quadruples”), which are pipelined by a set of four programmable shaders 160.

[0027] In some embodiments, the image writing unit (IWU) 170 is configured to store processed tiles of an image and can perform operations on the rendered image before transferring it for display or to memory for storage. In some embodiments, the graphics unit 150 is configured to perform tiled deferred rendering (TBDR). In tiled rendering, different portions of the screen space (e.g., squares or rectangles of pixels) can be processed individually. In various embodiments, the memory interface 180 facilitates communication with one or more of various memory hierarchies.

[0028] Overview of On-Demand Memory Allocation

[0029] Graphics shader processors typically use dedicated memory space, for example, to store data while executing a graphics working set and then write the results (e.g., for kicks) to shared memory space. Providing these processors with fixed dedicated memory allocations can be inefficient in certain scenarios, such as when some execution paths of a program use significantly larger memory footprints than others, when migrating work from one part of the GPU to another (e.g., moving background processes to allocate resources to higher-priority work) is valuable, and when a program has different types of memory requirements for different parts (e.g., an application that requires a large thread-specific allocation to start but later needs a smaller thread-specific allocation paired with a thread group-specific allocation). Furthermore, fixed allocations may not allow the shader processor to share memory space with other circuitry.

[0030] In the disclosed implementations discussed in detail below, the GPU dynamically allocates and maps dedicated memory space. In some implementations, the memory allocator circuitry is configured to reserve and map pages of the dedicated memory space for circuits using dedicated memory. In some implementations, this may allow multiple memory spaces to be merged into a shared global memory space. In some implementations, the memory allocator supports the following operations: reserve, translate-map, translate-no-map, unmap, and release.

[0031] The reservation command reserves one or more dedicated pages (which may include any pages to be used in the page table) from the virtual page pool. This command may not actually map any pages, but it causes a counter of available virtual pages to decrement. In some implementations, reserving pages before they are actually mapped can prevent deadlock when multiple circuits require the mapped pages.

[0032] The translate-map command translates dedicated memory addresses into virtual addresses, including mapping virtual pages from the page pool to the page table when necessary. Note that this command can provide mapping even if, for example, all or part of the page table (which can be hierarchical) is not created. Therefore, at the start of a graphics working set, the page table for its dedicated memory space may not exist. The translate-map command can set mask information in the page table hierarchy indicating the validity of lower-level entries, which can be used to track allocated pages and allow the page table hierarchy to be dismantled after a page is unmapped.

[0033] The translate-no-map command translates the provided private address into a virtual address and returns an indication of whether the corresponding sector has been modified. If the sector has not been modified, the requested read from the provided address is not performed. If a virtual page has not been mapped for the requested private page, the translate-no-map command will not cause the page to be mapped.

[0034] The unmapping command clears the modified fields corresponding to the provided private address. Once all modified fields have been cleared, the corresponding virtual data page can be released back to the page pool. In some implementations, the release command releases the mapped page and returns it to the virtual page pool.

[0035] In some implementations, the device implements multiple dedicated memory spaces with varying ranges, which can be merged within a backup global memory space. Accesses within each dedicated space can be translated to virtual addresses in the global memory space. For example, dedicated memory spaces for general-purpose and stack registers can have SIMD group ranges. As another example, thread group dedicated memory spaces can have tile ranges. Additional examples of dedicated spaces include interfaces, shader cores, local image blocks, and execution state types. For example, dynamically allocating memory for these structures can provide efficient allocation relative to fixed buffers. Different types of spaces can have different numbers of virtual IDs (which can be mapped to hardware IDs of the requesting circuitry) allowed to request space, and different maximum sizes for each virtual ID.

[0036] The disclosed techniques advantageously allow for device-to-memory backup of dedicated memory spaces, provide flexibility in allocating dedicated memory storage for different purposes, offer fast translation, allow determination of whether sufficient virtual pages are available for a given task, reduce software memory footprint, and provide the desired memory access patterns from a cache perspective. Specifically, allocation flexibility may include the ability to dynamically adjust the amount of memory allocated to different types of dedicated memory (e.g., general-purpose registers in thread-specific memory or local memory space in thread group-specific memory) instead of using fixed buffers for these purposes. Furthermore, the disclosed on-demand techniques reduce the time required to allocate memory (e.g., compared to pre-allocated memory), which reduces overall memory usage.

[0037] Figure 2 This is a block diagram illustrating an exemplary dedicated memory allocator according to some embodiments. In the illustrated embodiment, the system includes circuitry 210, a memory allocator 220, a memory management unit 230, and storage elements 240.

[0038] In the illustrated implementation, circuit 210 uses dynamically allocated dedicated memory space. Programmable shader 160 is an example of circuit 210. In the illustrated implementation, circuit 210 is configured to send a page reservation request to memory allocator 220 and receive page grants. Note that the reservation may not actually map pages, but rather a counter may be decremented to reserve pages for circuit 210. Circuit 210 is also configured to send a mapping request to memory allocator 220 with a dedicated address and receive the corresponding virtual address based on the dynamic mapping of pages with dedicated addresses. Circuit 210 then uses the virtual address to access memory element 240 via MMU 230.

[0039] In the illustrated implementation, memory allocator 220 is configured to receive and respond to requests from circuitry 210, as described above. Memory allocator 220 communicates with MMU 230, for example, to access page pool information stored in the global memory space (e.g., this may be implemented by storage element 240, which may be part of a cache / memory hierarchy). Memory allocator 220 can determine whether an element of the page table hierarchy exists for a given request and dynamically create the non-existent structure. Memory allocator 220 or circuitry 210 may include various cache circuitry for caching page table information at one or more hierarchy levels.

[0040] In some implementations, MMU 230 is configured to translate virtual addresses in the global memory space into physical addresses in memory element 240. In some implementations, MMU 230 does not involve dedicated memory allocation and can therefore be implemented using any of a variety of suitable conventional architectures. Note that MMU 230 can implement a paging scheme for translating virtual addresses to physical addresses, which can be separate from the paging techniques discussed herein for translating dedicated addresses to virtual addresses. In some implementations, the page tables of MMU 230 are memory-backed up based on a known memory size, while the page tables used by memory allocator 220 can be dynamically grown and shrunk.

[0041] In the illustrated implementation, storage element 240 is accessed via a physical address and can be implemented using any of a variety of suitable memory technologies. Note that various data cache levels in a cache / memory hierarchy can be accessed using either virtual or physical addresses. Therefore, if the requested data is already cached in a cache using virtual address data tags, MMU 230 may not be involved in processing the requested data. Furthermore, storage element 240 can be, for example, a data cache using physical address tags, random access memory, or a hard disk drive.

[0042] Exemplary memory allocator

[0043] Figure 3 This is a block diagram illustrating a detailed exemplary memory allocator according to some embodiments. In the illustrated embodiment, the system includes shaders 360A-360N, page table caches (PTCs) 310A-310N, a memory allocator 220, a global page manager (PM) 350, and a global memory (GM) 365. The memory allocator 220 includes a page catalog cache (PCC) 322 (which includes page queues 330 and page catalog (PC) storage 325) and a page directory cache (PDC) 324 (which includes page queues 335 and a PTC arbitrator 340). The illustrated example provides a cache of page table information to improve the performance of dynamic allocation of dedicated memory for shaders 360.

[0044] Shader 360 is an example of circuit 210 and can be configured to execute shader programs, typically single-instruction multiple-data (SIMD) programs. Shader 360 can perform various types of work that can utilize dedicated memory, including pixel shading tasks, vertex processing, or general computational tasks. As shown, shader 360 can initiate mapping requests using dedicated addresses and receive virtual addresses mapped to dedicated addresses. Shader 360 can then provide the virtual addresses to a cache / memory hierarchy, which, if needed, translates the virtual addresses in the global memory space into physical addresses in memory elements. As shown, shader 360 can also send page reservation requests and receive page grants (if there are enough pages in the page pool).

[0045] In some implementations, the PTC 310 is configured to cache page table entries. Note the following reference... Figure 4 A detailed discussion includes an exemplary hierarchical page table structure comprising page tables, page directories, and page index entries. In some implementations, each PTC entry includes multiple (e.g., 2, 4, 8, etc.) dedicated to virtual translation. The PTC 310 can implement a Least Recently Used (LRU) replacement strategy. The PTC 310 can implement various settings / path implementations and buffer depths (e.g., for storing received requests or received page table information), and these parameters can be configurable. The label for each entry can be part of a hash of a dedicated address. Each entry can also include a field indicating the number of incomplete requests for that entry (and in some implementations, the entry is replaced only when that count is zero).

[0046] For page reservation, PTC 310 can communicate with distributed page manager 345, which in turn can communicate with global page manager 350 to determine if enough pages are available and decrement the page count if a grant request is made. If a page table entry corresponding to a private address exists in PTC 310, it is configured to provide the specified virtual address from that entry. If the requested page table entry does not exist in PTC 310 (cache miss), it sends the private address to memory allocator 220 and receives the mapped virtual address (in some embodiments, memory allocator 220 may provide multiple virtual addresses, for example, those virtual addresses sharing the same mask bit for caching). In the illustrated embodiment, memory allocator 220 is also configured to provide the virtual address of the page table page to PTC 310. Each PTC 310 may include a page queue (not shown) configured to queue received page information, and page queues 330 and 335 of PCC 322 and PDC 324 may operate in a similar manner for their respective caches.

[0047] In some implementations, the PTC entry includes a page table base address, which avoids the need to request this information from a higher-level cache upon eviction. In some implementations, the cache described herein includes one or more additional buffers or FIFOs, including, for example, a hit FIFO, a delayed FIFO / buffer, and a write buffer for communication between tag checking circuitry and data cache circuitry. Therefore, in some implementations, requests can be returned out of order. Various features of the PTC can be similarly implemented for the PCC 322 or PDC 324.

[0048] In some implementations, PDC 324 is configured as a cached page directory entry. PTC arbitrator 340 can arbitrate among multiple page table caches to select which requests are allowed to access PDC 324 in a given cycle. PTC can access PDC when PDC has a cache miss. In some implementations, PCC 322 is configured as a cached page directory entry. PDC 324 can access PCC when PCC has a cache miss.

[0049] In some implementations, the distributed page manager 345 is configured to communicate with the global page manager 345 to retain pages from the page pool and release pages after they are no longer in use. In some implementations, the global page manager 350 is configured to communicate with multiple distributed page managers. In some implementations, the global page manager 350 is configured to generate an interrupt if a counter tracking the number of pages in the page pool goes too low, and the device can take corrective action based on this interrupt.

[0050] Global Memory (GM) 365 is a global memory space accessible via virtual addresses. In some embodiments, the memory of a computing device is consolidated within Global Memory 365, allowing various dedicated or shared memory spaces to be backed up within Global Memory 365. Note that the device can implement the global memory space using a memory hierarchy with one or more data cache levels and backup storage elements. In some embodiments, the disclosed techniques can provide efficient cache access patterns within a data cache hierarchy.

[0051] In various implementation schemes, Figure 3Various components can support out-of-order return of requested information, which can provide low latency. In some implementations, portions of the page pool can be reserved for specific types of work, for example, to allow producer-consumer relationships and protect a portion of the pool for consumer-type work. In some implementations, the device is configured to allow software adjustment of the page pool size. In some implementations, the driver allocates space in memory for the page's ring buffer and fills the addresses associated with those pages. A page pool descriptor table can describe the layout of each page pool that is accessible to software. In some implementations, this can allow developers to create different page pools for different applications, contexts, channels, etc.

[0052] In some implementations, the graphics processor includes coherence circuitry configured to maintain at least partial coherence of page tables across programmable shaders. The coherence circuitry can also maintain at least partial coherence of page tables across multiple programmable shader processors included in the same GPU. This allows dedicated memory allocations to migrate from one shader processor to another. Furthermore, the coherence circuitry can allow GPU-wide dedicated memory allocations.

[0053] Example page table hierarchical structure

[0054] Figure 4 This is a diagram illustrating an exemplary page table hierarchy according to some embodiments. Note that this page table hierarchy for translating from dedicated memory space to virtual memory space (e.g., global memory) may be separate from the page tables used by the MMU to translate virtual addresses to physical addresses. However, in some embodiments, two page table hierarchies may be constructed similarly.

[0055] In the illustrated implementation, the device is configured to generate a Hash Private Address (HPA) by performing a hash function on the provided private address. The hash can map a number of IDs to the same page table page. For example, this can allow adjacent SIMD groups of shader programs to share page table pages. In some implementations, such as Figure 4 As shown, different bit fields of the hashed private address are used to access different levels in the page table hierarchy. Note that the private address can be processed before hashing, for example, to rearrange fields, convert a hardware ID to a virtual ID, etc. The hardware ID can be used to track limited hardware resources and allow devices to track jobs in flight. The virtual ID allows for preemption of thread groups, for example, one work set is swapped out while another work set takes over the same hardware resources. In some implementations, when a corresponding thread group is preempted, the PTC is responsible for writing out a data structure containing the tokens of the preempted kernel and thread group along with the corresponding virtual ID.

[0056] In the illustrated example, the higher bits of HPA are used to index into the page directory page to select the page directory base address and mask. As shown, each page directory entry includes a page directory mask and a page directory base address. The base address points to the page directory address. For a specific number of consecutive page directory entries in a page directory page (e.g., 1, 2, 4, 8, etc.), the mask bits can each indicate whether any of those entries are valid. The memory allocator 220 can use the mask to determine when to invalidate and release a page, for example, after canceling a mapping request has cleared all its mask bits. Thus, in various embodiments, the mask can advantageously allow the page table hierarchy to be dynamically dismantled when it is no longer needed. While bitmasks have been discussed herein for illustrative purposes, various encodings can be used in other embodiments. For example, a count field can count the number of valid entries in a portion of the second lowest level of the hierarchy.

[0057] In the illustrated example, a higher-bit control multiplexer based on HPA is used. The page directory may include a set of entries for each kick slot, where a kick is a unit of work to be processed by the graphics unit. Note that entries at each level in the hierarchical structure may include valid fields (e.g., bits), but valid fields are not shown for illustrative purposes.

[0058] In the illustrated example, the higher-middle bits of the HPA are used to index into the page directory page indicated by the selected PC base address. As shown, each page directory entry includes a page directory mask and a page directory base address. The mask can be used similarly to the PC mask described above. For a specific number of consecutive page table entries in a page table page, the mask bits indicate whether any of those entries are valid. The base address points to the page table address.

[0059] In the illustrated example, the lower-middle bits of the HPA are used to index into the page table page indicated by the selected PD base address. As shown, each page table entry includes a page table mask and a page table base address. The base address points to a virtual page. For a specific number of consecutive virtual address entries in a virtual page, the mask bits indicate whether any of those entries are valid.

[0060] In the illustrated example, the lower bits of HPA are used to index the virtual address mask and virtual address into the virtual page to access the private address. The VA mask field tracks whether sectors have been written to memory, and its bits can be used as indicators of which sectors have been modified / dirty. For clean translation-no-map requests with clean VA mask bits, the requested data may not need to be returned from memory.

[0061] Example configuration of a page hierarchy structure

[0062] Figure 5This is a flowchart illustrating an exemplary technique, according to some embodiments, for mapping private addresses to virtual addresses when page tables are not set. In some embodiments, this can be omitted when page table information has already been cached or allocated. Figure 5 Various elements; Figure 5 Examples are provided where no page table, page name, or page directory entry for mapping is initially valid.

[0063] At 510, in the illustrated implementation, shader 360 sends a mapping request (e.g., a translation-mapping request) to PTC 310, and the request includes a private address in a private memory space.

[0064] At 520, in the illustrated implementation, PTC 310 determines that a miss has occurred, for example, because it does not include an entry whose label matches a private address. The PTC then sends a page table base address lookup request to memory allocator 220. Memory allocator 220 arbitrates between the PTC requests and processes the lookup request at PDC 324 when the request wins the arbitration.

[0065] At 530, in the illustrated implementation, if a private address in the PDC is not found, the PDC sends a page directory base address lookup request to the PCC 322.

[0066] At 540, in the illustrated implementation, a private address is not hit in the PCC, which checks the requested page directory (PC). This check can utilize on-chip pointers to determine that the PC does not exist. In the illustrated example, the PCC requests the distributed page manager 345 to allocate pages for the page directory.

[0067] At 550, in the illustrated implementation, the distributed page manager returns unused pages, and the PCC requests a program directory entry from memory (e.g., read from an offset based on a portion of the PC base address and a private address). The PCC may update the on-chip pointer to point to the PC base address.

[0068] At 560, in the illustrated implementation, the entry (page directory) returned by the PC is invalid, so the PCC requests the page manager to allocate pages for the page directory.

[0069] At 570, in the illustrated implementation, the distributed page manager 345 returns unused pages from the page directory to the PCC, which updates cache entries and returns the page directory base address to the page directory cache. The PDC requests page directory entries from memory.

[0070] At 580, in the illustrated implementation, the returned page directory entry (page table) is invalid, so the PDC makes a request to the distributed page manager to allocate pages for the page table.

[0071] At 590, in the illustrated implementation, the distributed page manager 345 returns the unused pages of the page table, and the PDC updates the cache entries. The PDC also sends a request to the PCC to set the page directory mask and returns the page table base address to the PDC.

[0072] At 595, in the illustrated implementation, the PTC initializes a page table entry and requests to retrieve a page table entry from memory. The page table is invalid, so the PTC requests the distributed page manager 345 to allocate a page for dedicated data. The page manager 345 provides an unused page. The PTC updates the cache entry, sends a request to set the page table mask to the memory allocator 220 (which can arbitrate among multiple requests), and returns the virtual address corresponding to the updated PTC entry to the shader 360.

[0073] In this example, the device dynamically sets up the entire portion of the page table hierarchy required to map private addresses to virtual addresses, including appropriately adjusting the corresponding mask to reflect the settings. If a portion of the hierarchy has already been generated, this can be skipped. Figure 5 Various elements, and can utilize existing information.

[0074] Exemplary methods

[0075] Figure 6 This is a flowchart illustrating an exemplary method for processing access requests that include a private address, according to some implementation schemes. Figure 6 The methods shown can be used in conjunction with any of the computer circuit systems, systems, devices, components, or parts disclosed herein. In various embodiments, some of the method elements shown may be performed concurrently in a different order than that shown, or may be omitted. Additional method elements may also be performed as needed.

[0076] At 610, in the illustrated embodiment, a dedicated memory allocation circuit (e.g., circuit 220) receives a request including a first address in the dedicated memory space. For example, the request could be a translation-mapping request.

[0077] At 620, in the illustrated implementation, a dedicated memory allocation circuit determines whether a page in the virtual space is mapped for a first address. In some implementations, this may include checking caches at multiple levels of the page table hierarchy to determine whether a page is mapped. In some implementations, a first cache circuit (e.g., PTC 310) is configured to cache page table entries corresponding to requests from the first circuit. In some implementations, a second cache circuit (e.g., PDC 324 or PCC 322) is configured to cache page table information at one or more non-lowest levels of the page table hierarchy for multiple different requesting circuits.

[0078] At 630, in the illustrated embodiment, in response to determining that a page is not mapped, the dedicated memory allocation circuitry generates page table information for the dedicated memory space and maps the dedicated memory page at the first address to the virtual space. For example, this may include generating a page directory, page name list, and page table entries for the dedicated memory pages. In some embodiments, the page table information includes multiple hierarchical levels, and the means is configured to at each level (e.g., Figure 4 The mask field maintains tracking information indicating whether entries at lower levels are valid. In some embodiments, the device is configured to release pages of the page table hierarchy in response to one or more unmapping requests that cause the tracking information indication page to have no corresponding valid entries.

[0079] At 640, in the illustrated implementation, the system generates a virtual address for the request based on the mapped private memory pages. The private memory allocation circuitry can then provide the virtual address back to the requesting circuitry. In some implementations, in order to generate a virtual address for the request based on the mapped private memory pages, the private memory allocation circuitry is configured to generate a hash of a first address and access multiple levels of the page table hierarchy based on portions of the hash result.

[0080] At 650, in the illustrated implementation, the system translates the virtual address into a physical address and uses the physical address to access the requested data. The device is configured to access the first page table hierarchy (e.g., Figure 4 A hierarchical structure (e.g., a traditional page table hierarchy) is used to translate the first address into a virtual address, and a second page table hierarchy (e.g., a traditional page table hierarchy) is accessed to translate the virtual address into a physical address.

[0081] In some embodiments, the apparatus is configured to, for example, maintain a count of available pages in a page pool, and dedicated memory allocation circuitry is configured to decrement the count and provide an authorized response to page reservation requests. In some embodiments, the dedicated memory allocation circuitry includes multiple distributed units and a global unit, each distributed unit dedicated to a set of shader processors, and the global unit configured to communicate with the distributed units to manage page requests.

[0082] In some implementations, the dedicated memory allocation circuitry is configured to unmap virtual pages from dedicated memory pages in response to an unmapping request. In some implementations, the dedicated memory allocation circuitry is configured to process translate-no-mapping requests that specify translating a dedicated address to a virtual address where the corresponding dedicated memory page is mapped to a dedicated address, but not otherwise mapping the dedicated virtual page at that address.

[0083] Exemplary device

[0084] Now for reference Figure 7 This figure illustrates a block diagram of an exemplary embodiment of device 700. In some embodiments, the components of device 700 may be included within a system-on-a-chip. In some embodiments, device 700 may be included in a mobile device that may be battery-powered. Therefore, the power consumption of device 700 may be an important design consideration. In the illustrated embodiment, device 700 includes a structure 710, a computing complex 720, an input / output (I / O) bridge 750, a cache / memory controller 745, a graphics unit 150, and a display unit 765. In some embodiments, in addition to and / or replacing the components shown, device 700 may include other components (not shown), such as video processor encoders and decoders, image processing or recognition elements, computer vision elements, etc.

[0085] Structure 710 may include various interconnects, buses, MUXs, controllers, etc., and may be configured to facilitate communication between various components of device 700. In some embodiments, portions of structure 710 may be configured to implement various different communication protocols. In other embodiments, structure 710 may implement a single communication protocol, and components coupled to structure 710 may internally switch from a single communication protocol to other communication protocols.

[0086] In the illustrated embodiments, computing complex 720 includes a bus interface unit (BIU) 725, a cache 730, and cores 735 and 740. In various embodiments, computing complex 720 may include a variety of numbers of processors, processor cores, and / or caches. For example, computing complex 720 may include one, two, or four processor cores, or any other suitable number. In one embodiment, cache 730 is a set of associative L2 caches. In some embodiments, cores 735 and / or 740 may include internal instruction and / or data caches. In some embodiments, coherence units (not shown) in architecture 710, cache 730, or elsewhere in device 700 may be configured to maintain coherence between the various caches of device 700. BIU 725 may be configured to manage communication between computing complex 720 and other elements of device 700. Processor cores such as cores 735 and 740 may be configured to execute instructions of a specific instruction set architecture (ISA) that may include operating system instructions and user application instructions.

[0087] The cache / memory controller 745 can be configured to manage data transfer between the structure 710 and one or more caches and / or memories. For example, the cache / memory controller 745 can be coupled to an L3 cache, which in turn can be coupled to system memory. In other embodiments, the cache / memory controller 745 can be directly coupled to memory. In some embodiments, the cache / memory controller 745 may include one or more internal caches.

[0088] As used herein, the term "coupled to" can indicate one or more connections between elements, and coupling can include intermediate elements. For example, in Figure 7 In this context, the graphics unit 150 can be described as being "coupled" to memory via structure 710 and cache / memory controller 745. In contrast, in... Figure 7 In the exemplary implementation, the graphics unit 150 is "directly coupled" to the structure 710 because there are no intermediate elements.

[0089] The graphics unit 150 may include one or more processors and / or one or more graphics processing units (GPUs). For example, the graphics unit 150 may receive graphics-oriented instructions, such as... Metal or Instructions. The graphics unit 150 may execute dedicated GPU instructions or perform other operations based on received graphics-oriented instructions. The graphics unit 150 may typically be configured to process large blocks of data in parallel and may construct an image in a frame buffer for output to a display. The graphics unit 150 may include transformation, lighting, triangle, and / or rendering engines in one or more graphics processing pipelines. The graphics unit 150 may output pixel information for displaying the image. In various embodiments, the programmable shader 160 may include highly parallel execution cores configured to execute graphics programs, which may include pixel tasks, vertex tasks, and computation tasks (which may be graphics-dependent or may not be graphics-dependent).

[0090] In some implementations, the graphics unit 150 includes the memory allocator circuitry, shader circuitry, MMU, etc., discussed herein.

[0091] Display unit 765 can be configured to read data from a frame buffer and provide a stream of pixel values ​​for display. In some embodiments, display unit 765 can be configured to display a pipeline. Additionally, display unit 765 can be configured to blend multiple frames to produce an output frame. Furthermore, display unit 765 may include one or more interfaces for coupling to a user display (e.g., a touchscreen or an external display). Or embedded display port (eDP)).

[0092] I / O bridge 750 may include various components configured to implement functions such as Universal Serial Bus (USB) communication, security, audio, and / or low-power always-on functionality. I / O bridge 750 may also include interfaces such as pulse width modulation (PWM), general purpose input / output (GPIO), serial peripheral interface (SPI), and / or internal integrated circuit (I2C). Various types of peripheral devices and equipment can be coupled to device 700 via I / O bridge 750.

[0093] Exemplary computer-readable media

[0094] Various exemplary circuits have been described in detail above in this disclosure. It is intended that this disclosure cover not only embodiments including such circuit systems, but also computer-readable storage media including design information specifying such circuit systems. Therefore, this disclosure is intended to support claims that cover not only means including the disclosed circuit systems, but also storage media specifying circuit systems in a format recognized by a manufacturing system configured to generate hardware (e.g., integrated circuits) including the disclosed circuit systems. Claims regarding such storage media are intended to cover entities that, for example, generate circuit designs but do not themselves manufacture such designs.

[0095] Figure 8 This is a block diagram illustrating an exemplary non-transitory computer-readable storage medium for storing circuit design information according to some embodiments. In the illustrated embodiment, a semiconductor manufacturing system 820 is configured to process design information 815 stored on a non-transitory computer-readable medium 810 and manufacture an integrated circuit 830 based on the design information 815.

[0096] The non-transitory computer-readable storage medium 810 may include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 810 may be an installation medium, such as a CD-ROM, floppy disk, or magnetic tape device; computer system memory or random access memory such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; non-volatile memory such as flash memory, magnetic media, such as hard disk drives or optical storage devices; registers, or other similar types of memory elements. The non-transitory computer-readable storage medium 810 may also include other types of non-transitory memory or combinations thereof. The non-transitory computer-readable storage medium 810 may include two or more memory media that may reside in different locations, such as different computer systems connected via a network.

[0097] Design information 815 can be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information 815 can be used by semiconductor manufacturing system 820 to manufacture at least a portion of integrated circuit 830. The format of design information 815 can be recognized by at least one semiconductor manufacturing system 820. In some embodiments, design information 815 may also include one or more cell libraries specifying the synthesis and / or layout of integrated circuit 830. In some embodiments, the design information is specified, wholly or partially, in the form of a netlist specifying cell library elements and their connectivity. Design information 815 acquired separately may or may not include sufficient information for manufacturing the corresponding integrated circuit. For example, design information 815 may specify circuit elements to be manufactured but not their physical layout. In this case, design information 815 may need to be combined with layout information to actually manufacture the specified circuit system.

[0098] In various implementations, integrated circuit 830 may include one or more custom macrocells, such as memory, analog or mixed-signal circuitry, etc. In this case, design information 815 may include information associated with the included macrocells. Such information may include, but is not limited to, a circuit diagram capture database, mask design data, behavioral models, and device or transistor-level netlists. As used herein, mask design data may be formatted according to a Graphical Data System (GDSII) or any other suitable format.

[0099] The semiconductor manufacturing system 820 may include any of the various suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of the deposited material, modifying the material (e.g., by doping the material or by using ultraviolet light treatment to modify the dielectric constant), etc. The semiconductor manufacturing system 820 may also be configured to perform various tests on the manufactured circuits for proper operation.

[0100] In various implementations, integrated circuit 830 is configured to operate according to a circuit design specified in design information 815, which may include any of the functions described herein. For example, integrated circuit 830 may include Figure 1B , Figure 2 , Figure 3 or Figure 7 Any of the various components shown herein. Additionally, integrated circuit 830 can be configured to perform the various functions described herein in conjunction with other components. Furthermore, the functionality described herein can be performed by multiple interconnected integrated circuits.

[0101] As used herein, a phrase in the form of “design information specifying the design of a circuit configured to…” does not imply that the circuit in question must be manufactured in order to satisfy this element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated action or will include the specified components.

[0102] ***

[0103] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of this disclosure, even where only a single embodiment is described with respect to a particular feature. The examples of features provided in this disclosure are intended to be illustrative and not limiting, unless otherwise stated. The foregoing description is intended to cover such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art to the effectiveness of this disclosure.

[0104] The scope of this disclosure includes any feature or combination of features or any generalization thereof disclosed herein (expressly or implicitly), whether or not it alleviates any or all the problems addressed herein. Therefore, new claims may be made for any such combination of features during the proceedings of this patent application (or a patent application claiming priority thereto). Specifically, referring to the appended claims, features of dependent claims may be combined with features of independent claims, and features from the respective independent claims may be combined in any suitable manner rather than solely by the specific combinations listed in the appended claims.

Claims

1. An apparatus comprising: A first circuit is configured to request access to the dedicated memory space using a first address in the dedicated memory space. A dedicated memory allocation circuit, wherein the dedicated memory allocation circuit is configured to: Determine whether a page in the virtual space is mapped to the first address; In response to determining that a page is not mapped, page table information for the dedicated memory space is generated and the dedicated memory page at the first address is mapped to the virtual space; as well as Based on the mapped dedicated memory page, the first address is translated into a virtual address for the request; as well as A memory management unit (MMU) circuit configured to translate the virtual address into a physical address in the storage element of the device.

2. The apparatus according to claim 1, further comprising: A first cache circuit is configured to cache page table entries corresponding to requests from the first circuit.

3. The apparatus of claim 2, wherein the dedicated memory allocation circuit comprises: A second cache circuit is configured to cache page table information at one or more non-lowest levels of the page table hierarchy for multiple different request circuits.

4. The apparatus of claim 3, wherein the second cache circuit comprises a page name cache and a page directory cache.

5. The apparatus of claim 1, wherein the apparatus is configured to maintain a count of available pages; and In response to a page reservation request, the dedicated memory allocation circuit is configured to decrement the count and provide a page grant response.

6. The apparatus of claim 1, wherein the dedicated memory allocation circuitry comprises a plurality of distributed units and a global unit, each distributed unit being dedicated to a set of shader processors, the global unit being configured to communicate with the distributed units to manage page requests.

7. The apparatus of claim 1, wherein the dedicated memory allocation circuit is further configured to: Processing translation-no-mapping requests, which specify translating a private address to a virtual address when the corresponding private memory page is mapped to a virtual address of a private address, but not otherwise mapping the private virtual page of the address.

8. The apparatus of claim 1, wherein the dedicated memory allocation circuit is further configured to: In response to a demapping request, unmap the virtual page from the dedicated memory page.

9. The apparatus of claim 1, wherein, in order to translate the first address into the virtual address for the request based on the mapped dedicated memory page, the dedicated memory allocation circuit is configured to generate a hash of the first address and to access multiple levels of the page table hierarchy based on a portion of the hash result.

10. The apparatus of claim 1, wherein the page table information comprises a plurality of hierarchical levels, wherein the apparatus is configured to maintain tracking information at each level indicating whether an entry at a lower level is valid, and wherein the apparatus is configured to release pages of the page table hierarchy in response to one or more unmapping requests that cause the tracking information to indicate that the page does not have any corresponding valid entry.

11. The apparatus of claim 1, wherein the apparatus is configured to access a first page table hierarchy to translate the first address into the virtual address, and to access a second page table hierarchy to translate the virtual address into the physical address.

12. A non-transitory computer-readable storage medium having stored thereon design information specifying at least a portion of a design of a hardware integrated circuit in a format recognizable by a semiconductor manufacturing system, the semiconductor manufacturing system being configured to use the design information to manufacture the circuit according to the design, wherein the design information specifying the circuit includes: A first circuit is configured to request access to the dedicated memory space using a first address in the dedicated memory space. A dedicated memory allocation circuit, wherein the dedicated memory allocation circuit is configured to: Determine whether a page in the virtual space is mapped to the first address; In response to determining that a page is not mapped, page table information for the dedicated memory space is generated and the dedicated memory page at the first address is mapped to the virtual space; as well as Based on the mapped dedicated memory page, the first address is translated into a virtual address for the request; as well as A memory management unit (MMU) circuit configured to translate the virtual address into a physical address in a memory element.

13. The non-transitory computer-readable storage medium according to claim 12, further comprising: A first cache circuit is configured to cache page table entries corresponding to requests from the first circuit. as well as A second cache circuit is configured to cache page table information at one or more non-lowest levels of the page table hierarchy for multiple different request circuits.

14. The non-transitory computer-readable storage medium of claim 13, wherein the second cache circuitry includes a page name cache and a page directory cache.

15. The non-transitory computer-readable storage medium of claim 12, wherein the dedicated memory allocation circuit is further configured to: Processing translation-no-mapping requests, which specify translating a private address to a virtual address when the corresponding private memory page is mapped to a virtual address of a private address, but not otherwise mapping the private virtual page of the address.

16. The non-transitory computer-readable storage medium of claim 12, wherein, in order to translate the first address into the virtual address for the request based on the mapped dedicated memory pages, the dedicated memory allocation circuitry is configured to generate a hash of the first address and to access multiple levels of the page table hierarchy based on a portion of the hash result.

17. The non-transitory computer-readable storage medium of claim 12, wherein the circuitry is configured to access a first page table hierarchy to translate the first address into the virtual address, and to access a second page table hierarchy to translate the virtual address into the physical address.

18. A method comprising: The dedicated memory allocation circuit receives a request including a first address in the dedicated memory space; The dedicated memory allocation circuit determines whether a page in the virtual space is mapped to the first address; In response to determining that a page is not mapped, the dedicated memory allocation circuit generates page table information for the dedicated memory space and maps the dedicated memory page at the first address to the virtual space; Based on the mapped dedicated memory page, the first address is translated into a virtual address for the request; as well as The virtual address is translated into a physical address and the requested data is accessed using the physical address.

19. The method of claim 18, further comprising: The first cache circuit caches the page table entries corresponding to the request from the circuit that issued the request; as well as The second cache circuit caches the page name and page directory information.

20. The method of claim 18, wherein translating the first address to the virtual address includes accessing a first page table hierarchy to translate the first address to the virtual address, and wherein translating the virtual address to a physical address includes accessing a second page table hierarchy.

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