Multi-terminal phase change memory device

Abstract

A phase change memory device is provided. The phase change memory device includes a phase change memory material within an electrically insulating wall, a first heater terminal in the electrically insulating wall, and two read terminals in the electrically insulating wall.

Description

Background Technology

[0001] The present invention generally relates to a phase change memory (PCM) device, and more specifically to a phase change memory (PCM) device having multiple terminals.

[0002] Phase change memory (PCM) can establish the state of memory cells using the resistivity difference between an amorphous phase and a crystalline phase, where the crystalline and amorphous states of the PCM material can have detectably different resistivity values. The amorphous state of the PCM material can have high resistivity. Summary of the Invention

[0003] According to an embodiment of the present invention, a phase change memory device is provided. The phase change memory device includes a phase change memory material within an electrically insulating wall, a first heater terminal within the electrically insulating wall, and two read terminals within the electrically insulating wall.

[0004] According to another embodiment of the present invention, a phase change memory device is provided. The phase change memory device includes a phase change memory material located within an electrically insulating wall. The phase change memory device also includes two heater terminals and two read terminals within the electrically insulating wall, wherein the heater terminals are located on opposite sides of the phase change memory material, and the read terminals are located on opposite sides of the two heater terminals.

[0005] According to yet another embodiment of the present invention, a method for forming a phase change memory device is provided. The method includes forming a substrate layer on a substrate. The method further includes forming a first read terminal and a first heater terminal in the substrate layer. The method further includes forming a patterned phase change material having a first phase on the substrate layer, and forming an encapsulation layer on the patterned phase change material. The method further includes forming a second read terminal in the encapsulation layer, wherein the second read terminal is in electrical contact with the patterned phase change material.

[0006] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which will be read in conjunction with the accompanying drawings. Attached Figure Description

[0007] Referring to the following figures, the following description will provide details of preferred embodiments, in which:

[0008] Figure 1 This is a cross-sectional side view of a phase-change memory device having a pair of write terminals and a pair of separate read terminals according to an embodiment of the present invention;

[0009] Figure 2 This is a cross-sectional side view of a phase-change memory device during the write process according to an embodiment of the present invention;

[0010] Figure 3 This is a cross-sectional side view of a phase-change memory device during the reading process according to an embodiment of the present invention;

[0011] Figure 4 This is a cross-sectional side view showing a fully configured phase-change memory device according to an embodiment of the present invention;

[0012] Figure 5 This is a cross-sectional side view of a phase-change memory device that has been partially reset according to an embodiment of the present invention;

[0013] Figure 6 This is a cross-sectional side view showing a phase-change memory device that has been partially configured according to an embodiment of the present invention;

[0014] Figure 7 This is a cross-sectional side view showing a fully configured phase-change memory device according to an embodiment of the present invention;

[0015] Figure 8 This is a cross-sectional side view of a phase-change memory device according to another embodiment of the present invention, which has a pair of write terminals and different arrangements of read terminals showing the write process;

[0016] Figure 9 This is a cross-sectional side view of a phase-change memory device according to another embodiment of the present invention, which has a pair of write terminals and different arrangements of read terminals showing the read process;

[0017] Figure 10 This is a cross-sectional side view of a phase-change memory device having a three-terminal arrangement illustrating the writing process, according to another embodiment of the present invention;

[0018] Figure 11 This is a cross-sectional side view of a phase-change memory device having a three-terminal arrangement illustrating a read process, according to another embodiment of the present invention;

[0019] Figure 12 This is a cross-sectional side view of a substrate layer according to another embodiment of the present invention;

[0020] Figure 13 This is a cross-sectional side view showing heater terminals and reading terminals formed in a substrate layer according to another embodiment of the present invention;

[0021] Figure 14 This is a cross-sectional side view showing a phase change material layer formed on a substrate layer according to another embodiment of the present invention;

[0022] Figure 15 This is a cross-sectional side view showing a phase change material layer patterned on a substrate layer according to another embodiment of the present invention;

[0023] Figure 16 This is a cross-sectional side view showing an encapsulation layer formed on the patterned phase change material layer and the substrate layer according to another embodiment of the present invention; and

[0024] Figure 17 This is a cross-sectional side view showing a second heater terminal and a second read terminal formed in an encapsulation layer according to another embodiment of the present invention. Detailed Implementation

[0025] Embodiments of the present invention provide a multi-terminal phase-change memory (PCM) device that exhibits less resistance drift than a two-terminal PCM device. Using separate read and write terminals to control the phase transition of the PCM provides a more linear conductance for analog computing devices. The multi-terminal device avoids amorphous resistivity drift caused by using the heater terminal for read cycles.

[0026] Embodiments of the present invention provide a method for manufacturing a multi-terminal phase-change memory (PCM) device. This method avoids amorphous resistivity drift by forming separate heaters to control the writing process that alters the phase of the PCM material. Four electrical terminals are formed, two of which are used to read data stored in the PCM device. Furthermore, the two separate terminals, which alter the volume of the amorphous PCM material, enhance the control over the phase shift of the PCM device.

[0027] Embodiments of the present invention provide a method for reading and writing to a multi-terminal phase-change memory (PCM) device that avoids amorphous resistivity drift. Using two terminals to read data stored in the PCM device and using two separate terminals to write data into the device by changing the relative volume of the amorphous and crystalline PCM materials enhances control over the phase shift of the PCM device. The read current path can bypass the amorphous volume of the PCM using a separate read terminal.

[0028] Embodiments of the present invention provide a multi-terminal phase change memory (PCM) device that can store multiple data bits by controlling the relative volume of amorphous and crystalline phase change memory materials in the electrical read path of the device.

[0029] Exemplary applications / uses that can be applied to this invention include, but are not limited to: non-volatile memory devices, storage-class memory, embedded caches, weighted storage for analog computing applications, and application-specific integrated circuits (ASICs).

[0030] It should be understood that various aspects of the invention will be described based on the given illustrative framework; however, other frameworks, structures, substrate materials, and process features and steps may vary within the scope of various aspects of the invention.

[0031] Referring now to the accompanying drawings, where similar numbers denote the same or similar elements and originally seen... Figure 1 The image shows a cross-sectional side view of a phase-change memory device having a pair of write terminals and a separate pair of read terminals according to an embodiment of the present invention.

[0032] In one or more embodiments, the phase change memory device 100 may have a phase change material in a first phase 110 and a phase change material in a second phase 115, wherein the first phase and the second phase have different resistivities. An electrically insulating wall 120 may surround the phase change material to contain current flowing to the phase change material.

[0033] In one or more embodiments, the phase change memory material may be Ge2Sb2Te5 (GST), wherein GST may have a crystalline phase and an amorphous phase, wherein the crystalline phase has a lower resistivity than the amorphous phase. The crystalline phase can be transformed into an amorphous phase by quenching the phase change material in the amorphous phase by heating the crystalline phase to a phase change temperature and rapidly cooling the amorphous phase change material.

[0034] In various embodiments, the phase-change memory device 100 may have two read terminals 130 formed in an electrically insulating wall 120, each of which is electrically coupled to a phase-change material volume. In various embodiments, the phase-change memory device 100 may have two heater terminals 140 formed in the electrically insulating wall 120, each of which is electrically coupled to a phase-change material volume. The two heater terminals 140 may be formed in opposing electrically insulating walls 120, wherein the two heater terminals 140 may be directly opposite each other across an intermediate volume of the phase-change memory material. The two read terminals 130 may be on opposite sides of the two or more heater terminals 140, such that current flows between the two read terminals 130. In various embodiments, the read terminals 130 may be on opposing electrically insulating walls 120.

[0035] In various embodiments, the heater terminal 140 may have a width or diameter of less than 40 nanometers (nm), or in the range of about 5 nm to about 40 nm, or about 10 nm to about 30 nm, or about 10 nm to about 20 nm, although other widths or diameters are considered.

[0036] In various embodiments, the read terminal 130 may have a width or diameter greater than 40 nanometers (nm), or in the range of about 40 nm to about 100 nm, or about 50 nm to about 90 nm, or about 70 nm to about 80 nm, although other widths or diameters are contemplated. The read terminal 130 may have a larger width or diameter to reduce resistance during read operations, while the heater terminal 140 may have a smaller width or diameter to concentrate heating on a smaller area of ​​the PCM.

[0037] In various embodiments, the heater terminal 140 may be made of a metal compound, including but not limited to metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and combinations thereof; metal silicides such as titanium silicide (TiSi), cobalt silicide (CoSi), nickel silicide (NiSi), and combinations thereof; and metal carbides such as titanium carbide (TiC), tantalum carbide (TaC), high-resistivity metals such as tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), or tantalum (Ta), and combinations thereof.

[0038] In one or more embodiments, the volume of the phase change material within the electrically insulating wall 120 can be in a first phase 110 and a second phase 115. The second phase 115 can be an amorphous phase with a higher resistivity than the crystalline phase. The shape of the second phase 115 can be hemispherical and overlap with the edge of the heater terminal 140, wherein the diameter and shape of the second phase 115 region of the phase change material can be determined by heat transfer from the heater terminal 140 to the phase change material. In different embodiments, the second phase 115 region of the phase change material can be hemispherical. By controlling the amount of amorphous volume, the continuum of resistive states can be programmed. In different embodiments, the size of the volume of the phase change material within the electrically insulating wall 120 can be in the range of approximately 50 nm (length) x 50 nm (width) x 50 nm (height) to approximately 250 nm (length) x 250 nm (width) x 100 nm (height), (0.000123 μm) 3 From approximately 0.00625 μm 3 ), or approximately 100nm (length) x 100nm (width) x 50nm (height) to approximately 150nm (length) x 150nm (width) x 100nm (height), (0.0005um 3 From approximately 0.00225um 3 However, other lengths, widths, heights, and volumes can be envisioned.

[0039] Figure 2 This is a cross-sectional side view illustrating a phase-change memory device during the write process according to an embodiment of the present invention.

[0040] In one or more embodiments, information can be written into the phase change memory device 100 by allowing current to pass from a first heater terminal 140 in the electrically insulating wall 120 through a region of the phase change material to a second heater terminal 140 in the electrically insulating wall 120 (at a distance from the first heater terminal 140). The current passing through each of the heater terminals 140 can increase the temperature of the heater terminal 140 due to resistive heating, while the high conductivity of the first phase 110 of the phase change material allows current to be conducted without sufficient heating to induce a phase change. The current through the heater terminals 140 and the first phase 110 of the phase change material (e.g., the crystalline phase) can be a current pulse I in the range of about 50 microamperes (µA) to about 900 µA, or about 50 microamperes (µA) to about 900 µA, or about 70 µA to about 900 µA, or about 70 µA to about 800 µA. prog The pulse lasts from about 40 nanoseconds (ns) to about 200 ns, or from about 70 ns to about 150 ns, wherein the current pulse is sufficient to cause resistive heating of the heater terminal 140 and to melt and amorphize the first phase 110 (e.g., crystalline phase) of the phase change material.

[0041] In various embodiments, the heater terminal 140 can generate a temperature increase of the temperature of the surrounding first phase 110 (e.g., crystalline phase) of the phase change material in the range of about 600°C to about 900°C, or about 650°C to about 750°C, wherein the temperature change is sufficient to cause a change in the phase change material in an adjacent region of the phase change material from the first phase 110 (e.g., crystalline phase) to a second phase 115 (e.g., amorphous phase). In various embodiments, the region of the phase change material that is converted into the second phase 115 (e.g., amorphous phase) can be a protrusion having a hemispherical shape adjacent to each of the heater terminals 140.

[0042] In different embodiments, the crystalline phase of the phase change material may have a resistivity in the range of about 0.01 ohm-cm to about 6 ohm-cm, or in the range of about 0.1 ohm-cm to about 4 ohm-cm, or about 1 ohm-cm, but other resistivities are possible.

[0043] In different embodiments, the amorphous phase of the phase change material can have a range of approximately 1 x 10⁻⁶. 3 ohm-cm to approximately 1x10 6 Within the range of ohm-cm, or greater than approximately 1x10 6 The resistivity is in ohm-cm, but other resistivities are possible.

[0044] Figure 3 This is a cross-sectional side view showing a phase-change memory device during the reading process according to an embodiment of the present invention.

[0045] In one or more embodiments, the state of the phase-change memory device 100 can be determined by measuring the resistance between two read terminals 130 along an electrical path through a first phase 110 of the phase-change material, wherein at least a portion of the electrical path lies between regions of a second phase 115 of the phase-change material. The read current can bypass the second phase 115 region of the phase-change material.

[0046] The second phase 115 region of the phase change material can be hemispherical, having a radius ranging from about 40 nanometers (nm) to about 70 nm, or from about 50 nm to about 60 nm, wherein heating of the PCM is symmetrical about heater terminals 140. In different embodiments, the normalized conductivity of the PCM device can be related to 1-2R / H, where R is the radius of the hemispherical second phase 115 region and H is the height of the wall of the phase change material volume.

[0047] In different embodiments, the phase-change memory device may have two or more states, for example, two, three, four, or five states. The ratio of the cross-sectional area of ​​the second phase 115 of the phase-change material to the first phase 110 of the phase-change material can determine the state of the phase-change memory device 100. The states of the phase-change material passing through the cross-sectional area may be non-uniform, so the current density passing through the high-conductivity phase material and the low-conductivity phase material may be non-uniform.

[0048] In different embodiments, the state of the phase-change memory device can be determined by measuring the resistance of the device through these read terminals.

[0049] Figure 4 This is a cross-sectional side view showing a fully configured phase-change memory device according to an embodiment of the present invention.

[0050] In one or more embodiments, the phase change memory device 100 can be fully configured by crystallizing the entire volume of the phase change material into the first phase 110 (e.g., the crystalline phase). This can be achieved by fully heating the phase change memory device 100 with a large current followed by a slow decrease in current, allowing the phase change memory material to slowly cool and recrystallize in its crystalline state. When fully configured, the distance D1 between the heater terminals 140 occupied by the first phase 110 of the phase change material can be equal to the full height H of the phase change memory device 100. Therefore, the resistance experienced by the read current will be the resistance of the first phase 110 of the phase change material (e.g., the crystalline phase resistance).

[0051] In various embodiments, the phase-change memory device 100 may have a height in the range of about 40 nm to about 100 nm, although other heights are contemplated. In various embodiments, the phase-change memory device 100 may have a width in the range of about 40 nm to about 300 nm, although other widths are contemplated.

[0052] Figure 5 This is a cross-sectional side view showing a partially configured phase-change memory device according to an embodiment of the present invention.

[0053] In one or more embodiments, the phase change memory device 100 can be partially configured by using a current pulse to amorphize a portion of the first phase 110 of the phase change material between heater terminals 140 and quenching the first phase 110 to form a region of the second phase 115 adjacent to the heater terminals 140. The size and shape of the second phase 115 region can be determined by the amount and duration of the current pulse used to amorphize the first phase 110 of the phase change material. The distance D2 occupied by the first phase 110 of the phase change material can be less than twice the radius of the second phase 115 region, 1-2R / H, than the full height H of the phase change memory device 100. Therefore, the resistance experienced by the read current will be the resistance (e.g., crystalline phase resistance) of the first phase 110 of the phase change material with respect to the cross-sectional distance D2.

[0054] Figure 6 This is a cross-sectional side view showing a partially configured phase-change memory device according to an embodiment of the present invention.

[0055] In one or more embodiments, the phase change memory device 100 can be further partially defined by using current pulses to amorphize a large portion of the first phase 110 of the phase change material between these heater terminals 140 and by quenching the first phase 110 to form a region of the second phase 115 adjacent to these heater terminals 140. The size and shape of the second phase 115 region can be determined by the amount and duration of the current pulses used to amorphize the first phase 110 of the phase change material. The distance D3 occupied by the first phase 110 of the phase change material can be smaller than the cross-sectional distance D2 of the phase change memory device 100 by an increase in radius 1-2R / H of the second phase 115 region. Therefore, the resistance experienced by the read current will be the resistance (e.g., crystalline phase resistance) of the first phase 110 of the phase change material with respect to the cross-sectional distance D3.

[0056] Figure 7 This is a cross-sectional side view showing a fully reset phase-change memory device according to an embodiment of the present invention.

[0057] In one or more embodiments, the phase change memory device 100 can be completely reset by using a current pulse to amorphize even a larger portion of the first phase 110 of the phase change material between heater terminals 140 and quenching the first phase 110 to form a region of the second phase 115 adjacent to the heater terminals 140. The size and shape of the second phase 115 region can be determined by the amount and duration of the current pulse used to amorphize the first phase 110 of the phase change material. The distance D4 occupied by the first phase 110 of the phase change material can be smaller than the cross-sectional distance D3 of the phase change memory device 100 by an increased radius of 1-2R / H of the second phase 115 region. Therefore, the resistance experienced by the read current will be the resistance of the first phase 110 of the phase change material with respect to the cross-sectional distance D4 (e.g., the crystalline phase resistance). In various embodiments, the second phase 115 region does not extend across the entire distance between heater terminals 140, and the entire cross-section of the phase change memory device 100 will not be amorphized. Providing an electrical path through the crystalline phase of the PCM can reduce or avoid resistance drift.

[0058] Different distances D1, D2, D3 and D4 can each identify different states of the phase change memory device 100 based on the resistance between the read terminals 130, and thereby store different data values.

[0059] Figure 8 This is a cross-sectional side view of a phase-change memory device according to another embodiment of the present invention, which has a pair of write terminals and a different arrangement of read terminals showing the write process.

[0060] In another embodiment, both read terminals 130 may be located along the same electrically insulating wall 120 and separated by the two heater terminals 140 and any second phase region 115. Depending on the width of the device, the two read terminals 130 may be spaced apart by a distance ranging from approximately 80 nm to approximately 300 nm, where such distance is sufficient to allow the formation of a second phase 115 region with a predetermined maximum radius. In different embodiments, the two read terminals 130 may be located in the same sidewall of the electrically insulating wall 120.

[0061] In various embodiments, current pulses between opposing heater terminals 140 can be used to write to the phase change memory device 100.

[0062] Figure 9 This is a cross-sectional side view of a phase-change memory device according to another embodiment of the present invention, which has a different arrangement of a pair of write terminals and read terminals showing the read process.

[0063] In one or more embodiments, the state of the phase-change memory device 100 can be determined by passing a read current between two read terminals 130.

[0064] Figure 10 This is a cross-sectional side view of a phase change memory device having a three-terminal arrangement illustrating the writing process, according to another embodiment of the present invention.

[0065] In one or more embodiments, the phase change memory device 100 may have a single heater terminal 140 and two read terminals 130, wherein the read terminal 130 opposite the heater terminal 140 may be used to generate current pulses to write data to the phase change material. A second phase 115 region may be formed adjacent to the single heater terminal 140 and protruding toward one of the two read terminals 130, wherein the second phase 115 region may have an inclined dome shape having a height different from the radius. The distance D5 occupied by the first phase 110 of the phase change material may be between the second phase 115 region and the opposing electrically insulating wall 120.

[0066] Figure 11 This is a cross-sectional side view showing a phase-change memory device with a three-terminal arrangement illustrating the read process, according to another embodiment of the present invention.

[0067] In one or more embodiments, the state of the phase-change memory device 100 can be determined by passing a read current between two read terminals 130.

[0068] Figure 12 This is a cross-sectional side view of a substrate layer according to another embodiment of the present invention.

[0069] In one or more embodiments, a substrate layer 122 may be formed on a substrate 101, wherein the substrate layer 122 may be formed by overlay deposition (e.g., chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), conformal deposition (e.g., atomic layer deposition (ALD), plasma-enhanced ALD (PEALD)), or combinations thereof). The substrate 101 may include a semiconductor material, such as silicon (Si) or silicon germanium (SiGe), on which other devices may be formed.

[0070] In different embodiments, the substrate layer 122 may be an insulating dielectric material, including but not limited to silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), borosilicate carbonitride (SiBCN), and combinations thereof.

[0071] In different embodiments, the substrate layer 122 may have a thickness in the range of about 10 nm to about 60 nm, or about 20 nm to about 40 nm, although other thicknesses are also considered.

[0072] Figure 13 This is a cross-sectional side view showing heater terminals and reading terminals formed in a substrate layer according to another embodiment of the present invention.

[0073] In one or more embodiments, openings may be formed in the substrate layer 122 using photolithography and etching (e.g., RIE). These openings may be configured and sized to form read terminals 130 and heater terminals 140.

[0074] In one or more embodiments, conductive material for the read terminal 130 may be deposited in an opening configured for the read terminal. Suitable conductive material for the heater terminal 140 may be deposited in an opening configured for the heater terminal.

[0075] Figure 14 This is a cross-sectional side view showing a phase change material layer formed on a substrate layer according to another embodiment of the present invention.

[0076] In one or more embodiments, a phase change material layer 111 may be formed on a substrate layer 122, wherein the phase change material layer 111 may be formed by blanket deposition. The phase change material layer 111 may cover and be in electrical and thermal contact with the heater terminal 140, and in electrical contact with the readout terminal 130.

[0077] In various embodiments, the phase change material layer 111 may have a thickness in the range of about 40 nm to about 100 nm or about 50 nm to about 100 nm, although other thicknesses are also conceivable.

[0078] Figure 15 This is a cross-sectional side view showing a phase change material layer patterned on a substrate layer according to another embodiment of the present invention.

[0079] In one or more embodiments, the phase change material layer 111 may be patterned using photolithography and etching to remove multiple portions of the phase change material layer 111 and expose multiple portions of the substrate layer 122.

[0080] In various embodiments, the phase change material layer 111 may have a width in the range of about 40 nm to about 300 nm, or about 50 nm to about 250 nm, although other widths are also contemplated.

[0081] Figure 16This is a cross-sectional side view showing an outer shell layer formed on a patterned phase change material layer and a substrate layer according to another embodiment of the present invention.

[0082] In one or more embodiments, the encapsulation layer 124 may be formed on a patterned phase change material having a first phase 110 and a substrate layer 122. The encapsulation layer 124 may be formed by conformal deposition, overlay deposition, or a combination thereof. The encapsulation layer 124 may surround the patterned phase change material layer 111 and cover exposed portions of the substrate layer 122 to form an electrically insulating wall 120 that may surround the patterned phase change material.

[0083] In different embodiments, the encapsulation layer 124 may be an insulating dielectric material, including but not limited to silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), borosilicate carbonitride (SiBCN), and combinations thereof.

[0084] Figure 17 This is a cross-sectional side view showing a second heater terminal and a second read terminal formed in an encapsulation layer according to another embodiment of the present invention.

[0085] In one or more embodiments, a second heater terminal 140 and a second read terminal 130 may be formed in an encapsulation layer 124. The second heater terminal 140 and the second read terminal 130 may be formed by forming openings at predetermined locations in the encapsulation layer 124 using photolithography and etching. A conductive material for the read terminal 130 may be deposited in the opening configured for the read terminal. A suitable conductive material for the heater terminal 140 may be deposited in the opening configured for the heater terminal.

[0086] This embodiment may include the design of an integrated circuit chip, which can be created using a graphical computer programming language and stored in a computer storage medium (such as a disk, magnetic tape, physical hard disk, or virtual hard disk, such as in a storage access network). If the designer does not manufacture the chip or the photomask used to manufacture the chip, the designer may transfer the obtained design directly or indirectly to such an entity by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). The stored design is then converted into a suitable format (e.g., GDSII) for use in manufacturing the photomask, which typically comprises multiple copies of the chip design in question to be formed on a wafer. The photomask is used to define areas of the wafer (and / or layers thereon) to be etched or otherwise processed.

[0087] The methods described herein can be used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chip is mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other more advanced carrier) or a multi-chip package (such as a ceramic carrier with one or both surface-mount or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product that includes the integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0088] It should also be understood that the material compounds will be described based on the listed elements (e.g., SiGe). These compounds include elements in different proportions within the compound; for example, SiGe includes Si. x Ge 1-x Where x is less than or equal to 1, etc. Furthermore, other elements may be included in the compound and still function according to the principles of the invention. Compounds with additional elements will be referred to herein as alloys.

[0089] References to "one embodiment" or "embodiment" and other variations thereof in the specification mean that a particular feature, structure, characteristic, etc., described in connection with that embodiment is included in at least one embodiment. Therefore, the phrases "in one embodiment" or "in an embodiment" and any other variations appearing in various places throughout the specification do not necessarily refer to the same embodiment.

[0090] It should be understood that, for example, in the cases of “A / B,” “A and / or B,” and “at least one of A and B,” the use of any one of the following “ / ,” “and / or,” and “at least one” is intended to cover selecting only the first listed item (A), or only the second listed item (B), or selecting both options (A and B). As another example, in the cases of “A, B, and / or C” and “at least one of A, B, and C,” this wording is intended to cover selecting only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed items (A and C), or only the second and third listed items (B and C), or selecting all three options (A, B, and C). It will be apparent to those skilled in the art that this can be extended for many of the listed items.

[0091] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to also include the plural forms. It should be further understood that, when used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0092] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship of an element or feature as shown in the figures to other elements or features. It should be understood that spatial relative terms are intended to include different orientations of the device in use or operation, other than those depicted in the figures. For example, if the device in the figure is flipped, an element described as “below” or “under” other elements or features would be oriented as “above” other elements or features. Thus, the term “below” can include both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly. Furthermore, it should be understood that when a layer is referred to as “between” two layers, the layer may be the only layer between the two layers, or one or more intermediate layers may exist.

[0093] It will be understood that although the terms first, second, etc., may be used herein to describe different elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the scope of the inventive concept, the first element discussed below may be referred to as the second element.

[0094] It should also be understood that when a component, such as a layer, region, or substrate, is referred to as being "on" or "above" another component, the component may be directly on the other component, or there may be intermediate components. Conversely, when a component is referred to as being "directly on" or "directly on" another component, there are no intermediate components. It should also be understood that when a component is referred to as being "connected" or "coupled" to another component, the component may be directly connected or coupled to the other component, or there may be intermediate components. Conversely, when a component is referred to as being "directly connected" or "directly coupled" to another component, there are no intermediate components.

[0095] Preferred embodiments of the device and methods of manufacturing the device have been described (these are intended to be illustrative and not restrictive). It should be noted that modifications and variations can be made by those skilled in the art based on the above teachings. Therefore, it should be understood that changes may be made to the specific embodiments disclosed within the scope of the invention as outlined in the appended claims. Various aspects of the invention, having the details and features required by patent law, have thus been described, and the claimed and desired protection by a patent certificate is set forth in the claims.

Claims

1. A phase-change memory device, comprising: Phase change memory material within an electrically insulating wall, wherein the phase change memory material is configured to store a plurality of data bits; The first heater terminal in the electrically insulating wall; The first and second read terminals within the electrically insulating wall each have a top and a bottom surface. An electrical read path is formed between the two read terminals, passing through the first heater terminal. Multiple data bits are stored by controlling the relative volumes of the amorphous and crystalline phases of the phase change memory material within the electrical read path. The top and bottom surfaces of the first read terminal are horizontally aligned with the top and bottom surfaces of the first heater terminal, respectively, and the widths of the first and second read terminals from their top and bottom surfaces are identical. The second heater terminal is located in the electrically insulating wall, wherein the second heater terminal and the first heater terminal are separated by the thickness of the phase change memory material, and wherein the top and bottom surfaces of the second read terminal are horizontally aligned with the top and bottom surfaces of the second heater terminal, respectively.

2. The phase-change memory device according to claim 1, wherein, The second heater terminal is opposite to the first heater terminal.

3. The phase-change memory device according to claim 1, wherein, At least a portion of the phase change memory material is in the crystalline phase.

4. The phase-change memory device according to claim 3, wherein, At least a portion of the phase change memory material is in an amorphous phase.

5. The phase-change memory device according to claim 4, wherein, The amorphous phase of the phase change memory material is a hemispherical shape adjacent to the first heater terminal.

6. The phase-change memory device according to claim 4, wherein, The phase change memory material has dimensions ranging from 50 nm length x 50 nm width x 50 nm height to 250 nm length x 250 nm width x 100 nm height.

7. The phase-change memory device according to claim 4, wherein, The amorphous phase of the phase change memory material includes a first hemisphere adjacent to the first heater terminal and a second hemisphere adjacent to the second heater terminal.

8. The phase-change memory device according to claim 7, wherein, The distance between the first hemisphere and the second hemisphere determines the state of the phase-change memory device.

9. A phase-change memory device, comprising: Phase change memory material within an electrically insulating wall; Two heater terminals in the electrically insulating wall, wherein the two heater terminals are located on opposite sides of the phase change memory material, such that the phase change memory material stores multiple data bits by controlling the relative volumes of the amorphous and crystalline phases of the phase change memory material in the electrical read path of the device; and Two read terminals are located on opposite sides of the two heater terminals and configured to form the electrical read path. The top and bottom surfaces of the first read terminal are horizontally aligned with the top and bottom surfaces of the first heater terminal, respectively, and the top and bottom surfaces of the second read terminal are horizontally aligned with the top and bottom surfaces of the second heater terminal, respectively. The width or diameter of the two heater terminals is less than 40 nm, and the width or diameter of the two read terminals is greater than 40 nm.

10. The phase-change memory device according to claim 9, wherein, The two reading terminals are located on the same side along the electrically insulating wall.

11. The phase-change memory device according to claim 9, wherein, The two heater terminals are separated by the height of the phase change memory material within an electrically insulating wall in the range of 50 nm to 100 nm.

12. The phase-change memory device according to claim 9, wherein, The two heater terminals are made of a material selected from the group consisting of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicide (TiSi), cobalt silicide (CoSi), nickel silicide (NiSi), titanium carbide (TiC), tantalum carbide (TaC), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), or tantalum (Ta), and combinations thereof.

13. The phase-change memory device according to claim 12, wherein, The phase change memory material is Ge2Sb2Te5, or GST.

14. A method for forming a phase-change memory device, comprising: A substrate layer is formed on the substrate; A first reading terminal and a first heater terminal are formed in the substrate layer; A patterned phase change material having a first phase is formed on the substrate layer; An encapsulation layer is formed on the patterned phase change material; as well as A second read terminal is formed in the encapsulation layer, wherein the second read terminal is in electrical contact with the patterned phase change material, wherein multiple data bits are stored by controlling the relative volumes of the amorphous and crystalline phases of the phase change memory material in the electrical read path passing through the first heater terminal between the first and second read terminals, the phase change memory device is configured to have four or more storage states, wherein the top and bottom surfaces of the first read terminal are horizontally aligned with the top and bottom surfaces of the first heater terminal, respectively, and wherein the widths of the first and second read terminals from the top to the bottom surfaces are the same; and A second heater terminal is formed in the encapsulation layer, wherein the second heater terminal and the first heater terminal are separated by the thickness of the phase change memory material, and wherein the top and bottom surfaces of the second read terminal are horizontally aligned with the top and bottom surfaces of the second heater terminal, respectively.

15. The method according to claim 14, wherein, The width or diameter of the two heating terminals is less than 40 nm, and the width or diameter of the two reading terminals is greater than 40 nm.

16. The method according to claim 15, wherein, The phase change memory material is Ge2Sb2Te5, or GST.

17. The method according to claim 16, wherein, At least a portion of the phase change memory material is in the crystalline phase.

18. The method according to claim 17, wherein, The two heater terminals are separated by the height of the phase change memory material within an electrically insulating wall in the range of 50 nm to 100 nm.

19. The method according to claim 18, wherein, The first heater terminal and the second heater terminal are made of a material selected from the group consisting of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicide (TiSi), cobalt silicide (CoSi), nickel silicide (NiSi), titanium carbide (TiC), tantalum carbide (TaC), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), or tantalum (Ta), and combinations thereof.

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