System and method for providing write termination for one-time programmable memory cells

Abstract

A one-time programmable (OTP) memory includes a first driver coupled to a reference cell by a first bit line, a second driver coupled to an OTP cell by a second bit line, and a comparator having a first input coupled to the first bit line and the reference cell, a second input coupled to the second bit line and the OTP cell, and an output coupled to a logic circuit configured to control the first driver and the second driver.

Description

[0001] Priority requirements

[0002] This patent application claims priority to non-provisional application number 16 / 811,145, filed on March 6, 2020, entitled “SYSTEMS AND METHODS TOPROVIDE WRITE TERMINATION FOR ONE TIME PROGRAMMABLE MEMORY CELLS”, which has been assigned to the assignee of this application and is expressly incorporated herein by reference. Technical Field

[0003] This application relates to One-Time Program (OTP) data, and more specifically, to systems and techniques for writing OTP data. Background Technology

[0004] Mobile computing devices, such as smartphones, incorporate multiprocessor chips to provide computing power. These multiprocessor chips store secure data in one-time programmable (OTP) memory. An example of OTP memory includes an array of electronic fuses that can be programmed once by selectively blowing some of the fuses in the array. For example, a blown fuse can represent a binary 1, and an unblowed fuse can represent a binary 0. These fuses can only be blown once and may not be repairable afterward; therefore, data stored after programming by blowing fuses is considered read-only.

[0005] Continuing this example, security data is read during chip power-on or boot. Examples of security data that can be stored include hardware keys, boot read-only memory (ROM) patches, chip configuration information, and original equipment manufacturer (OEM) information.

[0006] An example OTP cell includes a transistor and a fuse chain, where the transistor can be turned on to allow current to flow through the fuse to blow it. Continuing with this example, an unblown fuse can have low resistance, while a blown fuse can have high resistance. Furthermore, some existing OTP memories may include thousands (e.g., 20,000) of OTP cells, each with its own fuse. Process variations may cause some fuses to be physically different from the others, making some fuses potentially require more current to blow than others. Therefore, some systems may apply a relatively large amount of current to all the fuses to be blown for a relatively long time, ensuring that even the fuses using more current than others are expected to blow. In other words, such an example system processes all the fuses to be blown according to a worst-case scenario so that all the fuses to be blown are blown.

[0007] However, systems that apply relatively large currents to all fuses to be blown for relatively long periods of time may encounter some drawbacks. For example, a large current for a long period of time may damage other circuit components in the current path in some cases. Furthermore, in the presence of process variations within the OTP memory, treating all fuses to be blown in a similar manner may result in performance distributions, where the lowest resistance of a blown fuse differs significantly from its highest resistance within the same system. And because some existing systems lack a verified fuse-blowing mechanism and rely instead on current and time to ensure fuse blowing, it is possible that some fuses may not blow at all due to abnormal variations, which could reduce benefits.

[0008] Additional drawbacks can include the time spent programming the OTP memory. For example, if each fuse to be blown takes approximately 0.5 μs, and the OTP memory comprises thousands of fuses to be blown one after another, the total time spent programming the OTP memory can be significant and expensive.

[0009] A more robust technique is needed to program OTP memory, ensuring that the fuse to be blown is blown, while reducing the time spent programming. Summary of the Invention

[0010] Various implementations include systems and methods employing closed-loop OTP programming technology. In one example implementation, current is applied to a fuse, and when fuse blowing is detected, the system stops the current by, for example, disabling the fuse driver.

[0011] In one embodiment, the system includes an one-time programmable (OTP) memory, comprising: a first driver coupled to a reference cell via a first bit line; a second driver coupled to the OTP cell via a second bit line; and a comparator having a first input coupled to the first bit line and the reference cell, a second input coupled to the second bit line and the OTP cell, and an output coupled to logic circuitry configured to control the first driver and the second driver.

[0012] In another embodiment, the method includes: applying a driver control signal to a first driver, the first driver being coupled to a reference cell via a first bit line; applying a driver control signal to a second driver, the second driver being coupled to an OTP cell via a second bit line; generating a first current from the first driver to generate a reference voltage at a first input of a comparator coupled to the first bit line; generating a second current from the second driver to generate an OTP cell voltage at a second input of a comparator coupled to the second bit line; and adjusting the driver control signal in response to a change in the OTP cell voltage associated with an OTP cell fused by the second current.

[0013] In yet another embodiment, the read-only memory (ROM) includes: means for generating a first current on a first bit line; means for generating a second current on a second bit line; a reference resistor coupled between the first bit line and ground; an one-time programmable (OTP) unit coupled between the second bit line and ground; and means for turning off the second current generating means in response to a change in voltage at the second bit line relative to voltage at the first bit line. Attached Figure Description

[0014] Figure 1 This is an illustration of an example OTP module according to various implementation methods.

[0015] Figure 2 This is a diagram of an example physical architecture of an OTP unit and a programmable feedback loop according to one implementation.

[0016] Figure 3 This is a diagram of an example physical architecture of an OTP unit and a programmable feedback loop according to one implementation.

[0017] Figure 4 It is adapted according to one implementation method. Figure 2 , Figure 3 , Figure 9 An example timing diagram illustrating the physical architecture.

[0018] Figure 5 This is a diagram of multiple fuses coupled to a multiplexer according to one embodiment.

[0019] Figure 6 This is a diagram illustrating an example current path for a fuse according to one embodiment.

[0020] Figure 7 It is used with Figure 2 , Figure 3 and Figure 9 An illustration of an example comparator used in conjunction with a programming feedback loop.

[0021] Figure 8 yes Figure 7 A diagram illustrating example signal levels within the comparator.

[0022] Figure 9 This is a diagram of an example physical architecture of an OTP unit and a programmable feedback loop according to one implementation.

[0023] Figure 10 This is a diagram illustrating the distribution of the OTP unit resistors according to one embodiment.

[0024] Figure 11 This is an illustration of an example method for programming an OTP unit according to one embodiment. Detailed Implementation

[0025] Various implementations provide systems and methods for programming OTP units. Specifically, some implementations include a feedback loop to determine when a fuse blows. When the feedback loop determines that a fuse has blown, it can shut off the fusing current. In some implementations, once a fuse has blown, the system moves to the next fuse to be blown and performs the same technique. The system can blow each of the fuses to be blown in this manner.

[0026] An example architecture includes a first fuse current driver coupled to a reference resistor and a second fuse current driver coupled to an OTP cell. The reference resistor is coupled to a node on a pseudo-bit line, and the fuse of the OTP cell is coupled to a node on its corresponding bit line. The comparator has one input from a node on the pseudo-bit line and another input from a node on the corresponding bit line. When both fuse current drivers are on, and before the fuse blows, the voltage at the node on the corresponding bit line can be lower than the voltage at the node on the pseudo-bit line. However, when the fuse blows, the situation changes because the voltage at the node on the corresponding bit line increases, exceeding the voltage level at the node on the pseudo-bit line. This causes the comparator output to flip. When the comparator output flips, the controller circuitry can then disable both drivers, thereby shutting off the current to the reference resistor and the fuse.

[0027] As described above, some systems may include thousands of OTP cells. Therefore, the example system can move to the next fuse to be blown and perform the same blowing technique. One example system includes a multiplexing function, controlled by or implemented as part of control circuitry, to apply control (e.g., enable) signals to multiple fuse current drivers. For example, when the first OTP cell is being blown, the multiplexer can apply an enable signal to the first fuse current driver, and after the first OTP cell has blown, the multiplexer can apply an enable signal to the second fuse current driver to blow the second OTP cell, and so on. The multiplexing function can also multiplex the voltage from each corresponding bit line to a comparator. The multiplexing function can allow the same reference fuse current driver, reference resistor, and comparator to be used for multiple OTP cells.

[0028] In one example, the control circuitry can be as simple as a logic gate (such as an OR gate that receives an enable signal and a signal from a comparator). In another example, the control circuitry can be more complex, including, for example, multiplexing functionality.

[0029] In one example, the voltage input to the comparator can be detected by writing to the bit line. In another example, the voltage input to the comparator can be detected by reading from the bit line. In either case, the detected voltage change can be the bit line voltage. One advantage of measuring the voltage on the bit line is that it can have a higher voltage, and therefore can have a larger detection margin compared to measuring voltages elsewhere (such as at the source line).

[0030] Various implementations can offer one or more advantages over known systems. For example, various implementations can save time programming the OTP memory compared to systems that simply apply the same amount of current to all OTP units for the same amount of time. One experiment showed that, even considering process variations, blowing a typical fuse with 20mA typically takes about 0.5μs. Nevertheless, some existing systems may apply 20mA to each fuse for as long as 10μs to 20μs to ensure that each fuse blows. In contrast, various implementations of this disclosure can apply current for a sufficient amount of time to blow each fuse, not more, thereby saving an order of magnitude or more of time compared to existing systems. Of course, due to process variations, some fuses may take longer to blow than others. However, overall time savings are expected because most fuses blow within a shorter amount of time, and only a few fuses may take as long as the 10μs or 20μs used by existing systems.

[0031] Another advantage of some embodiments of this disclosure includes reduced power consumption. Specifically, it is anticipated that power consumption for programming the OTP memory will be reduced for the same reasons as the time required for programming the OTP memory can be reduced. That is, the amount of time for which current is applied can be shortened across multiple OTP cells, thereby reducing power consumption.

[0032] It is anticipated that the reduction in power and time required for programming OTP memory will lower costs. For example, reducing power consumption can decrease the electricity costs of the entity programming the OTP memory. Furthermore, the time spent by personnel or machines performing programming can be reduced, thereby decreasing personnel and machine costs.

[0033] Furthermore, while OTP programming is typically performed at the manufacturing facility on which the chip on which OTP memory is built is built, it is expected that OTP programming will become more prevalent at customer facilities in the future. Customers (e.g., mobile phone manufacturers) are also expected to maintain their low costs, and therefore, the systems and technologies described herein are expected to offer a competitive advantage.

[0034] Additional advantages of some implementations may include increased consistency in the resistance of the fuse that has been broken. Specifically, in some applications, a fuse resistance of approximately 10 kΩ is typically expected to be broken. However, some systems that apply the same voltage to all fuses for the same amount of time may result in some fuses being slightly under-broken and some being slightly over-broken. When a fuse is under-broken or over-broken, its resistance may differ from its nominal value, for example, 10 kΩ. In contrast, the various implementations described herein can apply just enough current for just enough time to break the fuse, thereby reducing or avoiding under-broken and over-broken fuses. Overall, it can be expected that more consistent fuse breaking will provide a more consistent fuse resistance, which can lead to higher yields. The scope of the implementations is not limited to any particular fusing current level, time, or fusing resistance.

[0035] Furthermore, the use of a reference resistor can further provide the advantage of reducing or avoiding under-fusing and over-fusing, which is described in more detail below in this disclosure. In an example embodiment, the same reference resistor is used to program multiple OTP cells, thereby providing consistency across these multiple OTP cells.

[0036] Figure 1 This is a simplified diagram illustrating an example OTP module 100 (ROM) in which various implementation methods can be carried out. The OTP module 100 itself is... Figure 1As shown, but it should be understood that it can be included in a processing device, such as a central processing unit (CPU), a digital signal processor (DSP), a system-on-a-chip (SoC) with multiple processing cores on the chip, a package including multiple chips, etc.

[0037] According to the examples herein, the processing device implementing the OTP module 100 may include a tablet computer, a smartphone, or other suitable device. However, the scope of the implementation is not limited to smartphones or tablet computers, as other implementations may include laptop computers or other suitable devices. In fact, the scope of the implementation includes any particular computing device, whether mobile or not.

[0038] OTP module 100 is shown as having two halves, which are substantially similar and share a global control block 170 and a fuse controller 150. OTP module 100 has two OTP cores—a left core 110a and a right core 110b. Within each half, OTP elements are arranged as an array of rows and columns of memory elements. In this example, columns are referred to as bit lines, and rows as word lines. ROM rows 101 include check modes, and each half also includes spare rows 102. Core 110 contains security data. Each row is a word that can be read from OTP module 100 under the guidance of global control block 170.

[0039] Examples of security data in Core 110 may include, but are not limited to, configuration information for the processing device, hardware keys for the processing device, boot ROM patches, OEM manufacturer information, etc. Security data is typically included by the manufacturer of the processing device or the manufacturer of the computer in which the processing device is implemented, and is generally read only by low-level processes within the processing device and is not intended to be accessible to end users. Security data may or may not be encrypted.

[0040] Line 101 contains a pre-programmed check pattern of binary 0s and 1s. The firmware process reads check pattern line 101 during power-up to determine if security data in core 110 has been tampered with. In this way, the firmware process can compare what it reads with known values ​​of the check pattern, and if a mismatch exists, the firmware process can determine that an attack on the OTP module has occurred.

[0041] Security data and check modes are stored in OTP module 100 using fuses. For example, a blown fuse produces high resistance and can be read as binary 1, while an unblowed fuse can have low resistance and be read as binary 0. However, the scope of implementations can include systems in which a blown fuse is read as binary 0 and an unblowed fuse is read as binary 1. Furthermore, the scope of implementations is not limited to fuses, as other suitable memory elements can be used. Other examples include antifuses and nonvolatile RAM. However, for ease of illustration, the examples herein refer to fuses (e.g., electronic fuses or "e-fuse"). The fuses of core 110 and row 101 can be programmed according to the techniques described herein.

[0042] In item 140, the OTP module 100 also includes a sense amplifier that operates to read data stored in memory elements. In item 140, the OTP module 100 also includes a trigger and a driver to capture the read data. When reading data, each sense amplifier in the sense amplifier receives a voltage corresponding to a specific memory cell selected in its respective column. For example, a blown fuse can cause a high voltage, and an unblowed fuse can cause a low voltage. The sense amplifiers of item 140 can compare the resulting voltage from the fuse with a reference voltage and then output the resulting value to the trigger of item 140.

[0043] Global control block 170 includes firmware logic for decoding read requests and applying control signals to word lines, bit lines, sense amplifiers, and flip-flops. Global control block 170 may also include firmware logic for controlling global power switch 130, fuse controller 150, and multiplexing functions.

[0044] Continuing this example, each fuse data path 120 may include a local power switch for blowing the fuse, such as allowing current to flow through a given fuse by turning on or off word line transistors. A global power switch 130 may include a power switch within a shared power domain or a separate fuse power domain for supplying power to the fuse driver, which relates to... Figure 2 A more detailed description would follow. The fuse controller 150 is also related to... Figure 2 A more detailed description follows. In short, the fuse controller 150 may include logic for turning the fuse driver on or off, and may also include multiplexing logic. Furthermore, the OTP module 100 may also include electrostatic discharge (ESD) protection circuitry 160.

[0045] Figure 2 This is a diagram of an example physical architecture of an OTP unit and a programmable feedback loop according to one implementation. Figure 2The architecture includes a first fuse driver 205 and a second fuse driver 215. Each fuse driver in 205 and 215 applies current to its corresponding bit line when enabled. The driver enable signal is in Figure 2 It is shown as driver_en in the middle.

[0046] First, looking at the left side, the fuse driver 205 is coupled to the first bit line and the reference resistor 202. The first bit line is only used for fuse blowing purposes, therefore it is not used for reading or writing and does not include OTP cells. Therefore, the left bit line is called a pseudo bit line. The reference resistor 202 is coupled to the pseudo bit line at node DBL. The word line transistor 204 couples the reference resistor 202 to ground. Although in Figure 2 Not shown in the diagram, but word line transistor 204 can be derived from... Figure 1 The global control block 170 controls this. When the word line transistor 204 is turned on, it allows current to flow through the reference resistor 202, thereby generating a measurable reference voltage at node DBL.

[0047] Now looking at the right-hand side, the fuse driver 215 is coupled to the second bit line and the fuse 212. The second bit line is used to write to and read from the OTP cell including the fuse 212. Therefore, the second bit line is not a pseudo bit line.

[0048] When the fuse driver 215 is enabled by the enable signal driver_en, it provides current flowing through the fuse 212 when the word line transistor 214 is turned on. Like the word line transistor 204, the word line transistor 214 can be... Figure 1 The global control block 170 controls the process. When current flows through fuse 212 and fuse 212 does not melt, the current can cause electromigration in the metal of the fuse material, eventually creating a high-resistance path through fuse 212. Once a high-resistance path is created, the fuse is considered to have melted.

[0049] For example, in some examples, the resistance of an unfused fuse may be approximately 50 Ω, while the resistance of a fused fuse may be approximately 10 kΩ. Of course, these resistance values ​​are merely examples, and the scope of implementation can include any suitable resistance values ​​for both fused and unfused fuses. When current flows through the unfused fuse 212, the voltage at node BL is relatively low. Conversely, when current flows through the fused fuse 212, the voltage at node BL is relatively high. Therefore, in this example, the reference resistor 202 is sized to induce a reference voltage at node DBL that is greater than the voltage at node BL when fuse 212 is unfused and lower than the voltage at node BL when fuse 212 is fused.

[0050] In this example, Figure 2The architecture also includes comparator 220. Comparator 220 can include any suitable comparator design, such as, for example, a symmetric sense amplifier design. An example symmetric sense amplifier design is provided. Figure 7 More details are shown. Comparator 220 includes an inverting input coupled to node DBL and a non-inverting input coupled to node BL.

[0051] The fuse controller 150 receives the comparator's output and, in response, asserts or deasserts driver_en. In some embodiments, the fuse controller 150 may include transistor logic gates, or in another embodiment, it may include firmware-based functionality provided by larger processing circuitry. Furthermore, as discussed in more detail below, the fuse controller 115 may integrate multiplexing functionality or may control other multiplexing functions.

[0052] Looking at it now Figure 2 In this architecture, the fuse controller enable signal `blow_en` has not been asserted, and the output of fuse controller 150 is a digital 1, while both fuse drivers 205 and 215 are off. The fuse controller enable signal `blow_en` can be, for example... Figure 1 The global control block 170 is provided. Furthermore, at this time, comparator 220 is not yet enabled because its enable signal sense_en has not been asserted. Various implementations may disable comparator 220 at this time to avoid measuring undefined voltages.

[0053] Then, blow_en can be asserted, causing the output of fuse controller 150 to become a digital 0. The digital 0 of the driver enable signal driver_en turns on fuse drivers 205, 215. Subsequently, write line transistors 204, 214 can be turned on by providing an appropriate signal at their gate terminals. When fuse drivers 205, 215 and write line transistors 204, 214 are on, current flows through both reference resistor 202 and fuse 212. At this time, the voltage at node DBL is higher than the voltage at node BL. Comparator 220 can then be enabled by asserting sense_en, for example, through global control block 170.

[0054] Comparator 220 senses two different voltages at its input and, in response, outputs a digital 0. As described above, in some examples, fuse 212 may take approximately 0.5 μs to blow. However, the implementation is not limited to any specific value of the fusing current or the time used for fusing. As mentioned above, process variations may cause some fuses to take longer or shorter times to blow, even when the same fusing current is applied. In any case, after a certain amount of time, fuse 212 blows, and its resistance increases by several orders of magnitude. As a result, the voltage at node BL increases, while the voltage at node DBL may remain unchanged because the reference resistor 202 did not change during the fusing procedure.

[0055] As described above, when fuse 212 is not blown, the voltage at DBL can be higher than the voltage at BL. However, once fuse 212 blows, the voltage at BL becomes higher than the voltage at DBL. The voltage is sensed by comparator 220, and the change in the relationship between the voltages at nodes DBL and BL causes the comparator to change its output to a digital 1.

[0056] The fuse controller 150 receives the output from the comparator, which is now a digital 1. In response, the fuse controller 150 changes the driver enable signal driver_en from a digital 0 to a digital 1, thereby disabling fuse drivers 205 and 215. Therefore, fuse drivers 205 and 215 stop supplying current to their respective bit lines. (About...) Figure 2 The described operation causes fuse 212 to blow, wherein fuse 212 is exposed to a sufficient current to blow it, but not to a sufficient current to over-blow it.

[0057] In one example implementation, the delay caused by the fuse controller 150 receiving the digital 1 and then disabling the drivers 205, 215 is approximately 3 μs, which is about an order of magnitude lower than the time associated with the fuse 212. In other words, in this example implementation, the delay from the comparator 220 and the fuse controller 150 is negligible compared to the time associated with the fuse 212. Of course, the scope of the implementation is not limited to any particular time of operation of the comparator 220 or the fuse controller 150.

[0058] Figure 3 This is a diagram illustrating an example physical architecture of an OTP unit and a programmable feedback loop according to one implementation. Figure 3 In the examples, various components and Figure 2 The components shown are the same. However, an example implementation of the fuse controller 150 is shown in more detail. Specifically, in Figure 3In the example, the fuse controller 150 includes an OR gate 151 with two inputs. The first input receives the output from comparator 220, and the other input receives the inverted value of `blow_en`. The operation is indicated in truth table 300. According to truth table 300, fuse drivers 205 and 215 are turned on only if `blow_en` is 1 and the comparator's output (`write_ter`) is 0. Otherwise, drivers 205 and 215 are turned off. This is consistent with the above regarding... Figure 2 The described behavior is consistent.

[0059] Figure 4 It is a diagram of a timing diagram, which is suitable for... Figure 2 and Figure 3 The implementation is shown below. At time 401, fuse drivers 205 and 215 are turned on, and word line transistors 204 and 214 are also turned on, allowing the fuse current (i_blow) to pass through reference resistor 202 and fuse 212. At time 401, fuse 212 is not blown, so the voltage (Vref) at DBL is higher than the voltage (Vunblown) at BL. However, at time 402, fuse 212 blows, and the voltage (Vref) at DBL is now lower than the voltage (Vblown) at BL. This causes the output (write_ter) of comparator 220 to go high, which changes the state of the driver enable signal (driver_en), causing the fuse current i_blow to become zero. Again, drivers 205 and 215 turn off, thereby reducing or eliminating the current that would otherwise be applied to fuse 212 after it blows.

[0060] certainly, Figures 2-4 This applies only to a single fuse 212. However, as regarding... Figure 1 As indicated, core 110 may include an array of OTP elements arranged in rows and columns, where columns correspond to bit lines. In other words, various embodiments may use... Figures 2-4 The same arrangement is shown to fuse each of the OTP elements to be fused. In fact, in some embodiments, the OTP elements to be fused are fused one after another, column by column and row by row, until every fuse in the series to be fused has been fused. For example, global control block 170 can apply address signals to fuse controller 150 to control the column-by-column multiplexer function. Figure 5 The diagram illustrates an example implementation of a multiplexer that includes multiple bit lines.

[0061] Figure 5The example implementation illustrates an example with N bit lines in a given core (110a or 110b). N can be any suitable integer greater than 1, and in this example, it is 64. However, the scope of the implementation is not limited to any particular number of bit lines. The fuse controller 150 has an integrated multiplexing function controlled by N-bit inputs, where 0 in the N-bit inputs indicates that the corresponding fuse should not be blown, and where 1 in the N-bit inputs indicates that the corresponding fuse should be blown. The fuse controller 150 includes additional inputs 502 and 504, where, for example, input 502 can be blow_en, and input 504 can be write_ter. The fuse controller 150 can receive N-bit inputs from global control block 170.

[0062] After receiving an N-bit input, the fuse controller 150 controls each driver in the driver 215 one by one to either blow or not blow their corresponding fuses. Specifically, assuming the N-bit input indicates that driver 2150 should be blown, the fuse controller 150 can provide driver 2150 with driver_en as the number 0. Although Figure 5 Not shown in the diagram, but the fuse controller 150 also causes the fuse driver 205 of the pseudo bit line to turn on or off, as mentioned above. Figures 2-4 Described. And, although Figure 5 Not further shown, but the fuse controller 150 can also multiplex the input to comparator 220 so that, as the fuse controller 150 travels bit by bit, comparator 220 receives inputs from the appropriate bit lines BL0-BL0. N Voltage input.

[0063] Once driver 2150 blows fuse 2120, fuse controller 150 proceeds to the next driver 2151. If the next driver 2151 is associated with a fuse to be blown, fuse controller 150 performs the same blowing technique. However, if the next driver 2151 is associated with a fuse that is not blown, fuse controller 150 does not cause driver 2151 to generate a blowing current, but instead moves to the next driver 2152 and continues until fuse controller 150 has addressed driver 2151. N .

[0064] Once the fuse controller 150 has addressed the driver 215 N Then the same operation is performed on the next line (a different word line). In one example, global control block 170 provides a new N-bit input to fuse controller 150, and fuse controller 150 controls drivers 2150-215 based on the new N-bit input. N Each drive in the list. The process continues until the last drive 215 in the last line.N This process continues until the core has been addressed. The procedure is also performed on other 110a or 110b cores.

[0065] In the example above, as the fuse controller 150 advances through columns and rows, each fuse in the fuse 212 is blown one after another. As mentioned above, this process can take a considerable amount of time to complete. However, the above embodiment offers the advantage of taking less time overall to blow the fuses in the core 110, because it reduces or eliminates the time that would otherwise be used to over-blow some fuses.

[0066] The scope of implementation is not limited to fuse controllers with integrated multiplexing functionality. In some implementations, the multiplexing function may be performed by a separate multiplexer unit. Furthermore, some implementations may provide a single driver 215 and multiplex its fuse current, rather than as... Figure 5 As shown, N drives are provided. However, Figure 5 The implementation shown may be more suitable for some applications because it avoids the fusible current passing through the multiplexer, which could damage the multiplexer or interfere with the level of the fusible current.

[0067] Figure 6 An example path 600 from driver to ground for an OTP cell according to one embodiment is illustrated. In this example, the driver (not shown) may supply its current at 1.8V, as provided by a power supply. However, the scope of the embodiment is not limited to any particular voltage supply. The bit line itself has a parasitic resistance indicated as R1. Fuse 612 has a resistance indicated as Rfuse. As noted in the example above, the resistance of fuse 612 is smaller when the fuse is not blown and larger when the fuse is blown. The path from fuse 612 to ground includes a parasitic resistance R2 at the first terminal of word line transistor 614. Word line transistor 614 also has an associated resistance (Rtr), and the parasitic resistance between the other terminals of transistor 614 and ground is shown as R3.

[0068] For fuse current (ifuse), various resistors as described above, and node BL (corresponding to...) Figure 2 and Figure 3 The voltage at node BL in the table is provided in Table 610 as an example. Again, the values ​​in Table 610 are merely examples, and the scope of implementation is not limited to any particular value among these specific values. Rather, any suitable value may be used in other implementations.

[0069] In this example, it is worth noting the difference of 216mV between the BL voltage in the unfused state and the BL voltage in the fused state. In some examples, 216mV provides sufficient margin for comparator 222 to detect the difference between each of those voltages at BL and a reference voltage approximately in the middle of those voltages. This resistance value, voltage, and current can be implemented on a SOC, such as one used in a smartphone or tablet computer.

[0070] Figure 7 This is an illustration of an example comparator 700 according to one implementation. The comparator 700 can be implemented as follows: Figure 2 and Figure 3 Comparator 220 in the architecture shown. Figure 7 In the example, comparator 700 includes a symmetrical sense amplifier. Comparator 700 includes two NMOS inputs 702 and 704, which receive voltages from the DBL node and BL node, respectively. Comparator 700 is enabled by an inverted enable signal sense_en at transistor 706 and an enable signal sense_en at transistor 708. Figure 2 and Figure 3 Similar inputs are also shown in the examples.

[0071] The gate of transistor 702 represents the inverting input of the comparator. Similarly, the gate of transistor 704 represents the non-inverting input of the comparator.

[0072] Figure 7 The sense amplifier 720 compares the voltage from node BL with a reference voltage from node DBL and outputs a high or low voltage value at Vs_out accordingly. For example, if the voltage from node BL is lower than the reference voltage at node DBL, the sense amplifier can output a high voltage. On the other hand, if the voltage received from node BL is higher than the reference voltage at node DBL, the sense amplifier can output a low voltage. The sense amplifier 720 performs the comparison when it receives an enable signal (sense_en).

[0073] exist Figure 7 In the example, the output of the sense amplifier 720 is applied to the inverter 710. The inverter 710 inverts Vs_out to provide the signal write_ter, as... Figure 2 and Figure 3 As shown in the image.

[0074] Figure 8 yes Figure 7 The circuit shown is an example voltage diagram. It is worth noting that when the voltage at node BL swings by approximately 216mV (as shown in the diagram),... Figure 6As shown in the example, the output signal Vs_out swings in increments of approximately 1.08V. In this example, a 1.08V swing is sufficient to trigger the inverter 710, thus ensuring an accurate write_ter signal. Of course, the implementation is not limited to any particular voltage level, as other implementations can be designed differently. However, note that... Figures 6-8 The voltage, current, and resistance values ​​shown can be implemented on-chip.

[0075] Furthermore, the architecture of comparator 700 is merely an example, and the scope of implementation is not limited thereto. For example, other comparator architectures now known or discovered later can be used... Figure 2 and Figure 3 Comparator 220 in the example. However, such as Figure 7 The symmetrical sense amplifier shown in the example can have the advantage of being less sensitive to process changes and can have a larger sensing margin than other comparator designs.

[0076] Figure 9 This is a diagram illustrating another physical architecture of an OTP unit and a programmable feedback loop according to one implementation. Figure 9 The architecture is similar to Figure 2 and Figure 3 The architecture shown. However, Figure 9 The architecture senses the bit line voltage on the read bit line, rather than writing the voltage on the bit line (e.g., ...). Figure 2 and Figure 3 (As shown). In other words, Figure 9 This illustrates a separate bit cell architecture with read and write paths. Specifically, let's look more closely. Figure 9 The pseudo bit lines include pseudo write bit line 910 and pseudo read bit line 912. Similarly, the bit lines associated with fuse 212 include write bit line 920 and read bit line 922.

[0077] First, let's look at the pseudo bit lines, which include the write word line transistor 904 and the read word line transistor 906. This is related to... Figure 2 and Figure 3 In contrast to the examples, Figure 2 and Figure 3 The example has a word line transistor 204. Assuming the fusing current is in the range of approximately 20 mA, the word line transistor 204 can be designed to be large enough to handle that current. However, it can be expected that a larger transistor may have greater leakage, which is generally undesirable. Therefore, Figure 9 The example uses two different transistors, 904 and 906, to separate the read path from the write path, thereby allowing transistor 904 in the write path to be turned off and saving leakage current. Advantages of this implementation may include increased energy efficiency due to less leakage.

[0078] Now consider the bit line with fuse 212, which includes a write word line transistor 914 and a read word line transistor 916. Similar to the arrangement on the pseudo-bit line side, two transistors 914 and 916 are used to separate the read path and the write path. This allows transistor 914 in the write path to be turned off to save leakage current.

[0079] In one example, global control block 170 can provide control signals to the gates of transistors 904, 906, 914, and 916 to control these transistors to turn on and off during read and write operations. For example, during a write operation, transistors 904, 906 and 914, 916 are turned on, allowing comparator 220 to sense the voltages on the corresponding bit lines DRBL and RBL. During a read operation, transistors 904, 914 can be turned off, while transistors 906, 916 can be turned on.

[0080] and Figure 2 and Figure 3 Compared to the implementation method, although Figure 9 The implementation couples the input of comparator 220 to the read bit lines DRBL and RBL, but Figure 9 The implementation also compares the voltage from the bit line. Comparator 220 and fuse controller 150 are... Figure 2 and Figure 3 The implementation method operates in a basically the same way. In other words, once the comparator 220 detects that the fuse 212 has blown, the fuse controller 150 shuts down the drivers 205 and 215.

[0081] Figure 10 This is a diagram illustrating the resistance distribution of an OTP cell according to one embodiment. In the embodiment of Figure 1010, the OTP cell resistance is distributed along a relatively wide band. R0 represents the resistance in the system design at which the blown fuse triggers comparator 220 and turns off the fusing current. However, instead of using a comparator to turn off the fusing current, Figure 1010 corresponds to an embodiment where the same fusing current is applied to all OTP cells to be blown for the same amount of time. In other words, Figure 1010 corresponds to an open-loop embodiment where the blown fuse is not verified. Figure 1010 shows a small number of OTP cells under-blown, while many OTP cells over-blown, and the range from under-blown to over-blown is large.

[0082] In contrast, Figure 1020 corresponds to, for example, the above regarding... Figures 1-9 The described implementation uses a comparator to turn off the fuse current. As can be clearly seen from Figure 1020, there is almost no OTP unit under-fuse, and the resistance range is relatively narrow. Therefore, the above regarding... Figures 1-9The described implementations can provide increased accuracy in fuse resistance by applying sufficient current for sufficient time to blow the fuse, thereby verifying whether the fuse has blown and reducing or eliminating excessive blowing current. One advantage of these implementations is that they can increase throughput by writing to the fuse more accurately and also verifying whether the fuse has blown.

[0083] Furthermore, the increased accuracy shown in Figure 1020 may stem from using the same reference resistor to verify the fuse's melting state. Specifically, in Figure 2 , Figure 3 and Figure 9 In the architecture, reference resistor 202 can be used to verify the fusing state of each fuse in a given core 110a or 110b. In some embodiments, each core 110a, 110b may have its own pseudo bit line and its own reference resistor 202, thereby verifying the fusing state of each OTP cell in its array. In other embodiments, core 110a may share reference resistor 202. In any case, an advantage may include consistency, as shown in Figure 1020, because the fusing state of a fuse can be verified relative to a consistent reference voltage, regardless of its column or row position within the array.

[0084] Figure 11 The diagram illustrates a flowchart of an example method 1100 for writing data to an OTP memory. In one example, method 1100 is performed by... Figure 1 The fuse controller 150 and global control block 170 execute the method. Method 1100 can be performed during the manufacturing, assembly, or verification of the device. For example, method 1100 can be performed during the manufacturing or verification of a SOC implementing OTP memory. In another example, method 1100 can be performed during the assembly or verification of a larger device using an SOC (e.g., a smartphone or laptop computer). In this implementation, once the fuses blow, they cannot be reversed, so each fuse can only undergo a write process once and can be permanent.

[0085] At action 1110, a driver enable signal is applied to the first driver, which is coupled to the reference cell via the first bit line. Figure 2 , Figure 3 and Figure 9 An example is shown where the fuse driver 205 is coupled to the reference resistor 202 via a pseudo bit line. The example driver enable signal is shown as driver_en.

[0086] exist Figure 2 , Figure 3 , Figure 9In this implementation, fuse driver 205 is shown as an inverter coupled between a power supply (e.g., VCC) and ground. However, the scope of the implementation is not limited to using an inverter as a fuse driver, as any suitable driver circuitry can be used. Furthermore, although driver_en is shown as enabling drivers 205, 215 via a low signal (digit 0), it should be understood that any suitable enable signal for a given driver can be used. The enable signal can be provided by any suitable circuitry, such as fuse controller 150.

[0087] At action 1120, a driver enable signal is applied to the second driver, which is coupled to the OTP unit via the second bit line. Figure 2 , Figure 3 and Figure 9 An example is shown where the fuse driver 215 is coupled to the fuse 212 via a bit line. Furthermore, in this example, the driver enable signal (driver_en) is the same as the signal provided to the pseudo bit line and the reference resistor; however, the scope of the implementation may include separate enable signals for two drivers.

[0088] At operation 1130, the first driver generates a first current, thereby generating a reference voltage. In this example, the reference voltage is applied to the first input of the comparator coupled to the first bit line.

[0089] exist Figure 2 , Figure 3 , Figure 9 An example is shown in which the fuse driver 205 generates current through the reference resistor 202 and word line transistors 204, 904, thereby generating a reference voltage at node DBL, which is applied to the inverting input of comparator 220.

[0090] At action 1140, the second driver generates the second current. Figure 2 , Figure 3 and Figure 9 An example is shown where the fuse driver 215 generates current (respectively) through fuse 212 and word line transistors 214, 914. Fuse 212, when not blown, has a resistance that allows a relatively low voltage to be applied to the non-inverting input of comparator 220. Figure 2 In the example, at node BL, a voltage is applied to comparator 220. Figure 9 In the example, the voltage is applied to comparator 220 by reading the bit line RBL.

[0091] Continuing the example, the second current can blow the fuse, thereby changing the fuse's resistance. This change in fuse resistance increases the voltage at the bit line and the voltage at the non-inverting input of the comparator.

[0092] At operation 1150, the driver enable signal is adjusted in response to a change in the OTP unit voltage. Figure 2 , Figure 3 , Figure 9 In the example, the driver enable signal turns on drivers 205 and 215 using a low voltage (digital 0) value. Therefore, in some cases, action 1150 may include changing the driver enable signal to a high voltage (digital 1) value. Of course, the scope of the implementation is not limited to asserting the enable signal to turn off the driver. Instead, other implementations may deassert the enable signal or otherwise adjust the voltage or current event enable signal to turn off the driver on demand for a given driver.

[0093] At action 1150, in response to a change in the voltage of the OTP cell associated with the OTP cell that was blown by the second current, the driver enable signal is adjusted. Figure 2 , Figure 3 , Figure 9 For example, the voltage at node BL changes relative to the voltage at node DBL, causing a change in the output of comparator 220, which triggers the fuse controller to adjust the driver enable signal.

[0094] In an alternative embodiment, method 1100 can be performed using an antifuse instead of a fuse. In the antifuse embodiment, current is applied to the antifuse, which initially has a high resistance value, but as the current flows, it can cause changes in the metal constituting the antifuse, which can result in a lower resistance value. In other words, when the antifuse "melts," its resistance can decrease.

[0095] In the antifuse embodiment of method 1100, an antifuse can be used instead of fuse 212, and a reference resistor 202 can be selected such that its reference resistance is between the fused resistance value and the unfused resistance value of the antifuse. In this example, when compared with... Figure 2 , Figure 3 , Figure 9 Compared to the fuse implementation shown, from Figure 7 The output value of the sensing amplifier shown can be inverted. Therefore, the antifuse implementation can be derived from... Figure 7 The output of the sensing amplifier omits inverter 710. Alternatively, in the antifuse implementation, another inverter (not shown) may be added. Figure 7 The output of the sensing amplifier. In yet another example, Figure 7The sensing amplifier implementation can remain the same, but the input to comparator 220 can be switched so that a pseudo bit line voltage is applied to the non-inverting input and a bit line voltage is applied to the inverting input. In either case, once the antifuse blows, it causes the voltage at node BL to drop, thereby changing the output of comparator 220 and causing the fuse controller to adjust the driver enable signal, thereby turning off drivers 205 and 215.

[0096] In other words, the scope of the implementation is not limited to Figure 11 The specific method shown is not applicable. Instead, various implementations may use different OTP units (e.g., fuses and antifuse), different comparator architectures, different fuse controller architectures, etc.

[0097] Other implementations may add, omit, rearrange, or modify one or more actions. For example, method 1100 may be performed on each fuse to be blown in the OTP memory. For example, an array of OTP cells in a ROM may include thousands of fuses to be blown. In this case, Figure 11 The method can be applied to each of the fuses to be melted. Therefore, method 1100 can further include column-by-column multiplexing in the array of OTP cells so that each OTP cell to be melted is melted. An example is given above regarding... Figure 5 It has been described.

[0098] As those skilled in the art will now understand, and depending on the specific application at hand, many modifications, substitutions, and variations can be made to the materials, apparatus, configurations, and methods of using the device disclosed herein without departing from the spirit and scope of this disclosure. Therefore, since the specific embodiments illustrated and described herein are merely examples of this disclosure, the scope of this disclosure should not be limited to the specific embodiments illustrated and described herein, but should be fully commensurate with the scope of the appended claims and their functional equivalents.

Claims

1. A one-time programmable (OTP) memory, comprising: A first driver, the first driver being coupled to a reference cell via a first bit line; The second driver is coupled to the OTP unit via a second bit line; as well as A comparator having a first input coupled to the first bit line and the reference cell, a second input coupled to the second bit line and the OTP cell, and an output coupled to logic circuitry configured to control the first driver and the second driver.

2. The OTP memory according to claim 1, wherein the OTP unit includes an electronic fuse.

3. The OTP memory according to claim 1, wherein the OTP unit includes an antifuse.

4. The OTP memory according to claim 1, wherein the comparator comprises a symmetrical sensing amplifier.

5. The OTP memory of claim 1, wherein the logic circuitry includes an OR gate having a first input configured to receive an enable signal and a second input configured to receive an output signal from the comparator.

6. The OTP memory of claim 1, wherein the reference cell includes a resistor between the first bit line and the word line transistor, wherein the resistor is sized to induce a reference voltage at the first bit line that is lower than the voltage associated with the blown OTP cell at the second bit line.

7. The OTP memory of claim 1, wherein the reference cell includes a resistor between the first bit line and the word line transistor, wherein the resistor is sized to induce a reference voltage at the first bit line that is greater than the voltage associated with an unfused OTP cell at the second bit line.

8. The OTP memory of claim 1, wherein the OTP cell includes a fuse between the second bit line and word line transistors.

9. The OTP memory of claim 1, wherein the first input of the comparator is coupled to the first bit line via a read word line transistor.

10. The OTP memory of claim 1, wherein the second input of the comparator is coupled to the second bit line via a read word line transistor.

11. The OTP memory according to claim 1, wherein the first bit line includes a read bit line.

12. The OTP memory according to claim 1, wherein the second bit line includes a read bit line.

13. The OTP memory according to claim 1, further comprising: The logic circuitry includes a multiplexer coupled to a third driver having an additional OTP unit, and the multiplexer is configured to provide an enable signal to the second driver and the third driver.

14. A method for a one-time programmable (OTP) memory, comprising: A driver control signal is applied to a first driver, which is coupled to a reference cell via a first bit line; The driver control signal is applied to the second driver, which is coupled to the OTP unit via the second bit line; The first driver generates a first current, thereby generating a reference voltage at the first input of the comparator coupled to the first bit line; The second driver generates a second current, thereby generating an OTP cell voltage at the second input of the comparator coupled to the second bit line; In response to a change in the voltage of the OTP cell associated with the OTP cell that has been melted by the second current, the driver control signal is adjusted; Change the output signal of the comparator; and The driver control signal is adjusted based on the output signal of the comparator.

15. The method of claim 14, wherein adjusting the driver control signal includes deasserting the driver enable signal for the first driver and the second driver.

16. The method of claim 14, wherein adjusting the driver control signal includes asserting driver enable signals for the first driver and the second driver.

17. The method of claim 14, wherein adjusting the driver control signal includes causing the second driver to stop generating the second current.

18. The method of claim 14, wherein generating the second current comprises: The fuse of the OTP unit is blown.

19. The method of claim 14, wherein generating the second current comprises: The anti-fuse of the OTP unit is blown.

20. The method of claim 14, further comprising: Change the output signal of the comparator; as well as The driver control signal is adjusted based on the output signal of the comparator.

21. A read-only memory (ROM), comprising: A component used to generate the first current on the first line; A component used to generate a second current on the second bit line; A reference resistor is coupled between the first line and ground; A one-time programmable OTP unit is coupled between the second bit line and the ground; as well as A component for turning off the component for generating a second current on the second bit line in response to a change in voltage at the second bit line relative to voltage at the first bit line. The component for turning off the component for generating a second current on the second bit line in response to a change in voltage at the second bit line relative to voltage at the first bit line includes a comparator having a first input coupled to the first bit line, a second input coupled to the second bit line, and an output coupled to logic circuitry configured to enable the component for generating a first current on the first bit line and the component for generating a second current on the second bit line.

22. The ROM of claim 21, further comprising a multiplexer coupled to the means for generating a second current on a second bit line and the means for generating a third current on a third bit line.

23. The ROM of claim 22, further comprising control circuitry configured to provide an N-bit input to the multiplexer, wherein N is an integer equal to the number of OTP cells in the ROM.

24. The ROM of claim 21, wherein the component for turning off the component for generating a second current on the second bit line in response to a change in voltage at the second bit line relative to voltage at the first bit line includes a sense amplifier configured to receive the voltage at the second bit line and the voltage at the first bit line.

25. The ROM of claim 21, wherein the OTP unit includes an antifuse.

26. The ROM of claim 21, wherein the component for generating a first current on the first bit line includes an inverter coupled to the first bit line, the inverter being configured to receive an enable signal from the component for turning off the component for generating a second current on the second bit line in response to a change in voltage at the second bit line relative to voltage at the first bit line.

27. The ROM of claim 21, wherein the component for turning off the component for generating a second current on the second bit line in response to a change in voltage at the second bit line relative to voltage at the first bit line comprises: A comparator configured to receive the voltage at the first bit line and the voltage at the second bit line; as well as An OR gate, which receives the output of the comparator and is configured to provide an enable signal to the component for generating a first current on the first bit line and the component for generating a second current on the second bit line.

28. The ROM of claim 21, wherein the reference resistor is sized such that when the OTP cell is blown, the voltage at the first bit line is lower than the voltage at the second bit line.

29. The ROM of claim 21, wherein the reference resistor is sized such that when the OTP cell is not blown, the voltage at the first bit line is higher than the voltage at the second bit line.

30. The ROM of claim 21, wherein the first input of the component for turning off the component for generating a second current on the second bit line in response to a change in voltage at the second bit line relative to voltage at the first bit line is coupled to the first bit line via a read word line transistor.

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