Device carrier for interconnects, package implementing a device carrier with interconnects, and manufacturing process thereof

Abstract

A device comprising: a surface mount device carrier configured to be mounted to a metal base of a transistor package, the surface mount device carrier comprising an insulating substrate comprising a top surface and a bottom surface and a first pad and a second pad disposed on the top surface of the surface mount device carrier; at least one surface mount device comprising a first terminal and a second terminal, the first terminal of the surface mount device mounted on the first pad, the second terminal mounted on the second pad; at least one of the first terminal and the second terminal configured to be isolated from the metal base by the insulating substrate, wherein at least one of the first pad and the second pad is configured to be a wire bond pad.

Description

[0001] Citations of relevant applications

[0002] This application claims the benefit of U.S. Patent Application No. 16 / 797,290, filed February 21, 2020, entitled “Constructing a device carrier for interconnects, realizing a package of a device carrier having interconnects and a manufacturing process thereof,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a device carrier configured for interconnects. This disclosure further relates to a package implementing a device carrier having interconnects. This disclosure further relates to a radio frequency (RF) package implementing an RF device with a device carrier having interconnects. This disclosure further relates to an RF power amplifier transistor package implementing an RF device with a device carrier having interconnects. This disclosure further relates to a process for manufacturing a device carrier configured for interconnects. This disclosure further relates to a process for manufacturing a package implementing a device carrier having interconnects. This disclosure further relates to a process for manufacturing an RF package implementing an RF device with a device carrier having interconnects. This disclosure further relates to a process for manufacturing an RF power amplifier transistor package implementing an RF device with a device carrier having interconnects. Background Technology

[0004] Radio frequency (RF) power amplifier transistor products use high-quality Q capacitors closely spaced from the transistor die to achieve higher video bandwidth. Silicon-based capacitors (trench CAPs or similar capacitors) are currently being used because they can be attached to a heatsink close to the semiconductor transistor die. However, silicon-based capacitors are expensive and offer limited capacitance. These silicon-based capacitors use trenches or vias to increase their Q value, but the capacitance is limited to the nF range. This necessitates a greater number of silicon-based capacitors to provide the required capacitance, further increasing costs. Furthermore, the increased number of silicon-based capacitors increases manufacturing costs associated with die attachment, increases the number of wire bonds, and increases manufacturing complexity, thus reducing yield.

[0005] Compared to silicon-based capacitors (in the nF range), surface-mount device (SMD) ceramic capacitors are cheaper, have higher Q values, and offer greater capacitance (in the μF range). These SMD devices are designed to be mounted directly onto traces or contacts on a circuit board. SMD devices are incompatible with typical RF transistor packages because they cannot be mounted on the metal heatsinks typically used in RF packages. SMD capacitors have two terminals on their bottom surface—which would short-circuit when mounted on the metal flange (heatsink) of a typical RF transistor package. Furthermore, SMD devices cannot be connected using wire bonding, which is typically used in RF transistor packages.

[0006] Therefore, there is a need for an RF product that can realize a device carrier that can utilize various component structures to reduce packaging costs, packaging manufacturing costs, and manufacturing complexity. Summary of the Invention

[0007] This disclosure relates to a surface mount device (SMD) carrier that enables the use of any and all types of surface mount devices (SMDs), such as ceramic capacitors, oscillators, etc., in RF transistor packages using wire bonding and / or metal bases, thereby reducing costs without sacrificing performance. According to certain aspects of this disclosure, an RF power package includes a package support; at least one device carrier including at least one device; a substrate configured to support the at least one device; the substrate including at least one first terminal disposed on an upper surface of the carrier; the at least one device disposed on the substrate and connected to the at least one first terminal; the substrate including one of the following elements: a printed circuit board (PCB) element, a ceramic element, a glass element, a low-temperature co-fired ceramic (LTCC) element, a high-temperature co-fired ceramic (HTCC) element, and a thick-film substrate element; at least one interconnect pad connected to at least one second terminal; the at least one device disposed on the substrate and connected to the at least one second terminal. At least one device carrier further includes: wherein at least one device is configured to be connected to at least one secondary device via at least one interconnect pad through one or more interconnects; wherein at least one device includes at least one of the following: a surface mount device (SMD) capacitor, a surface mount device (SMD) ceramic capacitor, a surface mount device (SMD) oscillator, a surface mount device (SMD) inductor, a surface mount device (SMD) resistor, a surface mount device (SMD) power divider, a surface mount device (SMD) power splitter, a surface mount device (SMD) amplifier, a surface mount device (SMD) balanced amplifier, or a surface mount device (SMD) combiner. At least one device carrier further includes a package support wherein a substrate is configured to be electrically connected to an RF package. At least one device carrier further includes a package support wherein at least one device is configured to be electrically connected to an RF package via at least one first terminal.

[0008] One aspect includes an RF transistor package comprising: a metal base; a transistor die mounted to the metal base; a surface mount device carrier mounted to the metal base, the surface mount device carrier including an insulating substrate including a top surface and a bottom surface, and a first pad and a second pad disposed on the top surface of the surface mount device carrier; at least one surface mount device including a first terminal and a second terminal, the first terminal of the surface mount device being mounted on the first pad and the second terminal being mounted on the second pad; at least one of the first terminal and the second terminal being configured to be isolated from the metal base by the insulating substrate; and at least one lead bonded to at least one of the first pad and the second pad.

[0009] One aspect includes a device comprising: a surface mount device carrier configured to be mounted to a metal base of a transistor package, the surface mount device carrier including an insulating substrate including a top surface and a bottom surface, and a first pad and a second pad disposed on the top surface of the surface mount device carrier; at least one surface mount device including a first terminal and a second terminal, the first terminal of the surface mount device being mounted on the first pad and the second terminal being mounted on the second pad; at least one of the first terminal and the second terminal being configured to be isolated from the metal base by the insulating substrate, wherein at least one of the first pad and the second pad is configured as a wire bonding pad.

[0010] One aspect includes a process for implementing an RF transistor package, the process comprising: providing a metal substrate; mounting a transistor die onto the metal substrate; mounting a surface mount device carrier onto the metal substrate, the surface mount device carrier including an insulating substrate including a top surface and a bottom surface, and a first pad and a second pad disposed on the top surface of the surface mount device carrier; providing a first terminal and a second terminal on the surface mount device; mounting the first terminal of the surface mount device to the first pad and mounting the second terminal of the surface mount device to the second pad; configuring at least one of the first terminal and the second terminal to be isolated from the metal substrate by the insulating substrate; and attaching at least one wire bond to at least one of the first pad and the second pad.

[0011] One aspect includes a process for implementing a device, the process comprising: constructing a surface mount device carrier for mounting onto a metal substrate of a transistor package; constructing the surface mount device carrier with an insulating substrate to include a top surface and a bottom surface, and a first pad and a second pad disposed on the top surface of the surface mount device carrier; constructing at least one surface mount device having a first terminal and a second terminal; mounting the first terminal of the surface mount device onto the first pad, and mounting the second terminal of the surface mount device onto the second pad; and constructing at least one of the first terminal and the second terminal to be isolated from the metal substrate by the insulating substrate, wherein at least one of the first pad and the second pad is constructed as a wire bonding pad.

[0012] One general aspect includes an RF power package comprising: a package support; at least one device carrier including at least one device; a substrate configured to support the at least one device; the substrate including at least one first terminal disposed on a upper surface of the substrate; at least one device disposed on the substrate and connected to the at least one first terminal; the at least one device being configured to be electrically connected to the package support of the RF power package via the at least one first terminal and at least one interconnect pad; the at least one interconnect pad being connected to at least one second terminal; and at least one device disposed on the substrate and connected to the at least one second terminal and at least one secondary device, the at least one secondary device including secondary device interconnect pads; the at least one device being configured to be electrically connected to the package support of the RF power package via at least one interconnect pad. The pads are connected to at least one secondary device via one or more interconnects, wherein at least one device comprises at least one of the following: a surface mount device (SMD) capacitor, a surface mount device (SMD) oscillator, a surface mount device (SMD) ceramic capacitor, a surface mount device (SMD) inductor, a surface mount device (SMD) resistor, a surface mount device (SMD) power divider, a surface mount device (SMD) power splitter, a surface mount device (SMD) amplifier, a surface mount device (SMD) balanced amplifier, or a surface mount device (SMD) combiner; and wherein the substrate is configured to be mounted on the upper surface of the package support by at least one of the following methods: adhesive bonding, soldering, sintering, eutectic bonding, or ultrasonic welding.

[0013] In one embodiment, this disclosure relates to an RF package having metal flanges, metal leadframes, bases, etc., as described herein. The metal flange implementation may have a ceramic cap; and the metal leadframe implementation may be sealed with a molding compound. The RF package may house RF devices, such as GaN-based HEMT dies, silicon-based LDMOS transistor dies, etc., as described herein. These RF devices may include matching networks. Prior art RF packages use expensive silicon-based capacitors that are wire-bonded to RF devices such as dies via input and / or output leads. In some aspects of this disclosure, this disclosure utilizes less expensive ceramic-based surface mount devices (SMDs). More specifically, this disclosure utilizes less expensive ceramic-based surface mount devices (SMDs) with traces that can be directly mounted onto a PCB, instead of using wire bonding as used with capacitors in typical RF packages, to replace more expensive silicon-based capacitors. In various aspects, this disclosure relates to mounting one or more surface mount discrete devices (SMDs) onto a base that can be mounted on metal flanges, metal leadframes, bases, etc. The base can be connected to RF devices, such as dies, via wire bonding or similar means using the input and / or output leads of the RF package. The base can be metal-based.

[0014] Additional features, advantages, and aspects of this disclosure may be apparent or understood by considering the following detailed description, accompanying drawings, and claims. Furthermore, it should be understood that the foregoing overview and the following detailed description of this disclosure are exemplary and intended to provide further explanation, without limiting the scope of the claimed disclosure. Attached Figure Description

[0015] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. These drawings illustrate various aspects of the present disclosure and, together with the detailed description, serve to illustrate the principles of the present disclosure. No attempt is made to show the structural details of the present disclosure in greater detail, but rather they may be necessary for a basic understanding of the present disclosure and its various possible practices. In the drawings:

[0016] Figure 1 The illustration shows a perspective view of the package according to this disclosure.

[0017] Figure 2 The diagram illustrates the following: Figure 1 A cross-sectional view of the package.

[0018] Figure 3 The illustration shows a perspective view of the package according to this disclosure.

[0019] Figure 4 The diagram illustrates the following: Figure 3 A cross-sectional view of the package.

[0020] Figure 5 The illustration shows a perspective view of a device carrier according to the present disclosure implemented in a package including at least one secondary device.

[0021] Figure 6 The diagram illustrates the following: Figure 5 An end view of the device carrier.

[0022] Figure 7 The diagram illustrates the following: Figure 5 A perspective view of the device carrier.

[0023] Figure 8 The diagram illustrates the following: Figure 5 A top view of the device carrier.

[0024] Figure 9 The diagram illustrates the following: Figure 5 An end view of the device carrier.

[0025] Figure 10 The diagram illustrates the following: Figure 7 A top view of the device carrier.

[0026] Figure 11 The diagram illustrates the following: Figure 10An end view of the device carrier.

[0027] Figure 12 The figure shows a top view of the device carrier according to the present disclosure.

[0028] Figure 13 The diagram illustrates the following: Figure 12 An end view of the device carrier.

[0029] Figure 14 The illustration shows a perspective view of a device carrier according to another aspect of this disclosure.

[0030] Figure 15 The diagram illustrates the following: Figure 14 An end view of the device carrier.

[0031] Figure 16 The diagram illustrates the following: Figure 14 A top view of the device carrier.

[0032] Figure 17 The diagram illustrates the following: Figure 14 An end view of the device carrier.

[0033] Figure 18 The diagram illustrates the following: Figure 17 A top view of the device carrier.

[0034] Figure 19 The diagram illustrates the following: Figure 14 An end view of the device carrier.

[0035] Figure 20 The diagram illustrates the following: Figure 19 A top view of the device carrier.

[0036] Figure 21 The diagram illustrates the following: Figure 7 A top view of the device carrier.

[0037] Figure 22 The diagram illustrates the following: Figure 14 A top view of the device carrier.

[0038] Figure 23 The diagram illustrates the following: Figure 7 A top view of the device carrier.

[0039] Figure 24 The diagram illustrates the following: Figure 14 A top view of the device carrier.

[0040] Figure 25 The process of manufacturing a device carrier according to this disclosure is shown.

[0041] Figure 26 The illustration shows a top view of the panel of the device carrier according to the present disclosure.

[0042] Figure 27 The diagram illustrates the following: Figure 26 A perspective view of the panel of the device carrier.

[0043] Figure 28 The process of manufacturing a package according to this disclosure is shown. Detailed Implementation

[0044] The various aspects, features, and advantageous details of this disclosure are illustrated more fully with reference to the non-limiting aspects and examples described and / or illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features shown in the drawings are not necessarily drawn to scale, and as those skilled in the art will recognize, features of one aspect may be used in conjunction with those of other aspects, even if not explicitly stated herein. Descriptions of well-known elements and processing techniques may be omitted to avoid unnecessarily obscuring the aspects of this disclosure. The examples used herein are intended only to facilitate an understanding of how this disclosure may be practiced and to further enable those skilled in the art to practice the aspects of this disclosure. Therefore, the examples and aspects herein should not be construed as limiting the scope of this disclosure, which is defined only by the appended claims and applicable law. Furthermore, it should be noted that the same reference numerals denote similar parts in various views of the drawings and in different embodiments disclosed.

[0045] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0046] It should be understood that when an element, such as a layer, region, or substrate, is referred to as "on" or "extending" to another element, it can be directly on or directly extended to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly on" or "directly extended" to another element, no intermediate elements are present. Similarly, it should be understood that when an element, such as a layer, region, or substrate, is referred to as "over" or "extending" above another element, it can be directly over or directly extended above the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly over" or "directly over" and extending, no intermediate elements are present. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements are present.

[0047] As shown in the figure, this paper may use relative terms such as “below” or “above” or “over” or “under” or “horizontal” or “vertical” to describe the relationship between one element, layer, or region and another element, layer, or region. It should be understood that these terms, and those discussed above, are intended to cover different orientations of the device other than those depicted in the figure.

[0048] The terminology used herein is for descriptive purposes only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. It should be further understood that, when used herein, the terms “comprising,” “including,” and / or “containing” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0049] Unless otherwise defined, all terms used herein, including technical and scientific terms, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms used herein should be interpreted as having the same meaning as they have in the context of this specification and the relevant field, and should not be interpreted as having an idealized or overly formal meaning unless expressly defined herein.

[0050] Figure 1 The illustration shows a perspective view of the package according to this disclosure.

[0051] Figure 2 The diagram illustrates the following: Figure 1 A cross-sectional view of the package.

[0052] In particular, Figure 1 and Figure 2 An exemplary implementation of package 100 is shown, which may include any one or more other features, elements, arrangements, etc., as described herein. In particular, Figure 1 and Figure 2 This document illustrates a package 100 that can be implemented as an RF package, an RF amplifier package, an RF power amplifier package, a radio frequency (RF) power transistor package, a radio frequency (RF) power amplifier transistor package, and / or as described herein. Package 100 may include one or more semiconductor devices 400, at least one surface mount device carrier 200, and at least one secondary device 300. At least one surface mount device carrier 200 and / or at least one secondary device 300 may be implemented as an RF device as described herein. At least one surface mount device carrier 200 and / or at least one secondary device 300 may implement matching networks, harmonic termination circuits, integrated passive devices (IPDs), capacitors, resistors, inductors, etc.

[0053] One or more semiconductor devices 400 may be wide-bandgap semiconductor devices, ultra-wide-bandgap devices, GaN-based devices, metal-semiconductor field-effect transistors (MESFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), junction field-effect transistors (JFETs), bipolar junction transistors (BJTs), insulated-gate bipolar transistors (IGBTs), high electron mobility transistors (HEMTs), wide-bandgap (WBG) semiconductors, power modules, gate drivers, such as general-purpose broadband components, telecommunications components, L-band components, S-band components, X-band components, C-band components, Ku-band components, satellite communication components, Doherty structures, etc.

[0054] Package 100 may be implemented as including an open-cell configuration suitable for use with at least one surface mount device carrier 200 and at least one secondary device 300 of the present disclosure. In particular, the open-cell configuration may utilize an open-cell packaging design. In some aspects, the open-cell configuration may include a cover or other package for protecting interconnects, circuit elements, at least one surface mount device carrier 200, at least one secondary device 300, one or more semiconductor devices 400, etc. Package 100 may include a ceramic body 402 and one or more metal contacts 404.

[0055] Within package 100, one or more semiconductor devices 400 can be attached to support 102 via die attachment material 422. One or more bonding wires 424 can connect one or more semiconductor devices 400 to a first and a second of one or more metal contacts 404. Furthermore, within package 100, at least one surface mount device carrier 200 and at least one secondary device 300 can be arranged on support 102 as described herein via one or more interconnects 104 illustrated in an exemplary configuration, which can connect the packages 100, at least one surface mount device carrier 200, at least one secondary device 300, and / or one or more semiconductor devices 400. Support 102 can dissipate heat generated by one or more semiconductor devices 400, at least one surface mount device carrier 200, and at least one secondary device 300, while isolating and protecting one or more semiconductor devices 400, at least one surface mount device carrier 200, and at least one secondary device 300 from external environmental influences.

[0056] Package 100 may include a support member 102. The support member 102 may be a metal base, or it may be a support, surface, package support, package surface, package support surface, flange, metal flange, heat sink, common source support, common source surface, common source package support, common source package surface, common source package support surface, common source flange, common source heat sink, lead frame, metal lead frame, etc. The support member 102 may include insulating materials, dielectric materials, etc.

[0057] Furthermore, package 100 may include one or more transistors having one or more transistor dies directly or indirectly attached to substrate 102, such as Figure 2 and Figure 4 As shown. One or more transistors having one or more transistor dies may include one or more laterally diffused metal-oxide-semiconductor (LDMOS) transistors, GaN-based transistors, metal-semiconductor field-effect transistors (MESFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), junction field-effect transistors (JFETs), bipolar junction transistors (BJTs), insulated-gate bipolar transistors (IGBTs), high electron mobility transistors (HEMTs), wide bandgap (WBG) transistors, etc.

[0058] Figure 3 The illustration shows a perspective view of the package according to this disclosure.

[0059] Figure 4 The diagram illustrates the following: Figure 3 A cross-sectional view of the package.

[0060] In particular, Figure 3 and Figure 4 Another exemplary implementation of package 100 is shown, which may include any one or more other features, components, arrangements, etc., as described herein. In particular, Figure 3 and Figure 4 This illustration shows a package 100 that can be implemented as an RF package, an RF amplifier package, an RF power amplifier package, a radio frequency (RF) power transistor package, a radio frequency (RF) power amplifier transistor package, and / or as described herein. Package 100 may include one or more semiconductor devices 400, at least one surface mount device carrier 200, and at least one secondary device 300.

[0061] Furthermore, within package 100, at least one surface mount device carrier 200 and at least one secondary device 300 can be arranged on support 102 via one or more interconnects 104 illustrated in the exemplary configuration herein. Package 100 may include overmolded portion 530, one or more input / output pins 532, and support 102. Overmolded portion 530 may substantially surround one or more semiconductor devices 400 mounted on support 102 using die attachment material 538. Overmolded portion 530 may be formed of plastic or plastic polymer compound and may be injection molded around support 102, one or more semiconductor devices 400, at least one surface mount device carrier 200, and at least one secondary device 300 to provide protection against external environmental influences. One or more semiconductor devices 400 may be coupled to one or more input / output pins 532 via bonding wires 540.

[0062] In one aspect, the overmolded component configuration may substantially surround one or more semiconductor devices 400, at least one surface mount device carrier 200, and at least one secondary device 300. The overmolded component configuration may be formed from plastics, molding compounds, plastic compounds, polymers, polymer compounds, plastic polymer compounds, etc. The overmolded component configuration may be injection molded, transfer molded, and / or compression molded around one or more semiconductor devices 400, at least one surface mount device carrier 200, and at least one secondary device 300, thereby providing protection for at least one surface mount device carrier 200, at least one secondary device 300, one or more semiconductor devices 400, and other elements of the package 100 from external environmental influences.

[0063] Figure 5 The illustration shows a perspective view of a device carrier according to the present disclosure implemented in a package including at least one secondary device.

[0064] Figure 6 The diagram illustrates the process based on... Figure 5An end view of the device carrier according to the present disclosure, which is implemented in a package including at least one secondary device.

[0065] In particular, Figure 5 and Figure 6 The illustration shows a package 100 and at least one surface mount device carrier 200 implementing at least one device 202. At least one surface mount device carrier 200 can be implemented within the package 100. At least one surface mount device carrier 200 can be implemented as an RF device, and at least one surface mount device carrier 200 can connect at least one device 202 to the package 100, to at least one secondary device 300, to one or more semiconductor devices 400, etc. At least one surface mount device carrier 200 can be implemented as a device carrier. At least one surface mount device carrier 200 can be implemented as a base.

[0066] In one embodiment, package 100 can be implemented as an RF package having a support 102, which can be implemented as a metal base including a metal flange, a metal lead frame, a base, etc., as described herein. The metal flange can be implemented with a ceramic cap; and the metal lead frame can be implemented by sealing with a molding compound. Other configurations are described herein. Package 100 can be implemented as an RF package and can accommodate an RF device. The RF device can be constructed and implemented in at least one surface mount device carrier 200 and / or at least one secondary device 300. In particular, the RF device can be constructed and implemented in at least one surface mount device carrier 200 and / or at least one secondary device 300, and can include GaN-based HEMT dies, silicon-based LDMOS transistor dies, etc., as described herein. The RF device can include a matching network, harmonic termination circuitry, integrated passive devices (IPDs), etc.

[0067] Specifically, RF devices can be constructed and implemented as matching networks, harmonic termination circuits, integrated passive devices (IPDs), etc., in at least one surface mount device carrier 200 and / or at least one secondary device 300, and can utilize cheaper ceramic-based surface mount devices (SMDs) with traces typically directly mounted to at least one surface mount device carrier 200 instead of more expensive silicon-based capacitors. In various aspects, this disclosure is intended to mount one or more surface mount discrete devices (SMDs) onto at least one surface mount device carrier 200, which is implemented as a base that can be mounted on a support 102 such as a metal flange, metal lead frame, base, etc. The base can be connected to the RF device, such as a die, via wire bonding or similar means using the input and / or output leads of the RF package, and the base can be metal-based.

[0068] Although the accompanying drawings illustrate at least one surface mount device carrier 200 implementing a single one of at least one device 202, at least one surface mount device carrier 200 may implement a plurality of at least one device 202. Similarly, although the accompanying drawings illustrate a package 100 implementing a single one of at least one surface mount device carrier 200, package 100 may implement a plurality of at least one surface mount device carrier 200.

[0069] Figure 5 and Figure 6 Further illustration shows that at least one surface mount device carrier 200 can connect at least one device 202 to at least one secondary device 300 via one or more interconnects 104. More specifically, at least one surface mount device carrier 200 may include interconnect pads 206; and at least one secondary device 300 may include interconnect pads 306. Interconnect pads 206 may be interconnect bonding pads; and interconnect pads 306 may be interconnect bonding pads. One or more interconnects 104 may be connected to interconnect pads 206 and interconnect pads 306. Other types of connections for at least one surface mount device carrier 200 and / or at least one secondary device 300 are also contemplated.

[0070] One or more interconnects 104 can be implemented as one or more wires, leads, vias, edge plating, circuit traces, tracks, clips, etc. In one aspect, one or more interconnects 104 can utilize the same type of connection. In another aspect, one or more interconnects 104 can utilize different types of connections.

[0071] One or more interconnects 104 may utilize ball soldering, wedge soldering, compliant soldering, strip soldering, metal clip attachment, etc. In one aspect, one or more interconnects 104 may utilize the same type of connection. In another aspect, one or more interconnects 104 may utilize different types of connections.

[0072] One or more interconnects 104 may comprise various metallic materials, including one or more of aluminum, copper, silver, gold, etc. In one aspect, one or more interconnects 104 may utilize the same type of metal. In another aspect, one or more interconnects 104 may utilize different types of metal.

[0073] One or more interconnects 104 may be connected to interconnect pads 206 by adhesives, soldering, sintering, eutectic bonding, thermocompression bonding, ultrasonic bonding / soldering, clip components, and / or the like described herein. One or more interconnects 104 may be connected to interconnect pads 306 by adhesives, soldering, sintering, eutectic bonding, thermocompression bonding, ultrasonic bonding / soldering, clip components, and / or the like described herein. In one aspect, the connections may utilize the same type of connection. In another aspect, the connections may utilize different types of connections.

[0074] Package 100 may be implemented to include an open cavity configuration, an overmolded configuration, etc. In this regard, package 100 may be implemented to include an open cavity configuration suitable for use with at least one surface mount device carrier 200 and at least one secondary device 300 of this disclosure. In particular, the open cavity configuration may utilize an open cavity packaging design. In some aspects, the open cavity configuration may include a cover or other package for protecting interconnects, circuit elements, at least one surface mount device carrier 200, at least one secondary device 300, etc.

[0075] Alternatively, the package 100 may be implemented as including an overmolded structure suitable for use with at least one surface mount device carrier 200 and at least one secondary device 300 of the present disclosure. In one aspect, the overmolded structure may substantially surround at least one surface mount device carrier 200 and at least one secondary device 300. The overmolded structure may be formed of plastic, molding compound, plastic compound, polymer, polymer compound, plastic polymer compound, etc. The overmolded structure may be injection molded or compression molded around at least one surface mount device carrier 200 and at least one secondary device 300, thereby providing protection for at least one surface mount device carrier 200, at least one secondary device 300, and other components of the package 100 from external environmental influences.

[0076] At least one surface mount device carrier 200 may include a substrate 204. The substrate 204 may be a printed circuit board (PCB) component, a ceramic component, a glass component, a low-temperature co-fired ceramic (LTCC) component, a high-temperature co-fired ceramic (HTCC) component, a thick-film substrate component, etc. In one or more aspects, the substrate 204 may include polytetrafluoroethylene and / or hydrocarbon materials. In one or more aspects, the substrate 204 may include Teflon and / or hydrocarbon materials mixed with a ceramic filler, wherein the ceramic filler is implemented as a radio frequency (RF) material.

[0077] At least one device 202 may be one or more of the following: surface mount device (SMD) element, surface mount device (SMD) capacitor, ceramic capacitor, surface mount device (SMD) oscillator, surface mount device (SMD) ceramic capacitor, inductor, surface mount device (SMD) inductor, resistor, surface mount device (SMD) resistor, power divider, surface mount device (SMD) power divider, power splitter, surface mount device (SMD) power splitter, amplifier, balanced amplifier, surface mount device (SMD) amplifier, surface mount device (SMD) balanced amplifier, combiner, surface mount device (SMD) combiner, etc. At least one device 202 may be implemented as an RF device, RF circuit device, RF component device, etc. At least one device 202 can be implemented as a radio frequency device, radio frequency circuit device, radio frequency component device, etc., and can be one or more of the following: surface mount device (SMD) radio frequency component, surface mount device (SMD) radio frequency capacitor, radio frequency ceramic capacitor, surface mount device (SMD) oscillator, surface mount device (SMD) radio frequency ceramic capacitor, radio frequency inductor, surface mount device (SMD) radio frequency inductor, radio frequency resistor, surface mount device (SMD) radio frequency resistor, radio frequency power divider, surface mount device (SMD) radio frequency power divider, radio frequency power splitter, surface mount device (SMD) radio frequency power splitter, radio frequency amplifier, balanced radio frequency amplifier, surface mount device (SMD) radio frequency amplifier, surface mount device (SMD) radio frequency balanced amplifier, radio frequency combiner, surface mount device (SMD) radio frequency combiner, etc.

[0078] Package 100 can be implemented as an RF package and at least one device 202 can be implemented as a radio frequency (RF) device, which may include, connect to, and support a transmitter, transmitter functions, a receiver, receiver functions, a transceiver, transceiver functions, a matching network function, harmonic termination circuitry, an integrated passive device (IPD), etc. At least one device 202 implemented as an RF device can be configured to support transmitting radio waves and modulating the waves to carry data with permissible transmitter power output, harmonics, and / or band edge requirements. At least one device 202 implemented as an RF device can be configured to support receiving radio waves and demodulating radio waves. At least one device 202 implemented as an RF device can be configured to support transmitting radio waves and modulating the waves to carry data with permissible transmitter power output, harmonics, and / or band edge requirements; and can be configured or can support receiving radio waves and demodulating radio waves.

[0079] In this respect, at least one device 202 may include terminals disposed on the bottom surface. Therefore, directly mounting a device such as at least one device 202 onto the support 102 of package 100 will result in a short circuit. For example, at least one device 202 implemented as a surface mount device (SMD) element, such as a surface mount device (SMD) ceramic capacitor, may include one or more terminals disposed on the bottom surface of the surface mount device (SMD) element. Therefore, mounting at least one device 202 configured as a surface mount device (SMD) element onto the support 102 of package 100 will result in a short circuit.

[0080] Therefore, this disclosure utilizes a substrate 204 of at least one surface mount device carrier 200 to support at least one device 202. The substrate 204 can be mounted on the upper surface 106 of the support 102. The substrate 204 can be mounted on the upper surface 106 of the support 102 by adhesives, soldering, sintering, eutectic bonding, ultrasonic welding, and / or similar methods described herein. In one aspect, the substrate 204 can be directly mounted on the upper surface 106 of the support 102. In another aspect, the substrate 204 can be mounted on the upper surface 106 of the support 102 by means of intervening structures, elements, etc. Figure 5 As shown, the upper surface 106 of the support member 102 can be parallel to the x-axis; and as... Figure 5 As shown, substrate 204 may be arranged vertically above support 102 along the y-axis. In one aspect, substrate 204 may be at least partially insulated. More specifically, substrate 204 may at least partially insulate at least one device 202 from support 102.

[0081] At least one secondary device 300 can be mounted on the upper surface 106 of the support 102. The at least one secondary device 300 can be mounted on the upper surface 106 of the support 102 by means of adhesives, welding, sintering, eutectic bonding, ultrasonic welding, etc. In one aspect, at least one secondary device 300 can be directly mounted on the upper surface 106 of the support 102. In another aspect, at least one secondary device 300 can be mounted on the upper surface 106 of the support 102 by means of intervening structures, components, etc. Figure 5 As shown, at least one secondary device 300 may be arranged vertically above the support 102 along the y-axis. As described herein, at least one secondary device 300 may be attached to the support 102 by adhesives, soldering, sintering, eutectic bonding, ultrasonic welding, and / or similar methods. At least one secondary device 300 may be a printed circuit board (PCB) component, a ceramic component, a glass component, a low-temperature co-fired ceramic (LTCC) component, a high-temperature co-fired ceramic (HTCC) component, a thick film substrate component, etc.

[0082] The adhesive disclosed herein can be used in an adhesive bonding process that may include applying an intermediate layer to bond surfaces to be bonded. The adhesive may be organic or inorganic; and the adhesive may be deposited on one or both surfaces to be bonded. The adhesive can be used in an adhesive bonding process that may include applying an adhesive material with a specific coating thickness in an environment that may include applying specific tooling pressure at a specific bonding temperature and a specific processing time. In one aspect, the adhesive may be a conductive adhesive, an epoxy-based adhesive, a conductive epoxy-based adhesive, etc.

[0083] The solder disclosed herein can be used to form solder interfaces that may include solder and / or be formed by solder. The solder can be any fusible metal alloy that can be used to form a bond between surfaces to be joined. The solder can be lead-free solder, lead solder, eutectic solder, etc. Lead-free solder may contain tin, copper, silver, bismuth, indium, zinc, antimony, trace amounts of other metals and / or the like. Lead solder may contain lead, other metals such as tin, silver, and / or the like. The solder may further include flux as needed.

[0084] The sintering disclosed herein can utilize a process of compacting and forming a solid material block by heat and / or pressure. The sintering process can be carried out without melting the material to its liquefaction point. The sintering process can include the sintering of metal powders. The sintering process can include sintering in a vacuum. The sintering process can include sintering using a protective gas.

[0085] The eutectic bonding disclosed herein can utilize bonding processes that form a eutectic system through an intermediate metal layer. The eutectic system can be used between the surfaces to be joined. Eutectic bonding can utilize a eutectic metal, which can be an alloy that transforms from a solid to a liquid state or from a liquid to a solid state without two-phase equilibrium at specific compositions and temperatures. The eutectic alloy can be deposited by sputtering, dual-source evaporation, electroplating, and / or similar methods.

[0086] The ultrasonic welding disclosed herein utilizes a process in which high-frequency ultrasonic acoustic vibrations are locally applied to components held together under pressure. Ultrasonic welding can produce a solid-state weld between the surfaces to be joined. In one aspect, ultrasonic welding may include applying an ultrasonic force.

[0087] Package 100 can be implemented in any number of different applications. In this regard, Package 100 can be implemented in applications such as high video bandwidth power amplifier transistors, single-path RF power transistors, single-stage RF power transistors, multi-path RF power transistors, Doherty-structured multi-stage RF power transistors, GaN-based RF power amplifier modules, side-diffused metal-oxide-semiconductor (LDMOS) devices, LDMOS RF power amplifier modules, RF power devices, ultra-wideband devices, GaN-based devices, metal-semiconductor field-effect transistors (MESFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), junction field-effect transistors (JFETs), bipolar junction transistors (BJTs), insulated-gate bipolar transistors (IGBTs), high electron mobility transistors (HEMTs), wide-bandgap (WBG) semiconductors, power modules, gate drivers, and components such as general-purpose broadband components, telecommunications components, L-band components, S-band components, X-band components, C-band components, Ku-band components, satellite communication components, etc. Package 100 can be implemented as a power package. Package 100 can be implemented as a power package and can realize the applications and components described herein.

[0088] Package 100 can be implemented as a radio frequency (RF) package. Package 100 can be implemented as an RF package and can realize the applications and components as described herein. Package 100 implemented as an RF package can include, connect to, and support a transmitter, transmitter function, receiver, receiver function, transceiver, transceiver function, etc. Package 100 implemented as an RF package can be configured to support transmitting radio waves and modulating the waves to carry data with permissible transmitter power output, harmonics, and / or band edge requirements. Package 100 implemented as an RF package can be configured to support receiving radio waves and demodulating radio waves. Package 100 implemented as an RF package can be configured to support transmitting radio waves and modulating the waves to carry data with permissible transmitter power output, harmonics, and / or band edge requirements; and can be configured to support receiving radio waves and demodulating radio waves.

[0089] At least one secondary device 300 can be an active device, a passive device, an integrated passive device (IPD), a transistor device, etc. At least one secondary device 300 can include any electrical component for any application. In this respect, at least one secondary device 300 can be a high video bandwidth power amplifier transistor, a single-path RF power transistor, a single-stage RF power transistor, a multi-path RF power transistor, a multi-stage RF power transistor, a GaN-based RF power amplifier module, a side-diffused metal-oxide-semiconductor (LDMOS) device, an LDMOS RF power amplifier module, an RF power device, an ultra-wideband device, a GaN-based device, a metal-semiconductor field-effect transistor (MESFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a junction field-effect transistor (JFET), a bipolar junction transistor (BJT), an insulated-gate bipolar transistor (IGBT), a high electron mobility transistor (HEMT), a wide bandgap (WBG) semiconductor, a power module, a gate driver, or components such as general-purpose broadband components, telecommunications components, L-band components, S-band components, X-band components, C-band components, Ku-band components, satellite communication components, etc. At least one secondary device 300 can be implemented as a radio frequency (RF) device, RF circuit, RF element, etc. The at least one secondary device 300 implemented as an RF device, RF circuit, RF element, etc., can include, connect to, and support a transmitter, transmitter function, receiver, receiver function, transceiver, transceiver function, etc. The at least one secondary device 300 implemented as an RF device can be configured to support transmitting radio waves and modulating the waves to carry data with permissible transmitter power output, harmonics, and / or band edge requirements. The at least one secondary device 300 implemented as an RF device can be configured to support receiving radio waves and demodulating radio waves. The at least one secondary device 300 implemented as an RF device can be configured to support transmitting radio waves and modulating the waves to carry data with permissible transmitter power output, harmonics, and / or band edge requirements; and can be configured or can support receiving radio waves and demodulating radio waves.

[0090] In one aspect, at least one secondary device 300 may be a high electron mobility transistor (HEMT). In this respect, the HEMT may be a group III nitride-based device, and such an HEMT may be implemented for high-power radio frequency (RF) applications, low-frequency high-power switching applications, and other applications. For example, the material properties of group III nitrides such as GaN and its alloys enable high voltage and high current, as well as high RF gain and linearity for RF applications. A typical group III nitride HEMT relies on the formation of a two-dimensional electron gas (2DEG) at the interface between a higher bandgap group III nitride (e.g., AlGaN) barrier layer and a lower bandgap group III nitride material (e.g., GaN) buffer layer, where the smaller bandgap material has higher electron affinity. The 2DEG is an accumulation layer in the smaller bandgap material and may contain high electron concentration and high electron mobility.

[0091] Figure 7 The diagram illustrates the following: Figure 5 A perspective view of the device carrier.

[0092] Figure 8 The diagram illustrates the following: Figure 5 A top view of the device carrier.

[0093] Figure 9 The diagram illustrates the following: Figure 5 An end view of the device carrier.

[0094] refer to Figure 7 , Figure 8 and Figure 9 The substrate 204 may include an upper surface 222. The upper surface 222 may lie in a plane generally parallel to the x-axis or in a plane generally parallel to the upper surface 106. The upper surface 222 may support interconnect pads 206. The interconnect pads 206 may include a first pad region 208, a second pad region 210, and a third pad region 212. However, based on applications such as package 100, at least one surface mount device carrier 200, at least one secondary device 300, etc., it is conceivable that the interconnect pads 206 may include any number of bonding pad regions. The interconnect pads 206, the first bonding pad region 208, the second bonding pad region 210, the third bonding pad region 212, and any other bonding pad region may be formed by a metal surface on the upper surface 222 of the substrate 204 and may include metallic materials such as copper, gold, nickel, palladium, silver, etc., and combinations thereof. In this regard, it can generally be defined as within 0°-15°, 0°-2°, 2°-4°, 4°-6°, 6°-8°, 8°-10°, 10°-12° or 12°–15°.

[0095] The upper surface 222 may further include a first terminal bonding pad 216. The first terminal bonding pad 216 may be located in a plane generally parallel to the x-axis or in a plane generally parallel to the upper surface 106. The first terminal bonding pad 216 may be connected to a first terminal 224 of at least one device 202. In this respect, a first connection 220 may be formed between the first terminal bonding pad 216 and the first terminal 224. The first connection 220 may include adhesives, soldering, sintering, eutectic bonding, ultrasonic welding, and / or similar methods as described herein. The first terminal bonding pad 216 may be formed from a metallic surface on the upper surface 222 of the substrate 204 and may include metallic materials such as copper, gold, nickel, palladium, silver, etc., and combinations thereof.

[0096] The upper surface 222 may further include a second terminal bonding pad 214. The second terminal bonding pad 214 may be located in a plane generally parallel to the x-axis or in a plane generally parallel to the upper surface 106. The second terminal bonding pad 214 may be connected to a first terminal 226 of at least one device 202. In this respect, a second connection 218 may be formed between the second terminal bonding pad 214 and the second terminal 226. The second terminal bonding pad 214 may be partially electrically connected to the interconnecting pad 206. The second connection 218 may include adhesives, soldering, sintering, eutectic bonding, ultrasonic welding, and / or similar methods as described herein. The second terminal bonding pad 214 may be formed from a metallic surface on the upper surface 222 of the substrate 204 and may include metallic materials such as copper, gold, nickel, palladium, silver, etc., and combinations thereof. Furthermore, the upper surface 222 of the substrate 204 may, as needed, include additional terminals for at least one device 202.

[0097] At least one surface mount device carrier 200 may include a metallization layer 240 located on the lower surface of a substrate 204 opposite to the upper surface 222. The metallization layer 240 may be located in a plane generally parallel to the x-axis or in a plane generally parallel to the upper surface 106. In one aspect, the metallization layer 240 may be implemented as a full-surface metallization layer on the lower surface of the substrate 204 opposite to the upper surface 222. Additionally or alternatively, at least one surface mount device carrier 200 may be single-sided (one metallization layer), double-sided (two metallization layers on either side of a substrate layer), or multi-layered (outer and inner layers of aluminum, copper, silver, gold, etc., alternating with the substrate layer). At least one surface mount device carrier 200 may include individual wires, traces, circuit traces, pads for connections, vias for transmitting connections between layers of aluminum, copper, silver, gold, etc., and features such as solid conductive areas for electromagnetic shielding or other purposes.

[0098] Additionally or alternatively, at least one surface mount device carrier 200 may include conductors on different layers that can be connected to vias, which may be metal-plated vias, such as copper-plated, aluminum-plated, silver-plated, gold-plated, etc., which can serve as electrical tunnels through an insulating substrate. At least one surface mount device carrier 200 may include "through-hole" elements that can be mounted via their leads passing through the substrate 204 and soldered to traces on another surface. At least one surface mount device carrier 200 may include "surface mount" elements that can be attached via their leads and / or terminals.

[0099] At least one surface mount device carrier 200 and / or metallization layer 240 can be manufactured using one or more manufacturing techniques, including printing screening or dispensing for solder paste, printing screening or dispensing for epoxy resin, screen printing, photolithography, printing on a transparent film, photomask process, photosensitive plate process, laser resist ablation process, milling process, laser etching process, and / or similar processes. In one or more aspects, at least one surface mount device carrier 200 can be a printed circuit board (PCB). In one or more aspects, at least one surface mount device carrier 200 can be configured to mechanically support and electrically connect at least one device 202 to at least one secondary device 300 and other electronic components.

[0100] Figure 10 The diagram illustrates the following: Figure 7 A top view of the device carrier.

[0101] Figure 11 The diagram illustrates the following: Figure 10 An end view of the device carrier.

[0102] In particular, Figure 10 and Figure 11 The illustration shows at least one surface mount device carrier 200, which may include any and all features, constructions, arrangements, embodiments, aspects, and / or similarities as described herein. Furthermore, Figure 10 and Figure 11The illustration shows that at least one surface mount device carrier 200 may include a via 228. The via 228 extends from a first terminal bonding pad 216 to a metallization layer 240. Thus, a first terminal 224 of at least one device 202 can be connected to the first terminal bonding pad 216 via a first connection 220 and at least connected to the metallization layer 240 via the via 228 to make electrical connection and / or electrical contact with the support 102. The via 228 may also extend through the metallization layer 240 to the support 102 to make electrical connection and / or electrical contact with the support 102. In other aspects, the via 228 may be implemented as a partial via. The via 228 may be a metal-plated via or a metal-filled via, which can serve as an electrical tunnel through the substrate 204. The via 228 may include metallic materials such as copper, gold, nickel, palladium, silver, etc., and combinations thereof. Furthermore, Figure 10 and Figure 11 The illustration shows that at least one surface mount device carrier 200 can implement two through holes 228. However, this is merely for illustrative purposes. At least one surface mount device carrier 200 may include 1-20 through holes 228, 1-2 through holes 228, 2-3 through holes 228, 3-4 through holes 228, 4-6 through holes 228, 6-8 through holes 228, 8-12 through holes 228, 12-16 through holes 228, or 16-20 through holes 228. The through holes 228 may have an axis that can be located in a plane generally perpendicular to the x-axis, a plane generally parallel to the x-axis, and / or a plane generally perpendicular to the upper surface 106.

[0103] Figure 12 The figure shows a top view of the device carrier according to the present disclosure.

[0104] Figure 13 The diagram illustrates the following: Figure 12 An end view of the device carrier.

[0105] In particular, Figure 12 and Figure 13 The illustration shows at least one surface mount device carrier 200, which may include any and all features, constructions, arrangements, embodiments, aspects, and / or similarities as described herein. Furthermore, Figure 12 and Figure 13The illustration shows that at least one surface mount device carrier 200 may include an edge plating layer 230. The edge plating layer 230 extends from a first terminal bonding pad 216 to a metallization layer 240. In this respect, the first terminal bonding pad 216 may extend to the edge 232 of at least one device 202 to connect to the edge plating layer 230. The edge plating layer 230 may be located in a plane generally perpendicular to the x-axis or in a plane generally perpendicular to the upper surface 106. Thus, a first terminal 224 of at least one device 202 can be connected to the first terminal bonding pad 216 via a first connection 220 and at least connected to the metallization layer 240 via the edge plating layer 230 to make electrical connection and / or electrical contact with the support 102. The edge plating layer 230 may also extend the metallization layer 240 to the support 102 to make electrical connection and / or electrical contact with the support 102. The edge plating layer 230 may include metallic materials such as copper, gold, nickel, palladium, silver, etc., and combinations thereof. In one or more aspects, the edge plating 230 includes a wiring and plating constellation configuration and / or an elongated via configuration also referred to as a castle-shaped or edge plating. In one or more aspects, the edge plating 230 can further reduce costs compared to using through-holes, since through-holes can sometimes become clogged.

[0106] Additionally or alternatively, at least one surface mount device carrier 200 may include one or more interconnects. One or more interconnects may extend from the first terminal bonding pad 216 to the support 102 for electrical connection and / or electrical contact with the support 102. One or more interconnects may be implemented as one or more wires, leads, through-holes, edge plating, circuit traces, tracks, clips, etc. In one aspect, one or more interconnects may utilize the same type of connection. In one aspect, one or more interconnects may utilize different types of connections. One or more interconnects may utilize ball bonding, wedge bonding, compliant bonding, strip bonding, metal clip attachment, etc. In one aspect, one or more interconnects may utilize the same type of connection. In one aspect, one or more interconnects may utilize different types of connections. One or more interconnects may include various metallic materials, including one or more of aluminum, copper, silver, gold, etc. In one aspect, one or more interconnects may utilize the same type of metal. In one aspect, one or more interconnects may utilize different types of metal. One or more interconnects may be connected to the first terminal bonding pad 216 by adhesives, soldering, sintering, eutectic bonding, thermocompression bonding, ultrasonic bonding / welding, clip components, and / or similar methods described herein. One or more interconnects may be connected to the support 102 by adhesives, soldering, sintering, eutectic bonding, thermocompression bonding, ultrasonic bonding / welding, clip components, and / or similar methods described herein.

[0107] Figure 14 The illustration shows a perspective view of a device carrier according to another aspect of this disclosure.

[0108] Figure 15 The diagram illustrates the following: Figure 14 An end view of the device carrier.

[0109] Figure 16 The diagram illustrates the following: Figure 14 A top view of the device carrier.

[0110] In particular, Figure 14 , Figure 15 and Figure 16 The illustration shows at least one surface mount device carrier 200, which may include any and all features, constructions, arrangements, embodiments, aspects, and / or similarities as described herein. Furthermore, Figure 14 , Figure 15 and Figure 16 The illustration shows that at least one surface-mount device carrier 200 can be implemented with a thinner construction relative to the x-axis. Therefore, Figure 14 , Figure 15 and Figure 16 The aspect may exclude the first bonding pad region 208 and the third bonding pad region 212.

[0111] Figure 17 The diagram illustrates the following: Figure 14 An end view of the device carrier.

[0112] Figure 18 The diagram illustrates the following: Figure 17 A top view of the device carrier.

[0113] In particular, Figure 17 and Figure 18 The illustration shows at least one surface mount device carrier 200, which may include any and all features, constructions, arrangements, embodiments, aspects, and / or similarities as described herein. Furthermore, Figure 17 and Figure 18 The illustration shows that at least one surface mount device carrier 200 may include a reference. Figure 10 and Figure 11 The described through-hole is 228.

[0114] Figure 19 The diagram illustrates the following: Figure 14 An end view of the device carrier.

[0115] Figure 20 The diagram illustrates the following: Figure 20 A top view of the device carrier.

[0116] In particular, Figure 19 and Figure 20The illustration shows at least one surface mount device carrier 200, which may include any and all features, constructions, arrangements, embodiments, aspects, and / or similarities as described herein. Furthermore, Figure 19 and Figure 20 The illustration shows that at least one surface mount device carrier 200 may include a reference. Figure 12 and Figure 13 The edge coating 230 is described.

[0117] Figure 21 The diagram illustrates the following: Figure 7 A top view of the device carrier.

[0118] In particular, Figure 21 The illustration shows at least one surface mount device carrier 200, which may include any and all features, constructions, arrangements, embodiments, aspects, and / or similarities as described herein. Additionally, Figure 21 Exemplary dimensions of at least one surface mount device carrier 200 and at least one device 202 are illustrated. The width of at least one device 202 can be defined as a depth d1. Depth d1 can be obtained along a line generally parallel to the x-axis. Furthermore, depth d1 can be defined as the length of at least one surface mount device carrier 200 along a line generally parallel to the x-axis or as a percentage of depth d2. In some aspects, depth d1 can be 10%–70% of depth d2, 10%–20% of depth d2, 20%–30% of depth d2, 30%–40% of depth d2, 40%–50% of depth d2, 50%–60% of depth d2, or 60%–70% of depth d2.

[0119] The length of at least one device 202 can be defined as a depth d3. Depth d3 can be obtained along a line generally parallel to the z-axis. Furthermore, depth d3 can be defined as the length of at least one surface mount device carrier 200 along a line substantially parallel to the z-axis, or as a percentage of depth d4. In some aspects, depth d3 can be 20%–90%, 20%–30%, 30%–40%, 40%–50%, 50%–60%, 60%–70%, 70%–80%, or 80%–90% of depth d4.

[0120] Figure 22 The diagram illustrates the following: Figure 14 A top view of the device carrier.

[0121] In particular, Figure 22 The illustration shows at least one surface mount device carrier 200, which may include any and all features, constructions, arrangements, embodiments, aspects, and / or similarities as described herein. Additionally, Figure 22Exemplary dimensions of at least one surface mount device carrier 200 and at least one device 202 are illustrated. The width of at least one device 202 can be defined as a depth d1. Depth d1 can be obtained along a line generally parallel to the x-axis. Furthermore, depth d1 can be defined as the length of at least one surface mount device carrier 200 along a line generally parallel to the x-axis or as a percentage of depth d2. In some aspects, depth d1 can be 10%–70% of depth d2, 10%–20% of depth d2, 20%–30% of depth d2, 30%–40% of depth d2, 40%–50% of depth d2, 50%–60% of depth d2, or 60%–70% of depth d2.

[0122] The length of at least one device 202 can be defined as a depth d3. Depth d3 can be obtained along a line generally parallel to the z-axis. Furthermore, depth d3 can be defined as a percentage of the length of at least one surface mount device carrier 200 along a line substantially parallel to the z-axis or of depth d4. In some aspects, depth d3 can be 20%–90% of depth d4, 20%–30% of depth d4, 30%–40% of depth d4, 40%–50% of depth d4, 50%–60% of depth d4, 60%–70% of depth d4, 70%–80% of depth d4, or 80%–90% of depth d4. In some aspects, as referenced herein... Figure 21 and Figure 22 The dimensions of d1, d2, d3 and / or d4 of the at least one surface mount device carrier 200 are crucial for ensuring close proximity to at least one secondary device 300 and / or other components of the package 100 to ensure higher performance of the package 100, etc.

[0123] Figure 23 The diagram illustrates the following: Figure 7 A top view of the device carrier.

[0124] In particular, Figure 23 The illustrations depict various possible arrangements and configurations of at least one surface mount device carrier 200, at least one secondary device 300, and / or one or more interconnects 104. For example... Figure 23 As shown, at least one secondary device 300 may be disposed on one side of at least one surface mount device carrier 200, and one or more interconnects 104 may be connected to a second bonding pad region 210; at least one secondary device 300 may be disposed on the other side of at least one surface mount device carrier 200, and one or more interconnects 104 may be connected to a third bonding pad region 212; and / or at least one secondary device 300 may be disposed on the other side of at least one surface mount device carrier 200, and one or more interconnects 104 may be connected to a first bonding pad region 208.

[0125] Figure 24 The diagram illustrates the following: Figure 14 A top view of the device carrier.

[0126] In particular, Figure 24 The illustrations depict various possible arrangements and configurations of at least one surface mount device carrier 200, at least one secondary device 300, and / or one or more interconnects 104. For example... Figure 24 As shown, at least one secondary device 300 may be arranged on one side of at least one surface mount device carrier 200, and one or more interconnects 104 may be connected to interconnect pads 206; at least one secondary device 300 may be arranged on the other side of at least one surface mount device carrier 200, and one or more interconnects 104 may be connected to interconnect pads 206; and / or at least one secondary device 300 may be arranged on the other side of at least one surface mount device carrier 200, and one or more interconnects 104 may be connected to interconnect pads 206.

[0127] Figure 25 The process of manufacturing a device carrier according to this disclosure is shown.

[0128] Figure 26 The illustration shows a top view of the panel of the device carrier according to the present disclosure.

[0129] Figure 27 The diagram illustrates the following: Figure 26 A perspective view of the panel of the device carrier.

[0130] In particular, Figure 25 The illustration shows a process 600 for forming a device carrier in relation to the surface mount device carrier 200 described herein. It should be noted that aspects of the process 600 for forming the device carrier can be performed in a different order consistent with the aspects described herein. Furthermore, it should be noted that portions of the process 600 for forming the device carrier can be performed in a different order consistent with the aspects described herein. Additionally, the process 600 for forming the device carrier can be modified to have more or fewer processes consistent with the aspects disclosed herein.

[0131] Initially, the process 600 for forming the device carrier may include a process 602 for forming a substrate. More specifically, the substrate 204 may be constructed, configured, and / or arranged as described herein. The process 602 for forming the substrate may include forming the substrate 204 into a printed circuit board (PCB) element, a ceramic element, a glass element, a low-temperature co-fired ceramic (LTCC) element, a high-temperature co-fired ceramic (HTCC) element, a thick-film substrate element, etc. In one aspect, the process 602 for forming the substrate may include forming the substrate 204 into a printed circuit board (PCB) element using a printed circuit board (PCB) manufacturing process.

[0132] Furthermore, the process 600 for forming the device carrier may include forming a metallization layer 604. More specifically, the metallization layer 240 may be constructed, configured, and / or disposed on at least a portion of the substrate 204 as described herein. The process 604 for forming the metallization layer may include utilizing one or more manufacturing techniques, including printing screening for solder paste, printing screening for epoxy resin, screen printing, photolithography, printing on a transparent film, photomask process, a combination of photomask and etching processes, photosensitive plate process, laser resist ablation process, milling process, laser etching process, direct metal printing process, and / or similar processes.

[0133] Furthermore, the process 600 for forming the device carrier may include forming interconnect pads 606. More specifically, interconnect pads 206 may be constructed, configured, and / or arranged on substrate 204 as described herein. The process 606 for forming interconnect pads may include utilizing one or more manufacturing techniques, including printing screens for solder paste, printing screens for epoxy resin, screen printing processes, photolithography processes, printing processes on transparent films, photomask processes, combinations of etching processes, photosensitive plate processes, laser resist ablation processes, milling processes, laser etching processes, direct metal printing processes, and / or similar processes.

[0134] Furthermore, the process 600 for forming the device carrier may include arranging at least one device on a substrate 608. More specifically, at least one device 202 may be constructed, configured, and / or arranged on a substrate 204 as described herein. In one aspect, at least one device 202 may be arranged on a substrate 204 with adhesives, solders, sintering, eutectic bonding, ultrasonic welding, etc., as described herein.

[0135] More specifically, the process 600 for forming the device carrier may include fabricating at least one surface-mount device carrier 200 in the panel 250 using a printed circuit board (PCB), such as Figure 26 and Figure 27 As shown. The process 600 for forming a device carrier may include implementing a pick-and-place assembly to place at least one device 202 onto at least one surface mount device carrier 200 of the panel 250. The process 600 for forming a device carrier may include performing a reflow process with the panel 250. The process 600 for forming a device carrier may include cutting the panel 250 using a cutting device such as a wafer, PCB, or package sawing equipment to singularize the at least one surface mount device carrier 200 with the panel 250. This may have the advantage that at least one surface mount device carrier 200 can be arranged on a cutting tape on an annular frame, which can be directly loaded onto a die mounting device for subsequent assembly into the package 100.

[0136] Figure 28 The process of manufacturing a package according to this disclosure is shown.

[0137] In particular, Figure 28 The illustration shows a process 700 for forming a package related to the package 100 described herein. It should be noted that various aspects of the package forming process 700 can be performed in a different order consistent with the aspects described herein. Furthermore, it should be noted that parts of the package forming process 700 can be performed in a different order consistent with the aspects described herein. Additionally, the package forming process 700 can be modified to have more or fewer processes consistent with the aspects disclosed herein.

[0138] Initially, the process of forming the package 700 may include a process of forming a support member 702. More specifically, the substrate 102 may be constructed, configured, and / or arranged as described herein. In one aspect, the process of forming the support member 702 may include forming the support member 102 as a support, surface, package support, package surface, package support surface, flange, heat sink, common source heat sink, etc.

[0139] The process of forming a package 700 may include a process 704 of forming at least one secondary device. More specifically, at least one secondary device 300 may be constructed, configured, and / or arranged as described herein. In one aspect, the process 704 of forming at least one secondary device may include forming at least one secondary device 300 as an active device, a passive device, an integrated passive device (IPD), a transistor device, etc. In one aspect, the process of forming at least one secondary device 704 may include forming at least one secondary device 300 as any electrical element for any application. In this regard, at least one secondary device 300 may be a high video bandwidth power amplifier transistor, a single-path RF power transistor, a single-stage RF power transistor, a multi-path RF power transistor, a multi-stage RF power transistor, a GaN-based RF power amplifier module, a side-diffused metal-oxide-semiconductor (LDMOS) device, an LDMOS RF power amplifier module, an RF power device, an ultra-wideband device, a GaN-based device, a metal-semiconductor field-effect transistor (MESFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a junction field-effect transistor (JFET), a bipolar junction transistor (BJT), an insulated-gate bipolar transistor (IGBT), a high electron mobility transistor (HEMT), a wide bandgap (WBG) semiconductor, a power module, a gate driver, or other components such as general-purpose broadband components, telecommunications components, L-band components, S-band components, X-band components, C-band components, Ku-band components, satellite communication components, etc.

[0140] The process of forming the package 700 may include the process of forming a device carrier 600. More specifically, at least one surface mount device carrier 200 may be as described herein. Figure 25 The device carrier is constructed, configured, and / or arranged as described in the relevant description. Subsequently, the process 600 for forming the device carrier may further include attaching at least one surface-mount device carrier 200 to the support 102. In this regard, at least one surface-mount device carrier 200 and / or substrate 204 may be mounted on the upper surface 106 of the support 102 by adhesives, soldering, sintering, eutectic bonding, ultrasonic welding, and / or similar methods as described herein.

[0141] The process of forming a package 700 may include a process 706 of forming one or more interconnects. More specifically, one or more interconnects 104 may be constructed, configured, and / or arranged as described herein. In one aspect, the process 706 of forming one or more interconnects may include forming one or more interconnects 104 by forming one or more wires, leads, vias, edge plating, circuit traces, tracks, etc. In one aspect, the process 706 of forming one or more interconnects may include connecting one or more interconnects 706 by adhesives, soldering, sintering, eutectic bonding, ultrasonic welding, clip elements, and / or similar methods as described herein.

[0142] The process of forming a package 700 may include a process of hermetically sealing the package 700. More specifically, the package 100 may be constructed, configured, and / or arranged as described herein. In one aspect, the process of hermetically sealing the package 700 may include forming an opening structure, an overmolding structure, etc.

[0143] In one or more aspects, this disclosure provides devices and processes for realizing high-quality factor Q capacitor devices at the final proximity of a transistor, for example, to achieve high video bandwidth for power amplifier transistors. Silicon-based capacitors, such as trench capacitors, have been used because they can be attached to a heat sink immediately adjacent to the semiconductor transistor die. This disclosure allows the use of ceramic surface mount device (SMD) capacitors to be attached within the package near the transistor by means of a substrate (e.g., PCB, LTCC, HTCC, ceramic, glass) on which the capacitor is mounted prior to die mounting. In this respect, having a substrate that can be mounted to a heat sink allows not only the addition of one or more different capacitors on one or more substrates, but also the addition of resistors, inductors, etc., on one or more substrates. In this respect, silicon-based capacitors typically provide only about 30 nanofarads (nF) of capacitance, while ceramic surface mount device (SMD) capacitors described in this disclosure typically provide 10 microfarads (μF) of capacitance. Therefore, this disclosure enables the realization of capacitances with much larger values.

[0144] Furthermore, ceramic surface mount device (SMD) capacitors with two terminals on the bottom surface may short-circuit when mounted on a metal flange (heat sink). To enable the use of such ceramic capacitors on heat sinks, this disclosure utilizes, for example, a PCB to route one terminal to the bottom of the substrate using VIA or edge plating, while keeping the other terminal isolated from the others and providing wire bonding pads so that it can be connected to a transistor die. In contrast, using silicon-based capacitors to improve the quality factor Q through trenches or vias to achieve a high quality factor Q capacitor device still only provides capacitance in the nF range, while ceramic capacitors can achieve capacitance in the μF range. In one aspect, as described in this disclosure, a cost-effective way to implement this disclosure is to use a PCB as the substrate material, create a small substrate using standard PCB manufacturing processes, attach ceramic capacitors to this small substrate using solder paste or epoxy printing screening or dispensing in a large-volume SMD production line, and assemble them in a large panel by picking and placing them through a reflow process. Furthermore, these substrates can be simplified using wafer sawing equipment, which has the advantage that the substrates are already placed on a dicing tape on a ring frame, which can be automatically loaded onto a chip mounting device for subsequent assembly into a package.

[0145] Therefore, this disclosure discloses devices and processes for achieving higher performance in a single package by placing devices close to each other. For example, high-quality Q-factor capacitor devices are placed close to related secondary devices. Furthermore, this disclosure discloses devices and processes that can be attached to a heat sink using a carrier device adjacent to and connected to a secondary device such as a semiconductor transistor die. Furthermore, this disclosure discloses devices and processes utilizing elements with greater capability, lower cost, and / or similar benefits. Furthermore, this disclosure discloses devices and processes that lead to reduced manufacturing costs. Furthermore, this disclosure discloses devices and processes that can implement various component configurations to reduce packaging costs, reduce packaging manufacturing costs, reduce manufacturing complexity, reduce yield losses, etc.

[0146] Although this disclosure has been described with reference to exemplary aspects, those skilled in the art will recognize that this disclosure can be practiced with modifications within the spirit and scope of the appended claims. The examples given above are merely illustrative and are not intended to be an exhaustive list of all possible designs, aspects, applications, or modifications of this disclosure.

Claims

1. An RF transistor package, comprising, Metal base; A transistor die is mounted onto the metal base; A surface mount device carrier is mounted on the metal base. The surface mount device carrier includes an insulating substrate, the insulating substrate includes a top surface and a bottom surface, and a first pad and a second pad disposed on the top surface of the surface mount device carrier. At least one surface mount device, including a first terminal and a second terminal, wherein the first terminal of the surface mount device is mounted to a first pad and the second terminal is mounted to a second pad; At least one of the first terminal and the second terminal is configured to be isolated from the metal base by the insulating substrate; as well as At least one wire bond is bonded to at least one of the first pad and the second pad of the surface mount device carrier; The transistor die is disposed on one side of the surface mount device carrier; Wherein, the width of the at least one surface mount device is 10% to 70% of the width of the surface mount device carrier, and / or the length of the at least one surface mount device is 30% to 90% of the length of the surface mount device carrier; and The at least one wire bond is configured to electrically connect the surface mount device to an integrated passive device, the integrated passive device being disposed on the metal base and also disposed on one side of the surface mount device carrier.

2. The RF transistor package of claim 1, wherein, The surface mount device includes a ceramic capacitor.

3. The RF transistor package according to claim 1, wherein: The transistor die includes one of the following components: an LDMOS transistor die and a GaN-based HEMT die; and The insulating substrate includes one of the following elements: a printed circuit board (PCB) element, a ceramic element, a glass element, a low-temperature co-fired ceramic (LTCC) element, a high-temperature co-fired ceramic (HTCC) element, and a thick film substrate element.

4. The RF transistor package of claim 1, wherein, The RF transistor package includes multiple transistors.

5. The RF transistor package of claim 4, wherein, The plurality of transistors are configured in a Doldie configuration.

6. The RF transistor package of claim 1, wherein, The surface mount device carrier includes a plurality of surface mount devices mounted on the top surface of the surface mount device carrier.

7. The RF transistor package of claim 1, wherein, The insulating substrate includes an edge plating layer configured to establish an electrical connection between the surface mount device and the metal base.

8. The RF transistor package of claim 1, wherein, The at least one wire bond is configured to electrically connect the surface mount device to the transistor die.

9. The RF transistor package of claim 1, wherein, The integrated passive device includes at least one matching network and / or harmonic termination circuit.

10. A device comprising: A surface mount device carrier is configured to be mounted on a metal base of a transistor package. The surface mount device carrier includes an insulating substrate, the insulating substrate including a top surface and a bottom surface, and a first pad and a second pad disposed on the top surface of the surface mount device carrier. At least one surface mount device, including a first terminal and a second terminal, wherein the first terminal of the surface mount device is mounted to a first pad and the second terminal is mounted to a second pad; At least one of the first terminal and the second terminal is configured to be isolated from the metal base by the insulating substrate; The surface mount device carrier is configured to be implemented in an RF transistor package including a transistor die, the transistor die being disposed on one side of the surface mount device carrier; Wherein, at least one of the first pad and the second pad is configured as a wire bonding pad; and In this embodiment, at least one wire bond is configured to electrically connect the surface mount device to an integrated passive device disposed on a metal base and also disposed on one side of the surface mount device carrier.

11. The device according to claim 10, wherein, The surface mount device includes a ceramic capacitor.

12. The device according to claim 10, wherein: The surface mount device carrier is configured to be implemented in an RF transistor package including a transistor die, the transistor die comprising one of the following elements: an LDMOS transistor die and a GaN-based HEMT die; and The insulating substrate includes one of the following elements: a printed circuit board (PCB) element, a ceramic element, a glass element, a low-temperature co-fired ceramic (LTCC) element, a high-temperature co-fired ceramic (HTCC) element, and a thick film substrate element.

13. The device according to claim 10, wherein, The surface mount device carrier is configured to be implemented in an RF transistor package that includes multiple transistors.

14. The device according to claim 13, wherein, The plurality of transistors are configured in a Doldie configuration.

15. The device according to claim 10, wherein, The surface mount device carrier includes a plurality of surface mount devices mounted on the top surface of the surface mount device carrier.

16. The device according to claim 10, wherein, The insulating substrate includes an edge plating layer configured to establish an electrical connection between the surface mount device and the metal base.

17. The device of claim 10, further comprising at least one wire bond configured to electrically connect the surface mount device to a die implemented in an RF transistor package.

18. The device according to claim 17, wherein, The at least one wire bond is configured to electrically connect the surface mount device to an integrated passive device.

19. A process for implementing RF transistor packaging, comprising, Metal base provided; The transistor die is mounted onto the metal base; A surface mount device carrier is mounted onto the metal base. The surface mount device carrier includes an insulating substrate, which includes a top surface and a bottom surface, as well as a first pad and a second pad disposed on the top surface of the surface mount device carrier. A first terminal and a second terminal are provided on the surface mount device; The first terminal of the surface mount device is mounted onto the first pad, and the second terminal of the surface mount device is mounted onto the second pad; At least one of the first terminal and the second terminal is configured to be isolated from the metal base by the insulating substrate; At least one wire bond is bonded to at least one of the first pad and the second pad of the surface mount device carrier; The at least one wire bond is configured to electrically connect the surface mount device to an integrated passive device, the integrated passive device being disposed on the metal base and also disposed on one side of the surface mount device carrier; The transistor die is disposed on one side of the surface mount device carrier; Wherein, the width of the at least one surface mount device is 10% to 70% of the width of the surface mount device carrier, and / or the length of the at least one surface mount device is 30% to 90% of the length of the surface mount device carrier.

20. The process for implementing RF transistor packaging according to claim 19, wherein, The surface mount device includes a ceramic capacitor.

21. The process for implementing an RF transistor package according to claim 19, further comprising constructing the insulating substrate as one of the following elements: a printed circuit board (PCB) element, a ceramic element, a glass element, a low-temperature co-fired ceramic (LTCC) element, a high-temperature co-fired ceramic (HTCC) element, and a thick-film substrate element. in, The transistor die includes one of the following components: LDMOS transistor die and GaN-based HEMT die.

22. The process for implementing an RF transistor package according to claim 19, further comprising implementing a plurality of transistors.

23. The process for implementing an RF transistor package according to claim 22, further comprising implementing the plurality of transistors in a Dultie configuration.

24. The process for implementing RF transistor packaging according to claim 19, further comprising: Realize a surface mount device carrier with multiple surface mount devices; as well as The plurality of surface mount devices are mounted onto the top surface of the surface mount device carrier.

25. The process for implementing an RF transistor package according to claim 19, further comprising configuring the insulating substrate to include an edge plating layer configured to establish an electrical connection between the surface mount device and the metal base.

26. The process for implementing an RF transistor package according to claim 19, further comprising constructing the at least one wire bond to electrically connect the surface mount device to the transistor die.

27. The process for implementing RF transistor packaging according to claim 19, wherein, The integrated passive device includes at least one matching network and / or harmonic termination circuit.

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