Red LED and manufacturing method

Abstract

A red light-emitting diode (LED) includes: an n-doped portion; a p-doped portion; and a light-emitting region located between the n-doped portion and the p-doped portion. The light-emitting region includes: a light-emitting indium gallium nitride layer that emits light with a peak wavelength between 600 nm and 750 nm under an electrical bias voltage across it; a group III nitride layer located on the light-emitting indium gallium nitride layer; and a group III nitride barrier layer located on the group III nitride layer. The LED also includes a porous region of group III nitride material. Red small LEDs, red micro-LEDs, micro-LED arrays, and methods for manufacturing red LEDs are also provided.

Description

Technical Field

[0001] This invention relates to red LEDs and an improved method for manufacturing red LEDs. Background Technology

[0002] III-V semiconductor materials, especially III-nitride semiconductor materials, are of particular interest in semiconductor device design.

[0003] "III-V" semiconductors include binary, ternary, and quaternary alloys of group III elements (such as Ga, Al, and In) and group V elements (such as N, P, As, and Sb), and have attracted much attention for many applications, including optoelectronics.

[0004] Of particular interest is the category of semiconductor materials known as "Group III nitrides," which includes gallium nitride (GaN), indium nitride (InN), and aluminum nitride (AlN), as well as their ternary and quaternary alloys. (Al,In)GaN is a term encompassing AlGaN, InGaN, and GaN. Group III nitride materials have not only achieved commercial success in solid-state lighting and power electronics but have also demonstrated particular advantages for quantum light sources and light-matter interactions.

[0005] For optoelectronic semiconductor devices, doping In into GaN semiconductor materials is of interest because changing the In content alters the electronic bandgap of the material, and thus the wavelength of light emitted by the semiconductor. However, changing the In content also affects the in-plane lattice constant of the semiconductor. For example, the in-plane lattice constant of InN is approximately 11% higher than that of GaN, where the lattice size of the intermediate composition varies with the In content. This raises a problem in device design where it is desirable to deposit an active semiconductor layer on top of a substrate layer with different lattice sizes. This is because lattice mismatch at the layer boundaries introduces strain into the lattice, leading to the formation of defects in the material that act as non-radiative recombination centers. This significantly degrades device performance.

[0006] The demand for red LEDs is enormous, but manufacturers have historically struggled to produce LEDs that emit light at red wavelengths.

[0007] For example, a major challenge in growing long-wavelength LEDs (such as red LEDs) on a GaN-based platform is the need to use high indium (In) content to reduce the bandgap in the active region to a level suitable for long-wavelength emission. The required InGaN active region has a larger lattice parameter than the underlying GaN, and the resulting strain leads to the formation of defects in the material that act as non-radiative recombination centers, thereby degrading device performance.

[0008] Therefore, due to the large lattice mismatch between InN and GaN, it is difficult to obtain high-quality InGaN (with a high indium content of >20%). The mismatch strain also leads to a reduction in indium content through a composition pull effect.

[0009] Shorter wavelength LEDs (such as green and yellow LEDs) are easier to manufacture because they can be made using InGaN emitting regions that contain a lower proportion of indium than are required for red light emission.

[0010] Due to these issues, existing attempts to fabricate red-wavelength LEDs on the GaN platform have not yet been successful. Summary of the Invention

[0011] This application relates to an improved method for manufacturing semiconductor devices, particularly red LEDs, and red LEDs manufactured using this method.

[0012] The invention is defined in the independent claim, which will now be referred to. Preferred or advantageous features of the invention are defined in the appended dependent claims.

[0013] The light-emitting diodes or LEDs described in this application are preferably formed of group III-V semiconductor materials, and particularly preferably of group III nitride semiconductor materials.

[0014] "III-V" semiconductors include binary, ternary, and quaternary alloys of group III elements (such as Ga, Al, and In) and group V elements (such as N, P, As, and Sb), and have attracted much attention for many applications, including optoelectronics.

[0015] Of particular interest is the category of semiconductor materials known as "Group III nitrides," which includes gallium nitride (GaN), indium nitride (InN), and aluminum nitride (AlN), as well as their ternary and quaternary alloys (Al,In)GaN. Different crystal orientations can be used in this invention, such as polar c-planes, nonpolar, and semipolar orientations. There are two main nonpolar orientations: the a-plane (11-20) and the m-plane (1-100). For semipolar orientations, there are (11-22), {2021}, where {2021} is a family of crystal planes. Group III nitride materials have not only achieved commercial success in solid-state lighting and power electronics but also exhibit particular advantages for quantum light sources and light-matter interactions.

[0016] While various group III nitride materials are of commercial interest, gallium nitride (GaN) is widely considered one of the most important new semiconductor materials and has received particular attention for many applications.

[0017] It is known that introducing pores into bulk group III nitrides (such as GaN) can profoundly affect their material properties (optical, mechanical, electrical, and thermal, etc.). Therefore, the possibility of tuning a wide range of material properties by changing the porosity of GaN and group III nitride semiconductors has made porous GaN of great interest for optoelectronic applications.

[0018] This invention will be described with reference to GaN and InGaN, but can be advantageously applied to alternative combinations of group III nitride materials.

[0019] In the following description, the substrate used for overgrowth is a semiconductor structure on which additional semiconductor layers will be grown to produce a semiconductor device. An exemplary substrate used for overgrowth in this invention may be a GaN semiconductor structure comprising multiple doped and undoped GaN layers.

[0020] The layers of a semiconductor structure can be porosilicated by electrochemical etching as described in international patent applications PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728).

[0021] The inventors have discovered that using the present invention can advantageously provide red LEDs.

[0022] semiconductor structure

[0023] According to a first aspect of the present invention, a red light-emitting diode (LED) is provided, comprising:

[0024] n-doped portion;

[0025] p-doped portion; and

[0026] The luminescent region is located between the n-doped and p-doped regions, and includes:

[0027] A light-emitting indium gallium nitride layer that emits light with a peak wavelength between 600 nm and 750 nm when subjected to an electrical bias voltage.

[0028] A group III nitride layer is situated on the light-emitting indium gallium nitride layer; and a group III nitride barrier layer is situated on the group III nitride layer.

[0029] The light-emitting diode includes a porous region of group III nitride material.

[0030] The inventors have recognized that electrochemical porosification of group III nitride materials advantageously leads to a reduction in strain in the group III nitride lattice and in the bending or curvature of the entire wafer. Without being bound by theory, it is believed that the process of porosifying the porous regions of the group III nitride material also etches away structural defects, such as penetrating dislocations formed during the growth of the first group III nitride material layer on top of it.

[0031] Removing dislocations from the porous semiconductor material during porosification significantly reduces strain in the porous regions, especially when the lattice size of the porous region mismatches with that of the underlying material. Therefore, during the epitaxial growth of the semiconductor structure, when a group III nitride layer is deposited on the porous region, the porous material is more compliant to match the lattice of the overlying non-porous layer. This results in the layer above the porous region experiencing significantly lower strain than in the absence of a porous region.

[0032] When group III nitride materials undergo lower strain, fewer structural defects exist in the non-porous layer to act as nonradiative recombination centers that impair device performance.

[0033] Composition Pull Effect: Kawaguchi et al. reported the so-called composition pull effect in InGaN, where the indium fraction is small in the initial stages of growth but increases with increasing growth thickness. This observation is, to some extent, independent of the underlying GaN or AlGaN layer. The authors suggest that this effect is caused by strain due to lattice mismatch at the interface. They found that a large lattice mismatch between InGaN and the bottom epitaxial layer is accompanied by a large variation in the In content.

[0034] In Inatomi et al.'s theoretical study on the compositional pull effect in the metal-organic vapor phase epitaxial growth of InGaN (Japanese Journal of Applied Physics, Vol. 56, No. 7) found that compressive strain inhibited the incorporation of InN. On the other hand, tensile strain promoted the incorporation of InN compared with relaxed bulk growth.

[0035] The inventors have discovered that using porous regions in semiconductor structures leads to reduced strain relaxation in the semiconductor structure layers, which may result in improvements regarding composition pull effects. Porosity reduces strain in the group III nitride layer and makes the semiconductor structure less strained, thus allowing for conditions with higher In incorporation. Therefore, this invention can facilitate the incorporation of more indium into LED layers grown on top of porous regions, which is highly desirable for longer wavelength emission.

[0036] The n-doped region, the light-emitting region, and the p-doped region are preferably disposed above the porous region. In other words, the porous region can be located below the n-doped region, the light-emitting region, and the p-doped region in the LED structure.

[0037] By providing porous regions of group III nitride material within the LED, the n-doped, emitting, and p-doped regions can thus grow over the porous regions with lower strain than would be possible without them. This reduced strain level in the layered semiconductor structure allows for the incorporation of more indium into one or more emitting layers of the LED, enabling the growth of high-quality InGaN emitting layers with high indium content. This allows sufficient indium to be incorporated into the emitting indium gallium nitride layer, resulting in LEDs emitting light with peak wavelengths between 600 nm and 750 nm when an electrical bias is applied across the entire LED.

[0038] As described in the background section above, despite the huge demand for red LEDs emitting light between 600 nm and 750 nm, the technical difficulty of incorporating sufficient indium into one or more emitting layers means that red InGaN LEDs are difficult to realize. However, shorter wavelength LEDs (e.g., green (500 nm-550 nm) and yellow (550 nm-600 nm) LEDs) are easier to manufacture because they can be fabricated using InGaN emitting regions containing a lower proportion of indium than required for red light emission.

[0039] The inventors have discovered that growing an LED structure over a porous region of a group III nitride material results in a significant shift in the emission wavelength toward longer wavelengths compared to the same LED structure grown on a non-porous substrate.

[0040] The inventors demonstrated this by growing a conventional green / yellow (emitting between 500nm and 550nm or 550nm and 600nm) InGaN LED structure on a porous GaN wafer and proving that the LED emitted green / yellow light as expected. Then, the same "green / yellow" InGaN LED structure was grown on a template containing porous regions, and when an electrical bias was applied across the entire LED, the LED emitted light in the red range between 600nm and 750nm.

[0041] Therefore, this invention allows conventional, easily manufactured LED structures to be shifted to emit at longer wavelengths, so structures previously used as yellow or green LEDs can be made into red LEDs by incorporating porous regions into the structure. This advantageously allows the manufacture of red LEDs without many of the technical problems encountered in prior art designs.

[0042] The LED emitting region can be an LED emitting region for emitting at a peak wavelength of 500nm to 600nm, or 500nm to 550nm, or 550nm to 600nm, or 510nm to 570nm, or 530nm to 560nm, or 540nm to 600nm. The LED emitting region can also be an LED emitting region emitting at a peak wavelength of 500nm to 600nm, or 510nm to 570nm, or 530nm to 560nm, or 540nm to 600nm when not overgrown on a porous group III nitride layer. However, growing the LED emitting region over a porous region of the group III nitride material may shift the emission wavelength of the emitting region to between 600nm and 750nm.

[0043] The light-emitting region can emit light with a peak wavelength between 600nm and 750nm under an electrical bias voltage, or emit light with a peak wavelength between 600nm and 700nm, or between 615nm and 675nm, or between 600nm and 660nm under an electrical bias voltage.

[0044] In one aspect of the present invention, a red light-emitting diode (LED) may be provided, comprising:

[0045] n-doped portion;

[0046] p-doped portion; and

[0047] The light-emitting region between the n-doped and p-doped portions includes a light-emitting indium gallium nitride layer for emitting at a peak wavelength of 500 nm to 550 nm or 550 nm to 600 nm.

[0048] The light-emitting diode is positioned on a porous region of a group III nitride material, and the porous region of the group III nitride material shifts the emission wavelength of the light-emitting region to a peak wavelength between 600 nm and 750 nm under an electrical bias voltage across it.

[0049] Red LEDs can include yellow or green InGaN LED structures grown over porous regions of group III nitride materials.

[0050] A light-emitting diode may include at least one feature selected from the following:

[0051] (a) The luminescent region comprises one, two, three, four, five, six, seven, or eight quantum wells (or at least one quantum well); or

[0052] (b) Group III nitride layers include aluminum gallium nitride layers having a composition of Al y Ga (I-y)N, where y is in the range of 0.1 to 1.0; or

[0053] (c) A UV or blue emitting InGaN / GaN or InGaN / InGaN superlattice or InGaN layer is located between the n-doped region and the emitting region.

[0054] The porous region may have a thickness of at least 1 nm, preferably at least 10 nm, and particularly preferably at least 50 nm. For example, the porous region may have a thickness between 1 nm and 10,000 nm. The porous region may have a porosity between 1% and 99%.

[0055] The porous region can be located below or beneath the n-type, light-emitting, and p-type regions of the LED. Preferably, the n-type, light-emitting, and p-type regions (LED structure) are located above or above the porous region, as defined by the growth sequence of the layers in the LED. The LED structure is preferably overgrown on the porous region, allowing the LED structure to benefit from strain relaxation in the porous group III nitride layer.

[0056] The red LED may include a linker layer of group III nitride material positioned between the n-doped portion and the porous region. Preferably, the linker layer has a thickness of at least 100 nm, but smaller or larger thicknesses are also possible.

[0057] Red LEDs preferably include a non-porous intermediate layer of a group III nitride material porous region between the porous region and the light-emitting region. Since the porous region is preferably formed by electrochemical porosification of a non-porous layer of group III nitride material using methods according to PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728), the non-porous layer of group III nitride material typically forms a non-porous intermediate layer retained on top of the porous region. This non-porous intermediate layer can advantageously provide a smooth surface for overgrowth of additional layers during manufacturing.

[0058] Preferably, the LED includes a non-porous intermediate layer of group III nitride material positioned between the porous region and the connecting layer. This can preferably be a non-porous layer through which the porous region is electrochemically etched.

[0059] The porous region can be a porous layer, such that the light-emitting diode comprises a porous layer of group III nitride material. Preferably, the porous region can be a continuously porous layer, for example, formed from a continuous layer of porous group III nitride material.

[0060] The porous region may include multiple porous layers and optionally multiple non-porous layers. In a preferred embodiment of the invention, the porous region is a stack of alternating porous and non-porous layers, wherein the top surface of the stack defines the top of the porous region, and the bottom surface of the stack defines the bottom of the porous region. A luminescent region may be formed over the porous region of the stack of porous layers comprising a group III nitride material.

[0061] In some embodiments, the luminescent region is positioned over a stack of multiple porous layers of a group III nitride material. Therefore, the porous region can be a stack of layers of group III nitride material in which at least some layers are porous, rather than a single porous layer of group III nitride material. The stack of porous layers can preferably be a stack of alternating porous and non-porous layers.

[0062] Alternatively, the porous region can be a group III nitride material layer containing one or more porous regions (e.g., one or more porous regions in other non-porous layers of a group III nitride material).

[0063] In a preferred embodiment, the porous region or porous layer may have a horizontal dimension equal to the horizontal dimension (width or length) of the substrate on which the porous layer or region is grown. For example, conventional substrate wafer sizes can have various dimensions, such as 1 cm. 2 The diameter can be 2 inches, 4 inches, 6 inches, 8 inches, 12 inches, or 16 inches. However, smaller porous regions that do not span the entire substrate can be formed by patterning one or more layers and / or depositing regions with different carrier concentrations in the same layer. Therefore, the horizontal dimension of the porous layer or region can vary from about 1 / 10 of a pixel (e.g., 0.1 μm) to the horizontal dimension of the substrate itself. The n-doped portion preferably comprises an n-doped group III nitride layer.

[0064] Preferably, the n-doped portion and / or n-doped layer includes n-GaN, or n-InGaN, or an alternating stack of n-GaN / n-InGaN, or an alternating stack of n-InGaN / n-InGaN containing different concentrations of indium.

[0065] The n-doped portion may include a single-crystal n-doped group III nitride portion, preferably wherein the n-doped portion includes a single-crystal n-doped group III nitride layer having a planar top surface.

[0066] The porous region and each layer between the porous region and the single-crystal n-doped group III nitride layer can be planar layers, each planar layer having its own top surface and its own bottom surface, the bottom surface being parallel to the planar top surface of the single-crystal n-doped group III nitride layer.

[0067] The light-emitting indium gallium nitride layer preferably includes one or more InGaN quantum wells, more preferably 1 to 7 quantum wells.

[0068] The luminescent indium gallium nitride layer can be a nanostructured layer of InGaN, which includes quantum structures such as quantum dots, segmented quantum wells, or discontinuous quantum wells.

[0069] The light-emitting indium gallium nitride layer and / or quantum well preferably have the component In x Ga 1-x N, wherein 0.15≤x≤0.40, preferably 0.20≤x≤0.40 or 0.26≤x≤0.40, and particularly preferably 0.30≤x≤0.40.

[0070] The red LED preferably includes a group III nitride layer on the light-emitting indium gallium nitride layer; and a group III nitride barrier layer on the group III nitride layer.

[0071] The group III nitride layer on the luminescent InGaN layer can be called a “capping layer”. This capping layer is used to 1) increase the quantum-confined Stark effect for band bending, thus increasing the redshift and achieving red emission, and 2) protect the high In% in InGaN to ensure that enough In% is incorporated to achieve long wavelengths and to provide a larger potential barrier.

[0072] The LED preferably includes a capping layer of group III nitride material between the quantum well and the p-doped region. The capping layer can be GaN, InGaN, AlGaN, or AlN.

[0073] The LED preferably includes a barrier layer of group III nitride material between the quantum well and the p-doped region. The barrier layer can be GaN, InGaN, AlGaN, or AlN.

[0074] The p-doped region may include a p-doped group III nitride layer and a p-doped aluminum gallium nitride layer positioned between the p-doped group III nitride layer and the light-emitting region. The p-doped aluminum nitride layer is preferably an electron blocking layer (EBL) positioned between the capping layer and the p-type layer, wherein the electron blocking layer contains 5 at% to 25 at% aluminum, and preferably, the electron blocking layer has a thickness between 10 nm and 50 nm.

[0075] The porous region is preferably not part of the distributed Bragg reflector (DBR).

[0076] Red micro LED

[0077] In a second aspect of the invention, a red micro-LED may be provided, comprising the red LED according to the first aspect of the invention, wherein the light-emitting region has a horizontal dimension (width and length) greater than 100 μm and less than 200 μm.

[0078] Red micro LED

[0079] In a third aspect of the invention, a red micro-LED can be provided, comprising the red LED according to the first aspect of the invention, wherein the light-emitting region has a horizontal dimension of less than 100 μm. The micro-LED may preferably have a horizontal dimension of less than 80 μm, or 70 μm, or 60 μm, or 50 μm or 30 μm, or 25 μm, or 20 μm, or 15 μm or 10 μm, or 5 μm or 3 μm or 1 μm.

[0080] Micro LED Array

[0081] In a fourth aspect of the invention, a micro-LED array may be provided, comprising a plurality of red micro-LEDs according to a third aspect of the invention.

[0082] Manufacturing method

[0083] In a fifth aspect of the invention, a method for manufacturing a red LED may be provided, comprising the steps of: overgrowing a porous region of a group III nitride material:

[0084] n-doped portion;

[0085] p-doped portion; and

[0086] The light-emitting region is located between the n-doped and p-doped portions. This light-emitting region includes a light-emitting indium gallium nitride layer that emits light with a peak wavelength between 600 nm and 750 nm under an electrical bias.

[0087] The n-doped region, p-doped region, and luminescent region can include a yellow or green InGaN LED structure, as further described below.

[0088] Alternatively, the method may include the step of growing a red LED structure over a porous region of a group III nitride material at a growth temperature higher than previously possible. Since the presence of a porous region in the group III nitride material implies semiconductor lattice strain relaxation, a higher growth temperature can be used to incorporate the desired indium when growing the InGaN emitting layer. The red LED structure overgrown on the porous region can be a known red LED structure; however, in this case, the use of a porous template advantageously allows the red LED emitting layer (e.g., an InGaN quantum well (QW)) to be grown at a higher growth temperature than possible when overgrown on a non-porous substrate.

[0089] In a sixth aspect of the invention, a method for manufacturing a red LED may be provided, comprising the steps of: overgrowing a porous region of a group III nitride material:

[0090] n-doped portion;

[0091] p-doped portion; and

[0092] The LED emitting region between the n-doped and p-doped portions includes a light-emitting indium gallium nitride layer for emitting light at a peak wavelength of 500 nm to 550 nm or 550 nm to 600 nm.

[0093] Among them, overgrowth on the porous region of the group III nitride material under an electrical bias voltage shifts the emission wavelength of the light-emitting region to a peak wavelength between 600 nm and 750 nm.

[0094] The following discussion applies to both the fifth and sixth aspects of the present invention.

[0095] The luminescent region may include a light-emitting indium gallium nitride (IGaN) layer for emitting at peak wavelengths of 500 nm to 550 nm, or 500 nm to 580 nm, or 510 nm to 570 nm, or 530 nm to 560 nm, or 550 nm to 600 nm. The light-emitting IGaN layer may be one or more layers known to emit at these wavelengths when grown in conventional LEDs (e.g., on a porous GaN substrate). However, the inventors have discovered that growing conventional yellow or green LED structures on porous group III nitride layers results in LEDs emitting at peak wavelengths between 600 nm and 750 nm under electrical bias.

[0096] The method may include the following steps: growing a yellow or green LED structure over a porous region of a group III nitride material.

[0097] Overgrowth in the porous regions of group III nitride materials can result in a light-emitting region that emits at a peak wavelength between 615 nm and 665 nm under electrical bias.

[0098] The following features also apply to the methods of both the fifth and sixth aspects of the present invention.

[0099] This method may include a first step of electrochemically porousening a group III nitride material layer to form porous regions of the group III nitride material. This can be achieved using wafer-scale porousening processes described in international patent applications PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728).

[0100] The method may preferably include the following steps: forming porous regions of a group III nitride material by electrochemical porosification using a non-porous layer of the group III nitride material, such that the non-porous layer of the group III nitride material forms a non-porous intermediate layer. The non-porous intermediate layer can advantageously provide a smooth surface for overgrowth of other layers (e.g., one or more connecting layers of group III nitride material).

[0101] Porous regions can be formed by porousening one or more layers or regions of a group III nitride material on a substrate. The substrate can be silicon, sapphire, SiC, or β-Ga₂O₃. The crystal orientation of the substrate can be polar, semi-polar, or non-polar. The substrate thickness typically varies between 100 μm and 1500 μm.

[0102] The porous region can be a porous layer, such that the method includes the steps of: overgrowing an n-doped portion, a p-doped portion, and an LED light-emitting region over a porous layer of group III nitride material. Preferably, the porous region can be a continuous porous layer, for example, formed from a continuous layer of porous group III nitride material.

[0103] The porous region may include multiple porous layers and optionally multiple non-porous layers. In a preferred embodiment of the invention, the porous region is a stack of alternating porous and non-porous layers, wherein the top surface of the stack defines the top of the porous region and the bottom surface of the stack defines the bottom of the porous region.

[0104] Alternatively, the porous region can be a group III nitride material layer containing one or more porous regions (e.g., one or more porous regions in other non-porous layers of a group III nitride material).

[0105] In a preferred embodiment, the porous region or porous layer may have a horizontal dimension equal to the horizontal dimension (width or length) of the substrate on which the porous layer or region is grown. For example, conventional substrate wafer sizes can have various dimensions, such as 1 cm. 2 The diameter can be 2 inches, 4 inches, 6 inches, 8 inches, 12 inches, or 16 inches. However, by patterning one or more layers and / or depositing regions with different carrier concentrations in the same layer, smaller porous regions that do not span the entire substrate can be formed. Therefore, the horizontal size of the porous layer or region can vary from about 1 / 10 of a pixel (e.g., 0.1 μm) to the horizontal size of the substrate itself.

[0106] Prior to the porousing step, doped regions of an n-doped group III nitride semiconductor material can be deposited on the substrate, preferably comprising layers or stacks of layers. One or more group III nitride layers may contain one or a combination of these elements: Al, Ga, and In (ternary or quaternary layers). The thickness of the group III nitride stack is preferably between 10 nm and 4000 nm. The doping concentration of the group III nitride regions can be 1 × 10⁻⁶. 17 cm -3 Up to 5×10 20 cm -3 between.

[0107] Preferably, an undoped group III nitride intermediate layer is deposited on top of the doped material before the doped material is porousened. The intermediate layer preferably has a thickness of 1 nm to 3000 nm, more preferably 5 nm to 2000 nm. Since the intermediate layer is undoped, it remains non-porous after the porousening step, which advantageously provides a good surface for epitaxial overgrowth of additional semiconductor layers.

[0108] In a preferred embodiment, the doped region is composed of alternating stacks of doped and undoped layers. In a preferred embodiment, the stack comprises 5 to 50 pairs of layers. The thickness of each highly doped layer can vary between 10 nm and 200 nm, and the thickness of the low-doped or undoped layer can range from 5 nm to 180 nm.

[0109] As is known in the art, electrochemical porosimetry removes material from the n-type doped regions of group III nitride materials and creates pores in semiconductor materials.

[0110] In a preferred embodiment, the red LED structure is formed over a stack of multiple porous layers of group III nitride material. Therefore, the porous region can be a stack of porous group III nitride material layers, where at least some layers are porous, rather than a single porous layer of group III nitride material. The stack of porous layers can preferably be a stack of alternating porous and non-porous layers.

[0111] The method may preferably include the following steps: depositing one or more group III nitride material interconnect layers on the surface of the intermediate layer of group III nitride material before overgrowing the n-doped region, the LED light-emitting region and the p-doped region on the interconnect layer.

[0112] Alternatively, in the absence of a non-porous intermediate layer above the porous region, the method may include the step of depositing a bonding layer of group III nitride material onto the surface of the porous region of the group III nitride material.

[0113] The method may include the following additional steps: overgrowing an n-doped region, an LED light-emitting region, and a p-doped region on the interconnect layer.

[0114] The red LED produced by this manufacturing method is preferably a red LED according to one of the first to fourth aspects of the present invention.

[0115] The features described herein with respect to one aspect of the invention are equally applicable to other aspects of the invention. Attached Figure Description

[0116] Embodiments of the invention will now be described with reference to the accompanying drawings, in which:

[0117] Figure 1 An example of a porous template suitable for red LEDs according to the present invention is shown;

[0118] Figures 2 to 13 The steps for manufacturing a red LED according to a preferred embodiment of the present invention are illustrated;

[0119] Figure 14 This is a graph of the normalized electroluminescence (EL) intensity of an InGaN LED above a porous region relative to wavelength, according to a preferred embodiment of the present invention.

[0120] Figure 15 This is a graph showing the normalized electroluminescence (EL) intensity of an InGaN LED on a non-porous substrate relative to wavelength under different current injection conditions.

[0121] Figure 16 It is a preferred embodiment of the present invention that grows above the porous region and Figure 15 Normalized electroluminescence (EL) intensity versus wavelength for the same InGaN LED under different current injection conditions;

[0122] Figure 17 These are IV curves measured for InGaN microLEDs of different pixel sizes on a hole-free substrate, with the inset showing yellow emission; and

[0123] Figure 18 These are IV curves measured for InGaN microLEDs of different pixel sizes on a porous substrate, with the inset showing red emission. Detailed Implementation

[0124] Figure 1 An example of a porous template suitable for red LEDs according to the present invention is shown.

[0125] The porous template includes porous regions of group III nitride material on a substrate, wherein a non-porous layer of group III nitride material is disposed on the top surface of the porous regions. Optionally, an additional layer of group III nitride material may be present between the substrate and the porous regions.

[0126] As described in more detail below, porous regions can be provided by epitaxially growing an n-doped region of a group III nitride material, then growing an undoped layer of the group III nitride material, and porousifying the n-doped region using the porousening process described in international patent applications PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728).

[0127] As mentioned above, this porosity leads to strain relaxation in the lattice, which means that the overgrowth of subsequent additional semiconductor layers benefits from the reduced compressive strain in their lattices.

[0128] The porous region may comprise one or more layers of one or more group III nitride materials and may have a certain thickness, while still providing strain relaxation benefits that cause a wavelength shift in the InGaN emitting layer overgrown above the porous region. In a preferred embodiment, the porous region may, for example, comprise GaN and / or InGaN.

[0129] Various LED structures can be used Figure 1 Overgrowth occurs above the template shown in the example.

[0130] In particular, LED structures containing an InGaN light-emitting layer can be overgrown on a porous template using standard LED manufacturing steps. These LED structures are known in the art to be yellow or green LEDs. However, when grown on a porous template, LED structures that typically emit yellow or green wavelengths will emit at red wavelengths of 600 nm to 750 nm.

[0131] Thus, using the porous regions of group III nitride materials as overgrowth templates or pseudo-substrates for yellow or green InGaN LEDs allows for the direct fabrication of red LEDs.

[0132] In a preferred embodiment, the red LED according to the present invention comprises the following layers and can be manufactured using the step-by-step process described below.

[0133] The following description of the LED structure refers to the top-emitting architecture described from bottom to top, but the invention is equally applicable to the bottom-emitting architecture.

[0134] Figure 2 - Substrate and Group III nitride layer for porousification

[0135] A compatible substrate is used as the starting surface for epitaxial growth. The substrate can be silicon, sapphire, SiC, β-Ga₂O₃, GaN, glass, or metal. The crystal orientation of the substrate can be polar, semi-polar, or non-polar. The substrate size can be as small as 1 cm. 2The diameters can vary from 2 inches, 4 inches, 6 inches, 8 inches, 12 inches, 16 inches and above, and the substrate can have a thickness greater than 1 μm (e.g., between 1 μm and 15000 μm).

[0136] A layer of group III nitride material or a stack of group III nitride material layers is epitaxially grown on a substrate. The group III nitride layer may contain one or a combination of these elements: Al, Ga, In (binary, ternary or quaternary layers).

[0137] The thickness T of the group III nitride stack is preferably at least 10 nm, or at least 50 nm, or at least 100 nm, for example, between 10 nm and 10,000 nm.

[0138] Group III nitride layers include n-type doping concentrations of 1 × 10⁻⁶. 17 cm -3 Up to 5×10 20 cm -3 The doped regions between the doped regions. The group III nitride layer may also include an undoped “cover” layer of group III nitride material above the doped regions.

[0139] The doped region can terminate at the exposed upper surface of the group III nitride layer, in which case the surface of the layer will be porous during electrochemical etching.

[0140] Alternatively, the doped regions of a group III nitride material can be covered by an undoped "capping" layer of group III nitride material, making the doped regions subsurfaces in the semiconductor structure. The subsurface initiation depth (d) of the doped regions can, for example, be between 1 nm and 2000 nm.

[0141] Figure 3 Porosification of porous regions

[0142] After deposition on the substrate, the group III nitride layer (or stack of layers) is porousened using a wafer-scale porousening process as described in international patent applications PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728). During this process, the doped regions of the group III nitride material become porous, while any undoped regions of the group III nitride material remain porous.

[0143] Following the porosimetry step, the structure thus includes porous regions that remain where the n-doped group III nitride material was previously present, and the structure optionally includes a non-porous intermediate layer covering the porous regions.

[0144] The porosity of the porous region is controlled by the electrochemical etching process and can be between 1% and 99%, preferably between 20% and 90% or between 30% and 80%, but smaller or larger porosities can also be used.

[0145] The thickness of the porous region after porousification is preferably greater than 1 nm, more preferably greater than 10 nm, and particularly preferably at least 40 nm, 50 nm, or 100 nm. However, the material thickness required to obtain the strain relaxation benefits provided by the porous region can vary depending on the type of Group III nitride material from which the porous region is formed.

[0146] The porous regions produced by the porousification process can be bulk layers of group III nitride materials with uniform composition and uniform porosity throughout the layers. Alternatively, the porous regions can comprise multiple layers of porous material with different compositions and / or porosities, thereby forming a porous stack of group III nitride materials. For example, the porous regions can be continuous layers of porous GaN, or continuous layers of porous InGaN, or stacks comprising one or more porous GaN layers and / or one or more porous InGaN layers. The inventors have discovered that the strain relaxation benefits for overgrown porous regions can be obtained over a wide range of porous regions with different thicknesses, compositions, and layered stacks.

[0147] In the embodiment illustrated in the figure, the porous region is a single porous layer.

[0148] When an undoped group III nitride capping layer is present above the doped region, the undoped region remains non-porous after the surface of the underlying doped region is porousened. The thickness D of this non-porous capping layer is preferably at least 2 nm, or at least 5 nm, or at least 10 nm, preferably from 5 nm to 3000 nm. Providing an undoped capping layer above the doped region advantageously results in a non-porous layer of group III nitride material covering the porous region after porousening. This non-porous capping layer can advantageously allow for better overgrowth of additional material over the porous region.

[0149] Since the pore-forming methods of PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728) can be performed on the entire semiconductor wafer, no processing / patterning / treatment is required to prepare a template for pore-forming.

[0150] Figure 4 -Connection layer

[0151] After forming the porous layer, the group III nitride LED epitaxial structure can be grown on the porous template / pseudo-substrate provided by the porous layer and the non-porous capping layer.

[0152] The first layer used to grow the LED structure onto the template can be called the connecting layer 1.

[0153] Although the LED epitaxial structure can be grown directly onto the non-porous capping layer, it is preferable to provide a connecting layer 1 above the capping layer before overgrowth of the LED structure. The inventors have discovered that using a group III nitride connecting layer 1 between the porous region and the LED epitaxial structure advantageously ensures a good epitaxial relationship between the LED and the porous template / substrate. The growth of this layer ensures that the subsequent overgrowth on top of the connecting layer is smooth and epitaxial, and of appropriate high quality.

[0154] The connecting layer 1 is formed of a group III nitride material and may contain one or a combination of these elements: Al, Ga, In (binary, ternary or quaternary layer).

[0155] The linker layer can be doped or undoped. The linker layer can optionally be doped with a suitable n-type dopant material, such as Si, Ge, C, or O. The group III nitride layer can have a density of 1 × 10⁻⁶. 17 cm -3 Up to 5×10 20 cm -3 The doping concentration between them.

[0156] The thickness of the connecting layer is preferably at least 100 nm, and can be, for example, between 100 nm and 10,000 nm.

[0157] Figure 5 -N doped region

[0158] After the growth of the connecting layer, the n-doped group III nitride region 2 of the growth body is formed.

[0159] The n-doped region 2 may comprise a group III nitride layer containing indium, or a stack of thin group III nitride layers with or without indium, or a bulk layer or stack of group III nitride layers in which the atomic percentage of indium varies throughout the layer or stack. For example, the n-doped region may be an n-GaN layer or an n-InGaN layer, or alternatively, the n-doped region may be an alternating stack of n-GaN / n-InGaN, or an alternating stack of n-InGaN / n-InGaN with different amounts of indium in the alternating layers.

[0160] Preferably, the n-doped region 2 comprises indium, such that the lattice of the n-doped region has lattice parameters similar to those of the InGaN light-emitting layer in an LED. The percentage of indium atoms in the n-doped region can vary, for example, between 0.1% and 25%.

[0161] In a preferred embodiment, the indium content of the n-doped region is within 20 at%, 15 at%, 10 at%, or 5 at% of the indium content of the InGaN light-emitting layer. This advantageously ensures that the lattice parameters of the n-doped region are sufficiently similar to those of the InGaN light-emitting layer to avoid excessive strain between these layers.

[0162] The total thickness of the n-doped region can be at least 2 nm, or at least 5 nm, or at least 10 nm, or at least 20 nm. For example, the thickness of the n-doped region can vary between 2 nm and 5000 nm, or even thicker. If the n-doped region comprises a stack of layers, the thickness of each individual layer in the stack is preferably between 1 nm and 40 nm.

[0163] The n-doped region preferably has a density of 1×10⁻⁶. 17 cm -3 Up to 5×10 20 cm -3 Between, preferably in 1×10 18 cm -3 Up to 5×10 20 cm -3 Between, especially preferred is greater than 1×10 18 cm -3 The n-type doping concentration.

[0164] Figure 6 - Illuminated area

[0165] After growth in the n-doped region 2, a bottom layer, a front layer, or a front well can be grown. Figure 6 (Not marked in the text) to release strain in one or more light-emitting layers. The bottom layer can be a single layer or stack / multilayer of GaN, InGaN, or GaN / InGaN, or InGaN / InGaN. Alternatively, the bottom layer can have a structure similar to an InGaN QW / GaN quantum barrier but with a lower indium ratio. For example, a bottom layer consisting of a bulk InGaN layer with a lower indium ratio than the light-emitting layer can be grown before depositing a light-emitting layer with a relatively high indium ratio. Alternatively, the bottom layer can take the form of an InGaN “dummy” QW with a lower indium ratio than the light-emitting layer and one or more GaN quantum barriers.

[0166] After growing the n-doped region 2 and an optional underlying layer, a light-emitting region 3 containing an InGaN light-emitting layer is grown.

[0167] The luminescent region 3 may contain at least one InGaN luminescent layer. Each InGaN luminescent layer may be an InGaN quantum well (QW). Preferably, the luminescent region may include 1 to 7 quantum wells. Adjacent quantum wells are separated by a barrier layer of group III nitride material having a different composition from the quantum wells.

[0168] Throughout this document, one or more light-emitting layers may be referred to as “quantum wells”, but they may take various forms. For example, the light-emitting layers may be continuous layers of InGaN, or these layers may be continuous, segmented, or discontinuous layers containing gaps, or nanostructures that allow the quantum well to effectively contain multiple 3D nanostructures that behave as quantum dots.

[0169] Quantum wells and barriers are grown in a temperature range of 600°C to 800°C.

[0170] Each quantum well is composed of an InGaN layer having an atomic indium percentage between 15% and 40%. Preferably, one or more light-emitting indium gallium nitride layers and / or quantum wells have an In composition. x Ga 1-x N, wherein 0.15≤x≤0.40, preferably 0.20≤x≤0.40 or 0.26≤x≤0.40, and particularly preferably 0.30≤x≤0.40.

[0171] The thickness of each quantum well layer can be between 1.5 nm and 8 nm, preferably between 1.5 nm and 6 nm, or between 1.5 nm and 4 nm.

[0172] Quantum wells can be covered with a thin (0.5 nm to 3 nm) group III nitride QW capping layer, which can contain one or a combination of these elements: Al, Ga, In (ternary or quaternary layers).

[0173] The QW capping layer, which is added immediately after QW growth, can be AlN, 0.01%-99.9% of any Al, AlGaN, GaN, or 0.01%-30% of any In, InGaN.

[0174] The group III nitride QW barrier separating the light-emitting layer (quantum well) can contain one or a combination of these elements: Al, Ga, and In (ternary or quaternary layers). The QW barrier can be AlN, AlGaN with any Al content from 0.01% to 99.9%, GaN, and InGaN with any In content from 0.01% to 15%. Preferably, the QW barrier layer contains AlN and / or AlGaN.

[0175] One or more QW capping layers and QW barriers are not indicated by separate reference numerals in the figure because these layers form part of the luminescent region 3.

[0176] The QW capping layer can be grown after each QW but before the barrier layer. For example, if an LED contains 3 QWs, then each of these QWs can be overgrown with a QW capping layer and then with a QW barrier layer, so that the light-emitting region contains 3 such QW capping layers and 3 such QW barrier layers.

[0177] 1. Caps can be grown under the same conditions as QW.

[0178] 2. Higher temperatures can be raised without growth, and the cap can be grown (this is actually an annealing step), and the temperature can be raised in different gas mixtures.

[0179] 3. It can increase its temperature and grow during the warming period.

[0180] For the manufacture of red LEDs, the large amount of indium in one or more light-emitting layers makes the capping layer even more important, as previous attempts to manufacture red LEDs failed due to insufficient indium incorporation. Therefore, the capping layer is crucial for ensuring that enough indium is captured within the light-emitting area.

[0181] Figure 7 - Covering layer

[0182] After growing one or more light-emitting layers, an undoped capping layer 4 is grown. The undoped capping layer 4 can be referred to as the light-emitting region capping layer because it is formed after the growth of the entire light-emitting region, for example, after the growth of a stack of QW, QW capping layer and QW barrier layer.

[0183] The capping layer (light-emitting area capping layer) 4 is a standard layer, which is well known in the growth scheme of group III nitride LEDs.

[0184] The thickness of the capping layer can be between 5nm and 30nm, preferably between 5nm and 25nm or between 5nm and 20nm.

[0185] The purpose of the luminescent region capping layer 4 is to protect the indium in the luminescent region (QW stack) and prevent its desorption / evaporation during subsequent processing. Because InGaN QWs are typically grown at lower temperatures, which is detrimental to GaN / AlGaN, a heating step is usually required before growing another layer over the luminescent region. The capping layer ensures that one or more InGaN luminescent layers are properly covered and protected, providing an opportunity and time window to modify the growth conditions of the p-doped layer to obtain better material quality. The luminescent region capping layer 4 also ensures that no Mg dopant enters the QW region during the growth of the p-type layer.

[0186] Electron blocking layer (EBL)

[0187] After growing the quantum well, capping layer, and barrier layer, an electron blocking group III nitride layer (EBL)5 containing aluminum is grown. The Al content can be, for example, between 5% and 25%, but higher Al contents are possible.

[0188] EBL is doped with suitable p-type doped materials. The preferred p-type doping concentration for EBL is 5 × 10⁻⁶. 18 cm -3 Up to 8×10 20 cm -3 between.

[0189] The thickness of the EBL can be between 10nm and 50nm, preferably 20nm.

[0190] Figure 8 -p doped layer

[0191] A p-doped layer 6 is grown on the electron blocking layer (EBL) 5.

[0192] The p-type region is preferably doped with Mg, and the p-type doping concentration of the p-type layer is preferably 5 × 10⁻⁶. 18 cm -3 Up to 8×10 20 cm -3 between.

[0193] p-doped group III nitride layers can contain In and Ga.

[0194] The thickness of the doped layer is preferably between 20 nm and 200 nm, and particularly preferably between 50 nm and 100 nm. The doping concentration can be varied throughout the p-type layer, and there can be a spike in the doping level in the last 10 nm-30 nm of the layer facing the LED surface to allow for better p-contact.

[0195] To activate the Mg acceptor in the p-doped layer, the structure can be annealed in an MOCVD reactor or an annealing furnace. Annealing temperatures can range from 700°C to 850°C in an N2 or N2 / O2 environment.

[0196] Since both the EBL and the p-doped layer are p-type doped, these layers can be referred to as p-doped regions.

[0197] Figure 9 -Transparent conductive layer

[0198] The stack of active semiconductor layers is covered with a transparent conductive layer 7. The transparent conductive layer may be made of Ni / Au, indium tin oxide, indium zinc oxide, graphene, Pd, Rh, silver, ZnO, or a combination of these materials.

[0199] The thickness of the transparent conductive layer can range from 10 nm to 250 nm.

[0200] Transparent conductive layers are well known in the art, and any suitable material and thickness can be used.

[0201] An annealing step may be required to create p-ohm contacts.

[0202] Figure 10

[0203] Depending on the structure of the LED being manufactured, the semiconductor structure can be processed into LEDs, small LEDs, or micro LED devices.

[0204] Normal LEDs are typically larger than 200 μm (referring to the horizontal dimensions of the LED structure, including width and length). Small LEDs typically have a horizontal dimension of 100 μm to 200 μm, while micro LEDs are typically smaller than 100 μm.

[0205] Figure 10 An example is shown of a semiconductor structure after layers 2-7 of the semiconductor structure have been etched into multiple discrete LED stacks or mesas, each LED stack or mesas having the same structure.

[0206] In the next step, the transparent conductive layer 7 is structured such that it covers only the top surface of the active emitting element. This structuring can be performed using standard semiconductor processing methods, including photoresist coating and photolithography. The transparent conductive layer is etched using wet chemistry or a sputtering etching process using argon. This step is followed by wet or dry etching of the group III nitride structure. Inductively coupled plasma reactive ion etching, reactive ion etching only, or neutral beam etching is used to create mesas in the group III nitride layer. The dry etching process may include one or more of Cl, Ar, BCl3, and SiCl4 gases.

[0207] The purpose of this step is to isolate the individual emitter elements and bring them close to the buried n-doped layer of the pn junction.

[0208] Following the dry etching process, a wet etching process is performed to remove the dry etching damage from the sidewalls of the mesa. The wet chemistry may involve KOH (1-20%), TMAH, or other basic chemicals.

[0209] Figure 11 - passivation

[0210] The next step is to deposit passivation layer 8 or a combination of passivation layers. The initial passivation layer can be Al2O3 (10-100 nm) (deposited by atomic layer deposition), followed by SiO2, SiN or SiON (50 nm-300 nm) by sputtering or plasma-enhanced chemical vapor deposition.

[0211] Al2O3 can be deposited between 50°C and 150°C.

[0212] SiO2, SiN and SiON can be deposited between 250°C and 350°C.

[0213] The sputtering process can be performed at room temperature.

[0214] Figure 12

[0215] The next step is to create openings in the oxide passivation layer 8 to expose p-GaN and n-GaN. This can be done by wet etching, dry etching, or a combination of both.

[0216] For wet etching buffer oxide etching, diluted hydrofluoric acid, phosphoric acid, or a mixture thereof can be used.

[0217] Figure 13

[0218] The final step in device fabrication is to cover the openings in the oxide with a metal layer 9. This covering can be done in a single step or multiple steps. In this example, a single step is used to simplify the details.

[0219] The metals can include Ti, Pt, Pd, Rh, Ni, and Au. The thickness of the entire metal stack can range from 200 nm to 2000 nm.

[0220] Furthermore, after all processing, the substrate can be thinned, and / or the porous regions can be removed, thereby exposing the interconnect layer 1.

[0221] Surface structuring or texturing can be performed on the substrate, in porous regions, or at layer 1 to enhance light output and control the emission angle, as well as other optical engineering and design.

[0222] Finally, the wafer / device can be flipped and bonded to another carrier substrate, which can be silicon / sapphire or any type of passive device. Alternatively, the device can be bonded to a CMOS silicon substrate for an active matrix micro-LED display panel.

[0223] Figures 14 to 18

[0224] Figure 14 An InGaN LED on a porous layer according to a preferred embodiment of the present invention is shown emitting at a peak wavelength of approximately 625 nm.

[0225] Figure 15 and Figure 16 Comparison of InGaN LEDs on porous substrates ( Figure 15 The comparison of these two figures demonstrates the shift towards longer emission wavelengths caused by the porous substrate, as the emission of the LED on the porous template is consistently 21 nm to 45 nm longer than that of the same LED on the non-porous template.

[0226] Figure 17 and Figure 18 Comparison of InGaN microLEDs on porous substrates ( Figure 17 IV characteristics of InGaN microLEDs on templates containing porous layers.

Claims

1. A red light-emitting diode (LED), comprising an LED structure, said LED structure comprising: n-doped portion; p-doped portion; and The light-emitting region located between the n-doped portion and the p-doped portion includes: A light-emitting indium gallium nitride layer that emits light with a peak wavelength of 600 nm to 750 nm under an electrical bias voltage across its two ends; A group III nitride capping layer is located on the light-emitting indium gallium nitride layer, wherein the group III nitride capping layer comprises an Al-containing layer. y Ga (I-y) An aluminum gallium nitride layer of N, wherein y is in the range of 0.1 to 1.0; and The group III nitride barrier layer located on the group III nitride capping layer, The light-emitting diode further includes: Porous regions in group III nitride materials; and A non-porous intermediate layer of group III nitride material is provided between the porous region and the LED structure, wherein the porous region is formed by electrochemical porousing through the non-porous intermediate layer. The light-emitting area is located above the porous area.

2. The red light-emitting diode (LED) according to claim 1, wherein, The light-emitting diode includes at least one feature selected from the following: (a) The luminescent region includes at least one quantum well; or (b) An InGaN / GaN or InGaN / InGaN superlattice or InGaN layer that emits UV or blue light is located between the n-doped portion and the emitting region.

3. The red light-emitting diode (LED) according to claim 1, wherein, The luminescent region emits light with a peak wavelength of 600 nm to 700 nm under an electrical bias voltage.

4. The red light-emitting diode (LED) according to claim 1, wherein, The porous region has a thickness of at least 10 nm.

5. The red light-emitting diode (LED) according to claim 4, wherein, The red light-emitting diode (LED) includes a bonding layer of group III nitride material positioned between the n-doped portion and the porous region.

6. The red light-emitting diode (LED) according to claim 5, wherein, The non-porous intermediate layer of the group III nitride material is located between the porous region and the connecting layer.

7. The red light-emitting diode (LED) according to claim 4, wherein, The n-doped portion includes an n-doped group III nitride layer, or wherein, The n-doped portion includes n-GaN, or n-InGaN, or an alternating stack of n-GaN / n-InGaN, or an alternating stack of n-InGaN / n-InGaN containing different concentrations of indium.

8. The red light-emitting diode (LED) according to claim 7, wherein, The n-doped portion includes a single-crystal n-doped group III nitride portion, or wherein the n-doped portion includes a single-crystal n-doped group III nitride layer having a planar top surface.

9. The red light-emitting diode (LED) according to claim 8, wherein, The porous region and each layer between the porous region and the single-crystal n-doped group III nitride layer are planar layers, each planar layer having a top surface and a bottom surface parallel to the planar top surface of the single-crystal n-doped group III nitride layer.

10. The red light-emitting diode (LED) according to claim 1, wherein, The luminescent indium gallium nitride layer includes one or more InGaN quantum wells.

11. The red light-emitting diode (LED) according to claim 10, wherein, The light-emitting indium gallium nitride layer is a nanostructure layer of InGaN, which includes quantum dots, segmented or discontinuous quantum wells.

12. The red light-emitting diode (LED) according to claim 10 or 11, wherein, The light-emitting indium gallium nitride layer and / or the quantum well have the component In x Ga 1-x N, where 0.15≤x≤0.

40.

13. The red light-emitting diode (LED) according to claim 10, wherein, The red light-emitting diode includes a capping layer of group III nitride material between the quantum well and the p-doped portion.

14. The red light-emitting diode (LED) according to claim 1, wherein, The p-doped portion includes a p-doped group III nitride layer and a p-doped aluminum gallium nitride layer located between the p-doped group III nitride layer and the light-emitting region.

15. The red light-emitting diode (LED) according to claim 14, wherein, The p-doped aluminum gallium nitride layer is an electron blocking layer (EBL) between the capping layer and the p-doped portion, wherein the electron blocking layer contains 5 at% to 25 at% aluminum, or wherein the electron blocking layer has a thickness of 10 nm to 50 nm.

16. The red light-emitting diode (LED) according to claim 1, wherein, The porous region is not part of the distributed Bragg reflector (DBR).

17. A small red LED, comprising the red light-emitting diode according to claim 1, wherein, The luminescent area has a horizontal dimension greater than 100 μm and less than 200 μm.

18. A red micro LED, comprising the red light-emitting diode according to claim 1, wherein, The luminescent area has a horizontal dimension of less than 100 μm.

19. A red micro-LED array comprising a plurality of red micro-LEDs as claimed in claim 18.

20. A method for manufacturing a red light-emitting diode (LED), comprising the steps of: Porous regions of a group III nitride material are formed by electrochemical porousification through the non-porous regions of the material, thereby creating a non-porous intermediate layer within the non-porous regions of the group III nitride material; and Overgrowth was performed over the non-porous intermediate layer and the porous region of the group III nitride material: n-doped portion; p-doped portion; and The light-emitting region is located between the n-doped portion and the p-doped portion, the light-emitting region including a light-emitting indium gallium nitride layer, the light-emitting indium gallium nitride layer emitting light with a peak wavelength of 600 nm to 750 nm under an electrical bias voltage across its two ends; A group III nitride capping layer is located on the light-emitting indium gallium nitride layer, wherein the group III nitride capping layer comprises an Al-containing layer. y Ga (I-y) An aluminum gallium nitride layer of N, wherein y is in the range of 0.1 to 1.0; and A group III nitride barrier layer located on the group III nitride capping layer.

21. The method of claim 20, further comprising the step of: depositing one or more group III nitride material interconnect layers on the surface of the intermediate layer of the group III nitride material before overgrowing the n-doped portion, the luminescent region and the p-doped portion on the interconnect layer.

22. The method according to claim 20 or 21, wherein, The red light-emitting diode (LED) is The red light-emitting diode (LED), red miniature LED, red micro LED, or micro LED array as defined in any one of claims 1 to 16.

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