Treatments for improved thin film encapsulation

Abstract

A method and apparatus for forming an encapsulation layer on an organic light emitting diode (OLED) patterned substrate is described. A sidewall planarization layer fills voids in the scalloped sidewalls of wall features on the OLED patterned substrate. The sidewall planarization layer is cured in the same chamber as the deposition of the sidewall planarization layer. A barrier layer is formed on the sidewall planarization layer. The sidewall planarization layer provides a planarized surface for good adhesion of the barrier layer over the sidewall planarization layer, which minimizes the possibility of defects on the OLED patterned substrate due to moisture from oxygen penetrating the OLED patterned substrate.

Description

Technical Field

[0001] Embodiments of the present invention are generally directed to a method and apparatus for encapsulating organic light emitting diode device structures and wall features formed on an organic light emitting diode substrate. Background Art

[0002] Electronic devices that utilize displays, such as handheld devices, televisions, monitors, and watches, among other display devices, typically utilize organic light emitting diode (OLED) displays because, for example, OLED displays have faster response times, greater viewing angles, higher contrast, lighter weight, lower power, and conformability to flexible substrates compared to liquid crystal displays (LCDs). However, as shown in FIG. 1 , other accessory features associated with the display device, such as camera lenses, speakers, and sensors, are positioned in an area of ​​the electronic device that is separate from the area that includes the OLED display. The need to separate other accessory features from the display area undesirably reduces the size of the active display area. The current trend is to utilize as much as possible the larger and larger displays on the front side of the user-facing surface of the electronic device. Therefore, what is needed is to integrate additional electronic device accessory features into the OLED display to at least increase the size of the active display area. However, conventional processing and support structures for integrating accessory features into the display area of ​​an electronic device typically include, for example, Figure 4A 4B, which renders the formed structure susceptible to moisture and oxygen degradation. Therefore, what is needed is a device structure and method of forming the same that addresses these issues. Summary of the invention

[0003] In one embodiment, a method for encapsulating a structure on an OLED patterned substrate is provided, the method comprising: positioning the OLED patterned substrate in a plasma processing chamber, the OLED patterned substrate having a wall structure, the wall structure having at least one scalloped surface; and depositing a sidewall planarization layer directly on the wall structure to fill at least one of a plurality of gaps along the at least one scalloped surface.

[0004] In another embodiment, a patterned substrate is provided. The substrate has a plurality of OLED devices formed on a surface of the substrate, and at least one wall structure formed on the surface of the substrate, wherein the wall structure has at least one sector-shaped surface. The wall structure further includes a sidewall planarization layer, which is disposed on the wall structure and fills at least one of a plurality of gaps along the at least one sector-shaped surface.

[0005] In yet another embodiment, a plasma processing chamber for forming a packaging structure on an OLED patterned substrate is provided. The plasma processing chamber has: a substrate support, the substrate support is disposed in a processing region of the plasma processing chamber; a showerhead, the showerhead is disposed in the processing region opposite to the substrate support; a gas source, the gas source is coupled to the showerhead; an ampoule, the ampoule is configured to provide a liquid precursor to the chamber; and a controller, the controller is configured to control a process for forming a packaging structure on the patterned substrate. The process for forming the packaging structure on the patterned substrate includes: positioning an OLED patterned substrate in the plasma processing chamber, the OLED patterned substrate having a wall structure, the wall structure having at least one scalloped surface; and depositing a sidewall planarization layer directly on the wall structure, thereby filling at least one of a plurality of gaps along the at least one scalloped surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order that the above-mentioned features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above may be obtained by reference to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the drawings only illustrate typical embodiments of the present disclosure and are therefore not to be considered as limiting the scope thereof, as the present disclosure may admit to other equally effective embodiments.

[0007] 1 is a schematic top view of a conventional handheld display device having electronic features separate from an OLED display.

[0008] Figure 2A is a schematic top view of a handheld device having electronic features integrated into the area of ​​an OLED display.

[0009] Figure 2B It extends through Figure 2A Schematic cross-sectional view formed by cutting planes showing the integrated device attachment features.

[0010] Figure 3A yes Figure 2A A top view of a portion of an OLED patterned substrate used in FIG.

[0011] Figure 3B It extends through Figure 3A A schematic cross-sectional view formed by a cutting plane of a portion of an OLED patterned substrate is shown.

[0012] Figure 4A yes Figure 3B A schematic cross-sectional view of a wall section is shown.

[0013] Figure 4B is from Figure 4A A schematic cross-sectional view of a conventional enclosure wall portion formed by the wall portions shown.

[0014] Figure 5 is a schematic cross-sectional view of a PECVD apparatus chamber that can be used to perform the methods described herein.

[0015] Figure 6 is a flow chart of a method of encapsulating features on an OLED substrate according to one embodiment of the present disclosure.

[0016] FIG. 7A to FIG. 7C Shown in Figure 6 Schematic cross-sectional views of OLED substrate features during different stages of the method.

[0017] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0018] FIG. 1 is a schematic top view of a conventional handheld display device having electronic device accessory features separate from an OLED display. In this example, the handheld display device is a mobile phone. The display device 100 includes a display area 110 and a camera lens 120 on a front surface of the display device 100. The camera lens 120 is positioned in an upper area 115 of the front surface of the display device 100, separate from the display area 110. Separating the upper area 115 having the camera lens 120 from the display area 110 limits the size of the display area 110 (i.e., the active area) of the display device 100.

[0019] Figure 2A 2 is a schematic top view of a display device 200 (e.g., a mobile phone) having electronic device accessory features (e.g., a camera lens 220) integrated into an OLED display area 210 according to embodiments described herein. By integrating device accessory features (such as a camera lens 220) into the display area 210, the display area 210 covers a larger area of ​​the front surface of the display device 200. Thus, the display area 210 can cover the entire front surface (e.g., the surface facing the user) of the display device 200, such as Figure 2A Thus, compared to the display device 100 of FIG. 1 , the display device 200 having a display area 210 integrated with accessory features provides an enhanced user experience by fitting a larger display area 210 on the front surface of the same size device.

[0020] Figure 2B It is along Figure 2ASchematic cross-sectional view formed by cutting plane 2B-2B extending through an integrated device attachment feature (camera lens 220) as shown. Display device 200 includes an OLED patterned substrate 250. OLED patterned substrate 250 includes a substrate 252 having a top surface 255, and a pre-formed OLED device structure 260 is provided on the top surface 255 of substrate 252. In one embodiment, substrate 252 is made of glass or plastic, such as polyethylene terephthalate (PET), polyethylene terephthalate (PEN), or polyimide (PI). OLED patterned substrate 250 includes a pre-formed wall 270. Wall 270 is disposed on the top surface 255 of substrate 252 to provide support for an integrated device feature provided as part of display area 210. In one example, wall 270 is made of photoresist. In another example, wall 270 is made of polyimide. In one embodiment, wall 270 is configured to support and surround camera lens 220, such as Figure 2B In another embodiment, the wall 270 is configured to support a sensor, such as an optical sensor or a thermal sensor. In another embodiment, the wall 270 is configured to support a microphone or a speaker.

[0021] Figure 3A Yes Figure 2A A top view of a portion of an OLED patterned substrate 250 located underneath a protective screen in a display area 210 is shown. Figure 3B It extends through Figure 3A Schematic cross-sectional view formed by cutting plane 3B-3B of a portion of an OLED patterned substrate 250 is shown. The OLED patterned substrate 250 includes a plurality of OLED device structures 260 disposed on a top surface 255 and includes a wall 270 (e.g., a circular wall as shown) configured to surround a camera lens 220. The slot 275 is configured to accommodate, for example, a speaker for the display device 200. In some embodiments, the slot 275 is a slot-shaped hole passing through the substrate 252. In some embodiments not shown, the slot 275 is surrounded by a wall similar to the wall 270 to provide support for the speaker disposed therein. In some embodiments not shown, the wall portions may be positioned at various locations on the substrate 252 to support additional device features, such as microphones, speakers, and sensors. Reference Figure 3B For clarity, the wall 270 is shown as a cross-section of a circular wall showing two portions of the wall 270 .

[0022] Figure 4A yes Figure 3BSchematic cross-sectional view of wall 270 is shown. Wall 270 is shown on substrate 252. As discussed above, substrate 252 can be glass or plastic, such as polyethylene terephthalate (PET) or polyethylene terephthalate (PEN) or polyimide (PI). Wall 270 can be formed using common patterning methods used in semiconductor device manufacturing, such as pattern resist processing using photolithography. Wall 270 may include multiple layers of polymer-based photoresist. Each of these layers can be deposited, cured and rinsed, and the process can be repeated to form wall 270 with a height and width designed to support integrated device accessories (such as camera lens 220 or sensor). For example, in one embodiment, wall 270 may have a height and width of 5 microns by 5 microns, requiring dozens of layers of photoresist. In this embodiment, the sidewalls 271 of the wall 270 are not uniform because the photoresist is deposited in separate layers using a deposition, curing, and rinsing process, thereby leaving the sidewalls 271 with scalloped edges, such as Figure 4A As shown, this provides a sidewall roughness of approximately 80 nm to 90 nm (peak-to-valley).

[0023] Figure 4B is from Figure 4A Schematic cross-sectional view of a conventional encapsulation wall portion formed by the wall portion shown. Encapsulation layer 410 is disposed over wall 270 and also over OLED device patterned substrate 250 and OLED device (not shown) to provide a barrier to the intrusion of moisture or oxygen that limits the life of the OLED device patterned substrate and OLED device. Encapsulation layer 410 is a dielectric layer such as SiN, SiON, SiO 2 、Al 2 O 3 , AlN or other suitable dielectric layers. The encapsulation layer 410 may be deposited by a suitable deposition technique, such as CVD, PVD, spin coating or other techniques. A conventional encapsulation layer may have a thickness of about 0.1 μm to about 1.5 μm, such as about 0.7 μm. In this conventional structure, the deposited encapsulation layer 410 leaves a plurality of gaps 420 along the scalloped sidewalls 271. The gaps 420 provide a risk of increasing the degradation of the OLED patterned substrate 250 by providing shortening paths and defects that allow moisture or oxygen that causes degradation of the OLED patterned substrate 250 and the OLED device structure 260 to pass through the encapsulation layer. Additionally, the seams 422 between the portion of the encapsulation layer 410 on the sidewalls 271 and the portion of the encapsulation layer 410 on the OLED patterned substrate 250 provide gaps, gaps and shortening paths for moisture and oxygen to penetrate the encapsulation layer 410 and limit the life of the OLED patterned substrate 250.

[0024] Figure 55 is a schematic cross-sectional view of a plasma enhanced chemical vapor deposition (PECVD) apparatus that can be used to perform the operations described herein. The apparatus includes a chamber 500 in which one or more films can be deposited onto an OLED patterned substrate 250. The chamber 500 generally includes a wall 502, a bottom 504, and a showerhead 506 that define a processing volume. A substrate support 518 is disposed within the processing volume. Access to the processing volume is provided through a slit valve opening 508 so that the OLED patterned substrate 250 can be transferred into and out of the chamber 500. The substrate support 518 is coupled to an actuator 516 to raise and lower the substrate support 518. A lift pin 522 is movably disposed through the substrate support 518 to move the OLED patterned substrate 250 into and out of the substrate receiving surface of the substrate support 518. The substrate support 518 also includes a heating and / or cooling element 524 to maintain the substrate support 518 at a desired temperature. The substrate support 518 also includes RF return straps 526 to provide an RF return path around the perimeter of the substrate support 518. The chamber 500 is connected to a system controller 501 that is configured to store and / or implement aspects of the subject matter disclosed herein.

[0025] The spray head 506 is connected to the backing plate 512 by a fastening mechanism 550. The spray head 506 is connected to the backing plate 512 by one or more fastening mechanisms 550 to help prevent sagging of the spray head 506 and / or control the straightness / curvature of the spray head 506.

[0026] The gas source 532 is fluidly coupled to the backing plate 512 via a valve 557 to provide gas to the processing area between the showerhead 506 and the OLED patterned substrate 250 through the gas passage in the showerhead 506. An ampoule 551 for supplying a liquid precursor to the chamber 500 is connected to a pump 552, a fluid degasser 553, a vaporizer 555, and a valve 556. A vacuum pump 510 is coupled to the chamber 500 to maintain the processing volume at a desired pressure. An RF source 528 is coupled to the backing plate 512 and / or the showerhead 506 through a matching network 590 to provide RF current to the showerhead 506. The RF current forms an electric field between the showerhead 506 and the substrate support 518, so that a plasma can be generated from the gas between the showerhead 506 and the substrate support 518.

[0027] A remote plasma source 530, such as an inductively coupled remote plasma source, is coupled between the gas source 532 and the backing plate 512. During processing of a substrate, a cleaning gas may be provided to the remote plasma source 530 such that a remote plasma is generated. Radicals from the remote plasma generated by the remote plasma source 530 may be provided to the chamber 500 to clean components of the chamber 500. The cleaning gas may be further excited by the RF source 528 provided to the showerhead 506.

[0028] The showerhead 506 is additionally connected to the backing plate 512 by a showerhead hanger 534. In one embodiment, the showerhead hanger 534 is a flexible metal skirt. The showerhead hanger 534 may have a lip 536 on which the showerhead 506 may rest. The backing plate 512 may rest on an upper surface of the ledge 514 connected to the chamber wall 502 to seal the chamber 500.

[0029] The system controller 501 is configured to control the various components of the chamber 500. The system controller 310 includes a programmable central processing unit (CPU) that is operable with memory (e.g., non-volatile memory) and support circuits. The support circuits are conventionally coupled to the CPU and include caches, clock circuits, input / output subsystems, power supplies, etc. and combinations thereof coupled to the various components of the chamber 500 to facilitate control thereof. The CPU is one of any form of general-purpose computer processor used in an industrial environment, such as a programmable logic controller (PLC), for controlling the various components and sub-processors of the additive manufacturing system 300. The memory coupled to the CPU is non-transitory and is typically one or more of readily available memories, such as random access memory (RAM), read-only memory (ROM), a floppy disk drive, a hard disk, or any other form of digital storage device (local or remote).

[0030] Figure 6 is a flow chart of a method 600 for encapsulating an OLED patterned substrate 250 according to an embodiment described herein. Although the method 600 operates in conjunction with Figure 5 and FIG. 7A to FIG. 7C 600 is described herein, but one skilled in the art will understand that any chamber configured to perform the method operations in any order falls within the scope of the embodiments described herein. Embodiments of method 600 may be implemented with one or more chambers described herein, such as Figure 5 The method 600 may be stored in the controller 501 or accessible by the controller 501 as a computer readable medium containing instructions, which, when executed by a processor of the controller 501, causes the chamber 500 to perform the method 600.

[0031] FIG. 7A to FIG. 7C Shown in Figure 6 Schematic cross-sectional views of wall 270 structures during different stages of packaging method 600 of the present invention. Method 600 begins at process 610 by positioning OLED patterned substrate 250 into a plasma processing chamber, such as processing chamber 500. OLED patterned substrate 250 has OLED device structures (e.g., device 260 (not shown)) on a surface of substrate 252 and preformed wall 270, such as Fig. 7A As shown, and similar to reference Figure 3B discussed.

[0032] At process 620, a sidewall planarization layer is deposited over the OLED patterned substrate 250 including the walls 270, such as Figure 7B As shown. The sidewall planarization layer 710 provides a planarized interface layer that fills one or more voids or gaps on the scalloped sidewall 271 and overcomes the surface roughness of the wall 270, thereby forming a planarized sidewall layer without voids or seams on the sidewall 271 and the OLED patterned substrate 250, thereby minimizing the possibility of defects caused by moisture or oxygen. The sidewall planarization layer 710 may include fluorinated plasma polymerized hexamethyldisiloxane (pp-HMDSO:F) and may be deposited in a PECVD chamber (such as chamber 500) to provide excellent particle coverage and surface planarization effects. The sidewall planarization layer 710 has a total thickness between about 0.1 μm and about 1.0 μm, such as between about 0.1 μm and about 0.3 μm, to overcome the pattern sidewall roughness of about 80 nm to 90 nm (peak-to-valley). The deposition of the pp-HMDSO:F layer is by mixing one or more fluorine-containing gases and HMDSO gas with O 2 or N 2 O gas flows together. The fluorine-containing gas can be nitrogen fluoride (NF 3 ), silicon fluoride (SiF 4 ), fluorine (F 2 ), carbon tetrafluoride (CF 4 ) or any combination thereof. The fluorine-doped plasma polymerized HMDSO layer has excellent particle coverage and surface planarization effect. The resulting sidewall planarization layer 710 has a fluorine content of less than 10 atomic percent.

[0033] During the deposition of pp-HMDSO:F, the ratio of the flow rates of the fluorine-containing gas and the HMDSO gas may be between about 0.25 and about 1.5. The carbon content in the HMDSO may be greater than 10%. When depositing the sidewall planarization layer 710, the HMDSO is initially a liquid precursor provided by the ampoule 551, but provides better coverage and uniformity when it is in a vapor state. Therefore, the HMDSO is converted to a vapor by first flowing through a fluid degasser 553 and then flowing through a vaporizer 555 before being delivered to the chamber 500. In one embodiment, the PECVD of pp-HMDSO:F is performed under the following conditions. SiF 4 has a flow rate of 125 standard cubic centimeters per minute (sccm), while HMDSO has a flow rate of 300 sccm. 4The ratio of HMDSO is between about 0.40 and about 0.45. The plasma is generated at 700W and the chamber pressure is about 1800 mTorr. The PECVD deposition is performed at about 80 degrees Celsius, and the distance between the OLED patterned substrate 250 and the showerhead 506 of the PECVD chamber 500 is between about 500 mils and 1200 mils, such as about 650 mils.

[0034] In one embodiment, a mask (not shown) is aligned over the OLED patterned substrate 250 so that the walls 270 are exposed through the openings in the mask. The mask is positioned so that the OLED device structure 260 is covered by the mask so that any subsequently deposited pp-HMDSO:F material is deposited through the openings in the mask but not on the OLED device covered by the mask. The mask can be made of a metallic material.

[0035] The sidewall planarizing layer 710 comprising pp-HMDSO:F may have properties including stress relief, particle conformality, and flexibility. These properties of the pp-HMDSO:F sidewall planarizing layer 710 allow the sidewall planarizing layer 710 comprising pp-HMDSO:F to planarize surface irregularities to form a smooth surface. However, due to the formation process of the pp-HMDSO:F sidewall planarizing layer, the pp-HMDSO:F sidewall planarizing layer may be physically soft, which poses integration problems when stacked with a barrier layer (i.e., an encapsulation layer). When the barrier layer is stacked on top of the soft pp-HMDSO:F buffer layer, a wrinkled surface is formed. The wrinkled surface may form one or more voids and gaps, thereby forming defects that are susceptible to moisture intrusion. In addition, the soft pp-HMDSO:F layer loses its optical transmittance, making the device unsuitable as a top-emitting OLED device.

[0036] In order to harden the sidewall planarization layer 710 and prevent the formation of a wrinkled surface, a plasma curing of the sidewall planarization layer 710 is performed. At process 630, the sidewall planarization layer 710 is cured in a vacuum environment. In one embodiment, the sidewall planarization layer 710 is cured (i.e., an in-situ curing process) in the same processing chamber as the deposition of the sidewall planarization layer 710. A plasma curing process is performed using a chamber configured to generate water (H 2 The curing is performed by a mixed gas plasma of ammonia (NH 2 O) or a plasma generated from a gas mixture. The mixed gas plasma is configured to generate water for condensation curing, which introduces moisture into the chamber. The mixed gas plasma may include a mixture selected from ammonia (NH 3 ), nitrous oxide (N 2 O), hydrogen (H 2 ) and oxygen (O 2 ) group. For example, the mixed gas plasma may contain NH3 and N 2 O, H 2 and N 2 O, H 2 and O 2 or NH 3 and O 2 In one embodiment, the mixed gas plasma may also contain fluorine, such as nitrogen fluoride (NF 3 ), silicon fluoride (SiF 4 ), fluorine (F 2 ) and / or carbon tetrafluoride (CF 4 ).

[0037] The ratio of the mixed gas in the mixed gas plasma depends on the distance between the OLED patterned substrate 250 and the showerhead 506 of the processing chamber 500. For example, if the distance between the OLED patterned substrate 250 and the showerhead 506 is about 650 mils, the ratio of NH 3 With N 2 O can be used for a curing duration of about 10 seconds to 15 seconds. In another example, if the spacing between the OLED patterned substrate 250 and the showerhead is about 1000 mils, a ratio of 3:1 NH 3 With N 2 O can be used for a curing duration of about 30 seconds. Therefore, the curing duration depends on the ratio of the mixed gases in the mixed gas plasma and the spacing between the OLED patterned substrate 250 and the showerhead 506. Therefore, the curing duration can be increased to compensate for the higher ratio between the mixed gases in the mixed gas plasma and the larger spacing between the OLED patterned substrate 250 and the showerhead 506. With the subsequent deposition of one or more buffer layers thereon, the hardened sidewall planarization layer 710 maintains its flexibility and optical transmittance.

[0038] In process 640, process 620 and process 630 are repeated one or more times to deposit one or more additional sidewall planarization layers 710, thereby curing each deposited layer individually before depositing additional layers. Each additional layer maintains its flexibility and light transmittance as one or more additional layers are subsequently deposited thereon.

[0039] The complete sidewall planarization layer 710 may have a thickness of about 0.1 μm to 1.0 μm. In one embodiment, 1 to 10 additional layers may be deposited on the first solidified sidewall planarization layer 710 to form a complete sidewall planarization layer 710 with a desired thickness. In another embodiment, the complete sidewall planarization layer 710 includes 3 layers, each having a thickness of about 0.1 μm, with a total thickness of 0.3 μm. The complete sidewall planarization layer 710 maintains its flexibility and overcomes the sidewall surface roughness, thereby providing a planarized surface for a barrier layer subsequently deposited thereon.

[0040] At process 650 of method 600, a barrier layer, i.e., an encapsulation layer, is deposited over the sidewall planarization layer 710 on the substrate to serve as a capping layer to protect the OLED device structure and patterned features (such as wall 270) from moisture and oxygen. At process 650, a barrier layer 720 is deposited over the sidewall planarization layer 710 and substrate 252, such as Figure 7C The barrier layer 720 is a dielectric layer such as silicon nitride (SiN), silicon oxynitride (SiON), silicon dioxide (SiO 2 ) or other suitable dielectric layer. Barrier layer 720 may have a thickness between about 0.1 μm and 1.0 μm, such as about 0.7 μm. Barrier layer 720 may be deposited by a suitable deposition technique such as CVD, PECVD, physical vapor deposition (PVD), spin coating, or other suitable technique. Additional barrier layers may be added to further encapsulate and protect the OLED device patterned substrate and features provided thereon.

[0041] Deposition of the sidewall planarization layer, curing of the sidewall planarization layer, and deposition of the barrier layer as described herein may be performed in the vacuum environment of a single deposition chamber, such as PECVD chamber 500. Performing the deposition and curing operations in the vacuum environment of a single deposition chamber allows the sidewall planarization layer 710 and the barrier layer 720 to be formed without breaking the vacuum, which eliminates or reduces delamination of the various layers and further eliminates or reduces the risk of contaminants being introduced into the processing chamber.

[0042] Purging of the processing chamber 500 may be performed between deposition cycles to further minimize the risk of contamination. In one embodiment, the first sidewall planarization layer 710 is deposited and then the chamber is purged so that there is no gas for depositing the sidewall planarization layer in the chamber for subsequent curing treatment. As each of the multiple layers of the sidewall planarization layer is deposited, the chamber 500 is purged and then the sidewall planarization layer is cured. A purge process is performed after each deposition and curing process until the desired thickness of the sidewall planarization layer is reached. The chamber may then be purged again so that there is no gas for deposition and curing of multiple layers of the sidewall planarization layer in the chamber for subsequent barrier layer deposition processes. In one embodiment, the chamber is not purged after the sidewall deposition process and is only purged after each curing process. Finally, the barrier layer is deposited. Single chamber processing may be advantageous in reducing cycle time and reducing the number of chambers (and equipment costs) for multi-chamber processing.

[0043] In summary, an OLED patterned substrate for a display device is formed with a sidewall planarization layer that fills the fan-shaped gaps along the sidewalls of the wall features of the OLED patterned substrate. The wall features are integrated into the OLED patterned substrate to provide support for additional display device features, such as camera lenses, speakers, microphones, and sensors. The wall planarization layer can be a plurality of layers of pp-HMDSO:F, each of which is cured before forming the next layer. A barrier layer is formed on the sidewall planarization layer to protect the wall features on the OLED patterned substrate and the OLED device from moisture and oxygen that limit the life of the OLED device. In addition, the sidewall planarization layer and the barrier layer are deposited and cured in the vacuum environment of a single processing chamber. Performing deposition and curing operations in the vacuum environment of a single deposition chamber allows the sidewall planarization layer and the barrier layer to be formed without breaking the vacuum, which further eliminates or reduces the delamination and possible defects of the individual layers. In addition, the risk of contaminants being introduced into the processing chamber is eliminated or reduced, which enables the sidewall planarization layer to maintain its flexibility and optical transmittance. Additionally, performing deposition and curing operations in the vacuum environment of a single deposition chamber simplifies the method of forming an encapsulated OLED patterned substrate, which can reduce associated costs.

[0044] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be envisaged without departing from the basic scope of the disclosure, and the scope of the disclosure is to be determined by the scope of the appended claims.

Claims

1. A method for forming an encapsulation structure on an organic light emitting diode (OLED) patterned substrate, comprising: positioning an OLED patterned substrate in a plasma processing chamber, the OLED patterned substrate having a wall structure formed on a surface of the OLED patterned substrate, the wall structure having at least one sector-shaped surface; as well as A sidewall planarization layer is deposited directly on the wall structure to fill at least one of the plurality of voids along the at least one scalloped surface.

2. The method of claim 1, wherein depositing the sidewall planarization layer comprises flowing fluorinated plasma polymerized hexamethyldisiloxane (pp-HMDSO:F).

3. The method of claim 1, further comprising: The sidewall planarization layer is cured in the processing chamber using a mixed gas plasma.

4. The method of claim 1, further comprising: The sidewall planarization layer is deposited repeatedly.

5. The method of claim 4, further comprising: The sidewall planarization layer is repeatedly cured. The method of claim 1 , wherein the sidewall planarization layer has a thickness between 0.1 μm and 1.0 μm.

7. The method of claim 1, wherein the sidewall planarization layer has a carbon content greater than 10%.

8. The method of claim 2, wherein the fluorinated plasma polymerized hexamethyldisiloxane (pp-HMDSO:F) flows through a degasser prior to entering the plasma processing chamber.

9. The method of claim 8, wherein the fluorinated plasma polymerized hexamethyldisiloxane (pp-HMDSO:F) flows from the degasser and through a vaporizer before entering the processing chamber.

10. The method of claim 1, further comprising forming a barrier layer on the sidewall planarization layer.

11. A patterned substrate, comprising: substrate; A plurality of organic light emitting diode (OLED) devices, wherein the plurality of OLED devices are formed on a surface of the substrate; at least one wall structure, the at least one wall structure being formed on the surface of the substrate, the wall structure having at least one sector-shaped surface; as well as A sidewall planarization layer is disposed on the wall structure and fills at least one of the plurality of voids along the at least one sector-shaped surface. 12 . The patterned substrate of claim 11 , wherein the sidewall planarization layer comprises fluorinated plasma polymerized hexamethyldisiloxane (pp-HMDSO:F). 13 . The patterned substrate of claim 12 , wherein the sidewall planarization layer has a carbon content greater than 10%.

14. The patterned substrate of claim 11, wherein the wall planarization layer is deposited directly on the at least one wall structure.

15. The patterned substrate of claim 11, wherein the wall structure is formed from multiple layers of resist material.

16. The patterned substrate of claim 15, wherein the at least one scalloped surface is formed by the plurality of layers of the resist material. 17 . The patterned substrate of claim 11 , wherein the sidewall planarization layer is cured using a mixed gas plasma, the mixed plasma comprising at least NH 3 and N 2 O. 18 . The patterned substrate of claim 11 , further comprising a barrier layer formed on the sidewall planarization layer.

19. A plasma processing chamber for forming a packaging structure on an organic light emitting diode (OLED) patterned substrate, the plasma processing chamber comprising: a substrate support disposed within a processing region of the plasma processing chamber; a showerhead, the showerhead being disposed in the processing area opposite to the substrate support; a gas source coupled to the showerhead; an ampoule configured to provide a liquid precursor to the chamber; as well as a controller configured to control a process for forming a package structure on the patterned substrate, the process comprising: positioning an OLED patterned substrate in the plasma processing chamber, the OLED patterned substrate having a wall structure formed on a surface of the OLED patterned substrate, the wall structure having at least one sector-shaped surface; as well as A sidewall planarization layer is deposited directly on the wall structure to fill at least one of the plurality of voids along the at least one scalloped surface.

20. The plasma processing chamber of claim 19, wherein the process further comprises forming a barrier layer on the sidewall planarization layer.

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