Power conversion device

Abstract

Provided is a power conversion device including: a capacitor that smoothes an input voltage; a first switching section; a second switching section; a reactor; an isolation transformer; a second capacitor; and a control section that controls switching of the first switching section and the second switching section, converts direct-current power into alternating-current power by means of the reactor and the isolation transformer, converts the alternating-current power into direct-current power by means of the second capacitor, and controls at least any one of first switching control signals as a reference signal, the control section including: a phase shift amount calculation section that calculates a phase shift amount that shifts a phase of the reference signal; and a logic calculation section that performs a logic calculation using a signal that shifts the phase of the reference signal by the phase shift amount as an input and outputs a second switching control signal.

Description

Technical Field

[0001] This invention relates to an electric power conversion device. Background Technology

[0002] Conventionally, in bidirectional DC / DC converters used as power conversion devices, as described in Patent Documents 1-4, circuit operation is achieved by utilizing the current carrying capacity of switching elements and body diodes. However, if GaN is used in the switching elements for high-frequency driving aimed at miniaturizing the transformer, the conduction losses increase due to the characteristics of the body diode. To achieve higher efficiency, an external Schottky barrier diode can be connected in parallel with the switching elements, but this increases cost and circuit area.

[0003] Therefore, in order to achieve high efficiency without using an external Schottky barrier diode, synchronous rectification is considered. However, the following challenges exist: achieving synchronous rectification requires high-speed and high-precision instantaneous current measurement, and determining continuous and discontinuous modes requires a high-performance CPU, which also increases costs.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2017-204998

[0007] Patent Document 2: Japanese Patent Application Publication No. 2017-204999

[0008] Patent Document 3: Japanese Patent Application Publication No. 2017-205000

[0009] Patent Document 4: Japanese Patent Application Publication No. 2017-205001 Summary of the Invention

[0010] The present invention was made in view of the above-mentioned problems, and its object is to provide a high-efficiency power conversion device that can achieve synchronous rectification without reducing costs or increasing circuit area.

[0011] The present invention, which addresses the aforementioned problems, is a power conversion device, characterized in that it comprises:

[0012] Capacitors smooth the input voltage;

[0013] First switch section;

[0014] Second switch section;

[0015] Reactor;

[0016] Insulating transformer;

[0017] The second capacitor; and

[0018] The control unit controls the switching of the first switch unit and the second switch unit.

[0019] The control unit converts DC power to AC power via the reactor and the insulation transformer, and then converts the AC power back to DC power via the second capacitor.

[0020] The control unit uses at least one of the first switch control signals that control the switch of the first switch unit as a reference signal. The control unit has:

[0021] The phase offset calculation unit calculates the phase offset amount that causes the reference signal to shift its phase; and

[0022] The logic operation unit performs logic operations on a signal that shifts the phase of the reference signal by the phase shift amount as at least one input, and outputs a second switch control signal that controls the switch of the second switch unit.

[0023] According to the present invention, at least one of the first switch control signals controlling the switch of the first switch unit is used as a reference signal. Based on the required control of the switch of the second switch unit, a phase offset is calculated, and then logical operations are performed, thereby generating a second switch control signal controlling the switch of the second switch unit. The phase offset calculation unit can utilize the functions of a known control unit such as a microcomputer, and the logical operations can be implemented using simple hardware such as circuits containing logic elements. Therefore, if the phase offset required for synchronization is calculated based on the reference signal included in the first switch control signal, and the second switch control signal is generated through logical operations, a high-efficiency power conversion device that achieves synchronous rectification without increasing circuit area can be provided.

[0024] If it is a bidirectional power conversion device, the input, the first switch section and the second switch section in this invention are interchanged depending on the direction of input and output.

[0025] In addition, the power conversion device of the present invention includes, for example, a bidirectional DC / DC converter, but is not limited thereto.

[0026] Alternatively, in this invention,

[0027] The control unit has:

[0028] The continuity determination unit determines whether the current flowing through the reactor is continuous or discontinuous.

[0029] Therefore, the determination result of whether the current flowing through the reactor is continuous or discontinuous can be obtained through the continuity determination unit, so a second switch control signal corresponding to the case of discontinuity can be generated.

[0030] According to the present invention, a high-efficiency power conversion device that can achieve synchronous rectification without reducing costs or increasing circuit area can be provided. Attached Figure Description

[0031] Figure 1 This is a schematic structural diagram of the power conversion device involved in Embodiment 1 of the present invention.

[0032] Figure 2 This is a block diagram of the control unit of the power conversion device according to Embodiment 1 of the present invention.

[0033] Figure 3 This is a timing diagram of the control signals of the DC / DC converter in buck mode according to Embodiment 1 of the present invention.

[0034] Figure 4 This is a diagram illustrating an example of a logic operation circuit according to Embodiment 1 of the present invention.

[0035] Figure 5 This is a diagram illustrating the current path in buck mode of the DC / DC converter according to Embodiment 1 of the present invention.

[0036] Figure 6 This is a diagram illustrating the current path in buck mode of the DC / DC converter according to Embodiment 1 of the present invention.

[0037] Figure 7 This is a diagram illustrating the current path in buck mode of the DC / DC converter according to Embodiment 1 of the present invention.

[0038] Figure 8 This is a diagram illustrating the current path in buck mode of the DC / DC converter according to Embodiment 1 of the present invention.

[0039] Figure 9 This is a diagram illustrating the current path in buck mode of the DC / DC converter according to Embodiment 1 of the present invention.

[0040] Figure 10 This is a diagram illustrating the current path in buck mode of the DC / DC converter according to Embodiment 1 of the present invention.

[0041] Figure 11 This is a timing diagram of the control signals of the DC / DC converter in another buck mode according to Embodiment 1 of the present invention.

[0042] Figure 12This is a timing diagram of the control signals of the DC / DC converter in boost mode according to Embodiment 1 of the present invention.

[0043] Figure 13 This is a diagram illustrating an example of another logic operation circuit according to Embodiment 1 of the present invention.

[0044] Figure 14 This is a diagram showing the current path in boost mode of the DC / DC converter according to Embodiment 1 of the present invention.

[0045] Figure 15 This is a diagram showing the current path in boost mode of the DC / DC converter according to Embodiment 1 of the present invention.

[0046] Figure 16 This is a diagram showing the current path in boost mode of the DC / DC converter according to Embodiment 1 of the present invention.

[0047] Figure 17 This is a diagram showing the current path in boost mode of the DC / DC converter according to Embodiment 1 of the present invention.

[0048] Figure 18 This is a diagram showing the current path in boost mode of the DC / DC converter according to Embodiment 1 of the present invention.

[0049] Figure 19 This is a diagram showing the current path in boost mode of the DC / DC converter according to Embodiment 1 of the present invention.

[0050] Figure 20 This is a timing diagram of the control signals for another boost mode of the DC / DC converter involved in Embodiment 1 of the present invention.

[0051] Figure 21 This is a block diagram of the control unit of the power conversion device according to Embodiment 2 of the present invention.

[0052] Figure 22 This is a timing diagram of the control signals of the DC / DC converter in buck mode according to Embodiment 2 of the present invention.

[0053] Figure 23 This is a diagram illustrating an example of a logic operation circuit according to Embodiment 2 of the present invention.

[0054] Figure 24 This is a timing diagram of the control signals of another buck mode of the DC / DC converter involved in Embodiment 2 of the present invention.

[0055] Figure 25This is a timing diagram of the control signals of the DC / DC converter in boost mode according to Embodiment 2 of the present invention.

[0056] Figure 26 This is a diagram illustrating another example of the logic operation circuit involved in Embodiment 2 of the present invention.

[0057] Figure 27 This is a timing diagram of the control signals for another boost mode of the DC / DC converter involved in Embodiment 2 of the present invention. Detailed Implementation

[0058] (Application Example)

[0059] Hereinafter, application examples of the present invention will be described with reference to the accompanying drawings.

[0060] This invention can be applied to Figure 1 The power conversion device shown includes an insulated bidirectional DC / DC converter 10.

[0061] The power conversion device 1 includes a DC / DC converter 10, a control unit 20, two pairs of input / output terminal pairs 13 (13p, 13m), and an input / output terminal pair 14 (14p, 14m). Capacitors C1 and C2 are connected between the input / output terminals 13m and 13p, and between the input / output terminals 14m and 14p, respectively, to smooth the input voltage. Here, capacitor C1 corresponds to the first capacitor of the present invention. Furthermore, capacitor C2 corresponds to the second capacitor of the present invention. Moreover, depending on the input / output direction, the correspondences between capacitors C1 and C2, and between the first and second capacitors of the present invention, are interchangeable.

[0062] DC / DC converter 10 is an isolated bidirectional DC / DC converter mainly composed of a transformer TR, two reactors Lr1 and Lr2, and two full-bridge circuits 11 and 12. Reactors Lr1 and Lr2 generate AC power under the control of the first full-bridge circuit 11 and the second full-bridge circuit 12, and capacitors C1 and C2 smooth the AC power into DC power. The transformer TR can be an insulated transformer or a non-insulated transformer.

[0063] The second full-bridge circuit 12 of the DC / DC converter 10 includes: a third branch L3 having a fifth switching element SW5 and a seventh switching element SW7 connected in series; and a fourth branch L4 having a sixth switching element SW6 and an eighth switching element SW8 connected in series. As shown, an nth diode Dn (n=5-8) is connected in parallel between the terminals of the nth switching element SWn (n=5-8) in each branch. Furthermore, both the third branch L3 and the fourth branch L4 are connected to the second input / output terminal 14. Additionally, the connection point p3 between the fifth switching element SW5 and the seventh switching element SW7 in the third branch L3 is connected to one end of the second winding Wn2 of the transformer TR via the second reactor Lr2, and the connection point p4 between the sixth switching element SW6 and the eighth switching element SW8 in the fourth branch L4 is connected to the other end of the second winding Wn2 of the transformer TR. Here, the first full-bridge circuit 11 corresponds to the first switching section of the present invention. Furthermore, the second full-bridge circuit 12 corresponds to the second switching section of the present invention.

[0064] Figure 2 This is a functional block diagram of the control unit 20 of the DC / DC converter 10 involved in this embodiment. The control unit 20 includes a main control unit 21 composed of a microcontroller or the like, and a synchronous rectification logic operation unit 22 composed of analog circuits or a small CPU or the like. In addition, the main control unit 21 includes a reference signal generation unit 211, a synchronous rectification phase offset calculation unit 212, and a control signal output unit 213.

[0065] Figure 3 This is a timing diagram showing the signals used when the DC / DC converter 10 operates as a buck converter.

[0066] Signal Toff2_1 is a signal that causes the phase of the basic control signal G2 to lead by only f1(T, TON, Vin, Vout) by half a period of delay. Signal Toff2_2 is a signal that reverses the phase of Toff2_1. Here, T is the period, TON is the period during which the basic control signals G1 and G4 are simultaneously ON, Toff is the period during which the basic control signals G2 and G3 are simultaneously ON, Vin is the input voltage of the DC / DC converter 10, Vout is the output voltage of the DC / DC converter 10, and f1(T, TON, Vin, Vout) is a predetermined function that uses them as variables, and is a function with negative values ​​removed.

[0067] The signal G2_shift is used to delay the phase of the reference control signal G2 by only f2(T, TON, Vin, Vout), and the signal G4_shift is used to reverse the phase of G2_shift. Here, f2(T, TON, Vin, Vout) is a predetermined function with T, TON, Vin, and Vout as variables, and is a function with negative values ​​removed.

[0068] f1(T, TON, Vin, Vout) and f2(T, TON, Vin, Vout) correspond to the phase offset for synchronous rectification in this invention. For example, the zero-current interval in discontinuous mode and the regeneration interval in continuous mode are used as the phase offset for synchronous rectification.

[0069] like Figure 4 As shown in (A), control signals G6 and G7 are the logical product of signals Toff2_2 and G2_shift based on AND logic element 22011. This logic operation circuit 2201 is provided in the synchronous rectification logic operation unit 22. Similarly, as... Figure 4 As shown in (B), control signals G5 and G8 are the logical product of signals Toff2_1 and G4_shift based on AND logic element 22012. This logic operation circuit 2202 is provided in the synchronous rectification logic operation unit 22.

[0070] In this way, the generated control signals G1 to G8 are output from the control signal output unit 213. Figure 3 The bottom segment represents the reactor current IL1 when the DC / DC converter 10 is driven by control signals G1 to G8. At this time, the DC / DC converter 10 sequentially switches to the following states #11 to #16. Synchronous rectification can be achieved in states #12, #13, #15, and #16.

[0071] Thus, in the power conversion device 1 that includes the DC / DC converter 10, a control signal for synchronous control of the switching elements SW5 to SW8 can be generated based on the reference signal (G2 in this case) through the calculation of the phase offset and the logic operation of the logic operation circuit. This eliminates the need for external Schottky barrier diodes or high-performance CPUs, and thus provides a high-efficiency power conversion device that can achieve synchronous rectification without reducing costs or increasing the circuit area.

[0072] [Example 1]

[0073] The power conversion device 1 according to embodiments of the present invention will now be described in more detail with reference to the accompanying drawings.

[0074] <Structure of Power Conversion Device>

[0075] Figure 1 This shows a schematic structure of the power conversion device 1 according to an embodiment of the present invention.

[0076] The power conversion device 1 according to this embodiment is a device capable of bidirectional power conversion. As shown in the figure, the power conversion device 1 includes a DC / DC converter 10, a control unit 20, two pairs of input / output terminal pairs 13 (13p, 13m) and input / output terminal pairs 14 (14p, 14m). It should be noted that in the input / output terminal pairs 13 and 14, the input / output terminals 13p and 14p are also high-potential side input / output terminals, and the input / output terminals 13m and 14m are also low-potential side input / output terminals. In addition, a capacitor C1 for smoothing the input / output voltage is connected between the input / output terminals 13m and 13p. Similarly, a capacitor C2 for smoothing the input / output voltage is also connected between the input / output terminals 14m and 14p. Electrolytic capacitors can be used as capacitors C1 and C2.

[0077] DC / DC converter 10 is an isolated bidirectional DC / DC converter mainly composed of transformer TR, two reactors Lr1 and Lr2, and two full-bridge circuits 11 and 12. The following will... Figure 1 The full-bridge circuit 11 on the left and the full-bridge circuit 12 on the right are labeled as the first full-bridge circuit 11 and the second full-bridge circuit 12, respectively. Similarly, Figure 1 The reactors Lr1 and Lr2 on the left and right sides of the transformer TR are labeled as reactor Lr1 and reactor Lr2, respectively. Figure 1 The left winding Wn1 and the right winding Wn2 are labeled as the first winding Wn1 and the second winding Wn2, respectively. Additionally, Figure 1 The input / output terminal pairs 13 (13p, 13m) on the left and right sides of the circuit are labeled as the first input / output terminal pair 13 and the second input / output terminal pair 14, respectively. The first reactor Lr1 and the second reactor Lr2 can also utilize the leakage inductance of the first winding Wn1 and the second winding Wn2 of the transformer TR. It should be noted that the transformer TR of the DC / DC converter 10 may not be a transformer with a turns ratio of 1:1. Furthermore, the following description assumes that the turns ratio of the transformer TR is 1:1, and the structure and operation of the power conversion device 1 will be explained accordingly.

[0078] The first full-bridge circuit 11 of the DC / DC converter 10 includes: a first branch L1 having a first switching element SW1 and a third switching element SW3 connected in series; and a second branch L2 having a second switching element SW2 and a fourth switching element SW4 connected in series. As shown, an nth diode Dn (n=1 to 4) is connected in parallel between the terminals of the nth switching element SWn (n=1 to 4) in each branch. Each branch is connected to the first input / output terminal pair 13. The connection point p1 between the first switching element SW1 and the third switching element SW3 in the first branch L1 is connected to one end of the first winding Wn1 of the transformer TR via a first reactor Lr1. Similarly, the connection point p2 between the second switching element SW2 and the fourth switching element SW4 in the second branch L2 is connected to the other end of the first winding Wn1 of the transformer TR.

[0079] The second full-bridge circuit 12 of the DC / DC converter 10 includes: a third branch L3 having a fifth switching element SW5 and a seventh switching element SW7 connected in series; and a fourth branch L4 having a sixth switching element SW6 and an eighth switching element SW8 connected in series. As shown, an nth diode Dn (n=5~8) is connected in parallel between the terminals of the nth switching element SWn (n=5~8) in each branch. Furthermore, both the third branch L3 and the fourth branch L4 are connected to the second input / output terminals 14. Additionally, the connection point p3 between the fifth switching element SW5 and the seventh switching element SW7 in the third branch L3 is connected to one end of the second winding Wn2 of the transformer TR via the second reactor Lr2, and the connection point p4 between the sixth switching element SW6 and the eighth switching element SW8 in the fourth branch L4 is connected to the other end of the second winding Wn2 of the transformer TR.

[0080] The semiconductor materials used for switching elements SW1 to SW8 can be gallium nitride (GaN), silicon (Si), silicon carbide (SiC), etc., but are not limited to these. MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) can also be used as semiconductor switching elements. For these semiconductor switching elements used as switching elements SW1 to SW8, diodes D1 to D8 are connected in anti-parallel.

[0081] Current sensors 15p and 15s are installed on the DC / DC converter 10 to measure the current flowing through the first reactor Lr1 and the second reactor Lr2, respectively. It should be noted that various sensors (not shown) are also installed on the DC / DC converter 10 to measure the input and output voltages and currents.

[0082] The control unit 20 controls the DC / DC converter 10 (the ON / OFF state of each switching element within the DC / DC converter 10) by changing the level of the control signal sent to each switching element within the DC / DC converter 10. Hereinafter, the control signal used for the nth switching element SWn (n = 1 to 8) will be labeled as control signal Gn.

[0083] The control unit 20 consists of a processor (a microcontroller in this embodiment) and a gate driver, etc., and the outputs of the various sensors (current sensors 15p, 15s, etc.) mentioned above are input to the control unit 20.

[0084] In addition, the control unit 20 is configured (programmed) to determine, based on the input data (current value, voltage value), which of the following four types of converters the DC / DC converter 10 should operate as, and to control the DC / DC converter 10 to operate as the determined converter.

[0085] • Boost converter with the first input / output terminal pair on the 13th side as the primary side

[0086] • A buck converter with the first input / output terminal pair on the 13th side as the primary side.

[0087] • Boost converter with 14 primary sides connected to the second input / output terminal

[0088] • A buck converter with the second input / output terminal pair on the 14th side as the primary side.

[0089] In addition, the control unit 20 is configured (programmed) to immediately execute a change in the control content of the DC / DC converter 10 (from controlling the DC / DC converter 10 to operate the boost converter on the primary side of 13 as the first input / output terminal, to controlling the DC / DC converter 10 to operate the buck converter on the primary side of 14 as the second input / output terminal).

[0090] Synchronous Rectification Method

[0091] The structure and operation of the power conversion device 1 involved in this embodiment will be described in detail below.

[0092] Figure 2This is a functional block diagram of the control unit 20 of the DC / DC converter 10 involved in this embodiment. The control unit 20 includes a main control unit 21 composed of a microcontroller or the like, and a synchronous rectification logic operation unit 22 composed of analog circuits or a small CPU. In addition, the main control unit 21 includes a reference signal generation unit 211, a synchronous rectification phase offset calculation unit 212, and a control signal output unit 213. The specific functions of these parts will be described later.

[0093] <Breakdown Mode 1>

[0094] Figure 3 This is a timing diagram showing the signals used when the DC / DC converter 10 according to this embodiment operates as a buck converter. Here, the control unit 20 generates control signals for the four switching elements SW5 to SW8 included in the second full-bridge circuit 12 on the secondary side, based on control signals G1 to G4 for the four switching elements SW1 to SW4 included in the first full-bridge circuit 11 on the primary side of the DC / DC converter 10. Therefore, the control signals for the switching elements SW1 to SW8 that form the basis for generating the control used to implement the operation of the DC / DC converter 10 according to this embodiment are called basic control signals. The control signals for the switching elements SW1 to SW4 included in the first full-bridge circuit 11 in the basic control signals are used directly without modification, but the control signals for the switching elements SW5 to SW8 included in the second full-bridge circuit 12 are generated by processing G2 in the basic control signals, such as shifting the phase amount. Therefore, the basic control signals that are the object of signal processing when generating control signals for synchronous rectification are specifically called reference signals. The reference signal generation unit 211 outputs a reference signal from the basic control signal containing the control signals of the switching elements SW1 to SW4 of the first full-bridge circuit 11 to the synchronous rectification phase offset calculation unit 212. Then, the reference signal generation unit 211 outputs a control signal from the basic control signal that is used as a control signal without modification to the control signal output unit 213. Figure 3 In the example shown, the four G1 to G4 signals from the top are the timing diagrams of the basic control signals.

[0095] exist Figure 3 In the example shown, G2 is selected as the reference signal.

[0096] Signal Toff2_1 is a signal that causes the phase of the basic control signal G2 to lead by only f1(T, TON, Vin, Vout) by half a period of delay. Signal Toff2_2 is a signal that reverses the phase of Toff2_1. Here, T is the period, TON is the period during which the basic control signals G1 and G4 are simultaneously ON, Toff is the period during which the basic control signals G2 and G3 are simultaneously ON, Vin is the input voltage of the DC / DC converter 10, Vout is the output voltage of the DC / DC converter 10, and f1(T, TON, Vin, Vout) is a predetermined function that uses them as variables, and is a function with negative values ​​removed.

[0097] Furthermore, signal G2_shift is a signal that delays the phase of reference control signal G2 by only f2(T, TON, Vin, Vout), and signal G4_shift is a signal that reverses the phase of G2_shift. Here, f2(T, TON, Vin, Vout) is a predetermined function with T, TON, Vin, and Vout as variables, and is a function with negative values ​​removed.

[0098] The synchronous rectification phase offset calculation unit 212 calculates f1(T, TON, Vin, Vout) and f2(T, TON, Vin, Vout), and outputs the signal generated by phase offsetting the reference signal to the synchronous rectification logic calculation unit 22. For example, the synchronous rectification phase offset is obtained by calculating the zero current interval in the discontinuous mode and the regeneration interval in the continuous mode. Such calculation of the synchronous rectification phase offset is performed in each period of the reference signal.

[0099] like Figure 4 As shown in (A), control signals G6 and G7 are the logical product of signals Toff2_2 and G2_shift based on AND logic element 22011. This logic operation circuit 2201 is provided in the synchronous rectification logic operation unit 22. Similarly, as... Figure 4 As shown in (B), control signals G5 and G8 are the logical product of signals Toff2_1 and G4_shift based on AND logic element 22012. This logic operation circuit 2202 is provided in the synchronous rectification logic operation unit 22. The control signals output from the synchronous rectification logic operation unit 22 are output to the control signal output unit 213 for controlling each switching element.

[0100] In this way, the generated control signals G1 to G8 are output from the control signal output unit 213. Figure 3The bottom segment represents the reactor current IL1 when the DC / DC converter 10 is driven by control signals G1 to G8. At this time, the DC / DC converter 10 sequentially switches to the following states #11 to #16. The reactor current IL1 can be the current value flowing through reactor Lr1 measured by current sensor 15p, or it can be the current value flowing through the equivalent reactor that combines reactors Lr1 and Lr2, converted from the secondary-side reactor Lr2 to the primary-side reactor.

[0101] In state #11, only switching elements SW1 and SW4 are ON, while the other switching elements are OFF. At this time, the current path in the DC / DC converter 10 is as follows: Figure 5 As shown.

[0102] • In state #12, switching elements SW1, SW4, SW5, and SW8 are ON, while other switching elements are OFF. At this time, the current path in the DC / DC converter 10 is as follows: Figure 6 As shown.

[0103] • In state #13, switching elements SW3, SW4, SW5, and SW8 are ON, while other switching elements are OFF. At this time, the current path in DC / DC converter 10 is as follows: Figure 7 As shown.

[0104] • In state #14, only switching elements SW2 and SW3 are ON, while the other switching elements are OFF. At this time, the current path in the DC / DC converter 10 is as follows: Figure 8 As shown.

[0105] • In state #15, switching elements SW2, SW3, SW6, and SW7 are ON, while other switching elements are OFF. At this time, the current path in DC / DC converter 10 is as follows: Figure 9 As shown.

[0106] In state #16, switching elements SW1, SW2, SW6, and SW7 are ON, while other switching elements are OFF. At this time, the current path in the DC / DC converter 10 is as follows: Figure 10 As shown.

[0107] Thus, synchronous rectification can be achieved in #12, #13, #15, and #16. Although synchronous rectification cannot be achieved in #11 and #14, the losses during these periods are small due to their short duration.

[0108] Thus, in the power conversion device 1 that includes the DC / DC converter 10, a control signal for synchronous control of the switching elements SW5 to SW8 can be generated based on the reference signal through the calculation of the phase offset and the logic operation based on the logic operation circuit. This eliminates the need for external Schottky barrier diodes, high-performance CPUs, etc., and thus provides a high-efficiency power conversion device that can achieve synchronous rectification without reducing costs or increasing the circuit area.

[0109] <Breakdown Mode 2>

[0110] Figure 11 This is an example of a situation where the reactor current IL1 is discontinuous depending on the input and output conditions in buck mode.

[0111] exist Figure 11 In the example shown, G2 is also selected as the reference signal.

[0112] Here, signal Toff2_1 is the signal that causes the phase of the basic control signal G2 to be ahead of the phase by only f1(T, TON, TOFF, Vin, Vout) from the phase of the delayed half-cycle, and signal Toff2_2 is the signal that reverses the phase of Toff2_1.

[0113] In addition, signal G2_shift is a signal that delays the phase of reference control signal G2 by only f2(T, TON, Vin, Vout), and signal G4_shift is a signal that reverses the phase of G2_shift.

[0114] In addition, such as Figure 4 As shown in (A), control signals G6 and G7 are the logical product of signals Toff2_2 and G2_shift based on AND logic element 22011. This logic operation circuit 2201 is provided in the synchronous rectification logic operation unit 22. Similarly, as... Figure 4 As shown in (B), control signals G5 and G8 are the logical product of signals Toff2_1 and G4_shift based on AND logic element 22012. This logic operation circuit 2202 is provided in the synchronous rectification logic operation unit 22. The logic operation circuits 2201 and 2202 that generate control signals G5 to G8 in this buck mode 2 are the same as in buck mode 1.

[0115] In this way, the generated control signals G1 to G8 are output from the control signal output unit 213. Figure 11The bottom segment represents the reactor current IL1 when the DC / DC converter 10 is driven by control signals G1 to G8. At this time, the DC / DC converter 10 sequentially switches to states #21 to #26. Although the description of the current path of the DC / DC converter 10 in each state is omitted, synchronous rectification can be achieved except for the discontinuous states #23 and #26.

[0116] Thus, in the power conversion device 1 that includes the DC / DC converter 10, a control signal for synchronous control of switching elements SW5 to SW8 can be generated based on the reference control signal through phase offset calculation and logic operation based on the logic operation circuit. This eliminates the need for external Schottky barrier diodes, high-performance CPUs, etc., and provides a high-efficiency power conversion device that can achieve synchronous rectification without reducing costs or increasing circuit area.

[0117] <Boost Mode 1>

[0118] Figure 12 This is a timing diagram showing the signals used when the DC / DC converter 10 according to this embodiment operates as a boost converter. Here, the control signals G1 to G4 of the four switching elements SW1 to SW4 included in the first full-bridge circuit 11 on the primary side of the DC / DC converter 10, and the control signals G7 and G8 for SW7 and SW8 are used as basic control signals. Based on these signals, control signals for the four switching elements SW5 to SW8 included in the second full-bridge circuit 12 on the secondary side are generated. Here, the control signals for the switching elements SW1 to SW4 included in the first full-bridge circuit 11 are used directly without modification. However, the control signals for the switching elements SW5 to SW8 included in the second full-bridge circuit 12 are generated by performing phase shifting and other processing on G2 of the basic control signals, and simultaneously performing logical operations with the basic control signals G07 and G08 for the switching elements SW7 and SW8 as inputs. Here, since the control signals for switching elements SW7 and SW8 are generated by processing the basic control signals, the basic control signals for switching elements SW7 and SW8 are labeled G07 and G08, respectively, and the final control signals generated for controlling switching elements SW7 and SW8 are labeled G7 and G8. Therefore, the basic control signal that becomes the object of signal processing when generating the control signals for synchronous rectification is specifically referred to as the reference signal. Figure 12 In the middle, the four G1 to G4, G07 and G08 from the top are reference signals.

[0119] Signal G1,4_shift is a signal that delays the phase of the reference control signal G1 by only f3(T, TON, Vin, Vout), and signal G2,3_shift is a signal that reverses the phase of signal G1,4_shift. Here, f3(T, TON, Vin, Vout) is a predetermined function with T, TON, Vin, and Vout as variables, and is a function with negative values ​​removed.

[0120] Additionally, signal Toff1_A is a signal that causes the phase of the basic control signal G2 to lead by f4(T, TON, Vin, Vout) by half a period of delay, and signal Toff1_B is a signal that reverses the phase of Toff1_A. Here, T is the period, TON is the period during which the basic control signals G1, G4, and G7 are simultaneously ON, TOFF is the period during which the basic control signals G1, G4, and G8 are simultaneously ON, Vin is the input voltage of DC / DC converter 10, Vout is the output voltage of DC / DC converter 10, and f4(T, TON, Vin, Vout) is a predetermined function that uses them as variables, and is a function with negative values ​​removed.

[0121] The synchronous rectification phase offset calculation unit 212 calculates f4(T, TON, Vin, Vout) and f3(T, TON, Vin, Vout), and outputs the signal generated by phase offsetting the reference signal to the synchronous rectification logic calculation unit 32. For example, the synchronous rectification phase offset is obtained by calculating the zero current interval in the discontinuous mode and the regeneration interval in the continuous mode. Such calculation of the synchronous rectification phase offset is performed in each cycle of the reference signal.

[0122] like Figure 13 As shown in (A), the control signal G5 is the logical product of the signals Toff1_A and G08 based on the AND logic element 22013. This logic operation circuit 2203 is provided in the synchronous rectification logic operation unit 22. As... Figure 13 As shown in (B), the control signal G6 is the logical product of the signals Toff1_B and G07 based on the AND logic element 22014. This logic operation circuit 2204 is provided in the synchronous rectification logic operation unit 22.

[0123] like Figure 13 As shown in (C), the control signal G7 is the logical sum of signals G2, 3shift, and G07 based on the OR logic element 22015. This logic operation circuit 2205 is provided in the synchronous rectification logic operation unit 22. Figure 13 As shown in (D), the control signal G8 is the logical sum of signals G1, 4shift, and G08 based on the OR logic element 22016. This logic operation circuit 2206 is provided in the synchronous rectification logic operation unit 22.

[0124] In this way, the generated control signals G1 to G8 are output from the control signal output unit 213. Figure 12 The bottom segment represents the reactor current IL1 when the DC / DC converter 10 is driven by control signals G1 to G8. At this time, the DC / DC converter 10 sequentially switches to the following states #31 to #36.

[0125] In state #31, switching elements SW1, SW4, and SW7 are ON, while other switching elements are OFF. At this time, the current path in the DC / DC converter 10 is as follows: Figure 14 As shown.

[0126] • In state #32, switching elements SW1, SW4, SW7, and SW8 are ON, while other switching elements are OFF. At this time, the current path in the DC / DC converter 10 is as follows: Figure 15 As shown.

[0127] • In state #33, switching elements SW1, SW4, SW5, and SW8 are ON, while other switching elements are OFF. At this time, the current path in DC / DC converter 10 is as follows: Figure 16 As shown.

[0128] In state #34, switching elements SW2, SW3, and SW8 are ON, while other switching elements are OFF. At this time, the current path in the DC / DC converter 10 is as follows: Figure 17 As shown.

[0129] • In state #35, switching elements SW2, SW3, SW7, and SW8 are ON, and the other switching elements are OFF. At this time, the current path in the DC / DC converter 10 is as follows: Figure 18 As shown.

[0130] • In state #36, switching elements SW2, SW3, SW6, and SW7 are ON, while other switching elements are OFF. At this time, the current path in the DC / DC converter 10 is as follows: Figure 19 As shown.

[0131] Thus, synchronous rectification can be achieved in #32, #33, #35, and #36. Although synchronous rectification cannot be achieved in #31 and #34, the losses during these periods are small due to their short duration.

[0132] Thus, in the power conversion device 1 that includes the DC / DC converter 10, a control signal for synchronous control of the switching elements SW5 to SW8 can be generated based on the reference signal through the calculation of the phase offset and the logic operation based on the logic operation circuit. This eliminates the need for external Schottky barrier diodes, high-performance CPUs, etc., and thus provides a high-efficiency power conversion device that can achieve synchronous rectification without reducing costs or increasing the circuit area.

[0133] <Boost Mode 2>

[0134] Figure 20 A timing diagram of the signals used when the DC / DC converter 10 according to this embodiment is operated as a boost converter is shown. Figure 20 This is an example of a situation where the reactor current IL1 is discontinuous due to input and output conditions in boost mode. The signal labeling is consistent with the description in boost mode 1. Here, the control signals G1 to G4 of the four switching elements SW1 to SW4 included in the first full-bridge circuit 11 on the primary side of the DC / DC converter 10, and the control signals G07 and G08 for SW7 and SW8 are used as basic control signals. Based on these signals, control signals for the four switching elements SW5 to SW8 included in the second full-bridge circuit 12 on the secondary side are generated. Here, the control signals for the switching elements SW1 to SW4 included in the first full-bridge circuit 11 are not changed and are directly used as control signals. However, the control signals for the switching elements SW5 to SW8 included in the second full-bridge circuit 12 are generated by performing phase shifting and other processing on G2 of the basic control signals, and simultaneously performing logical operations with the basic control signals for switching elements SW7 and SW8, namely G07 and G08, as inputs. Figure 20 In the middle, the four G1~G4, G07 and G08 from the top are reference signals.

[0135] Signal G1,4_shift is a signal that delays the phase of the reference control signal G1 by only f3(T, TON, Vin, Vout), and signal G2,3_shift is a signal that reverses the phase of signal G1,4_shift. Here, f3(T, TON, Vin, Vout) is a predetermined function with T, TON, Vin, and Vout as variables, and is a function with negative values ​​removed.

[0136] Furthermore, signal Toff1_A is a signal that causes the phase of the basic control signal G2 to be led by f4(T, TON, Vin, Vout) by half a cycle, and signal Toff1_B is a signal that reverses the phase of Toff1_A. Here, f4(T, TON, Vin, Vout) is a predetermined function with these variables as variables, a function with negative values ​​removed.

[0137] like Figure 13 As shown in (A), the control signal G5 is the logical product of the signals Toff1_A and G08 based on the AND logic element 22013. This logic operation circuit 2203 is provided in the synchronous rectification logic operation unit 22. As... Figure 13 As shown in (B), the control signal G6 is the logical product of the signals Toff1_B and G07 based on the AND logic element 22014. This logic operation circuit 2204 is provided in the synchronous rectification logic operation unit 22.

[0138] The logic circuits 2203 and 2204 that generate control signals G5 and G6 in boost mode 2 are the same as those in boost mode 1.

[0139] like Figure 13 As shown in (C), the control signal G7 is the logical sum of signals G2, 3shift, and G07 based on the OR logic element 22015. This logic operation circuit 2205 is provided in the synchronous rectification logic operation unit 22. Figure 13 As shown in (D), the control signal G8 is the logical sum of signals G1, 4shift, and G08 based on the OR logic element 22016. This logic operation circuit 2206 is provided in the synchronous rectification logic operation unit 22.

[0140] The logic circuits 2205 and 2206 that generate control signals G7 and G8 in boost mode 2 are the same as those in boost mode 1.

[0141] In this way, the generated control signals G1 to G8 are output from the control signal output unit 213. Figure 20 The bottom segment represents the reactor current IL1 when the DC / DC converter 10 is driven by control signals G1 to G8. At this time, the DC / DC converter 10 sequentially switches to states #41 to #46. Although the description of the current path of the DC / DC converter 10 in each state is omitted, synchronous rectification can be achieved except for the discontinuous states #43 and #46.

[0142] Thus, in the power conversion device 1 that includes the DC / DC converter 10, a control signal for synchronous control of the switching elements SW5 to SW8 can be generated based on the reference signal through the calculation of the phase offset and the logic operation based on the logic operation circuit. This eliminates the need for external Schottky barrier diodes, high-performance CPUs, etc., and thus provides a high-efficiency power conversion device that can achieve synchronous rectification without reducing costs or increasing the circuit area.

[0143] When generating control signals for synchronous control of the above-mentioned buck mode 1, buck mode 2, boost mode 1, and boost mode 2, G1 and G2 are used as reference signals, but G3 and G4 can also be used as reference signals.

[0144] [Example 2]

[0145] Hereinafter, the power conversion device 1 and the DC / DC converter 10 according to Embodiment 2 of the present invention will be described. The DC / DC converter 10 according to Embodiment 2 is the same as that in Embodiment 1 except for the structure of the control unit 30. Therefore, the same reference numerals are used for the same structure and detailed descriptions are omitted.

[0146] Figure 21 This is a block diagram of the control unit 30. The control unit 30 includes a main control unit 31 composed of a microcontroller or similar component and a synchronous rectification logic operation unit 32 composed of analog circuits or a small CPU. Furthermore, the main control unit 31 includes a reference signal generation unit 211, a synchronous rectification phase offset calculation unit 212, a control signal output unit 213, and a continuity determination unit 311. The main control unit 31 includes a continuity determination unit 311, and the structure of the synchronous rectification logic operation unit 32 differs from the control unit 20 described in Embodiment 1; other structures are the same. The continuity determination unit 311 acquires information such as the input and output conditions of the power conversion device 1, and uses a continuity determination unit such as a table to determine whether the operation of the DC / DC converter 10 is in continuous mode or discontinuous mode. Based on this determination result, it outputs a voltage equivalent to the voltage when the control signal is ON (i.e., 1) in continuous mode and OFF (i.e., 0) in discontinuous mode. The specific functions of these parts of the DC / DC converter 10 will be described later.

[0147] <Breakdown Mode 1>

[0148] Figure 22 This is a timing diagram showing the signals used when the DC / DC converter 10 according to this embodiment operates as a buck converter. Here, control signals for the four switching elements SW5 to SW8 included in the second full-bridge circuit 12 on the secondary side are generated based on control signals G1 to G4 for the four switching elements SW1 to SW4 included in the first full-bridge circuit 11 on the primary side of the DC / DC converter 10.

[0149] Therefore, the fundamental control signal used to generate the control signal for synchronous rectification, which becomes the object of signal processing, is specifically called the reference signal. Figure 3 In the example shown, the four G1 to G4 signals from the top are the timing diagrams of the basic control signals.

[0150] The generation methods of signals Toff2_1, Toff2_2, G2_shift, and G4_shift are the same as those of buck mode 1 in Example 1, so the description is omitted.

[0151] like Figure 23 As shown in (A), control signals G6 and G7 are the logical sum of the output of the logical product of signals Toff2_2 and G2_shift based on AND logic element 32011, and the output of signal G2_shift and the continuous determination signal based on AND logic element 32012, based on OR logic element 32013. Here, the continuous determination signal is the output signal of the continuous determination unit 311 described above. Furthermore, as... Figure 23 As shown in (B), control signals G5 and G8 are the logical sum of the output of the logical product of signal Toff2_1 and signal G4_shift based on AND logic element 32014, and the output of signal G4_shift and the output of the AND logic element 32015 based on continuous determination signal, based on OR logic element 32016. These logic operation circuits 3201 and 3202 are provided in the synchronous rectification logic operation unit 32.

[0152] In this way, the generated control signals G1 to G8 are output from the control signal output unit 213. Figure 22 The bottom segment represents the reactor current IL1 when the DC / DC converter 10 is driven by control signals G1 to G8. At this time, the DC / DC converter 10 sequentially switches to states #51 to #56. Although the description of the current path of the DC / DC converter 10 in each state is omitted, synchronous rectification can be achieved in all states #51 to #56 without changing the switching mode based on whether it is continuous or discontinuous by inputting a continuity determination signal to the logic operation circuits 3201 and 3202.

[0153] Thus, in the power conversion device 1 that includes the DC / DC converter 10, a control signal for synchronous control of the switching elements SW5 to SW8 can be generated based on the reference signal through the calculation of the phase offset and the logic operation based on the logic operation circuit. This eliminates the need for external Schottky barrier diodes, high-performance CPUs, etc., and thus provides a high-efficiency power conversion device that can achieve synchronous rectification without reducing costs or increasing the circuit area.

[0154] <Breakdown Mode 2>

[0155] Figure 24 This is an example of a situation where the reactor current IL1 is discontinuous depending on the input and output conditions in buck mode.

[0156] exist Figure 24 In the example shown, G2 is also selected as the reference signal.

[0157] The generation methods of signals Toff2_1, Toff2_2, G2_shift, and G4_shift are the same as those of buck mode 1 in Example 1, so the description is omitted.

[0158] like Figure 23 As shown in (A), control signals G6 and G7 are the logical sum of the output of the logical product of signals Toff2_2 and G2_shift based on AND logic element 32011, and the output of signals G2_shift and the AND logic element 32012 based on continuous decision signals, based on OR logic element 32013. Additionally, as... Figure 23 As shown in (B), control signals G5 and G8 are the logical sum of the output of the logical product of signal Toff2_1 and signal G4_shift based on AND logic element 32014, and the output of signal G4_shift and the output of the AND logic element 32015 of the continuous decision signal, based on OR logic element 32016. The logic operation circuits 3201 and 3202 that generate control signals G5 to G8 in this buck mode 2 are the same as those in buck mode 1 of embodiment 2.

[0159] In this way, the generated control signals G1 to G8 are output from the control signal output unit 213. Figure 24 The bottom segment represents the reactor current IL1 when the DC / DC converter 10 is driven by control signals G1 to G8. At this time, the DC / DC converter 10 sequentially transitions to states #61 to #66. By inputting a continuity determination signal to logic operation circuits 3201 and 3202, the AND logic elements 32012 and 32015 do not function when the states are discontinuous. Although the description of the current path of the DC / DC converter 10 in each state is omitted, synchronous rectification can be achieved except for the discontinuous states #63 and #66.

[0160] Thus, in the power conversion device 1 that includes the DC / DC converter 10, a control signal for synchronous control of the switching elements SW5 to SW8 can be generated based on the reference signal through the calculation of the phase offset and the logic operation based on the logic operation circuit. This eliminates the need for external Schottky barrier diodes, high-performance CPUs, etc., and thus provides a high-efficiency power conversion device that can achieve synchronous rectification without reducing costs or increasing the circuit area.

[0161] <Boost Mode 1>

[0162] Figure 25This is a timing diagram showing the signals used when the DC / DC converter 10 according to Embodiment 2 operates as a boost converter. Here, the control signals G1-G4 for the four switching elements SW1-SW4 included in the first full-bridge circuit 11 on the primary side of the DC / DC converter 10, and the control signals G07 and G08 for SW7 and SW8, are used as basic control signals. Control signals for the four switching elements SW5-SW8 included in the second full-bridge circuit 12 on the secondary side are generated based on these signals. Here, the control signals for the switching elements SW1-SW4 in the first full-bridge circuit 11 are used directly without modification, but the control signals for the switching elements SW5-SW8 in the second full-bridge circuit 12 are generated by performing phase shifting and other processing on G2 in the basic control signals, while simultaneously performing logical operations with the basic control signals for switching elements SW7 and SW8, namely G07 and G08, as inputs. Therefore, the basic control signals that are the object of signal processing when generating control signals for synchronous rectification are specifically called reference signals. Figure 25 In the middle, the four G1 to G4, G07 and G08 from the top are reference signals.

[0163] The generation methods for signals G1,4_shift, G2,3_shift, Toff1_A, and Toff1_B are the same as those for boost mode 1 in Example 1, so the description is omitted.

[0164] Control signal G5, such as Figure 26 As shown in (A), the output of the logical product of signal Toff1_A and signal G08 based on AND logic element 32017, and the output of the logical product of signal G08, signal G1,4_shift and continuous decision signal based on AND logic element 32018, are logically summed using OR logic element 32019. This logic operation circuit 3203 is provided in the synchronous rectification logic operation unit 32.

[0165] Control signal G6, such as Figure 26 As shown in (B), the output of the AND logic element 32020 for signal Toff1_B and signal G07, and the logical sum of the output of the AND logic element 32021 for signals G07, G2,3_shift and the continuous determination signal, based on the OR logic element 32022. This logic operation circuit 3204 is provided in the synchronous rectification logic operation unit 32.

[0166] like Figure 26As shown in (C), the control signal G7 is the logical sum of signals G2,3_shift and signal G07 based on the OR logic element 32023. The logic operation circuit 3205, which includes this OR logic element 32023, is provided in the synchronous rectification logic operation unit 32. Furthermore, as... Figure 26 As shown in (D), the control signal G8 is the logical sum of signals G1,4_shift and G08 based on the OR logic element 32024. The logic operation circuit 3206 containing the OR logic element 32024 is provided in the synchronous rectification logic operation unit 32.

[0167] In this way, the generated control signals G1 to G8 are output from the control signal output unit 213. Figure 25 The bottom segment represents the reactor current IL1 when the DC / DC converter 10 is driven by control signals G1 to G8. At this time, the DC / DC converter 10 sequentially switches to states #71 to #76. Although the description of the current path of the DC / DC converter 10 in each state is omitted, synchronous rectification can be achieved in all states #71 to #76 by inputting a continuity determination signal to the logic operation circuits 3201 and 3202, without changing the switching mode based on whether it is continuous or discontinuous.

[0168] Thus, in the power conversion device 1 that includes the DC / DC converter 10, a control signal for synchronous control of the switching elements SW5 to SW8 can be generated based on the reference signal through the calculation of the phase offset and the logic operation based on the logic operation circuit. This eliminates the need for external Schottky barrier diodes, high-performance CPUs, etc., and thus provides a high-efficiency power conversion device that can achieve synchronous rectification without reducing costs or increasing the circuit area.

[0169] <Boost Mode 2>

[0170] Figure 27 This is an example of a situation where the reactor current IL1 is discontinuous due to input and output conditions in boost mode.

[0171] The methods for generating signals G1,4_shift, G2,3_shift, Toff1_A, and Toff1_B are the same as those for boost mode 1 in Example 1, and therefore are omitted from the description. Similarly, the methods for generating control signals G5 to G8 are also the same as those for boost mode 1 in Example 2, and therefore are omitted from the description.

[0172] In this way, the generated control signals G1 to G8 are output from the control signal output unit 213. Figure 27The bottom segment represents the reactor current IL1 when the DC / DC converter 10 is driven by control signals G1 to G8. At this time, the DC / DC converter 10 sequentially transitions to states #81 to #86. Although the description of the current path of the DC / DC converter 10 in each state is omitted, by inputting a continuity determination signal to the logic operation circuits 3203 and 3204, the AND logic elements 32018 and 32021 do not function when the current path is discontinuous. Although the description of the current path of the DC / DC converter 10 in each state is omitted, synchronous rectification can be achieved except for the discontinuous states #83 and #86.

[0173] Thus, in the power conversion device 1 that includes the DC / DC converter 10, a control signal for synchronous control of the switching elements SW5 to SW8 can be generated based on the reference signal through the calculation of the phase offset and the logic operation based on the logic operation circuit. This eliminates the need for external Schottky barrier diodes, high-performance CPUs, etc., and thus provides a high-efficiency power conversion device that can achieve synchronous rectification without reducing costs or increasing the circuit area.

[0174] (Modified Example)

[0175] Alternatively, the operating status of the power operation / regeneration can be input to the synchronous rectification logic operation units 22 and 32 to determine which of the first full-bridge circuit 11 and the second full-bridge circuit 12 should be used as the secondary side.

[0176] In the above-described embodiments 1 and 2, the isolated-side bidirectional DC / DC converter 10 was used as an example. However, the present invention is not related to the isolated type or the non-isolated type, and can also be applied to bidirectional buck-boost choppers and bidirectional multi-functional choppers.

[0177] It should be noted that, in order to compare the constituent elements and the structure of the embodiments of the present invention, the constituent elements of the present invention will be described with additional reference numerals.

[0178] <Invention 1>

[0179] A power conversion device (1), characterized in that it comprises:

[0180] The capacitor (C1) smooths the input voltage.

[0181] First switch section (11);

[0182] Second switch section (12);

[0183] Reactors (Lr1, Lr2);

[0184] Insulation transformer (TR);

[0185] The second capacitor (C2); and

[0186] The control unit (20) controls the switching of the first switch unit (11) and the second switch unit (12).

[0187] The control unit (20) converts DC power into AC power through the reactors (Lr1, Lr2) and the insulation transformer (TR), and converts the AC power back into DC power through the second capacitor (C2).

[0188] The control unit (20) uses at least one of the first switch control signals that control the switches of the first switch unit (SW1 to SW4) as a reference signal. The control unit (20) has:

[0189] The phase offset calculation unit (212) calculates the phase offset amount that causes the reference signal to shift its phase; and

[0190] The logic operation unit (22) performs a logic operation on a signal that shifts the phase of the reference signal by the phase shift amount as at least one input, and outputs a second switch control signal that controls the switch of the second switch unit (SW5 to SW8).

[0191] Symbol Explanation

[0192] 1: Power conversion device

[0193] 11: First Full-Bridge Circuit

[0194] 12: Second Full-Bridge Circuit

[0195] C1, C2: Capacitors

[0196] Lr1, Lr2: Reactors

[0197] TR: Insulation Transformer

[0198] SW1~SW8: Switching elements

[0199] 20: Control Unit

[0200] 22: Logic unit for synchronous rectification

[0201] 212: Phase offset calculation unit for synchronous rectification.

Claims

1. A power conversion device, characterized in that, have: Capacitors smooth the input voltage; First switch section; Second switch section; Reactor; Insulating transformer; Second capacitor; as well as The control unit controls the switching of the first switch unit and the second switch unit. The control unit converts DC power to AC power via the reactor and the insulation transformer, and then converts the AC power back to DC power via the second capacitor. The control unit uses at least one of the first switch control signals that control the switch of the first switch unit as a reference signal. The control unit has: The phase offset calculation unit calculates the phase offset amount that causes the reference signal to shift its phase. as well as The logic operation unit takes a signal generated by shifting the phase of the reference signal by only the phase offset as at least one input, performs logic operations on the reference signal, and outputs the signal generated by the logic operation as a second switch control signal to control the switch of the second switch unit. The logic operation unit includes logic elements that take a signal generated by shifting the phase of the reference signal by only the phase shift amount and other signals as inputs to perform logical products or logical sums. The other signals are signals that cause the phase of the reference signal to shift only by a phase shift amount different from the stated phase shift amount, or basic control signals for the second switch control signal. The control unit generates the second switch control signal based on the output of the logic element.

2. The power conversion device according to claim 1, characterized in that, The control unit has: The continuity determination unit determines whether the current flowing through the reactor is continuous or discontinuous.

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