Power supply circuit and computing system

Abstract

A power supply circuit and a computing system are disclosed. The power supply circuit includes a power converter, an input voltage source, and a clamping circuit. The power converter has an input pin, an output pin, and an enable pin. The input voltage source is electrically connected to the input pin and provides an input voltage to the input pin. The clamping circuit is electrically connected to the enable pin of the power converter. When the input voltage rises to at least a critical input voltage, the clamping circuit is configured to enable the power converter to provide an output voltage to the output pin. When the input voltage drops below the critical input voltage, the clamping circuit is configured to disable the power converter and prevent the power converter from being re-enabled for a predetermined period of time.

Description

Technical Field

[0001] This disclosure generally relates to power supply circuits, and more particularly to power supply circuits having a clamping circuit to prevent output voltage spikes. Background Technology

[0002] The computing system and apparatus include various electronic components powered by a power supply unit. The power supply unit receives an input voltage and generates an output voltage usable by the electronic components of the computing system. The power supply unit may include protection against undervoltage conditions, which occur when the voltage supplied to the electronic components is lower than expected. To prevent undervoltage conditions, the power supply may include means or components that disable the output voltage generated for these electronic components when the input voltage drops below a threshold. During a standard power-down procedure, when the input voltage drops below a threshold, the ripple component of the input voltage briefly reactivates the output voltage, which can damage the electronic components. Therefore, an improved power supply unit is needed to prevent the ripple component from briefly reactivating the output voltage. Summary of the Invention

[0003] The term “embodiment” and similar terms, such as implementation, setting, pattern, example, and option, are intended to broadly refer to all the subject matter of the invention and the claims. Statements containing these terms should not be construed as limiting the subject matter described herein or limiting the meaning or scope of the claims. The embodiments of this disclosure as covered herein are defined by the claims rather than by the content of this invention. This summary is a high-level overview of various aspects of this disclosure and introduces some concepts that will be further described in the following description paragraphs. This summary is not intended to identify essential features of the claimed subject matter, nor is it intended to be used alone to determine the scope of the claimed subject matter. The subject matter of this application should be understood by referring to appropriate portions of the entire specification, any or all of the accompanying drawings, and each claim.

[0004] In a first embodiment, this disclosure relates to a power supply circuit. The power supply circuit includes a power converter, an input voltage source, and a clamping circuit. The power converter has an input pin, an output pin, and an enable pin. The input voltage source is electrically connected to the input pin of the power converter and configured to provide an input voltage. The clamping circuit is electrically connected to the enable pin of the power converter. In response to the input voltage increasing to at least a critical input voltage, the clamping circuit enables the power converter to provide an output voltage at the output pin. In response to the input voltage decreasing below the critical input voltage, the clamping circuit disables the power converter and prevents the power converter from being re-enabled for a predetermined period of time.

[0005] In some cases, the input voltage contains a ripple component, which causes the input voltage to vary periodically, with a ripple frequency and a ripple period. In some cases, in response to the input voltage initially dropping below a critical input voltage due to the ripple component and then rising to at least the critical input voltage, the clamping circuit prevents the power converter from being reactivated. In some cases, the ripple period is shorter than a predetermined time period, causing the ripple component to cause the input voltage to rise to at least the critical input voltage within a predetermined time period and then drop below the critical input voltage.

[0006] In some cases, the clamping circuit includes a transistor electrically connected to an input voltage source and an enable pin of the power converter. The transistor is configured to transition between an "on" and an "off" state to enable and disable the power converter. In some cases, the transistor transitions from an "off" state to an "on" state in response to the input voltage increasing to at least a critical input voltage. In some cases, in response to the input voltage increasing to at least a critical input voltage and the transistor transitioning to an "on" state, the transistor creates a threshold enable voltage to be provided to the enable pin of the power converter.

[0007] In some cases, the critical enable voltage is lower than the critical input voltage. In some cases, in response to the input voltage dropping below the critical input voltage, the transistor transitions from the "on" state to the "off" state, causing the voltage supplied to the enable pin of the power converter to be lower than the critical enable voltage.

[0008] In some cases, the transistor has a switching frequency that defines the time required for the transistor to transition from an "on" state to an "off" state, and the switching frequency is lower than the ripple frequency of the ripple component of the input voltage. In some cases, in response to the input voltage initially rising to at least a critical input voltage, the transistor transitions to an "on" state to enable the power converter. In response to the input voltage subsequently falling below the critical input voltage, the transistor transitions to an "off" state to disable the power converter. In some cases, in response to the ripple component of the input voltage causing the input voltage to rise to at least a critical input voltage within a pre-response period (i) and then fall below the input voltage, the transistor remains in an "off" state. In some cases, after the ripple component of the input voltage causes the input voltage to rise to at least a critical input voltage, the ripple component of the input voltage then causes the input voltage to fall below the critical input voltage after a first period. In some cases, in response to the input voltage rising to at least a critical input voltage, the transistor is configured to transition to an "on" state only after a second period. The second time period is longer than the first time period, causing the input voltage to rise to at least the critical input voltage due to the ripple component of the input voltage. The transistor will not transition to the "on" state until the input voltage drops below the critical input voltage due to the ripple component of the input voltage.

[0009] In some cases, a transistor comprises a base, an emitter, and a collector. The base is electrically connected to the input voltage source. The emitter is electrically connected to the input voltage source via an emitter-side resistor. The collector is electrically connected to the enable pin of the power converter. In some cases, when the input voltage is greater than or equal to a critical input voltage, the voltage supplied to the base of the transistor is greater than or equal to the transistor's startup voltage, causing an on-state voltage divider composed of emitter-side resistors. The on-state voltage divider provides a voltage greater than or equal to the critical enable voltage to the enable pin of the power converter.

[0010] In some cases, when the input voltage source is below the critical input voltage, the voltage supplied to the transistor's base is below the transistor's startup voltage, causing the off-state voltage divider to exclude the emitter resistor. The off-state voltage divider provides a voltage below the critical enable voltage to the power converter's enable pin. In some cases, the on-state voltage divider includes an emitter resistor and an additional resistor electrically connected in parallel between the input voltage source and the enable pin. The off-state voltage divider contains only the additional resistor electrically connected between the input voltage source and the enable pin.

[0011] In a second embodiment, this disclosure relates to a power supply circuit. The power supply circuit includes a power converter, an input voltage source, a first resistor, a second resistor, and a clamping circuit. The power converter has an input pin, an output pin, and an enable pin. The input voltage source is an input pin configured to provide an input voltage to the power converter. The first resistor is electrically connected to the input voltage source and the enable pin of the power converter, such that the input voltage source is electrically connected to the enable pin of the power converter through at least the first resistor. The second resistor is electrically connected to the first resistor and the enable pin of the power converter. The clamping circuit is electrically connected to the enable pin of the power converter. The clamping circuit includes a transistor having a base, an emitter, and a collector. The base is electrically connected to the input voltage source. The collector is electrically connected to the enable pin of the power converter. The clamping circuit also includes an emitter-terminated resistor electrically connected between the emitter and the input voltage source. In response to an input voltage rise to at least a critical input voltage, the on-state voltage divider, consisting of a first resistor, a second resistor, and an emitter resistor, enables the power converter and provides an output voltage at the output pin. In response to an input voltage drop below the critical input voltage, the off-state voltage divider, consisting of the first resistor and the second resistor, disables the power converter and prevents it from being re-enabled within a predetermined period.

[0012] In a third embodiment, this disclosure relates to a computer system comprising a chassis, one or more electronic components disposed within the chassis, and a power supply circuit disposed within the chassis and configured to assist in powering the one or more electronic components. The power supply circuit includes a power converter, an input voltage source, and a clamping circuit. The power converter has an input pin, an output pin, and an enable pin. The input voltage source is electrically connected to the input pin of the power converter and configured to provide an input voltage. The clamping circuit is electrically connected to the enable pin of the power converter. In response to the input voltage increasing to at least a critical input voltage, the clamping circuit enables the power converter to provide an output voltage at the output pin. In response to the input voltage decreasing below the critical input voltage, the clamping circuit disables the power converter and prevents the power converter from being re-enabled for a predetermined period of time.

[0013] The foregoing description is not intended to represent every embodiment or aspect of this disclosure. Rather, the foregoing description provides only examples of certain novel aspects and features listed herein. The foregoing features and advantages, as well as other features and advantages of this disclosure, will readily become apparent from the following detailed description of representative embodiments and modes used to practice the invention, in conjunction with the accompanying drawings and claims. Additional aspects of this disclosure will be apparent to those skilled in the art from the detailed description of various embodiments with reference to the accompanying drawings. A brief description of the accompanying drawings is provided below. Attached Figure Description

[0014] This disclosure, its advantages, and the accompanying drawings will be better understood from the following description of representative embodiments, accompanied by the accompanying drawings. These drawings depict only representative embodiments and are therefore not intended to limit the scope of the various embodiments or the claims.

[0015] Figure 1 It is a block diagram of a computing system based on certain aspects of this disclosure.

[0016] Figure 2 Based on certain aspects of this disclosure, for Figure 1 A circuit diagram of a power supply circuit that powers one or more components of a computing system.

[0017] Figure 3 Based on certain voltage-to-time diagrams of this disclosure, it is shown that in the absence of clamping circuitry, Figure 2 The power supply circuit's power-off procedure.

[0018] Figure 4 Based on certain voltage-to-time diagrams of this disclosure, the presence of a clamping circuit is illustrated. Figure 2 The power supply circuit's power-off procedure.

[0019] [Symbol Explanation]

[0020] 10: Computing System

[0021] 12: Chassis

[0022] 14: Power Supply Unit

[0023] 16: Central Processing Unit (CPU)

[0024] 18: Graphics Processing Unit (GPU)

[0025] 20: Memory

[0026] 22: Hard Disk Drive (HDD)

[0027] 24: Solid State Drive (SSD)

[0028] 26: Motherboard

[0029] 28: Expansion Card

[0030] 30: Field Programmable Gate Array (FPGA)

[0031] 32: Complex Programmable Logic Device (CPLD)

[0032] 100: Power supply circuit

[0033] 101: Ground

[0034] 102: Input voltage source

[0035] 104A-104C: Input capacitors

[0036] 106A, 106B: Resistors

[0037] 110: Power Converter

[0038] 112A, 112B: Input pins

[0039] 114A, 114B: Output pins

[0040] 116: IC power supply pin

[0041] 118: Enable pin

[0042] 120: Voltage feedback pin

[0043] 122: Output Inductor

[0044] 124A-124D: Output capacitors

[0045] 126A, 126B: Feedback resistors

[0046] 128: Feedback capacitor

[0047] 130: Output node

[0048] 140: Clamping circuit

[0049] 142: Transistor

[0050] 144A: Base

[0051] 144B: Emitter

[0052] 144C: ​​Collector

[0053] 146: Capacitor

[0054] 148A, 148B: Resistors

[0055] 149: Voltage divider output

[0056] 150: Emitter end resistor

[0057] 152: Resistor

[0058] 200: Voltage versus time plot

[0059] 202: Input voltage

[0060] 214: Output voltage

[0061] 230: Output node voltage

[0062] 300: Voltage versus time graph

[0063] 302: Input voltage

[0064] 330: Output node voltage Detailed Implementation

[0065] Computing systems and computing devices, such as servers, typically include various components powered by a power supply unit (PSU). The PSU is configured to convert primary alternating current (AC) power into usable direct current (DC) power to power the various components. According to an embodiment of this disclosure, the PSU may include power supply circuitry that assists in powering the components of the computing system. The power supply circuitry includes a power converter to convert DC voltage and clamping circuitry to prevent the power converter from being unintentionally reactivated after being deactivated.

[0066] Various embodiments are described with reference to the accompanying drawings, in which similar reference numerals are used throughout the drawings to indicate similar or equivalent elements. The drawings are not necessarily drawn to scale and are provided only to illustrate the manner and features of this disclosure. The numerous specific details, relationships, and methods enumerated provide a full understanding of certain manner and features of this disclosure; however, those skilled in the art will recognize that these manner and features can be implemented without one or more specific details, with other relationships, or with other methods. In some instances, known structures or operations are not shown for illustrative purposes. The various embodiments disclosed herein are not necessarily limited to the order of the actions or events depicted, as some actions may occur in different orders and / or simultaneously with other actions or events. Furthermore, implementing certain manner and features of this disclosure does not necessarily require all the actions or events depicted.

[0067] This invention can be embodied in many different forms. Representative embodiments are shown in the accompanying drawings and will be described in detail herein. This disclosure is an example or illustration of the principles of the invention and is not intended to limit the broad scope of the disclosure to the illustrated embodiments. Elements and limitations disclosed therein, such as in the abstract, summary, and description paragraphs, but not expressly listed in the claims, should not be incorporated into the claims individually, collectively, impliedly, inferentially, or otherwise. For the purposes of this detailed description, the singular form includes the plural form unless specifically denied; and the word “comprising” means “unrestrictedly comprising”. Furthermore, terms indicating approximation, such as “about,” “almost,” “generally,” “probably,” and similar terms, can be used herein to mean “within,” “near,” “close to,” “within 3-5%,” or “within acceptable manufacturing tolerances,” or any logical combination thereof.

[0068] Figure 1 This is a block diagram of an exemplary computing system 10, which may be a server. The computing system 10 includes a chassis 12 containing a power supply unit 14 and various internal electronic components that assist in different functions and tasks. The electronic components may include a central processing unit (CPU) 16, a graphics processing unit (GPU) 18, one or more memory devices 20, one or more hard disk drives (HDDs) 22, one or more solid-state drives (SSDs) 24, a motherboard 26, one or more expansion cards 28, a field-programmable gate array (FPGA) 30, and a complex programmable logic device (CPLD) 32. The power supply unit 14 may include an internal power supply circuit 100 configured to generate voltages usable by any electronic component of the computing system 10 and to prevent the electronic components from falling into an undervoltage state. The power supply unit 14 may also include other components. For example, power supply unit 14 may include components for converting main AC voltage to DC voltage. In this way, power supply circuit 100 can be used as a DC-to-DC converter.

[0069] Figure 2The power supply circuit 100 of the power supply unit 14 is shown. In some implementations, the power supply unit 100 may operate as a switched-mode power supply. The power supply circuit 100 includes an input voltage source 102, a power converter 110, an output node 130, and a clamping circuit 140. In the illustrated implementation, the power converter 110 is an integrated circuit (IC) with several input and output pins. The power converter 110 includes input pins 112A and 112B, output pins 114A and 114B, an IC power supply pin 116, an enable pin 118, and a voltage feedback pin 120. The input voltage source 102 provides the input voltage and is electrically connected to input pins 112A and 112B, the IC power supply pin 116, and a set of input capacitors 104A, 104B, and 104C. Input capacitors 104A, 104B, and 104C are electrically connected in parallel. The first terminal of each of the input capacitors 104A, 104B, and 104C is electrically connected to the input voltage source 102. The second terminal of each of the input capacitors 104A, 104B, and 104C is electrically connected to ground 101. Input capacitors 104A, 104B, and 104C are used to eliminate spikes in the input voltage supplied by the input voltage source 102.

[0070] Input voltage source 102 is electrically connected to enable pin 118 via resistors 106A and 106B. Input voltage source 102 is electrically connected to the first terminal of resistor 106A. The second terminal of resistor 106A is electrically connected to the first terminal of resistor 106B and to enable pin 118. The second terminal of resistor 106B is electrically connected to ground 101. Input voltage source 102, resistors 106A and 106B act as a voltage divider. The voltage supplied to enable pin 118 is equal to the voltage drop across resistor 106B and is typically less than the input voltage supplied by input voltage source 102 due to at least the voltage drop across resistor 106A.

[0071] Clamping circuit 140 includes a bipolar junction transistor 142 with a base 144A, an emitter 144B, and a collector 144C. In some implementations, transistor 142 is an NPN bipolar junction transistor. In other implementations, transistor 142 is a PNP bipolar junction transistor. Clamping circuit 140 also includes a capacitor 146 and a voltage divider composed of resistors 148A and 148B. The first terminals of resistors 148A and 148B are electrically connected to each other to form a voltage divider with a voltage divider output 149. Voltage divider output 149 is electrically connected to the first terminal of capacitor 146 and the base 144A of transistor 142. The second terminal of capacitor 146 is electrically connected to ground 101. The second terminal of resistor 148B is electrically connected to the input voltage source 102. The second terminal of resistor 148B is electrically connected to ground 101. Clamping circuit 140 also includes an emitter-side resistor 150 electrically connected between the emitter 144B of transistor 142 and the input voltage source 102. In some implementations, resistor 152 having a resistance of approximately zero ohms (sometimes referred to as a "zero-ohm link") may be electrically connected between the emitter 144B and emitter-side resistor 150. In some implementations, resistor 152 may have a resistance between 0 ohms and approximately 50 milliohms. The collector 144C of transistor 142 is electrically connected to resistors 106A and 106B, and the enable pin 118 of power converter 110.

[0072] Power converter 110 is configured to generate an output voltage located at output node 130, which can be used to power electronic components. Power converter 110 includes output pins 114A and 114B, which follow the voltages of input pins 112A and 112B. Thus, the voltages supplied at output pins 114A and 114B are the same as the voltages supplied to input pins 112A and 112B by input voltage source 102. Power supply circuit 100 also includes an output inductor 122 and a set of output capacitors 124A, 124B, 124C, and 124D, which act as a low-pass filter to filter out any ripple or noise in the output voltage supplied at output pins 114A and 114B. Therefore, output inductor 122 is electrically connected to output pins 114A and 114B. Output capacitors 124A-124D are electrically connected in parallel. The first terminal of each of output capacitors 124A-124D is electrically connected to ground 101. The second terminal of each of output capacitors 124A-124D is electrically connected to both output inductor 122 and output node 130.

[0073] The power supply circuit also includes feedback resistors 126A and 126B, and a feedback capacitor 128. Feedback resistors 126A and 128 are electrically connected in parallel. The first terminals of feedback resistors 126A and 128 are electrically connected to each of the output inductors 122, output capacitors 124A-124D, and output node 130. The second terminals of feedback resistors 124A and 128 are electrically connected to the voltage feedback pin 120 and the first terminal of feedback resistor 126B. The second terminal of feedback resistor 126B is electrically connected to ground 101. The voltage at output node 130 is determined by the resistance of feedback resistors 126A and 126B and the voltage at voltage feedback pin 120. In some implementations, the voltage at voltage feedback pin 120 is approximately 6 volts, the resistance of feedback resistor 126A is approximately 56 kΩ, and the resistance of feedback resistor 126B is approximately 12.4 kΩ, so the voltage at output node 130 is approximately 3.309 volts.

[0074] In some cases, the input voltage provided by input voltage source 102 may be lower than that required to power the electronic components; this is called an undervoltage condition. An undervoltage condition can occur during the power-on or power-off procedures of power supply unit 100. An undervoltage condition can also occur during normal operation of power supply unit 100. Enable pin 118 acts as an on-off switch for power converter 110 and can be used to protect the electronic components during undervoltage conditions. If power supply circuit 100 continues to operate normally as the input voltage decreases, the voltage supplied to the electronic components located at output node 130 will also decrease. If the voltage supplied to the electronic components drops below the undervoltage threshold, the electronic components may be damaged.

[0075] Enable pin 118 can prevent undervoltage conditions from occurring during the initial startup of the power supply circuit 100 by enabling the power converter 110 only when the input voltage provided by the input voltage source 102 is sufficient to properly power the electronic components. Enable pin 118 will also disable the power converter 110 when the power supply circuit 100 is turned off and the input voltage provided by the input voltage source 102 decreases.

[0076] In the power supply circuit 100, the voltage supplied to the enable pin 118 is based on the input voltage provided by the input voltage source 102. When the input voltage is greater than or equal to the threshold input voltage, the voltage supplied to the enable pin 118 will be greater than or equal to the threshold enable voltage, thus enabling the power converter 110. When enabled, the power converter 110 converts the input voltage provided by the input voltage source 102 into an output voltage provided at output pins 114A and 114B. When the input voltage drops below the threshold input voltage, the voltage supplied to the enable pin 118 drops below the threshold enable voltage. The power converter 110 is then deactivated, resulting in no output voltage provided at output pins 114A and 114B. Thus, the enable pin 118 can be used to prevent the electronic components from being powered by the power supply circuit 100 when the input voltage provided by the input voltage source 102 begins to decrease.

[0077] Figure 3 If provided to enable pin 118 ( Figure 2 The voltage of ) is only supplied by the input voltage source 102 ( Figure 2 The input voltage provided determines the value. Figure 2Voltage-to-time diagram 200 of power supply circuit 100. Voltage-to-time diagram 200 shows the input voltage provided by input voltage source 102 during a power-down procedure, at output pins 114A and 114B. Figure 2 The output voltage 214 provided by ) and at the output node 130 ( Figure 2 The output node voltage provided is 230.

[0078] In region A of voltage-to-time graph 200, the input voltage 202 gradually begins to decrease, thus causing the output voltage 214 (at output pins 114A and 114B) and the output node voltage 230 (at output node 130) to gradually decrease. However, the input voltage 202 is high enough that the voltage supplied to enable pin 118 ( Figure 2 The voltage of the power converter 110 is maintained at or above the critical enable voltage. Figure 2 The power supply circuit 100 remains enabled. As the power supply circuit 100 operates as a switching power supply, the output voltage 214 provided by the output pins 114A and 114B continuously increases and decreases, resulting in a block-shaped output signal in region A of the voltage-time graph 200.

[0079] In region B of voltage-to-time graph 200, the input voltage 202 has decreased sufficiently that the voltage supplied to enable pin 118 is below the critical enable voltage, and power converter 110 is deactivated. When power converter 110 is deactivated, the output voltage 214 (at output pins 114A and 114B) and the output node voltage 230 (at output node 130) both begin to decrease more drastically than in region A of voltage-to-time graph 200.

[0080] However, as shown in region C of the voltage-to-time diagram 200, both the output voltage 214 (at output pins 114A and 114B) and the output node voltage 230 (at output node 130) can periodically spike upwards after the power converter 110 is deactivated. These spikes are caused by the input voltage 202, which has a small ripple component. When an alternating current (AC) voltage is converted to a direct current (DC) voltage, the resulting voltage often contains a DC component (e.g., a constant voltage) and a ripple component (e.g., a fluctuating voltage) superimposed on the DC component. Thus, the resulting voltage typically exhibits periodic variations, accompanied by a series of recurring voltage spikes. The ripple component of the input voltage 202 can cause the input voltage 202 to change periodically according to the ripple frequency (e.g., the frequency at which voltage spikes occur in the input voltage 202) and the ripple period (e.g., the time interval between adjacent voltage spikes in the input voltage 202). In some implementations, the ripple frequency is approximately 100 kHz, and the ripple period is therefore approximately 10 microseconds (μs). In other implementations, the ripple period is approximately greater than 0 microseconds and less than or equal to 10 microseconds, and the ripple period is therefore typically greater than or equal to approximately 100 kHz.

[0081] When the input voltage 202 initially decreases and causes the voltage supplied to the enable pin 118 to drop below the critical enable voltage, the power converter 110 is deactivated. However, the ripple component of the input voltage 202 can cause the input voltage to continuously change, thus causing the voltage supplied to the enable pin 118 to continuously change near the critical enable voltage. The power converter 110 will be continuously enabled and disabled, causing spikes in the output voltage 214 and the output node voltage 230, as shown in region C of the voltage-to-time diagram 200. Enable and disable may occur repeatedly until the DC component of the input voltage 202 decreases to a level that keeps the voltage supplied to the enable pin 118 below the critical enable voltage, regardless of any changes in the input voltage 202 caused by the ripple component.

[0082] Finally, in region D of the voltage-to-time graph 200, the DC component of the input voltage 202 has decreased sufficiently to maintain the voltage supplied to the enable pin 118 below the critical enable voltage, even when the ripple component causes the input voltage 202 to increase. The output voltage 214 (provided at output pins 114A and 114B) and the output node voltage 230 (provided at output node 130) will therefore remain at zero voltage, even with the presence of the ripple component of the input voltage 202.

[0083] Back Figure 2Clamping circuit 140 assists in preventing temporary voltage spikes caused by the ripple component of the input voltage. When the input voltage provided by input voltage source 102 increases to at least the critical input voltage, clamping circuit 140 activates power converter 110, so that the output voltage is provided to output pins 114A and 114B of power converter 110. In response to the input voltage decreasing below the adjacent input voltage, clamping circuit 140 deactivates power converter 110 and also prevents power converter 110 from being reactivated within a predetermined period. Generally, the ripple period of the input voltage is less than the predetermined period. Even if the input voltage temporarily increases to at least the critical input voltage due to the ripple component, the input voltage will subsequently decrease to below the critical input voltage within the predetermined period, and power converter 110 will not be activated. Thus, clamping circuit 140 prevents voltage spikes in the voltage at output pins 114A and 114B or output node 130. In some implementations, the ripple component, which is greater than or equal to the input voltage, causes the input voltage to rise above the adjacent input voltage and then drop back to the critical voltage within a predetermined time period, which is the amount of time required.

[0084] The transistor 142 of the clamping circuit 140 is configured to transition between an "on" state and an "off" state to enable and disable the power converter 110. When the input voltage provided by the input voltage source 102 is greater than or equal to the critical input voltage, the voltage supplied to the base of the transistor 142 by the voltage divider output 149 is greater than or equal to the turn-on voltage of the transistor 142. Thus, the transistor 142 is in the "on" state, and current can flow between the collector 144C and the emitter 144B. Resistor 106A and emitter resistor 150 are electrically connected in parallel between the input voltage source 102 and resistor 106B. Therefore, the voltage divider in the "on" state consists of resistor 106A, resistor 106B, and emitter resistor 150. The voltage divider in the "on" state has a voltage divider output 107 formed between (i) resistor 106A and emitter resistor 150 and (ii) resistor 106B. The voltage divider output 107 is electrically connected to the enable pin 118 of the power converter 110.

[0085] When the input voltage provided by input voltage source 102 is lower than the critical input voltage, the voltage supplied by voltage divider output 149 to the base 144A of transistor 142 is lower than the start-up voltage of transistor 142. Therefore, transistor 142 is in the "off" state, and current cannot flow between collector 144C and emitter 144B. Emitter-end resistor 150 is disconnected from resistors 106A and 106B, leaving only resistor 106A connected between input voltage source 102 and resistor 106B. Thus, the off-state voltage divider consists of resistors 106A and 106B. Voltage divider output 107 is still formed between resistors 106A and 106B and is electrically connected to the enable pin 118 of power converter 110. Therefore, the off-state voltage divider does not include emitter-end resistor 150, and the enable pin 118 is electrically connected to input voltage source 102 only through resistor 106A.

[0086] Therefore, the resistance values ​​of resistors 106A, 106B, 148A, 148B, and emitter resistor 150 are selected such that when the input voltage is lower than the critical input voltage, the voltage supplied to transistor 142 is lower than the startup voltage of transistor 142, and the voltage supplied to the enable pin 118 of power converter 110 is lower than the critical enable voltage. When the voltage supplied to the enable pin 118 of power converter 110 is lower than the critical enable voltage, the power converter is disabled.

[0087] The resistance values ​​of resistors 106A, 106B, 148A, 148B, and emitter resistor 150 are also selected such that when the input voltage is greater than or equal to the critical input voltage, the voltage supplied to transistor 142 is greater than or equal to the startup voltage of transistor 142, and the voltage supplied to the enable pin 118 of power converter 110 is greater than or equal to the critical enable voltage. When the voltage supplied to the enable pin 118 of power converter 110 is greater than or equal to the critical enable voltage, the power converter is enabled.

[0088] In some implementations, resistor 106A has a resistance of approximately 200 kΩ. In some implementations, resistor 106B has a resistance of approximately 120 kΩ. In some implementations, resistor 148A has a resistance of approximately 205 kΩ. In some implementations, resistor 148B has a resistance of approximately 205 kΩ. In some implementations, emitter-terminal resistor 150 has a resistance of approximately 10 kΩ.

[0089] When the input voltage provided by input voltage source 102 initially increases to at least the critical input voltage during the power-up procedure, the voltage supplied to the base 144A of transistor 142 is greater than or equal to the startup voltage of transistor 142, and transistor 142 transitions from the "off" state to the "on" state. Since the transistor is in the "on" state, the voltage supplied to the enable pin 118 by voltage divider 107 is determined by the resistance values ​​of resistors 106A, 106B, and emitter resistor 150 (e.g., the voltage divider in the on state).

[0090] When resistor 106A is electrically connected in parallel with emitter resistor 150, the combined resistance of resistor 106A and emitter resistor 150 is lower than that of resistor 106A alone. For example, in some implementations, the resistance of resistor 106A is approximately 200 kΩ, while the resistance of emitter resistor 150 is approximately 10 kΩ. Resistor 106A and emitter resistor 150 have a combined resistance of approximately 9.5 kΩ because they are electrically connected in parallel.

[0091] Therefore, the voltage drop across the combined resistor 106A and emitter resistor 150 in the open-state voltage divider is less than the voltage drop across only resistor 106A in the closed-state voltage divider. Consequently, the voltage drop across resistor 106B in the open-state voltage divider is greater than the voltage drop across resistor 106B in the closed-state voltage divider. Therefore, the voltage supplied to enable pin 118 by the open-state voltage divider is greater than the voltage supplied to enable pin 118 by the closed-state voltage divider. The voltage supplied to enable pin 118 by the open-state voltage divider is greater than or equal to the critical enable voltage, and therefore, when the open-state voltage divider is formed, the power converter 110 is enabled. In some implementations, the critical enable voltage is lower than the critical input voltage.

[0092] When transistor 142 is in the "on" state during the power-down procedure and the input voltage drops below the critical input voltage, transistor 142 transitions back to the "off" state. In the "off" state, current can no longer flow between the collector 144C and emitter 144B, so the emitter resistor 150 and resistor 106A are not electrically connected in parallel. The resistance of resistor 106A is greater than the combined resistance of resistor 106A and emitter resistor 150. Therefore, the voltage drop across resistor 106A is greater than the voltage drop across the combined resistance of resistor 106A and emitter resistor 150.

[0093] Therefore, the voltage drop across resistor 106B in the off-state voltage divider is less than the voltage drop across resistor 106B in the on-state voltage divider, and the voltage supplied to enable pin 118 by the off-state voltage divider is less than the voltage supplied to enable pin 118 by the on-state voltage divider. Since the voltage supplied to enable pin 118 by the off-state voltage divider is below the critical enable voltage, the power converter 110 is disabled.

[0094] Transistor 142 has a switching frequency, defining how quickly it transitions from an "off" state to an "on" state, and / or from an "on" state to an "off" state. For example, if transistor 142 can only transition between the "on" and "off" states once per second, then the switching frequency of transistor 142 is 1 Hertz. The switching frequency of transistor 142 is lower than the ripple frequency of the input voltage ripple component. Therefore, the time required for transistor 142 to transition between states is greater than the time during which the input voltage temporarily increases due to the input voltage ripple component (ripple period). In some implementations, the switching period is greater than or equal to about 1 millisecond, while the switching frequency is less than or equal to 1 kilohertz.

[0095] During the power-down procedure, once the input voltage drops below the critical input voltage and transistor 142 has transitioned to the "off" state, the switching frequency of transistor 142 prevents the ripple component of the input voltage from temporarily transitioning transistor 142 back to the "on" state and activating power converter 110. If the ripple component causes the input voltage to rise to at least the critical input voltage, the input voltage will remain at the critical voltage (or above the critical voltage) for a period equal to the ripple period. Then, the input voltage will drop back below the critical input voltage at the end of the ripple period. During the brief period when the input voltage is greater than or equal to the critical input voltage, the voltage applied to the base 144A of transistor 142 is greater than or equal to the startup voltage of transistor 142. However, because the switching frequency is lower than the ripple frequency (and the switching period is greater than the ripple period), transistor 142 cannot transition from the "off" state to the "on" state before the input voltage drops back below the critical input voltage. In this way, once transistor 142 transitions from the "on" state to the "off" state, if the input voltage briefly increases due to ripple components, transistor 142 remains in the "off" state because it cannot transition back to the "on" state quickly enough. Therefore, clamping circuit 140 prevents voltage surges (such as those caused by ripple components of the input voltage) from occurring on the output voltage (at output pins 114A and 114B) and the output node voltage (at output node 130). Figure 3 (as shown in the image).

[0096] Figure 4 exhibit Figure 2The voltage-to-time diagram 300 of the power supply circuit 100 illustrates the effect of the clamping circuit 140. The voltage-to-time diagram 300 shows the input voltage 302 provided by the input voltage source 102 during the power-down procedure, and the voltage at output node 130 (…). Figure 2 The output node voltage 330 provided by transistor 142. In region A of voltage-to-time plot 300, the input voltage 302 is approximately constant, and correspondingly, the output node voltage 330 is also approximately constant. In region B of voltage-to-time plot 300, the input voltage 302 begins to gradually decrease, but remains above the critical input voltage. The output node voltage 330 also begins to decrease in response to the decrease in input voltage 302. However, since the input voltage 302 is still above the critical input voltage, transistor 142 ( Figure 2 The input voltage 302 remains in the "on" state, keeping the power converter 110 active and generating the output node voltage 330. In region C of the voltage-to-time diagram 300, the input voltage drops to zero more quickly. As the input voltage 302 falls below the critical input voltage, transistor 142 transitions to the "off" state, and the power converter 110 is activated. Consequently, the output node voltage 330 also drops to zero. Due to the presence of clamping circuit 140, the output node voltage 330 does not experience any temporary voltage spikes due to the ripple component of the input voltage 302.

[0097] Although the invention has been illustrated and described with reference to one or more embodiments, equivalent alternatives and modifications will be conceived or known by those skilled in the art upon reading and understanding this specification and the accompanying drawings. Furthermore, while specific features of the invention may have been disclosed with reference to only one of several embodiments, such features may be combined with one or more other features of other embodiments where necessary or advantageous for any given particular application.

[0098] While various embodiments of the invention have been described above, it should be understood that these embodiments are presented as examples only and not as limitations. Even though the invention has been illustrated and described with reference to one or more embodiments, equivalent substitutions and modifications will be conceived or known by those skilled in the art upon reading and understanding this specification and the accompanying drawings. Furthermore, while a particular feature of the invention may be disclosed only in one of several embodiments, such feature may be combined with one or more other features of other embodiments, which may be desirable or advantageous for any given or particular application. Therefore, the breadth and scope of the invention should not be limited to any of the embodiments described above. Rather, the scope of the invention should be defined by the claims and their equivalents.

Claims

1. A power supply circuit, comprising: The power converter has input pins, output pins, and enable pins; An input voltage source is electrically connected to the input pin of the power converter, and the input voltage source is configured to provide an input voltage; as well as The clamping circuit is electrically connected to the enable pin of the power converter, wherein: In response to the input voltage rising to at least a threshold input voltage, the clamping circuit enables the power converter to provide an output voltage at the output pin, and In response to the input voltage dropping below the critical input voltage, the clamping circuit disables the power converter and prevents the power converter from being reactivated within a predetermined period of time. The input voltage contains a ripple component, which causes the input voltage to vary periodically. This periodic variation has a ripple frequency and a ripple period. The clamping circuit includes a transistor electrically connected to the input voltage source and the enable pin of the power converter. The transistor is configured to transition between an "on" state and an "off" state to enable and disable the power converter. The transistor has a switching frequency that defines the time required for the transistor to transition from the "on" state to the "off" state, and the switching frequency is lower than the ripple frequency of the ripple component of the input voltage.

2. The power supply circuit of claim 1, wherein in response to the input voltage initially dropping below the critical input voltage due to the ripple component and then increasing to at least the critical input voltage, the clamping circuit prevents the power converter from being reactivated; and The ripple period is less than the predetermined time period, causing the ripple component to raise the input voltage to at least the critical input voltage within the predetermined time period, and then lower it below the critical input voltage.

3. The power supply circuit of claim 1, wherein the transistor transitions from the "off" state to the "on" state in response to the input voltage increasing to at least the critical input voltage.

4. The power supply circuit of claim 3, wherein in response to the input voltage increasing to at least the critical input voltage and the transistor transitioning to the "on" state, the transistor generates a threshold enable voltage to be provided to the enable pin of the power converter; and Where the critical enable voltage is lower than the critical input voltage; In response to the input voltage dropping below the critical input voltage, the transistor transitions from the "on" state to the "off" state, such that the voltage supplied to the enable pin of the power converter is lower than the critical enable voltage.

5. The power supply circuit as described in claim 1, In response to the input voltage initially increasing to at least the critical input voltage, the transistor transitions to the "on" state to enable the power converter; and In response to the input voltage subsequently dropping below the critical input voltage, the transistor transitions to an "off" state to disable the power converter; and The ripple component of the input voltage, in response to the input voltage, causes the input voltage to (i) rise to at least the critical input voltage within the predetermined time period, and then (ii) fall below the critical input voltage, while the transistor remains in the "off" state; and Wherein, after the ripple component of the input voltage causes the input voltage to rise to at least the critical input voltage, the ripple component of the input voltage causes the input voltage to subsequently decrease to below the critical input voltage after a first time period; and In response to the input voltage increasing to at least the critical input voltage, the transistor is configured to transition to the "on" state only after a second time period, which is longer than the first time period, such that the input voltage increases to at least the critical input voltage in response to the ripple component of the input voltage, and the transistor does not transition to the "on" state until the input voltage decreases below the critical input voltage due to the ripple component of the input voltage.

6. The power supply circuit of claim 1, wherein the transistor includes a base, an emitter, and a collector, the base being electrically connected to the input voltage source, the emitter being electrically connected to the input voltage source via an emitter-side resistor, and the collector being electrically connected to the enable pin of the power converter; and When the input voltage is greater than or equal to the critical input voltage, the voltage supplied to the base of the transistor is greater than or equal to the transistor's start-up voltage, such that the on-state voltage divider, composed of the emitter resistor, provides a voltage greater than or equal to the critical enable voltage to the enable pin of the power converter. When the input voltage is lower than the critical input voltage, the voltage supplied to the base of the transistor is lower than the transistor's startup voltage, causing the off-state voltage divider to exclude the emitter resistor. The off-state voltage divider provides a voltage lower than the critical enable voltage to the enable pin of the power converter. The on-state voltage divider includes the emitter resistor and an additional resistor, which are electrically connected in parallel between the input voltage source and the enable pin; and The off-state voltage divider contains only the additional resistor, which is electrically connected between the input voltage source and the enable pin.

7. A power supply circuit, comprising: The power converter has input pins, output pins, and enable pins; An input voltage source is configured to provide an input voltage to this input pin of the power converter; A first resistor is electrically connected to the input voltage source and the enable pin of the power converter, such that the input voltage source is electrically connected to the enable pin of the power converter through at least the first resistor. A second resistor is electrically connected to the first resistor and the enable pin of the power converter; and A clamping circuit, electrically connected to the enable pin of the power converter, the clamping circuit comprising: A transistor having a base, an emitter, and a collector, the base being electrically connected to the input voltage source and the collector being electrically connected to the enable pin of the power converter; and An emitter-terminal resistor is electrically connected between the emitter and the input voltage source, wherein: In response to the input voltage increasing to at least a critical input voltage, an on-state voltage divider, consisting of the first resistor, the second resistor, and the emitter resistor, enables the power converter and provides an output voltage at the output pin. as well as In response to the input voltage dropping below the critical input voltage, the off-state voltage divider, consisting of the first resistor and the second resistor, disables the power converter and prevents the power converter from being reactivated within a predetermined period of time.

8. A computing system, comprising: chassis; One or more electronic components are configured within the housing, and A power supply circuit, disposed within the housing, is configured to assist in supplying power to one or more electronic components, the power supply circuit comprising: The power converter has input pins, output pins, and enable pins; An input voltage source, electrically connected to the power converter, is configured to provide an input voltage; as well as The clamping circuit is electrically connected to the enable pin of the power converter, wherein: In response to the input voltage increasing to at least a critical input voltage, the clamping circuit enables the power converter to provide an output voltage at the output pin, and In response to the input voltage dropping below the critical input voltage, the clamping circuit disables the power converter and prevents the power converter from being reactivated within a predetermined period of time. The input voltage contains a ripple component, which causes the input voltage to vary periodically. This periodic variation has a ripple frequency and a ripple period. The clamping circuit includes a transistor electrically connected to the input voltage source and the enable pin of the power converter. The transistor is configured to transition between an "on" state and an "off" state to enable and disable the power converter. The transistor has a switching frequency that defines the time required for the transistor to transition from the "on" state to the "off" state, and the switching frequency is lower than the ripple frequency of the ripple component of the input voltage.

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