Method and storage device to improve nand flash performance for dense read workloads

Abstract

A method for reading data in a storage device is provided. The method includes receiving a read command from a host device, wherein the read command indicates stored data in the storage device and a logical block address (LBA) of the stored data; obtaining a physical block number (PBN) based on the LBA and a logical-to-physical (L2P) mapping; determining whether the PBN corresponds to a volatile memory of the storage device; reading the stored data directly from the volatile memory based on the PBN corresponding to the volatile memory; incrementing a read counter associated with the PBN based on the stored data read directly from the volatile memory; and reading the stored data from a non-volatile memory of the storage device based on the PBN not corresponding to the volatile memory.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Indian Patent Application No. 202141017782, filed on April 16, 2021, with the Indian Patent, Design and Trademark Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The methods, apparatus, and systems consistent with the example embodiments relate to solid-state drives (SSDs), and more specifically, to methods and storage devices for improving the performance of NOT AND (NAND) flash memory for intensive read workloads on storage devices. Background Technology

[0004] NAND flash memory typically uses a non-volatile storage method that does not require power to store data. For example, mobile phones include NAND flash memory (e.g., micro SD cards / memory chips) to store data files such as photos, videos, and music, which remain stored even when the NAND flash memory is powered off. NAND flash memory consists of multiple flash blocks that store / save / write data. Once data is written to NAND flash memory, it can be exposed to various physical disturbances, such as temperature variations and interference caused by read-intensive workloads. Due to these disturbances, data stored on NAND flash memory may be corrupted. Furthermore, intensive read workloads can impact performance. In this regard, storage devices with error correction codes and improved performance during intensive read workloads are needed. Summary of the Invention

[0005] One or more example embodiments provide a method and storage device for improving NAND flash memory performance during intensive read workloads. When read interference (e.g., RR errors) occurs on a flash block of NAND flash memory and exceeds the maximum read limit of the flash block of NAND flash memory, one or more example embodiments use volatile memory of the storage device to avoid data loss (e.g., UECC) during intensive read workloads on the storage device.

[0006] When read interference occurs on a NAND flash block and exceeds the maximum read limit of the NAND flash block, one or more example embodiments allocate buffers in volatile memory to improve NAND flash performance to accommodate intensive read workloads without additional restrictions on read commands received from the host device.

[0007] When recovery operations are performed on NAND flash memory blocks, one or more example embodiments optimize the read performance of the storage device to avoid data loss.

[0008] According to one aspect of an example embodiment, a method for reading data from a storage device includes: receiving a read command from a host device, wherein the read command includes a logical block address (LBA) of stored data to be read; obtaining a physical block number (PBN) by the storage device based on the LBA and a logical-to-physical (L2P) mapping; determining whether the PBN corresponds to volatile memory of the storage device; directly reading the stored data from the volatile memory based on the PBN corresponding to the volatile memory; incrementing a read counter associated with the PBN based on the stored data directly read from the volatile memory; and reading the stored data from non-volatile memory of the storage device based on the PBN not corresponding to the volatile memory.

[0009] According to one aspect of an example embodiment, a storage device includes: a memory; a non-volatile memory; and a storage device controller. The storage device controller is operatively connected to the volatile memory and the non-volatile memory, and is configured to: receive a read command from a host device, wherein the read command includes a logical block address (LBA) of stored data to be read; obtain a physical block number (PBN) based on the LBA and a logical-to-physical (L2P) mapping; determine whether the PBN corresponds to the volatile memory; read the stored data directly from the volatile memory based on the PBN corresponding to the volatile memory; increment a read counter associated with the PBN based on the stored data read directly from the volatile memory; and read the stored data from the non-volatile memory based on a PBN that does not correspond to the volatile memory.

[0010] According to one aspect of an example embodiment, a storage device controller includes: at least one processor configured to: receive a read command from a host device, wherein the read command includes a logical block address (LBA) of stored data to be read; obtain a physical block number (PBN) based on the LBA and a logical-to-physical (L2P) mapping; determine whether the PBN corresponds to volatile memory of the storage device; read stored data directly from the volatile memory based on the PBN corresponding to the volatile memory; increment a read counter associated with the PBN based on the stored data read directly from the volatile memory; and read stored data from non-volatile memory of the storage device based on a PBN not corresponding to the volatile memory. Attached Figure Description

[0011] The above and other aspects, features, and advantages will become more apparent from the following description of exemplary embodiments with reference to the accompanying drawings, in which:

[0012] Figure 1A block diagram of an error correction system for storing data in NAND flash memory is shown.

[0013] Figure 2 This is a flowchart illustrating a GC system for relocating old data in NAND flash memory.

[0014] Figure 3 A NAND flash memory system according to an example embodiment is shown.

[0015] Figure 4A and 4B A flowchart of a method for reading data from NAND flash memory according to an example embodiment is shown.

[0016] Figure 5 This is a block diagram of a host storage system according to an example embodiment. Detailed Implementation

[0017] The exemplary embodiments and their various features and advantages are explained more fully with reference to the accompanying drawings. Descriptions of well-known components and processing techniques are omitted to avoid unnecessarily obscuring the exemplary embodiments disclosed herein. Furthermore, the exemplary embodiments described herein are not necessarily mutually exclusive, as some exemplary embodiments can be combined with one or more other exemplary embodiments to form new embodiments. Unless otherwise stated, the term "or" as used herein means non-exclusive or. The examples used herein are intended only to aid in understanding how the exemplary embodiments are implemented and to further enable those skilled in the art to implement the exemplary embodiments. Therefore, the examples should not be construed as limiting the scope of the exemplary embodiments herein.

[0018] As is customary in the art, exemplary embodiments may be described and illustrated in blocks that perform the functions described herein. These blocks (which may be referred to herein as units or modules, etc.) are physically implemented by analog or digital circuitry (such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuitry, etc.) and may optionally be driven by firmware. For example, these circuits may be implemented in one or more semiconductor chips or on a substrate support such as a printed circuit board. The circuitry constituting a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmable microprocessors and associated circuitry), or by a combination of dedicated hardware to perform some functions of the block and a processor to perform other functions of the block. Each block may be physically separated into two or more interacting and discrete blocks without departing from the scope of the invention. Similarly, these blocks may be physically combined into more complex blocks without departing from the scope of the invention.

[0019] The accompanying drawings are provided to provide an overview of the technical features, and it should be understood that the exemplary embodiments are not limited to the drawings. Therefore, the invention should be construed as extending to any modifications, equivalents, and substitutions other than those specifically listed in the drawings. Although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are generally used only to distinguish one element from another.

[0020] Figure 1 A block diagram of an error correction system for storing data in NAND flash memory S1d is shown. Data S1a is stored / written on NAND flash memory S1d using an encoding process S1c for error correction code (ECC) and parity bits S1b (e.g., redundant bits). The stored data is read from NAND flash memory S1d using a decoding process S1e for ECC. The output S1f of the decoding process S1e for ECC indicates one of the following:

[0021] i. Uncorrectable ECC (UECC). The stored data is corrupted, and the ECC decoding process S1e cannot correct the stored data from the NAND flash memory S1d (i.e., obtain the original data).

[0022] ii. Read Reclaim (RR) error. The ECC decoding process S1e determines that the stored data is safe, but the data stored in the NAND flash memory S1d needs to be relocated to another flash block of the NAND flash memory S1d.

[0023] iii. Data recovery successful. The stored data was successfully recovered through ECC decoding process S1e.

[0024] Furthermore, NAND flash S1d has specific characteristics, such as not supporting overwrite attributes on flash blocks. Due to these characteristics, once a flash block is filled with data (old data / old block), new data may be written to the filled flash block after the old data is erased from the filled flash block. Each flash block in NAND flash S1d has an "erase count (EC)". If the EC of a flash block exceeds the maximum read limit of NAND flash S1d, NAND flash S1d will give an error when reading old data. Therefore, NAND flash S1d attempts to maintain a uniform EC count by repositioning the old data in NAND flash S1d (e.g., RR).

[0025] Figure 2This is a flowchart of a GC system for relocating old data in NAND flash memory. In S202, a read command is received from the host device to read stored data from the storage device; this read command includes a logical block address (LBA). In S204, a physical block number (PBN) is obtained from the LBA using a logical-to-physical (L2P) mapping. In S206, the stored data is read from the NAND flash memory of the storage device. In S208, it is determined whether a read interference (i.e., RR) has occurred while reading the stored data and whether the read threshold counter on the PBN has exceeded the maximum read limit. The maximum read limit is provided by the NAND flash memory manufacturer. In S210, if no read interference has occurred while reading the stored data and the read threshold counter on the PBN has not exceeded the maximum read limit, the read data is provided to the host device. In S212, if a read interference has occurred while reading the stored data or the read threshold counter on the PBN has exceeded the maximum read limit, the GC system is triggered for RR. Once triggered, the GC system begins relocating old data in the NAND flash memory.

[0026] During the relocation of old data in NAND flash memory, if a read command is received again from the host device on the same PBN (host read), the host read is given higher priority than the GC read used for relocation. This can create UECC when the read count (EC) on the PBN exceeds the maximum read limit after RR. As a result, an RR error occurs, the stored data is corrupted, and the ECC decoding process cannot correct the stored data / retrieve the original data from the NAND flash memory. RR errors increase with the flash block size, and this occurs every time a new version of NAND flash memory is released. Each version may require more time to complete one of the GC read operations. In this situation, the flash block that receives the RR error is likely to receive a read command again from the host device, and the read count (EC) on the PBN will exceed the maximum read limit after the RR, leading to data corruption (UECC). Therefore, it is hoped that a useful alternative can be provided to improve the performance of NAND flash memory for intensive read workloads.

[0027] Figure 3 A NAND flash memory system according to an example embodiment is shown.

[0028] refer to Figure 3In an example embodiment, the host storage system 10 includes a host device 100 and a storage device 200. The host device 100 may include, for example, a smartphone, a laptop, or a smart TV. The example embodiment is not limited to these specific devices, and the host device 100 may include other devices. The storage device 200 may include, for example, an SSD, a microSD card, or flash memory. The example embodiment is not limited to these specific devices, and the storage device 200 may include other devices. The host device 100 and the storage device 200 communicate with each other using interfaces and corresponding interface protocols (such as Serial Advanced Technology Attachment (SATA), Serial Attached SCSI (SAS), and Non-Volatile Memory Express (NVME)). The example embodiment is not limited to these specific interfaces and interface protocols, and other interfaces and interface protocols may be used.

[0029] In an example embodiment, storage device 200 includes storage device controller 202, volatile memory 204, and non-volatile memory 206. Storage device controller 202 is implemented by processing circuitry such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuitry, passive electronic components, active electronic components, optical components, hardwired circuitry, etc., and may be driven, for example, by firmware. For instance, this circuitry may be embodied in one or more semiconductor chips, or on one or more substrate supports (such as printed circuit boards).

[0030] Storage device controller 202 is configured to receive read commands from host device 100 to read data stored in storage device 200. The read command includes the LBA of the stored data. The LBA has a logical address ranging from a minimum LBA (e.g., 0) to a maximum LBA. The maximum LBA depends on the storage capacity of storage device 200 (e.g., 512 bytes for a 512kb storage device). The interface protocol may have an option to configure the logical address based on a request from host device 100. Furthermore, storage device controller 202 is configured to obtain the PBN from the LBA using L2P mapping. Additionally, storage device controller 202 is configured to determine whether the PBN corresponds to the volatile memory 204 of storage device 200. If the logical block address (LBA) of the stored data is mapped to a physical block number (PBN) in the volatile memory, then the LBA and PBN correspond to the volatile memory 204 of storage device 200. Furthermore, the storage device controller 202 is configured to directly read stored data from the volatile memory 204 in response to determining that the PBN corresponds to the volatile memory 204, and to increment a read counter associated with the PBN while reading the stored data. Additionally, the storage device controller 202 is configured to read stored data from the non-volatile memory 206 of the storage device 200 in response to determining that the PBN does not correspond to the volatile memory 204.

[0031] Furthermore, the storage device controller 202 is configured to determine whether read interference exceeds a threshold limit when reading stored data from non-volatile memory 206. Additionally, the storage device controller 202 is configured to read stored data from non-volatile memory 206 in response to determining that read interference does not exceed a threshold limit when reading stored data from non-volatile memory 206, and that the read threshold counter on the PBN does not exceed the maximum read limit. Furthermore, the storage device controller 202 is configured to allocate a buffer in volatile memory 204 in response to determining that read interference exceeds a threshold limit when reading stored data from non-volatile memory 206.

[0032] Storage device controller 202 is configured to determine whether the allocation of the buffer in volatile memory 204 was successful. Furthermore, storage device controller 202 is configured to, in response to determining that the allocation of the buffer in volatile memory 204 was successful, relocate the stored data from non-volatile memory 206 to volatile memory 204, update the L2P mapping, and read the stored data from volatile memory 204.

[0033] In addition, the storage device controller 202 is configured to relocate data from the volatile memory 204 to the non-volatile memory 206 in response to determining that buffer allocation in the volatile memory 204 has failed.

[0034] The data includes the low read counter among multiple read counters of the volatile memory 204. For example, the count could indicate the maximum PBN data that can be stored in the volatile memory. For example, the count of the maximum PBN data could be N, and there could be a structure that stores the key as a PBN (whose data is located in the i-th element of N elements) and a read counter corresponding to each entry. When all N entries are occupied and there is an pending request to allocate the (N+1)-th entry, the entry with the lowest read counter will be replaced with a new allocation (similar to Least Recently Used (LRU)).

[0035] Furthermore, the storage device controller 202 is configured to determine the buffer in volatile memory 204 with the lowest read counter. Additionally, the storage device controller 202 is configured to allocate single-cell (SLC) NAND flash memory in non-volatile memory 206 to store data. Furthermore, the storage device controller 202 is configured to relocate data in the SLC NAND flash memory and update the PBN associated with that data. The storage device controller 202 then attempts to allocate a buffer in the volatile memory.

[0036] In an example embodiment, the storage device controller 202 includes a host interface module 202a, a volatile media interface 202b, a non-volatile memory interface module 202c, a control module (CPU) 202d, and an error control module 202e.

[0037] Host interface module 202a receives commands (e.g., read commands, write commands) from host device 100 to perform specific tasks (e.g., read, write, etc.) associated with storage device 200. Volatile media interface 202b is configured to communicate with volatile memory 204. Non-volatile memory interface module 202c is configured to communicate with non-volatile memory 206. CPU 202d may include firmware that controls hardware interactions (i.e., 202a, 202b, 202c within storage device 200) according to requests issued by host device 100. CPU 202d is configured to execute instructions stored in storage device 200 and perform various processes. CPU 202d may include one or more processors, which may be a general-purpose processor (AP) such as an application processor, a graphics processing unit only (such as a graphics processing unit (GPU)), a vision processing unit (VPU), and / or an artificial intelligence (AI) dedicated processor (such as a neural processing unit (NPU)).

[0038] Error control module 202e controls error correction of data within flash memory storage (i.e., non-volatile memory 206 / NAND flash 206). Data can be stored / written to NAND flash 206 using parity bits through ECC encoding processing, and stored data can be read from NAND flash 206 using ECC decoding processing.

[0039] For example, host interface module 202a can receive write commands / captures / requests from host device 100 to store data (host data). In response to receiving a write request, host interface module 202a sends the write request to volatile memory 204 via volatile media interface 202b and stores the data in volatile memory 204. When storage device controller 202 accumulates a minimum unit of data value for NAND flash memory 206, storage device controller 202e refreshes the data from volatile memory 204 to NAND flash memory 206 via encoder 202ea. Encoder 202ea adds an error correction mechanism to the data using some additional data (such as parity bits). Parity bits define the maximum correction capacity. For example, parity bits define the maximum number of bits used for correction. Decoder 202eb removes the additional bits when reading back the data.

[0040] In addition to write cache, volatile memory 204 is also used to store information about metadata, such as mapping tables / L2P mappings. The mapping tables store logical-to-physical mapping information for all LBAs in storage device 200.

[0041] although Figure 3 Various hardware components of storage device 200 are illustrated, but it should be understood that the example embodiments are not limited thereto. In other example embodiments, storage device 200 may include fewer or more components. Furthermore, the labels and names of the components are for illustrative purposes only and do not limit the scope of the example embodiments. One or more components may be combined together to perform the same or substantially similar functions to improve the reliability of NAND flash memory 206 for intensive read workloads.

[0042] Figure 4A and 4B A flowchart S400 illustrates a method for reading data from NAND flash memory according to an example embodiment. For example, operations S402-S426 may be performed by the storage device controller 202.

[0043] In S402, a read command is received from the host device 100 to read data stored in the storage device 200. The read command includes the LBA of the stored data. In S404, the PBN is obtained from the LBA using L2P mapping. In S406, it is determined whether the PBN corresponds to the volatile memory 204 of the storage device 200. In S408, in response to determining that the PBN corresponds to the volatile memory 204, the stored data is read directly from the volatile memory 204, and the read counter associated with the PBN is incremented.

[0044] In S410, in response to determining that the PBN does not correspond to the volatile memory 204, stored data is read from the non-volatile memory 206 of the storage device 200. In S412, it is determined whether read interference exceeds a threshold limit when reading stored data from the non-volatile memory 206. The threshold limit defines the maximum correction capacity. For example, the threshold limit defines the maximum number of bits used for parity correction. The determination of whether read interference exceeds the correction capacity is based on the threshold limit. If read interference exceeds the threshold limit, the read threshold counter associated with the PBN also crosses the maximum read limit.

[0045] In S414, in response to determining that read interference does not exceed a threshold limit, stored data is read from non-volatile memory 206, and the read threshold counter on PBN does not cross the maximum read limit. In S416, in response to determining that read interference exceeds a threshold limit when reading stored data from non-volatile memory 206, a buffer in volatile memory 204 is allocated. In S418, it is determined whether the allocation of the buffer in volatile memory 204 was successful.

[0046] In S420a, in response to the determination that the buffer allocation in volatile memory 204 was successful, the stored data is relocated from non-volatile memory 206 to volatile memory 204. In S422a, the L2P mapping in storage device 200 is updated. In S424a, the stored data is read from volatile memory 204. In S426, the read data is provided to host device 100.

[0047] In S420b, in response to the determination that the allocation of a buffer in volatile memory 204 was unsuccessful, the buffer in volatile memory 204 with the lowest read counter is identified. In S422b, SLC NAND flash memory in non-volatile memory 206 is allocated to store data. In S424b, the data is repositioned in the SLC NAND flash memory, and the PBN associated with the data is updated. This data includes the low read counter among the multiple read counters of volatile memory 204. Thereafter, S416 is executed again, and the buffer in volatile memory is allocated.

[0048] Figure 5 This is a detailed block diagram of a host storage system 10 according to an example embodiment.

[0049] The host storage system 10 may include a host device 100 and a storage device 200. Furthermore, the storage device 200 may include a storage device controller 202, volatile memory 204, and non-volatile memory 206. According to an example embodiment, the host device 100 may include a host controller 110 and host memory 120. The host memory 120 may be used as a buffer memory and is configured to temporarily store data to be sent to or received from the storage device 200.

[0050] Storage device 200 may include a storage medium configured to store data in response to a request from host device 100. For example, storage device 200 may include at least one of an SSD, embedded memory, and removable external storage. When storage device 200 is an SSD, it may be an NVMe compliant device. When storage device 200 is embedded memory or external storage, it may be a UFS or eMMC compliant device. Each of host device 100 and storage device 200 may generate and send packets according to a standard protocol adopted.

[0051] When the non-volatile memory 206 of storage device 200 includes flash memory, the flash memory may include a 5D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, storage device 200 may include a variety of other types of non-volatile memory. For example, storage device 200 may include magnetic RAM (MRAM), spin-transfer torque MRAM, conductive bridged RAM (CBRAM), ferroelectric RAM (FRAM), PRAM, RRAM, and various other types of memory.

[0052] According to example embodiments, host controller 110 and host memory 120 may be implemented as separate semiconductor chips. Alternatively, in some example embodiments, host controller 110 and host memory 120 may be integrated into the same semiconductor chip. For example, host controller 110 may be any one of multiple modules included in an application processor (AP). The AP may be implemented as a system-on-a-chip (SoC). Furthermore, host memory 120 may be embedded memory included in the AP or an NVM or memory module located outside the AP.

[0053] The host controller 110 can manage operations that store data in the buffer of the host memory 120 in the non-volatile memory 206 (e.g., write data) or operations that store data in the buffer of the non-volatile memory 206 (e.g., read data).

[0054] Storage device controller 202 may include a host interface module 202a, a volatile media interface 202b, a non-volatile memory interface module 202c, and a control module 202d. Furthermore, storage device controller 202 may also include a flash translation layer (FTL) 214, a packet manager 215, a buffer memory 216, an error control module 202e, and an Advanced Encryption Standard (AES) engine 218. Buffer memory 216 may include a write buffer 202g and a read buffer 202f. Storage device controller 202 may also include working memory that loads the FTL 214. Control module 202d executes the FTL 214 to control data write and read operations on NVM 206.

[0055] Host interface module 202a can send and receive packets to and from host device 100. Packets sent from host device 100 to host interface module 202a may include commands or data to be written to non-volatile memory 206. Packets sent from host interface module 202a to host device 100 may include responses to commands or data read from non-volatile memory 206. Volatile media interface 202b can send data to be written to volatile memory 204 or receive data read from volatile memory 204. Memory interface 202c can send data to be written to non-volatile memory 206 or receive data read from non-volatile memory 206. Memory interface 202c can be configured to conform to standard protocols, such as switching or opening the NAND flash interface (ONFI).

[0056] FTL 214 can perform various functions, such as address mapping operations, wear leveling operations, and garbage collection operations. Address mapping operations can be operations that translate logical addresses received from host device 100 into physical addresses used to actually store data in non-volatile memory 206. Wear leveling operations can be techniques that prevent excessive degradation of specific blocks by allowing uniform use of blocks in non-volatile memory 206. For example, wear leveling operations can be implemented using firmware techniques that balance the erase counts of physical blocks. Garbage collection operations can be techniques that ensure available capacity in non-volatile memory 206 by erasing existing blocks after copying valid data from existing blocks to new blocks.

[0057] The packet manager 215 can generate packets according to the interface protocol of the host device 100, or parse various types of information from packets received from the host device 100. Furthermore, the buffer memory 216 can temporarily store data to be written to or read from the non-volatile memory 206. Although the buffer memory 216 may be a component included in the storage device controller 202, it can also be located outside the storage device controller 202.

[0058] Error control module 202e can perform error detection and correction operations on read data read from non-volatile memory 206. More specifically, error control module 202e can generate parity bits for write data to be written to non-volatile memory 206, and the generated parity bits can be stored in non-volatile memory 206 together with the write data. During data reading from non-volatile memory 206, error control module 202e can correct errors in the read data by using the parity bits read from non-volatile memory 206 and the read data, and output error-corrected read data.

[0059] The AES engine 218 can perform at least one of encryption and decryption operations on the data input to the storage device controller 202 using a symmetric key algorithm.

[0060] The example embodiments disclosed herein can be implemented using at least one hardware device and by performing network management functions to control these elements.

[0061] Although exemplary embodiments have been shown and described above, modifications and variations will be apparent to those skilled in the art without departing from the scope of the inventive concept as defined in the appended claims.

Claims

1. A method for reading data from a storage device, the method comprising: The storage device receives a read command from the host device, wherein the read command includes the logical block address (LBA) of the stored data to be read; The physical block number (PBN) is obtained by the storage device based on the LBA and logical-to-physical L2P mapping; The storage device determines whether the PBN corresponds to the volatile memory of the storage device; The storage device reads the stored data directly from the volatile memory based on the PBN corresponding to the volatile memory; The storage device increments the read counter associated with the PBN based on the stored data read directly from the volatile memory; The storage device reads stored data from the non-volatile memory of the storage device based on a PBN that does not correspond to the volatile memory; When reading stored data from the non-volatile memory, the storage device determines whether the read interference exceeds a threshold limit; When stored data is read from the non-volatile memory, the storage device reads the stored data from the non-volatile memory based on the read interference not exceeding the threshold limit; as well as When stored data is read from the non-volatile memory, the storage device allocates a buffer in the volatile memory based on the read interference exceeding the threshold limit; The buffer allocated in the volatile memory further includes: The storage device determines whether the buffer in the volatile memory has been successfully allocated. If the allocation of the buffer in the volatile memory fails, the data is relocated from the volatile memory to the non-volatile memory, wherein the relocated data includes the lowest read counter among the plurality of read counters of the volatile memory.

2. The method as described in claim 1, wherein, The stored data includes parity bits, and The threshold limit is the maximum number of bits used for parity correction.

3. The method as described in claim 1, wherein, The buffers allocated in the volatile memory also include: If the storage device successfully allocates the buffer in the volatile memory, the stored data is relocated from the non-volatile memory to the volatile memory. Based on the stored data being relocated to the volatile memory, the L2P mapping is updated; and Read the stored data from the volatile memory.

4. The method of claim 3, wherein, Relocating data from the volatile memory to the non-volatile memory includes: The buffer is identified by the storage device based on the buffer corresponding to the lowest read counter in the volatile memory; The storage device allocates single-cell SLC NAND flash memory blocks in the non-volatile memory to store data; The data in the SLC NAND flash memory is relocated by the storage device; and Update the PBN associated with the data to indicate the SLC NAND flash memory block.

5. The method of claim 1, further comprising: When stored data is read from the non-volatile memory, the storage device determines whether the read threshold counter associated with the PBN exceeds the maximum read limit; When stored data is read from the non-volatile memory, the storage device reads the stored data from the non-volatile memory based on the read threshold counter associated with the PBN not exceeding the maximum read limit; as well as When stored data is read from the non-volatile memory, the storage device allocates a buffer in the volatile memory based on the read threshold counter associated with the PBN exceeding the maximum read limit.

6. The method of claim 1, wherein, The L2P mapping indicates the actual physical location of each LBA in the storage device.

7. A storage device, comprising: Volatile memory; Non-volatile memory; as well as A storage device controller, operably connected to the volatile memory and the non-volatile memory, is configured to: Receive a read command from the host device, wherein the read command includes the logical block address (LBA) of the stored data to be read; The physical block number (PBN) is obtained based on the LBA and logical-to-physical L2P mapping. Determine whether the PBN corresponds to the volatile memory of the storage device; Based on the PBN corresponding to the volatile memory, the stored data is read directly from the volatile memory; Based on the stored data read directly from the volatile memory, increment the read counter associated with the PBN; Based on the PBN that does not correspond to the volatile memory, the stored data is read from the non-volatile memory of the storage device; When reading stored data from the non-volatile memory, determine whether the read interference exceeds a threshold limit; When stored data is read from the non-volatile memory, the stored data is read from the non-volatile memory based on the premise that the read interference does not exceed the threshold limit; When stored data is read from the non-volatile memory, a buffer in the volatile memory is allocated based on the read interference exceeding the threshold limit; Determine whether the buffer in the volatile memory has been successfully allocated; as well as If the allocation of the buffer in the volatile memory fails, the data is relocated from the volatile memory to the non-volatile memory, wherein the relocated data includes the lowest read counter among the plurality of read counters of the volatile memory.

8. The storage device of claim 7, wherein, The stored data includes parity bits, and The threshold limit is the maximum number of bits used for parity correction.

9. The storage device of claim 7, wherein, The storage device controller is also configured to: Based on the successful allocation of the buffer in the volatile memory, the stored data is relocated from the non-volatile memory to the volatile memory; The stored data is relocated to the volatile memory, and the L2P mapping is updated; as well as Read the stored data from the volatile memory.

10. The storage device of claim 9, wherein, The storage device controller is also configured to: The buffer is identified based on the buffer corresponding to the lowest read counter in the volatile memory; Allocate single-layer cell SLC NAND flash memory blocks in the non-volatile memory to store data; Relocate the data in the SLC NAND flash memory; as well as Update the PBN associated with the data to indicate the SLC NAND flash memory block.

11. The storage device of claim 9, wherein, The storage device controller is also configured to: When stored data is read from the non-volatile memory, determine whether the read threshold counter associated with the PBN exceeds the maximum read limit; When stored data is read from the non-volatile memory, the stored data is read from the non-volatile memory based on the read threshold counter associated with the PBN not exceeding the maximum read limit; as well as When stored data is read from the non-volatile memory, a buffer in the volatile memory is allocated based on the read threshold counter associated with the PBN exceeding the maximum read limit.

12. The storage device of claim 7, wherein, The L2P mapping indicates the actual physical location of each LBA in the storage device.

13. A storage device controller, comprising: At least one processor is configured as follows: Receive a read command from the host device, wherein the read command includes the logical block address (LBA) of the stored data to be read; The physical block number (PBN) is obtained based on the LBA and logical-to-physical L2P mapping. Determine whether the PBN corresponds to the volatile memory of the storage device; Based on the PBN corresponding to the volatile memory, the stored data is read directly from the volatile memory; Based on the stored data read directly from the volatile memory, increment the read counter associated with the PBN; Based on the PBN that does not correspond to the volatile memory, the stored data is read from the non-volatile memory of the storage device; When reading stored data from the non-volatile memory, determine whether the read interference exceeds a threshold limit; When stored data is read from the non-volatile memory, the stored data is read from the non-volatile memory based on the premise that the read interference does not exceed the threshold limit; When stored data is read from the non-volatile memory, a buffer in the volatile memory is allocated based on the read interference exceeding the threshold limit; Determine whether the buffer in the volatile memory has been successfully allocated; as well as If the allocation of the buffer in the volatile memory fails, the data is relocated from the volatile memory to the non-volatile memory, wherein the relocated data includes the lowest read counter among the plurality of read counters of the volatile memory.

14. The storage device controller of claim 13, wherein, The stored data includes parity bits; and The threshold limit is the maximum number of bits used for parity correction.

15. The storage device controller of claim 13, wherein, The at least one processor is further configured to: Based on the successful allocation of the buffer in the volatile memory, the stored data is relocated from the non-volatile memory to the volatile memory; as well as The stored data is relocated to the volatile memory, and the L2P mapping is updated; Read the stored data from the volatile memory.

16. The storage device controller of claim 15, wherein, The at least one processor is further configured to: The buffer is identified based on the buffer corresponding to the lowest read counter in the volatile memory; Allocate single-layer cell SLC NAND flash memory blocks in the non-volatile memory to store data; Relocate the data in the SLC NAND flash memory; as well as Update the PBN associated with the data to indicate the SLC NAND flash memory block.

17. The storage device controller of claim 13, wherein, The storage device controller is also configured to: When stored data is read from the non-volatile memory, determine whether the read threshold counter associated with the PBN exceeds the maximum read limit; When stored data is read from the non-volatile memory, the stored data is read from the non-volatile memory based on the read threshold counter associated with the PBN not exceeding the maximum read limit; as well as When stored data is read from the non-volatile memory, a buffer in the volatile memory is allocated based on the read threshold counter associated with the PBN exceeding the maximum read limit.

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