Signal checking method, medium, electronic device and program product

Abstract

The application relates to the technical field of processors, and discloses a signal checking method, a medium, an electronic device and a program product. The signal checking method comprises the following steps: a checking code generation unit acquires a to-be-checked signal of a dual-core lockstep system, the to-be-checked signal comprising a first type signal to be input into the dual-core lockstep system or to be output from the dual-core lockstep system; the checking code generation unit calculates the value of a check bit of the first type signal, and transmits the first type signal and a second type signal corresponding to the first type signal to a checking unit; and the checking unit determines whether the first type signal is correct according to the second type signal corresponding to the first type signal and the value of the check bit. The technical scheme can check whether the to-be-checked signal is incorrect without adding a new signal, improves the fault detection rate of the dual-core lockstep system, and reduces the cost.

Description

Technical Field

[0001] This application relates to the field of processor technology, and in particular to a signal verification method, medium, electronic device, and program product. Background Technology

[0002] In certain sectors, such as the automotive or civil aviation industries, there are high requirements for the functional safety of components within equipment. The central processing unit (CPU), as the core of these devices, faces even higher demands for functional safety. However, CPUs can also malfunction under certain circumstances, such as radiation, clock drift, or low voltage. Currently, a dual-core lockstep system (DCLS) is typically used to diagnose CPU malfunctions or errors. This involves adding signals within the DCLS to diagnose faults, but this approach increases costs.

[0003] A DCLS typically includes two identical logical units, such as a first CPU core, a second CPU core, and a detection unit. The two CPU cores generally input the same data and execute the same instructions, and the detection unit monitors the status of both CPU cores in real time. When a mismatch is detected in the outputs of the two CPU cores, a signal is output to an external system, which then intervenes to handle the error, such as restarting the system to restore the DCLS to normal operation and ensure system security. Summary of the Invention

[0004] This application provides a signal verification method, a medium, an electronic device, and a program product.

[0005] In a first aspect, embodiments of this application provide a signal verification method applied to an electronic device. The electronic device includes a dual-core lockstep system, a checksum generation unit, and a verification unit. The method includes: the checksum generation unit acquiring a signal to be verified from the dual-core lockstep system, the signal to be verified including a first type of signal to be input into or output from the dual-core lockstep system, wherein the first type of signal includes a signal corresponding to a function that will be activated or used after the dual-core lockstep system is started; the checksum generation unit calculating the value of the checksum bit of the first type of signal and transmitting the first type of signal and a second type of signal corresponding to the first type of signal to the verification unit, wherein the second type of signal is a signal corresponding to a function that will not be activated or used after the dual-core lockstep system is started; and the verification unit determining whether the first type of signal is correct based on the second type of signal corresponding to the first type of signal and the value of the checksum bit.

[0006] In the embodiments of this application, the first type of signal can be a security-related signal, such as a signal related to Random Access Memory (RAM) or an interrupt signal. The second type of signal can be a non-security-related signal, such as a debug-related signal.

[0007] The method provided in this application embodiment can verify whether safety-related signals have errors without adding new signals, thereby improving the fault detection rate of the dual-core lockstep system and reducing costs.

[0008] In one possible implementation of the first aspect described above, the check code generation unit includes a first check code generation unit and a second check code generation unit; the verification unit includes a first verification unit and a second verification unit; corresponding to the case where the first type of signal is a signal to be input into the dual-core lockstep system, the check code generation unit is the first check code generation unit, and the verification unit is the first verification unit; corresponding to the case where the first type of signal is a signal to be output from the dual-core lockstep system, the check code generation unit is the second check code generation unit, and the verification unit is the second verification unit; wherein, the first check code generation unit and the second verification unit are located outside the dual-core lockstep system, and the second check code generation unit and the first verification unit are located inside the dual-core lockstep system.

[0009] In one possible implementation of the first aspect above, the check code generation unit calculates the value of the check bit of the first type of signal based on the second type of signal corresponding to the first type of signal by: the check code generation unit calculates the value of the check bit of the first type of signal based on the second type of signal corresponding to the first type of signal by using a parity check algorithm.

[0010] In this embodiment, the correctness of the first type of signal is determined based on the correspondence between the first type of signal and the second type of signal. That is, the verification of the first type of signal can be completed without setting a new verification signal inside the system, which effectively improves the fault detection rate and the accuracy of the verification of the dual-core lockstep system.

[0011] In one possible implementation of the first aspect above, the second type of signal corresponding to the first type of signal to be input into the dual-core lockstep system includes: the second type of signal to be input into the dual-core lockstep system; the second type of signal corresponding to the first type of signal to be output from the dual-core lockstep system includes: the second type of signal included in the dual-core lockstep system.

[0012] In this embodiment, since the second type of signal is either the signal to be input into the dual-core lockstep system or a signal that already exists in the dual-core lockstep system itself, the verification of the first type of signal can be completed without setting a new signal, thus reducing costs.

[0013] In one possible implementation of the first aspect described above, when the first type of signal is an error signal, the verification unit outputs an error message.

[0014] In this embodiment of the application, when the first type of signal is detected as an error signal, the verification unit outputs an error message so that the external system can respond in a timely manner based on the error message.

[0015] In one possible implementation of the first aspect above, when the dual-core lockstep system is started, the dual-core lockstep system accepts the first type of signal; the dual-core lockstep system rejects the second type of signal.

[0016] In this embodiment, the dual-core lockstep system rejects the second type of signal to ensure that there are enough second type of signals to verify the first type of signal.

[0017] In one possible implementation of the first aspect described above, the original function of the second type of signal is disabled when the dual-core lockstep system is started.

[0018] In this embodiment of the application, when the dual-core lockstep system is started, although the second type of signal will not be activated or used, the second type of signal still has its original function. By disabling the original function of the second type of signal, the original function of the second type of signal is prevented from affecting the verification process of the first type of signal.

[0019] In one possible implementation of the first aspect described above, the second type of signal has configuration parameters, and the original function of disabling the second type of signal is determined based on the configuration parameters; corresponding to the case where the original function of the second type of signal is not disabled, the dual-core lockstep system passes the second type of signal; corresponding to the case where the original function of the second type of signal is disabled, the dual-core lockstep system rejects the second type of signal.

[0020] In this embodiment of the application, the user can set whether to verify the first type of signal based on the second type of signal according to actual needs.

[0021] Secondly, embodiments of this application provide a System-on-Chips (SOC), which includes a dual-core lockstep system, a checksum generation unit, and a verification unit. The SOC includes: a checksum generation unit for acquiring a signal to be verified from the dual-core lockstep system, the signal to be verified including a first type of signal to be input into or output from the dual-core lockstep system, wherein the first type of signal includes signals corresponding to functions that will be activated or used after the dual-core lockstep system is started; a checksum generation unit for calculating the value of the checksum bit of the first type of signal and transmitting the first type of signal and a corresponding second type of signal to the verification unit, wherein the second type of signal corresponds to signals that will not be activated or used after the dual-core lockstep system is started; and a verification unit for determining whether the first type of signal is correct based on the second type of signal corresponding to the first type of signal and the value of the checksum bit.

[0022] Thirdly, embodiments of this application provide a readable medium storing instructions that, when executed on an electronic device, cause the electronic device to implement any of the signal verification methods provided by the first aspect and various possible implementations of the first aspect.

[0023] Fourthly, embodiments of this application provide an electronic device, including: a memory for storing instructions executed by one or more processors of the electronic device, and a processor, which is one of the one or more processors of the electronic device, for implementing any of the signal verification methods provided by the first aspect and various possible implementations of the first aspect.

[0024] Fifthly, embodiments of this application provide a computer program product, including: execution instructions stored in a readable storage medium, at least one processor of an electronic device can read the execution instructions from the readable storage medium, and the at least one processor executes the execution instructions to enable the electronic device to implement any of the signal verification methods provided by the first aspect and various possible implementations of the first aspect.

[0025] Sixthly, embodiments of this application provide an electronic device, including a System-on-a-Chip (SOC). Attached Figure Description

[0026] Figure 1 According to some embodiments of this application, a schematic diagram of the workflow of a dual-core lockstep system is shown;

[0027] Figure 2 According to some embodiments of this application, a schematic diagram of a signal reception method when DCLS is not started is shown;

[0028] Figure 3 According to some embodiments of this application, a schematic diagram of a signal receiving method during DCLS startup is shown;

[0029] Figure 4 According to some embodiments of this application, a schematic diagram of a signal receiving method involving configuration parameters is shown when DCLS is not started;

[0030] Figure 5 According to some embodiments of this application, a schematic diagram is shown of a method for receiving configuration parameter signals during DCLS startup;

[0031] Figure 6 According to some embodiments of this application, a schematic diagram of a signal verification method after DCLS startup is shown;

[0032] Figure 7 According to some embodiments of this application, a schematic diagram of a signal reception method after DCLS is started is shown;

[0033] Figure 8 According to some embodiments of this application, a schematic diagram of a signal verification method involving configuration parameters after DCLS startup is shown;

[0034] Figure 9 According to some embodiments of this application, a schematic diagram of a signal receiving method involving configuration parameters after DCLS is started is shown;

[0035] Figure 10 According to some embodiments of this application, a structural block diagram of an electronic device 100 is shown. Detailed Implementation

[0036] The illustrative embodiments of this application include, but are not limited to, a signal verification method, a medium, an electronic device, and a program product.

[0037] To make the solution of this application clearer, the relevant technical terms will be introduced below.

[0038] Parity checking is a method for verifying the correctness of transmitted code. It involves checking whether the number of "1"s in the transmitted binary code is odd or even. Typically, a parity bit is specifically set up to ensure that the number of "1"s in the code is odd or even. The method that determines the correctness of binary code transmission based on the parity bit ensuring an odd number of "1"s is called odd parity; the method that determines the correctness of code transmission based on the parity bit ensuring an even number of "1"s is called even parity.

[0039] Specifically, the parity check method is as follows: the sending end calculates the value of the parity bit of the binary code and sends the binary code to the receiving end; after receiving the binary code, the receiving end calculates the value of the parity bit that makes the number of "1"s in the binary code odd; if the value of the parity bit calculated by the sending end is the same as the value of the parity bit calculated by the receiving end, it proves that the code is correct; if the value of the parity bit calculated by the sending end is different from the value of the parity bit calculated by the receiving end, it proves that the code is incorrect.

[0040] For example, if you need to transmit "11001110", which contains five "1"s, its parity bit is "0". When "11001110" is transmitted to the receiving end, the receiving end calculates the parity again. Since "11001110" still contains five "1"s, the parity bit calculated by the receiving end is still "0", which is consistent with the sender's result, indicating that no error occurred during this transmission.

[0041] To address the aforementioned issues, some embodiments of this application provide a signal verification method for use in an electronic device. Specifically, the signal verification method includes: when DCLS is started, detecting a signal to be input or output from DCLS, acquiring a verification signal for verifying safety-related signals in the signal to be input or output from DCLS, calculating the value of the verification bit of the safety-related signal in the signal to be input or output from DCLS based on the verification signal by a verification unit, and determining whether the safety-related signal in the signal to be input or output from DCLS is correct based on the value of the verification bit. If the determination result is negative, the verification unit outputs a system fault prompt message for external system intervention to handle the error, such as restarting the system to restore the normal operation of DCLS.

[0042] Safety-related signals can be input or output signals corresponding to functions that will be activated or used after DCLS is started; for example, signals related to Random Access Memory (RAM) and interrupt signals.

[0043] In this embodiment, the verification signal can be a pre-configured standard parameter, standard signal, etc. The verification unit can verify the correctness of security-related signals using methods such as parity check, checksum, XOR check, Cyclic Redundancy Check (CRC), and two's complement summation. Below, taking odd parity as an example, the method of calculating the value of the verification bit of the security-related signal in the input or output DCLS signal based on the verification signal, and determining the correctness of the security-related signal in the input or output DCLS signal based on the value of the verification bit, will be explained:

[0044] The method for determining the correctness of security-related signals using odd parity is as follows: First, the verification unit calculates the value of the parity bit that makes the number of "1"s in the security-related signal odd before the signal enters or leaves the electronic device system, based on the verification signal. Second, after the security-related signal enters or leaves the electronic device system, according to the correspondence between the verification signal and the security-related signal, the verification unit calculates the value of the parity bit that makes the number of "1"s in the security-related signal odd using the parity check algorithm. Finally, the verification unit determines whether the value of the parity bit calculated before the security-related signal enters the electronic device system is the same as the value of the parity bit calculated after the signal enters the electronic device system. If they are the same, the security-related signal is correct; if they are different, an error occurred in the transmission of the security-related signal.

[0045] It is understandable that the above scheme can effectively improve the fault detection rate of DCLS by detecting security-related signals to determine whether the security-related signals and / or the information they carry are erroneous, thereby further improving the security performance of the CPU.

[0046] However, in the above scheme, a verification signal is used to check whether the safety-related signals have errors. The verification signal is not the signal to be input or output to DCLS, but a new signal that has been set in advance. That is, a new signal is introduced into the system of the electronic device. Therefore, it will increase the detection cost and, to some extent, increase the burden on DCLS.

[0047] To address the aforementioned issues, this application proposes a signal verification method applied to an electronic device, which includes a DCLS, a checksum generation unit, and a verification unit.

[0048] The signal verification method includes: when DCLS is started, the signal to be input or output to DCLS is detected, and DCLS is controlled to transmit the safety-related signals in the signal to be input or output to DCLS, and transmit the non-safety-related signals and safety-related signals in the signal to be input or output to the verification unit. The verification unit determines whether the safety-related signals in the signal to be input to DCLS are correct based on the non-safety-related signals in the signal to be input to DCLS. If the determination result is negative, a system fault prompt message is output so that the external system can intervene to handle the error, such as restarting the system to restore the normal operation of DCLS.

[0049] The signals to be input into the DCLS include security-related signals and non-security-related signals located outside the DCLS; the signals to be output from the DCLS include security-related signals and non-security-related signals within the DCLS; and the verification unit includes a first verification unit and a second verification unit.

[0050] In this embodiment, since the signals to be input or output to DCLS include non-security-related signals, the verification unit can determine whether the security-related signals are correct based on the non-security-related signals. This eliminates the need to set new verification signals within the system, thereby improving the fault detection rate of DCLS, reducing costs, and enhancing the security performance of the CPU.

[0051] The above method for determining the correctness of security-related signals in the input or output DCLS signal based on non-security-related signals in the input or output DCLS signal can be as follows: First, the check bit value of the security-related signal in the input or output DCLS signal is calculated by the check code generation unit. Second, based on the correspondence between security-related signals and non-security-related signals, and combined with the security-related signals and the non-security-related signals whose original functions are disabled, the security-related signals are transmitted to the check unit based on the non-security-related signals. Finally, the check unit determines whether the security-related signals in the input or output DCLS signal are correct based on the check bit value of the security-related signal in the input or output DCLS signal and the non-security-related signals in the input or output DCLS signal.

[0052] Specifically, such as Figure 1 As shown, for the security-related signals to be input into the DCLS, firstly, the first checksum generation unit calculates the value of the checksum bit of the security-related signals in the input DCLS signal. Then, based on the correspondence between the security-related signals and non-security-related signals in the input DCLS signal, and combining the security-related signals with the non-security-related signals whose original functions are disabled, the security-related signals are then transmitted to the first verification unit based on the non-security-related signals. The first verification unit determines whether the security-related signals in the input DCLS signal are correct based on the value of the checksum bit of the security-related signals in the input DCLS signal and the non-security-related signals in the input DCLS signal. The first checksum generation unit is located outside the DCLS; the first verification unit is located inside the DCLS.

[0053] For the security-related signals of the DCLS to be output, firstly, the second checksum generation unit calculates the value of the check bits of the security-related signals in the DCLS signal to be output. Then, based on the correspondence between the security-related signals and non-security-related signals of the DCLS to be output, and combining the security-related signals with the non-security-related signals whose original functions are disabled, the security-related signals are then transmitted to the second checksum unit based on the non-security-related signals of the DCLS to be output. The second checksum unit determines whether the security-related signals in the DCLS signal to be output are correct based on the value of the check bits of the security-related signals and the non-security-related signals in the DCLS signal to be output. The second checksum generation unit is located inside the DCLS; the second checksum unit is located outside the DCLS.

[0054] Among them, safety-related signals can be input or output signals corresponding to some functions that will be activated or used after DCLS is started; for example, signals related to Random Access Memory (RAM) and signals related to interrupt signals.

[0055] Non-safety-related signals can be input or output signals corresponding to functions that will not be activated or used after DCLS is started, such as Debug-related signals.

[0056] In some embodiments, when DCLS is started, the original functions of non-security-related signals within the DCLS system can be disabled; this can effectively prevent the original functions of non-security-related signals from interfering with the verification process.

[0057] In some embodiments, the above-mentioned method of combining the security-related signals and non-security-related signals whose original functions are disabled, based on the correspondence between security-related signals and non-security-related signals, may include: determining whether the original function of the non-security-related signal to be input or output DCLS is disabled; if the determination result is yes, then combining the security-related signals with the non-security-related signals whose original functions are disabled, based on the correspondence between non-security-related signals and security-related signals; if the determination result is no, then ending the processing logic.

[0058] In some embodiments, a parity check method can be used to determine the correctness of security-related signals based on non-security-related signals. Specifically, for security-related signals to be input into the DCLS, verification can be performed based on non-security-related signals of the input DCLS; for security-related signals to be output into the DCLS, verification can be performed based on non-security-related signals within the DCLS.

[0059] For example, the method for determining the correctness of a DCLS safety-related signal input or output using odd parity is as follows: First, before the safety-related signal enters or leaves the electronic device's system, the parity check algorithm calculates the value of the parity bit that makes the number of "1"s in the safety-related signal odd. Second, after the safety-related signal enters or leaves the electronic device's system, based on the correspondence between non-safety-related signals and safety-related signals, the parity check algorithm calculates the value of the parity bit that makes the number of "1"s in the safety-related signal odd. Finally, it is determined whether the value of the parity bit calculated before the safety-related signal enters the electronic device's system is the same as the value of the parity bit calculated after the safety-related signal enters the electronic device's system. If they are the same, it proves that the safety-related signal is correct; if they are different, it proves that an error occurred in the transmission of the safety-related signal.

[0060] The following explanation uses the transmission of the security-related signal "11001110" as an example:

[0061] Before “11001110” enters or leaves the system, the calculated check bit is “0” because the data contains five “1”s. If, after “11001110” enters or leaves the system, the calculated check bit is still “0” based on the correspondence between non-security-related signals and security-related signals, then “11001110” is correct. If the calculated check bit is not “0”, then “11001110” has an error during transmission.

[0062] The method for determining the correctness of input or output DCLS safety-related signals using even parity is as follows: First, before the safety-related signal enters or leaves the electronic device's system, the parity bit value that makes the number of "1"s in the safety-related signal even is calculated using a parity check algorithm. Second, after the safety-related signal enters or leaves the electronic device's system, based on the correspondence between non-safety-related signals and safety-related signals, the parity bit value that makes the number of "1"s in the safety-related signal even is calculated using a parity check algorithm. Finally, it is determined whether the parity bit value calculated before the safety-related signal enters the electronic device's system is the same as the parity bit value calculated after the safety-related signal enters the electronic device's system. If they are the same, it proves that the safety-related signal is correct; if they are different, it proves that an error occurred in the transmission of the safety-related signal.

[0063] The following explanation uses the transmission of "11001110" as an example:

[0064] Before “11001110” enters or leaves the system, the check bit is calculated as “1” because the data contains five “1”s. If, after “11001110” enters or leaves the system, the check bit is still calculated as “1” based on the correspondence between non-security-related signals and security-related signals, then “11001110” is correct. If the calculated check bit is not “1”, then “11001110” has an error during transmission.

[0065] It is understandable that the above scheme can effectively improve the fault detection rate of DCLS by detecting security-related signals and / or whether the information carried by the security-related signals is erroneous, thereby further improving the security performance of the CPU.

[0066] It is understandable that users can decide whether to enable DCLS based on the tasks running on the CPU or actual needs.

[0067] In this embodiment of the application, when DCLS is started and a signal to be input or output to DCLS is detected, DCLS determines whether the signal to be input or output to DCLS is a safety-related signal. If the determination result is yes, that is, the signal to be input or output to DCLS is a safety-related signal, then DCLS is controlled to pass the signal to be input or output to DCLS. If the determination result is no, that is, the signal to be input or output to DCLS is a non-safety-related signal, then DCLS is controlled to reject the signal to be input or output to DCLS, and a preset value is input for the non-safety-related signal in DCLS.

[0068] Specifically, when DCLS is not started, such as Figure 2 As shown, DCLS allows both safety-related and non-safety-related signals to pass through; when DCLS is started, as... Figure 3 As shown, DCLS allows security-related signals to pass through, rejects non-security-related signals, and transmits both security-related and non-security-related signals to the verification unit.

[0069] In this embodiment of the application, a processing service for non-safety-related signals can be pre-configured in the system of the electronic device. When DCLS is started, non-safety-related signals will be distinguished.

[0070] Furthermore, in some embodiments of this application, the non-safety-related signals are configured with parameters. When DCLS is started, it detects the signal to be input or output to DCLS, controls DCLS to transmit the safety-related signals and the non-safety-related signals whose original functions are not disabled in the signal to be input or output to DCLS, and transmits the non-safety-related signals whose original functions are disabled and the safety-related signals in the signal to be input or output to DCLS to the verification unit. The verification unit determines whether the safety-related signals in the signal to be input or output to DCLS are correct based on the non-safety-related signals in the signal to be input or output to DCLS. If the determination result is negative, a system fault prompt message is output so that an external system can intervene to handle the error, such as restarting the system to restore the normal operation of DCLS.

[0071] In this embodiment, the correctness of security-related signals is determined by a verification unit based on the non-security-related signals already present in the system. Therefore, verification of security-related signals can be completed without setting new verification signals within the system, improving the fault detection rate of DCLS, reducing costs, and enhancing CPU security performance. Furthermore, users can adjust configuration parameters according to actual needs, allowing non-security-related signals to maintain their original function or disable their original function, increasing user choice and improving user experience.

[0072] In this embodiment of the application, when DCLS is not started, such as Figure 4As shown, DCLS allows safety-related signals, non-safety-related signals whose original functions are not disabled, and non-safety-related signals whose original functions are disabled to pass through; when DCLS is started, as... Figure 5 As shown, DCLS allows security-related signals and non-security-related signals whose original functions are not disabled to pass through, while denying the passage of non-security-related signals whose original functions are disabled, and transmitting security-related signals and non-security-related signals whose original functions are disabled to the verification unit.

[0073] In some embodiments, it can be determined based on configuration parameters whether the original function of non-safety-related signals in the DCLS signals to be input or output is disabled. For example, it can be determined whether the configuration parameters of non-safety-related signals are enabled. If the determination result is yes, it proves that the original function of non-safety-related signals is disabled. If the determination result is no, it proves that the original function of non-safety-related signals is not disabled.

[0074] For safety-related signals to be input into DCLS, verification can be performed based on non-safety-related signals whose original functions are disabled in the input DCLS; for safety-related signals to be output from DCLS, verification can be performed based on non-safety-related signals whose original functions are disabled in the DCLS.

[0075] In some embodiments, the above-described parity check method can be used to determine the correctness of security-related signals based on non-security-related signals that disable the original function, which will not be elaborated here.

[0076] It is understandable that the above scheme can effectively improve the fault detection rate of DCLS by detecting security-related signals to determine whether the security-related signals and / or the information carried by the security-related signals are erroneous, thereby further improving the security performance of the CPU.

[0077] It is understandable that users can decide whether to enable DCLS based on the tasks running on the CPU or actual needs.

[0078] The signal verification method provided in the embodiments of this application will be described in detail below. Figure 6 According to some embodiments of this application, a flowchart of a signal verification method is shown. The signal verification method provided in this application can be executed by an electronic device. The signal verification method includes:

[0079] 601: When DCLS is started, it detects the signal to be input or output to DCLS, controls DCLS to pass the security-related signal in the signal to be input or output to DCLS, and transmits the non-security-related signal and the security-related signal in the signal to be input or output to DCLS to the check code generation unit.

[0080] It is understood that in the embodiments of this application, when DCLS is started, the original device under test (DUT) will be copied and the input of the secondary DUT will be delayed. However, some input and output interfaces in the original DUT are not security-related and are not allowed to be activated or used when DCLS is started. The signals corresponding to these interfaces are treated as non-security-related signals, such as debug-related signals.

[0081] In this embodiment, the checksum generation unit includes a first checksum generation unit and a second checksum generation unit; it can transmit non-security-related signals and security-related signals from the input DCLS signal to the first checksum generation unit; and it can transmit non-security-related signals and security-related signals from the output DCLS signal to the second checksum generation unit. Figure 1 As shown, the first checksum generation unit is located outside the DCLS, and the second checksum generation unit is located inside the DCLS.

[0082] Safety-related signals can be input or output signals corresponding to functions that will be activated or used after DCLS is started; for example, RAM-related signals and interrupt signal-related signals.

[0083] It is understandable that although non-security-related signals are not allowed to be activated or used, they still have their original functions. In some embodiments, after DCLS is started, the original functions of non-security-related signals are disabled, thereby avoiding interference from the original functions of non-security-related signals with the verification process of security-related signals.

[0084] It is understandable that users can decide whether to enable DCLS based on the tasks running on the CPU or actual needs.

[0085] In this embodiment, since the signals to be input or output to the DCLS include non-security-related signals, the verification unit can determine whether the security-related signals are correct based on the non-security-related signals. This eliminates the need to set new verification signals within the system, thereby improving the fault detection rate of the DCLS, reducing costs, and enhancing the security performance of the CPU. The non-security-related signals to be output to the DCLS include the non-security-related signals within the DCLS.

[0086] 602: The check code generation unit calculates the value of the check bit of the security-related signal in the DCLS signal to be input or output, and transmits the security-related signal to the check unit based on the non-security-related signal.

[0087] In this embodiment, the check code generation unit first calculates the value of the check bit of the security-related signal to be input or output DCLS, and then determines whether the original function of the non-security-related signal to be input or output DCLS is disabled. If the determination result is no, the processing logic ends; if the determination result is yes, the non-security-related signal to be input or output DCLS and the security-related signal to be input or output DCLS are combined according to the correspondence between the security-related signal and the non-security-related signal.

[0088] In some embodiments, for a security-related signal to be input into DCLS, the first checksum generation unit calculates the value of the checksum bit of the security-related signal in the signal to be input into DCLS.

[0089] For the security-related signals of the DCLS to be output, the second check code generation unit calculates the value of the check bit of the security-related signals in the DCLS signal to be output.

[0090] 603: The verification unit determines whether the safety-related signals in the input or output DCLS signals are correct based on the value of the check bits of the non-safety-related signals and the safety-related signals in the input or output DCLS signals. If the result is negative, proceed to 604: Output system fault message. If the result is positive, end the processing logic.

[0091] The verification unit determines whether the safety-related signals in the input or output DCLS signal are correct based on the value of the check bits of the non-safety-related signals and the safety-related signals in the input or output DCLS signal. If the determination result is negative, a system fault message is output; if the determination result is positive, the processing logic ends.

[0092] Among them, the non-security-related signals of the DCLS to be output are the non-security-related signals within the DCLS. For the security-related signals of the DCLS to be input, verification can be performed based on the non-security-related signals of the DCLS to be input; for the security-related signals of the DCLS to be output, verification can be performed based on the non-security-related signals within the DCLS.

[0093] For the security-related signals to be input into the DCLS, the first verification unit determines whether the security-related signals in the input DCLS signal are correct based on the value of the check bit of the security-related signals and the non-security-related signals in the input DCLS signal. The first verification unit is located within the DCLS.

[0094] For the safety-related signals to be output from the DCLS, the second verification unit determines whether the safety-related signals in the DCLS signal to be output are correct based on the value of the check bit of the safety-related signals and the non-safety-related signals in the DCLS signal to be output. The second verification unit is located outside the DCLS.

[0095] In some embodiments, a parity check method can be used to determine the correctness of security-related signals based on non-security-related signals.

[0096] The method for determining the correctness of input or output DCLS safety-related signals using odd parity is as follows: First, before the safety-related signal enters or leaves the electronic device system, the parity check algorithm calculates the value of the parity bit that makes the number of "1"s in the safety-related signal odd. Second, after the safety-related signal enters or leaves the electronic device system, based on the correspondence between non-safety-related signals and safety-related signals, the parity check algorithm calculates the value of the parity bit that makes the number of "1"s in the safety-related signal odd. Finally, it is determined whether the value of the parity bit calculated before the safety-related signal enters the electronic device system is the same as the value of the parity bit calculated after the safety-related signal enters the electronic device system. If they are the same, it proves that the safety-related signal is correct; if they are different, it proves that an error occurred in the transmission of the safety-related signal.

[0097] The following explanation uses the transmission of the security-related signal "11001110" as an example:

[0098] Before “11001110” enters or leaves the system, the calculated check bit is “0” because the data contains five “1”s. If, after “11001110” enters or leaves the system, the calculated check bit is still “0” based on the correspondence between non-security-related signals and security-related signals, then “11001110” is correct. If the calculated check bit is not “0”, then “11001110” has an error during transmission.

[0099] The method for determining the correctness of input or output DCLS safety-related signals using even parity is as follows: First, before the safety-related signal enters or leaves the electronic device's system, the parity bit value that makes the number of "1"s in the safety-related signal even is calculated using a parity check algorithm. Second, after the safety-related signal enters or leaves the electronic device's system, based on the correspondence between non-safety-related signals and safety-related signals, the parity bit value that makes the number of "1"s in the safety-related signal even is calculated using a parity check algorithm. Finally, it is determined whether the parity bit value calculated before the safety-related signal enters the electronic device's system is the same as the parity bit value calculated after the safety-related signal enters the electronic device's system. If they are the same, it proves that the safety-related signal is correct; if they are different, it proves that an error occurred in the transmission of the safety-related signal.

[0100] The following explanation uses the transmission of "11001110" as an example:

[0101] Before “11001110” enters or leaves the system, the check bit is calculated as “1” because the data contains five “1”s. If, after “11001110” enters or leaves the system, the check bit is still calculated as “1” based on the correspondence between non-security-related signals and security-related signals, then “11001110” is correct. If the calculated check bit is not “1”, then “11001110” has an error during transmission.

[0102] It is understandable that the above scheme can effectively improve the fault detection rate of DCLS by detecting security-related signals to determine whether the security-related signals and / or the information carried by the security-related signals are erroneous, thereby further improving the security performance of the CPU.

[0103] 604: Outputs a system fault message.

[0104] It is understandable that the system fault information is output to the external system of DCLS so that the external system can respond in a timely manner based on the system fault information, such as restarting the system.

[0105] The signal receiving method of DCLS involved in the signal verification method provided in the embodiments of this application will be described in detail below with reference to electronic devices. Among them, Figure 7 The diagram illustrates a signal receiving method according to an embodiment of this application.

[0106] 701: When DCLS is started, upon detecting a signal to be input or output to DCLS, it determines whether the input or output signal is a safety-related signal through DCLS. If the determination result is yes, proceed to 702: control DCLS to allow the signal to be input or output to DCLS; if the determination result is no, proceed to 703: control DCLS to reject the signal to be input or output to DCLS, and input a preset value for non-safety-related signals in DCLS.

[0107] When DCLS is started, upon detecting a signal to be input or output to DCLS, it determines whether the input or output signal is a safety-related signal. If the determination result is yes, DCLS is controlled to allow the signal to be input or output to DCLS; if the determination result is no, DCLS is controlled to reject the signal to be input or output to DCLS, and a preset value is input for non-safety-related signals within DCLS.

[0108] In this embodiment of the application, a processing service for non-safety-related signals can be pre-configured in the system of the electronic device. When DCLS is started, non-safety-related signals will be distinguished.

[0109] It is understood that in the embodiments of this application, security-related signals may be input or output signals corresponding to some functions that will be activated or used after DCLS is started; for example, signals related to Random Access Memory (RAM) and signals related to interrupt signals.

[0110] Non-safety-related signals can be input or output signals corresponding to functions that will not be activated or used after DCLS is started, such as Debug-related signals.

[0111] When DCLS is not started, such as Figure 2 As shown, DCLS allows both safety-related and non-safety-related signals to pass through; when DCLS is started, as... Figure 3 As shown, DCLS allows security-related signals to pass through, rejects non-security-related signals, and transmits both security-related and non-security-related signals to the verification unit.

[0112] It is understandable that users can decide whether to enable DCLS based on the tasks running on the CPU or actual needs.

[0113] 702: Controls the DCLS through signals to be input to or output to the DCLS.

[0114] 703: Controls DCLS to reject signals to be input to or output to DCLS, and inputs preset values ​​for non-safety-related signals within DCLS.

[0115] The signal verification method involving configuration parameters provided in the embodiments of this application will be described in detail below with reference to electronic devices. Among them, Figure 8 The diagram illustrates a signal verification method according to an embodiment of this application.

[0116] 801: When DCLS is started, it detects the signal to be input or output to DCLS, controls DCLS to pass the security-related signal and the non-security-related signal whose original function is not disabled in the signal to be input or output to DCLS, and transmits the non-security-related signal whose original function is disabled and the security-related signal in the signal to be input or output to DCLS to the check code generation unit.

[0117] It is understood that in the embodiments of this application, when DCLS is started, the original device under test (DUT) will be copied and the input of the secondary DUT will be delayed. However, some input and output interfaces in the original DUT are not security-related and are not allowed to be activated or used when DCLS is started. The signals corresponding to these interfaces are treated as non-security-related signals, such as debug-related signals.

[0118] In this embodiment, the checksum generation unit includes a first checksum generation unit and a second checksum generation unit. It can transmit non-security-related signals with disabled original functions and security-related signals from the signal to be input into the DCLS to the first checksum generation unit; it can also transmit non-security-related signals with disabled original functions and security-related signals from the signal to be output into the DCLS to the second checksum generation unit. The first checksum generation unit is located outside the DCLS, and the second checksum generation unit is located inside the DCLS.

[0119] Safety-related signals can be input or output signals corresponding to functions that will be activated or used after DCLS is started; for example, RAM-related signals and interrupt signal-related signals.

[0120] It is understood that although non-security-related signals are not allowed to be activated or used, they still have their original functions. In this embodiment, after DCLS is started, the user can set whether to disable the original functions of non-security-related signals according to actual needs.

[0121] It is understandable that users can decide whether to enable DCLS based on the tasks running on the CPU or actual needs.

[0122] In this embodiment, since the signals to be input or output to DCLS include non-security-related signals, the verification unit can determine whether the security-related signals are correct based on the non-security-related signals whose original functions are disabled. This eliminates the need to set new verification signals within the system, thereby improving the fault detection rate of DCLS, reducing costs, and enhancing the security performance of the CPU. The non-security-related signals to be output to DCLS include the non-security-related signals within DCLS.

[0123] 802: The check code generation unit calculates the value of the check bit of the security-related signal in the DCLS signal to be input or output, and transmits the security-related signal to the check unit based on the non-security-related signal whose original function is disabled.

[0124] In some embodiments, the method of the above-described check code generation unit can be used to calculate the value of the check bit of the security-related signal, which will not be elaborated here.

[0125] 803: The verification unit determines whether the safety-related signals in the input or output DCLS signal are correct based on the value of the check bits of the non-safety-related signals whose original functions are disabled in the input or output DCLS signal and the safety-related signals in the input or output DCLS signal. If the result is negative, proceed to 804: Output system fault message. If the result is positive, end the processing logic.

[0126] The verification unit determines whether the safety-related signals in the input or output DCLS signals are correct based on the value of the check bits of the non-safety-related signals whose original functions are disabled in the input or output DCLS signals. If the result is negative, the system will output a fault message. If the result is positive, the processing logic will end.

[0127] Specifically, for the safety-related signals to be input into the DCLS, verification can be performed based on the non-safety-related signals whose original functions are disabled in the DCLS to be input; for the safety-related signals to be output from the DCLS, verification can be performed based on the non-safety-related signals whose original functions are disabled in the DCLS.

[0128] In some embodiments, the above-described parity check method can be used to determine the correctness of security-related signals based on non-security-related signals that disable the original function, which will not be elaborated here.

[0129] Among them, safety-related signals can be input or output signals corresponding to some functions that will be activated or used after DCLS is started; for example, RAM-related signals and interrupt signal-related signals.

[0130] In this embodiment, since the signals to be input or output to the DCLS include non-security-related signals, the verification unit can determine whether the security-related signals are correct based on the non-security-related signals. This eliminates the need to set new verification signals within the system, thereby improving the fault detection rate of the DCLS, reducing costs, and enhancing the security performance of the CPU. The non-security-related signals to be output to the DCLS include the non-security-related signals within the DCLS.

[0131] It is understandable that the above scheme can effectively improve the fault detection rate of DCLS by detecting security-related signals to determine whether the security-related signals and / or the information carried by the security-related signals are erroneous, thereby further improving the security performance of the CPU.

[0132] 804: Outputs system fault message.

[0133] It is understandable that the system fault information is output to the external system of DCLS so that the external system can respond in a timely manner based on the system fault information, such as restarting the system.

[0134] The following describes in detail the DCLS signal reception method involving configuration parameters in the signal verification method provided in the embodiments of this application, with reference to electronic devices. Among them, Figure 9 The diagram illustrates a signal verification method according to an embodiment of this application.

[0135] 901: After DCLS is started, DCLS determines whether the signal to be input or output to DCLS is a safety-related signal; if the determination result is yes, then proceed to 902: control DCLS to input or output the signal to DCLS; if the determination result is no, then proceed to 903: determine whether the original function of the signal to be input or output to DCLS is disabled based on the configuration parameters of the signal to be input or output to DCLS.

[0136] When DCLS is started, it determines whether the signal to be input or output to DCLS is a safety-related signal. If the determination result is yes, it controls DCLS to pass the signal to be input or output to DCLS. If the determination result is no, it determines whether the original function of the signal to be input or output to DCLS is disabled based on the configuration parameters of the signal to be input or output to DCLS.

[0137] In this embodiment of the application, a processing service for non-safety-related signals can be preset in the system of the electronic device. When DCLS is started, non-safety-related signals will be distinguished.

[0138] In this embodiment of the application, when DCLS is not started, such as Figure 4As shown, Figure 4 As shown, DCLS allows safety-related signals, non-safety-related signals whose original functions are not disabled, and non-safety-related signals whose original functions are disabled to pass through; when DCLS is started, as... Figure 5 As shown, DCLS allows security-related signals and non-security-related signals whose original functions are not disabled to pass through, while denying the passage of non-security-related signals whose original functions are disabled, and transmitting security-related signals and non-security-related signals whose original functions are disabled to the verification unit.

[0139] Among them, security-related signals can be input or output signals corresponding to some functions that will be activated or used after DCLS is started; for example, signals related to Random Access Memory (RAM) and signals related to interrupt signals.

[0140] Non-safety-related signals can be input or output signals corresponding to functions that will not be activated or used after DCLS is started, such as Debug-related signals.

[0141] 902: Controls the DCLS through signals to be input to or output to the DCLS.

[0142] 903: Determine whether the original function of the signal to be input or output to the DCLS is disabled based on the configuration parameters of the signal to be input or output to the DCLS. If the determination result is yes, proceed to 904: Control the DCLS to reject the signal to be input or output to the DCLS and input a preset value for non-safety related signals in the DCLS; if the determination result is no, proceed to 902: Control the DCLS to allow the signal to be input or output to the DCLS.

[0143] Based on the configuration parameters of the signal to be input to or output to the DCLS, determine whether the original function of the signal to be input to or output to the DCLS is disabled. If the determination result is yes, control the DCLS to reject the signal to be input to or output to the DCLS, and input a preset value for non-safety related signals within the DCLS; if the determination result is no, control the DCLS to allow the signal to be input to or output to the DCLS.

[0144] 904: Controls DCLS to reject signals to be input to or output to DCLS, and inputs preset values ​​for non-safety-related signals within DCLS.

[0145] In this embodiment of the application, the method for determining whether the original function of the non-security-related signal in the DCLS signal to be input or output is disabled based on the configuration parameters can be as follows: determine whether the configuration parameters of the non-security-related signal are enabled. If the determination result is yes, it proves that the original function of the non-security-related signal is disabled. If the determination result is no, it proves that the original function of the non-security-related signal is not disabled.

[0146] It is understandable that although non-security-related signals are not allowed to be activated or used, they still have their original functions. In some embodiments, after DCLS is started, the original functions of non-security-related signals are disabled based on configuration parameters, thereby avoiding interference from the original functions of non-security-related signals with the verification process of security-related signals.

[0147] This application provides a System-on-Chip (SoC) comprising a dual-core lockstepping system, a checksum generation unit, and a verification unit. The SoC includes: a checksum generation unit for acquiring the checksum signals of the dual-core lockstepping system, the checksum signals including security-related signals to be input into or output to the dual-core lockstepping system, wherein the security-related signals include signals corresponding to functions that will be activated or used after the dual-core lockstepping system is started; a checksum generation unit for calculating the checksum values ​​of the security-related signals and transmitting the security-related signals and their corresponding non-security-related signals to the verification unit, wherein the non-security-related signals are signals corresponding to functions that will not be activated or used after the dual-core lockstepping system is started; and a verification unit for determining whether the first type of signal is correct based on the second type of signal corresponding to the first type of signal and the checksum values.

[0148] This application provides a readable medium storing instructions that, when executed on an electronic device, cause the electronic device to implement any of the signal verification methods provided by the above-described scheme and various possible implementations of the above-described scheme.

[0149] This application provides an electronic device, including: a memory for storing instructions executed by one or more processors of the electronic device, and a processor, which is one of the one or more processors of the electronic device and can implement any of the signal verification methods mentioned in this application.

[0150] This application provides a computer program product, including: execution instructions stored in a readable storage medium, at least one processor of an electronic device can read the execution instructions from the readable storage medium, and the at least one processor executes the execution instructions to enable the electronic device to implement any of the signal verification methods mentioned in this application.

[0151] This application provides an electronic device, including a System-on-a-Chip (SOC).

[0152] further, Figure 10 According to some embodiments of this application, a schematic diagram of the structure of an electronic device 100 is shown. For example... Figure 10 As shown, the electronic device 100 includes one or more processors 101A, system memory 102, non-volatile memory (NVM) 103, communication interface 104, input / output (I / O) devices 105, and system control logic 106 for coupling the processors 101A, system memory 102, NVM 103, communication interface 104, and input / output (I / O) devices 105. Wherein:

[0153] The processor 101A can be used to control an electronic device to execute the signal verification method of this application. The processor 101A may include one or more processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a micro-programmed control unit (MCU), an AI (Artificial Intelligence) processor, or a field-programmable gate array (FPGA) processing module or processing circuit, which may include one or more single-core or multi-core processors. The system memory 102 is volatile memory, such as random-access memory (RAM), double data rate synchronous dynamic random access memory (DDR SDRAM), etc. The system memory is used for temporary storage of data and / or instructions. For example, in some embodiments, the system memory 102 may be used to store related instructions of the neural network model 10, asymmetric / symmetric quantization parameters, asymmetric / symmetric quantization constant data, etc., and may also be used to store the operational logic of preset symmetric quantization operators.

[0154] The non-volatile memory 103 may include one or more tangible, non-transitory computer-readable media for storing data and / or instructions. In some embodiments, the non-volatile memory 103 may include any suitable non-volatile memory such as flash memory and / or any suitable non-volatile storage device, such as a hard disk drive (HDD), a compact disc (CD), a digital versatile disc (DVD), a solid-state drive (SSD), etc. In some embodiments, the non-volatile memory 103 may also be a removable storage medium, such as a secure digital (SD) memory card, etc. In other embodiments, the non-volatile memory 103 may be used to store related instructions of the neural network model 10, asymmetric / symmetric quantization parameters, asymmetric / symmetric quantization constant data, etc., and may also be used to store the operational logic of a preset symmetric quantization operator.

[0155] Specifically, system memory 102 and non-volatile memory 103 may each include a temporary copy and a permanent copy of instruction 107. Instruction 107 may include, when executed by processor 101A, causing electronic device 100 to implement the method for running the neural network model provided in the embodiments of this application.

[0156] The communication interface 104 may include a transceiver for providing a wired or wireless communication interface for the electronic device 100, thereby enabling communication with any other suitable device via one or more networks. In some embodiments, the communication interface 104 may be integrated into other components of the electronic device 100, for example, the communication interface 104 may be integrated into the processor 101A. In some embodiments, the electronic device 100 may communicate with other devices through the communication interface 104; for example, the electronic device 100 may obtain a neural network model to be run from other electronic devices through the communication interface 104.

[0157] Input / output (I / O) device 105 may include input devices such as keyboard, mouse, etc., and output devices such as monitor, etc. Users can interact with electronic device 100 through input / output (I / O) device 105.

[0158] System control logic 106 may include any suitable interface controller to provide any suitable interface to other modules of electronic device 100. For example, in some embodiments, system control logic 106 may include one or more memory controllers to provide an interface to system memory 102 and non-volatile memory 103.

[0159] In some embodiments, at least one of the processors 101A may be packaged together with the logic of one or more controllers for system control logic 106 to form a system in package (SiP). In other embodiments, at least one of the processors 101A may also be integrated on the same chip with the logic of one or more controllers for system control logic 106 to form a SoC.

[0160] It is understood that electronic device 100 can be any electronic device capable of running DCLS, including but not limited to mobile phones, wearable devices (such as smartwatches), tablets, desktops, laptops, handheld computers, notebook computers, ultra-mobile personal computers (UMPCs), netbooks, as well as cellular phones, personal digital assistants (PDAs), augmented reality (AR) / virtual reality (VR) devices, etc., which are not limited in the embodiments of this application.

[0161] Understandable. Figure 10 The structure of the electronic device 100 shown is merely an example. In other embodiments, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0162] Various embodiments of the mechanisms disclosed in this application can be implemented in hardware, software, firmware, or combinations of these implementation methods. Embodiments of this application can be implemented as computer programs or program code executable on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0163] Program code can be applied to input instructions to execute the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor such as, for example, a Digital Signal Processor (DSP), a microcontroller, an Application Specific Integrated Circuit (ASIC), or a microprocessor.

[0164] The program code can be implemented using a high-level procedural language or an object-oriented programming language to communicate with the processing system. Assembly language or machine language can also be used when needed. In fact, the mechanisms described in this application are not limited to any particular programming language. In either case, the language can be a compiled language or an interpreted language.

[0165] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored thereon on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed via a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form, including but not limited to floppy disks, optical disks, CD-ROMs, magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable storage for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in the form of electrical, optical, acoustic, or other forms of propagated signals. Therefore, machine-readable media include any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine-readable (e.g., computer-readable) form.

[0166] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0167] It should be noted that all units / modules mentioned in the device embodiments of this application are logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed in this application. Furthermore, to highlight the innovative aspects of this application, the above-described device embodiments of this application have not introduced units / modules that are not closely related to solving the technical problems proposed in this application. This does not mean that the above-described device embodiments do not contain other units / modules.

[0168] It should be noted that, in the examples and description of this patent, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0169] Although this application has been illustrated and described with reference to certain preferred embodiments thereof, those skilled in the art should understand that various changes in form and detail may be made thereto without departing from the spirit and scope of this application.

Claims

1. A signal verification method, applied to electronic equipment, characterized in that, The electronic device includes a dual-core lockstep system, a checksum generation unit, and a checksum unit; the method includes: The verification code generation unit obtains the verification signal of the dual-core lockstep system. The verification signal includes a first type of signal to be input into the dual-core lockstep system or to be output from the dual-core lockstep system. The first type of signal includes signals corresponding to functions that will be activated or used after the dual-core lockstep system is started. The check code generation unit calculates the value of the check bit of the first type of signal and transmits the first type of signal and the corresponding second type of signal to the check unit. The second type of signal is the signal corresponding to a function that will not be activated or used after the dual-core lockstep system is started. The second type of signal corresponding to the first type of signal to be input to the dual-core lockstep system includes the second type of signal to be input to the dual-core lockstep system. The second type of signal corresponding to the first type of signal to be output from the dual-core lockstep system includes the second type of signal included in the dual-core lockstep system. The verification unit determines whether the first type of signal is correct based on the second type of signal corresponding to the first type of signal and the value of the verification bit.

2. The signal verification method according to claim 1, characterized in that, The check code generation unit includes a first check code generation unit and a second check code generation unit; the verification unit includes a first verification unit and a second verification unit. When the first type of signal is the signal to be input into the dual-core lockstep system, the check code generation unit is the first check code generation unit, and the check unit is the first check unit; Corresponding to the case where the first type of signal is the signal of the dual-core lockstep system to be output, the check code generation unit is the second check code generation unit, and the check unit is the second check unit; The first check code generation unit and the second check unit are located outside the dual-core lockstep system, while the second check code generation unit and the first check unit are located inside the dual-core lockstep system.

3. The signal verification method according to claim 1, characterized in that, The checksum generation unit calculates the check bit value of the first type of signal based on the second type of signal corresponding to the first type of signal, including: The check code generation unit calculates the value of the check bit of the first type of signal based on the second type of signal corresponding to the first type of signal using a parity check algorithm.

4. The signal verification method according to claim 1, characterized in that, When the first type of signal is an error signal, the verification unit outputs an error message.

5. The signal verification method according to claim 1, characterized in that, When the dual-core lockstep system is started The dual-core lockstep system uses the first type of signal; The dual-core lockstep system rejects the second type of signal.

6. The signal verification method according to claim 5, characterized in that, When the dual-core lockstep system is started, the original function of the second type of signal is disabled.

7. A SOC, characterized in that, The SOC includes a dual-core lockstep system, a checksum generation unit, and a check unit; including: The verification code generation unit is used to obtain the verification signal of the dual-core lockstep system. The verification signal includes a first type of signal to be input into the dual-core lockstep system or to be output from the dual-core lockstep system. The first type of signal includes signals corresponding to functions that will be activated or used after the dual-core lockstep system is started. The check code generation unit is used to calculate the value of the check bit of the first type of signal and transmit the first type of signal and the corresponding second type of signal to the check unit. The second type of signal is the signal corresponding to a function that will not be activated or used after the dual-core lockstep system is started. The second type of signal corresponding to the first type of signal to be input to the dual-core lockstep system includes the second type of signal to be input to the dual-core lockstep system. The second type of signal corresponding to the first type of signal to be output from the dual-core lockstep system includes the second type of signal included in the dual-core lockstep system. The verification unit is used to determine whether the first type of signal is correct based on the second type of signal corresponding to the first type of signal and the value of the verification bit.

8. A readable medium, characterized in that, The readable medium stores instructions that, when executed on an electronic device, cause the electronic device to perform the signal verification method according to any one of claims 1 to 6.

9. An electronic device, characterized in that, It includes: a memory for storing instructions executed by one or more processors of the electronic device, and the processor being one of the one or more processors of the electronic device for performing the signal verification method according to any one of claims 1 to 6.

10. A computer program product, characterized in that, include: An execution instruction is stored in a readable storage medium, and at least one processor of the electronic device can read the execution instruction from the readable storage medium. The at least one processor executes the execution instruction to cause the electronic device to implement the signal verification method according to any one of claims 1 to 6.

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