handshake circuit

Abstract

A handshake circuit portion 6 is provided for performing a handshake procedure to facilitate data reception by the associated circuit portion 4. The handshake circuit portion 6 comprises a request signal input 22 for detecting a request signal from a further handshake circuit portion 10 associated with a further circuit portion 8, an acknowledge signal output 24 for asserting an acknowledge signal to the further handshake circuit portion 10, and a block signal input 46 for detecting a block signal from the associated circuit portion 4. The handshake circuit portion 6 is arranged to detect the request signal via the request signal input 22, to determine whether the block signal input 46 is present with the block signal, and to assert the acknowledge signal via the acknowledge signal output 24 in response to the request signal if the block signal input 46 is not present with the block signal.

Description

Technical Field

[0001] The present invention relates to a handshake circuit section and a method for transmitting data between circuit sections. Background Technology

[0002] In electronic systems such as System-on-a-Chip (SoC), there may be two or more clock and / or power domains, which are different parts of a chip operating at different frequencies or logic voltages. Transferring data between different clock and / or power domains can be problematic because there is no common clock that can be synchronized with the data transmission protocol or a common voltage that can be used to send data signals.

[0003] Conventionally, handshake protocols can be used to facilitate data transmission between different domains. Typically, this uses a data line (or multiple data lines for parallel data transmission), a request line, and an acknowledgment line between the transmitter and receiver, possibly using voltage level shifters to accommodate differences in logic voltages. In a four-phase handshake, the transmitter (as the source) asserts the data it wishes to transmit on the data line and then sends a request signal to the receiver (Phase 1). The receiver (as the sink) sees the request signal, reads the data line, and then sends an acknowledgment signal to the transmitter (Phase 2). The transmitter sees the acknowledgment signal and decrements the request signal (Phase 3). Finally, the receiver sees the decremented request signal and decrements the acknowledgment signal (Phase 4). This cycle can be repeated until all data has been transmitted. Because each data bit is explicitly acknowledged by the receiver, transmission can be reliable even if the transmitter and receiver are out of sync or if level shifters introduce delays. Summary of the Invention

[0004] The applicant has recognized that the existing handshake protocol can be improved.

[0005] According to a first aspect of the present invention, a handshake circuit portion is provided for performing a handshake process to facilitate data reception of an associated circuit portion, the handshake circuit portion comprising:

[0006] The request signal input is used to detect a request signal from another handshake circuit section associated with another circuit section;

[0007] The confirmation signal output terminal is used to assert a confirmation signal for the other handshake circuit section.

[0008] The blocking signal input terminal is used to detect the blocking signal from the associated circuit section;

[0009] The handshake circuit section is arranged as follows:

[0010] The request signal is detected via the request signal input terminal;

[0011] Determine whether a blocking signal exists at the input terminal of the blocking signal; and

[0012] If there is no blocking signal at the blocking signal input terminal, the request signal is responded to via an assertion confirmation signal at the confirmation signal output terminal.

[0013] Therefore, those skilled in the art will see that the handshake circuit portion according to the invention can prevent the sending of an acknowledgment when the blocking signal is present. This allows the associated circuit portion to block data until it is ready to receive data, thereby improving the reliability of data transmission between circuit portions. In contrast, conventional handshake protocols always immediately acknowledge incoming requests to avoid data transmission delays. The applicant has recognized that while it is safe to assume in some cases that the associated circuit portion is always ready to receive data, this assumption may not always be accurate and may lead to data loss and / or errors. In embodiments of the invention, upon receiving the acknowledgment signal, the other circuit portion (i.e., the portion sending the data) can be certain that the circuit portion (i.e., the receiver) has correctly received the data.

[0014] Of course, when there is no blocking signal at the confirmation blocking signal input terminal, the handshake circuit part can immediately assert the confirmation signal to respond to the request signal, thereby ensuring that the handshake process is not unnecessarily delayed.

[0015] In some embodiments, the handshake circuit portion includes an AND logic gate, wherein the inverted forms of the request signal input and the blocking signal input serve as inputs, and the acknowledgment signal output serves as an output. This can represent a simplified implementation of the blocking function.

[0016] The handshake circuit section may include one or more synchronization components disposed on the request signal input terminal to ensure correct reception of the request signal (e.g., from a different clock or power domain) and to avoid metastability issues. For example, the synchronization components may include means for storing the input signal (e.g., the request signal) and for transmitting the stored input signal to the remainder of the handshake circuit section (e.g., after a clock transition of the handshake circuit section's clock). In some embodiments, the synchronization components may include one or more flip-flops connected in series.

[0017] The handshake circuitry can be configured to participate in a four-phase handshake process. The handshake circuitry can be arranged as a receiver in the four-phase handshake process, while another handshake circuitry acts as a transmitter. The four-phase handshake process allows the handshake circuitry to explicitly acknowledge each data bit (or group of data bits) sent by the other circuitry, thereby improving the reliability of data transmission. A request signal from the other handshake circuitry may include the first phase of the four-phase handshake. It is asserted that the acknowledgment signal may include the second phase of the four-phase handshake.

[0018] In some embodiments, the handshake circuitry is configured to detect whether the request signal has been downgraded after asserting the acknowledgment signal (i.e., the third stage of a four-phase handshake). The handshake circuitry may be configured to downgrade the acknowledgment signal in response to detecting that the request signal has been downgraded (the fourth stage of a four-phase handshake).

[0019] This invention extends to a circuit system comprising:

[0020] First circuit section;

[0021] The first handshake portion according to the first aspect of the invention disclosed herein is associated with the first circuit portion;

[0022] The second circuit section is connected to the first circuit section via one or more data lines; and

[0023] The second handshake circuit section is associated with the second circuit section;

[0024] The first and second handshake circuit sections are arranged to perform a handshake process including request and acknowledgment signals to facilitate data transmission from the second circuit section to the first circuit section using the one or more data lines.

[0025] The use of the handshake circuit portion allows the first circuit portion to reliably receive data from the second circuit portion, even when the second circuit portion operates in a different domain (e.g., a different clock and / or power domain) than the first circuit portion. In some embodiments, the first handshake circuit portion and the first circuit portion operate in a first domain (e.g., a first clock and / or power domain). The second handshake circuit portion and the second circuit portion may operate in a second domain (e.g., a second clock and / or power domain). The first domain and the second domain may be different. In one set of embodiments, the circuit system includes a first clock having a first frequency, the first clock being arranged to provide clock control for a first clock domain including the first handshake circuit portion and the first circuit portion; and a second clock having a second frequency, the second clock being arranged to provide clock control for a second clock domain including the second handshake circuit portion and the second circuit portion.

[0026] The first circuit section can also be used to transmit data to the second circuit section using the one or more data lines (i.e., the circuit system can facilitate bidirectional data transmission). In such embodiments, the first and second handshake circuit sections can be arranged to exchange request and acknowledgment signals as part of a handshake protocol to facilitate data transmission from the first circuit section to the second circuit section using the one or more data lines. The second handshake circuit section may also include handshake circuit sections as disclosed herein, i.e., including a blocking signal input for detecting a blocking signal from the second circuit section to facilitate reliable bidirectional data transmission. In general, the features disclosed herein regarding handshake circuit sections can be applied to the first and / or second handshake circuit sections of the circuit system, and vice versa.

[0027] The circuit system may include a system-on-a-chip (SoC), for example, wherein the first handshake circuit portion and the first circuit portion include a first subsystem of the SoC, and the second handshake circuit portion and the second circuit portion include a second subsystem of the SoC.

[0028] The first and second circuit portions can be connected via a single data line, allowing a single data bit to be transmitted in each handshake cycle. In some embodiments, the first and second circuit portions are connected via multiple data lines (e.g., forming a bus), thereby allowing multiple data bits to be transmitted in parallel in each handshake cycle.

[0029] The circuit system may include multiple first and second handshake circuit sections, i.e., facilitating multiple parallel handshakes. In some embodiments, the circuit system may include up to 64 or more first and / or second handshake circuit sections.

[0030] As described above, the use of the blocking signal prevents the request from being acknowledged before the receiver is ready to receive data. This can lead to unexpected delays in data transmission. In a conventional handshake protocol, the transmitter circuitry triggers a handshake request when data transmission is needed. However, if the handshake process is delayed, the transmitter may attempt to trigger a further handshake request before the previous handshake is complete. This can result in errors and data loss.

[0031] In some embodiments, the second handshake circuit portion includes:

[0032] The request signal output terminal is used to assert the request signal in the first handshake circuit section.

[0033] The confirmation signal input terminal is used to detect the confirmation signal from the first handshake circuit section;

[0034] The source command input terminal is used to receive transmission commands from the second circuit section;

[0035] The overflow signal output terminal is used to send an overflow signal to the second circuit section.

[0036] The second handshake circuit section is arranged as follows:

[0037] Upon receiving a transmission command from the second circuit section via the source command input, a handshake process with the first handshake circuit section is performed by asserting a request signal via the request signal output and detecting an acknowledgment signal via the acknowledgment signal input; and

[0038] If a further transmission command is received via the source command input before the handshake process is completed, an overflow signal is sent to the second circuit section via the overflow signal output.

[0039] Therefore, in such embodiments, the second handshake circuitry is arranged (using the overflow signal) to indicate when a new transmission command cannot be executed because the previous handshake was incomplete. The second circuitry can then take appropriate measures, such as later repeating the transmission command, taking compensatory measures (e.g., pausing the relevant ongoing process), or simply logging the overflow to aid in debugging. This can reduce errors and data loss. The transmission command can also be referred to as a "source pulse".

[0040] Once the acknowledgment signal is detected, the handshake process can be considered complete. However, in some embodiments, the handshake process further includes downgrading the request signal upon detection of the acknowledgment signal, and the handshake process may not be considered complete until the request signal has been downgraded. The handshake process may also include downgrading the acknowledgment signal (i.e., via the first handshake circuitry) after the request signal has been downgraded. In some such embodiments, the handshake process may not be considered complete until the second handshake circuitry detects that the acknowledgment signal has been downgraded. Generating an overflow signal for any transmission commands received before the acknowledgment signal is downgraded further reduces the possibility of errors and / or data loss, as any transmission commands that may interfere with the previous handshake may generate an overflow signal.

[0041] In some embodiments, the second handshake circuitry is configured to provide an indication of when the handshake process is in progress (e.g., when a request signal or acknowledgment signal is currently asserted). For example, the second handshake circuitry may include a handshake active signal output for asserting a handshake active signal. The second handshake circuitry may be configured to assert a handshake active signal when a request signal is asserted at the request signal output and / or when an acknowledgment signal is detected at the acknowledgment signal input. This can facilitate the implementation of the overflow signal function (i.e., and therefore when the overflow signal function should be active) by providing a single signal indicating when the handshake process is in progress.

[0042] In some such embodiments, the second handshake circuit portion includes an AND logic gate, wherein the handshake active signal output and the source command input serve as inputs, and the overflow signal output serves as an output. This can represent a simplified implementation of the overflow function.

[0043] In some sets of embodiments, additionally or alternatively, the second handshake circuitry is arranged to indicate to the second circuitry when the acknowledgment signal is detected. The second handshake circuitry may be arranged to indicate to the second circuitry when the acknowledgment signal is no longer asserted (i.e., once the handshake process is fully completed), ensuring that the operation taken by the second circuitry in response cannot interfere with the ongoing handshake process. For example, the second handshake circuitry may include a request acknowledgment signal output for asserting the request acknowledgment signal, and may be arranged to assert the request acknowledgment signal upon detection of the acknowledgment signal or upon detection of a subsequent decrease in the acknowledgment signal.

[0044] The second handshake circuit may include a synchronization component on the confirmation signal input terminal to avoid metastability issues.

[0045] As described above, the circuit system can facilitate bidirectional data transmission. Therefore, those skilled in the art will understand that each of the first and second handshake circuit portions can function as a transmitter (also referred to as a source) and a receiver (also referred to as a receiver). Each or any of the first and second handshake circuit portions may include features providing the blocking and / or overflow functionality disclosed herein. In other words, in some embodiments, the first handshake circuit portion includes:

[0046] The request signal output terminal is used to assert the request signal in the second handshake circuit section.

[0047] The confirmation signal input terminal is used to detect the confirmation signal from the second handshake circuit section;

[0048] The source command input terminal is used to receive transmission commands from the first circuit section;

[0049] The overflow signal output terminal is used to send an overflow signal to the first circuit section.

[0050] The first handshake circuit section is arranged as follows:

[0051] The source command input terminal receives the transmission command from the first circuit section.

[0052] The handshake process with the second handshake circuit is performed by asserting the request signal via the request signal output terminal and detecting the acknowledgment signal via the acknowledgment signal input terminal; and

[0053] If a further transmission command is received via the source command input before the handshake process is completed, an overflow signal is sent to the first circuit section via the overflow signal output.

[0054] Additionally or alternatively, in some embodiments, the second handshake circuit portion includes:

[0055] The request signal input terminal is used to detect the request signal from the first handshake circuit section;

[0056] The confirmation signal output terminal is used to assert a confirmation signal for the first handshake circuit section.

[0057] The blocking signal input terminal is used to detect the blocking signal from the second circuit section;

[0058] The handshake circuit section is arranged as follows:

[0059] The request signal is detected via the request signal input terminal;

[0060] Determine whether a blocking signal exists at the input terminal of the blocking signal; and

[0061] If there is no blocking signal at the blocking signal input terminal, the request signal is responded to by asserting an acknowledgment signal via the acknowledgment signal output terminal.

[0062] For example, both the first and second handshake circuit sections can be arranged to receive blocking signals from their respective first and second circuit sections, which, when the relevant handshake circuit section acts as a receiver, block the assertion of the acknowledgment signal. Both the first and second handshake circuit sections can also be arranged to send overflow signals to their respective first and second circuit sections when a further transmission command is received before the completion of the previous handshake process.

[0063] According to a second aspect of the present invention, a method is provided for transmitting data from a second circuit portion associated with a second handshake portion to a first circuit portion associated with a first handshake portion, the method comprising the steps of:

[0064] The second circuit section asserts the data signal;

[0065] The first and second handshake circuit sections perform the handshake process; and

[0066] The first circuit section receives the data signal;

[0067] The handshake process includes:

[0068] The second handshake circuit section asserts the request signal;

[0069] The first handshake circuit section detects the request signal;

[0070] The first handshake circuit section determines whether the first circuit section is ready to receive the data signal; and

[0071] If the first circuit section is ready to receive the data signal, the first handshake circuit section asserts an acknowledgment signal.

[0072] The first handshake circuit portion determining whether the first circuit portion is ready to receive the data signal may include detecting whether the first circuit portion asserts a blocking signal.

[0073] In some embodiments, the handshake process includes a four-stage handshake process. The first handshake circuit portion can detect the confirmation signal and, in response, lower the request signal. The second handshake circuit portion can detect the lowered request signal and, in response, lower the confirmation signal.

[0074] According to some embodiments of the present invention, the method further includes the following steps:

[0075] The second handshake circuit section initiates the handshake process by asserting the request signal in response to a transmission command from the second circuit section;

[0076] The second handshake circuit section receives further transmission commands from the second circuit section; and

[0077] If the further transmission command is received before the handshake process is completed, the second handshake circuit section sends an overflow signal to the second circuit section.

[0078] Although, as described above, there is a specific synergy between the blocking and overflow functions disclosed above (e.g., the overflow signal may be useful in cases where the blocking signal causes an unexpected delay to the assertion of the acknowledgment signal), the applicant considers the overflow feature to be original, and therefore, from a third aspect, the present invention provides a handshake circuit portion for facilitating data transmission between associated circuit portions, comprising:

[0079] The request signal output is used to assert a request signal for another handshake circuit section.

[0080] The confirmation signal input terminal is used to detect the confirmation signal from the other handshake circuit section;

[0081] The source input terminal is used to receive transmission commands from the associated circuit section;

[0082] The overflow signal output terminal is used to send an overflow signal to the associated circuit section;

[0083] The handshake circuit section is arranged as follows:

[0084] Receive transmission commands via the source input terminal;

[0085] The handshake process with the other handshake circuit section is performed by asserting the request signal via the request signal output and detecting the acknowledgment signal via the acknowledgment signal input; and

[0086] If a further transmission command is received via the source input before the handshake process is completed, an overflow signal is sent via the overflow signal output.

[0087] A third aspect of the invention extends to a circuit system comprising:

[0088] First circuit section;

[0089] The first handshake portion is associated with the first circuit portion;

[0090] The second circuit section is connected to the first circuit section via one or more data lines; and

[0091] The second handshake circuit portion is based on and associated with the second aspect of the invention disclosed herein;

[0092] The first and second handshake circuit sections are arranged to perform a handshake process including request and acknowledgment signals to facilitate data transmission from the second circuit section to the first circuit section using the one or more data lines.

[0093] According to a fourth aspect of the present invention, a method is provided for transmitting data from a second circuit portion associated with a second handshake portion to a first circuit portion associated with a first handshake portion, the method comprising the steps of:

[0094] The second circuit section asserts the data signal;

[0095] The second circuit section sends a transmission command to the second handshake circuit section;

[0096] The first and second handshake circuit sections perform the handshake process; and

[0097] The second circuit section sends further transmission commands to the second handshake circuit section;

[0098] If the further transmission command is received before the handshake process is completed, the second handshake circuit portion sends an overflow signal to the second circuit portion; and

[0099] The first circuit section receives the data signal.

[0100] Features of any aspect or embodiment described herein may be applied, where appropriate, to any other aspect or embodiment described herein. When referring to different embodiments, it should be understood that these embodiments are not necessarily different but may overlap. It should be understood that all preferred features of the first and / or second handshake circuit portions according to the first aspect described above may also be applied to the first and / or second handshake circuit portions according to other aspects of the invention. For example, a single handshake circuit portion may include the blocking functions of the first and second aspects (when acting as a receiver) and the overflow functions of the third and fourth aspects (when acting as a transmitter). Attached Figure Description

[0101] One or more non-limiting examples will now be described by way of example and with reference to the accompanying drawings, wherein:

[0102] Figure 1 This is a schematic diagram of a system-on-a-chip (SoC) according to an embodiment of the present invention;

[0103] Figure 2and Figure 3 It is shown Figure 1 Timing diagram of the operation of the on-chip system;

[0104] Figure 4 This is a schematic diagram of a handshake circuit portion according to another embodiment of the present invention;

[0105] Figure 5 and Figure 6 yes Figure 4 A partial view of the handshake circuit section shown; and

[0106] Figure 7 It is shown Figures 4 to 6 The timing diagram of the handshake circuit section shown is shown. Detailed Implementation

[0107] Figure 1 The system-on-a-chip (SoC) 2 is shown, including a first circuit section 4, a first handshake circuit section 6, a second circuit section 8, and a second handshake circuit section 10.

[0108] The first circuit section 4 and the first handshake circuit section 6 operate in a first clock domain 12, controlled by a first clock 3 operating at a first frequency. The second circuit section 8 and the second handshake circuit section 10 operate in a second clock domain 14, controlled by a second clock 15 operating at a second frequency different from the first frequency. The first circuit section 4 and the second circuit section 8 are connected via a data bus 16 comprising multiple data lines. However, because the two clock domains 12 and 14 operate at different frequencies, the data bus 16 cannot be used for conventional synchronous data transmission. Instead, a handshake protocol is used for data transmission, facilitated by the first handshake circuit section 6 and the second handshake circuit section 10, which will be further described below.

[0109] The first handshake circuit section 6 includes a source request signal output terminal 18, a source confirmation signal input terminal 20, a receiver request signal input terminal 22, and a receiver confirmation signal output terminal 24. These are connected to the corresponding inputs and outputs of the second handshake circuit section 10 to allow the handshake process to be performed. Specifically, the second handshake circuit section 10 includes a receiver request signal input terminal 26 connected to the source request signal output terminal 18 of the first handshake circuit section 6, a receiver confirmation signal output terminal 28 connected to the source confirmation signal input terminal 20 of the first handshake circuit section 6, a source request signal output terminal 30 connected to the receiver request signal input terminal 22 of the first handshake circuit section 6, and a source confirmation signal input terminal 32 connected to the receiver confirmation signal output terminal 24 of the first handshake circuit section 6.

[0110] These connections allow both handshake circuit sections 6 and 10 to send (i.e., as the source) and receive (as the receiver) handshake requests and corresponding acknowledgments. This allows data to be transmitted in either direction between the first circuit section 4 and the second circuit section 8.

[0111] The first circuit section 4 includes a source pulse output terminal 34 (i.e., for outputting transmission commands), a receiving pulse input terminal 36, a blocking signal output terminal 38, and an overflow signal input terminal 40. Correspondingly, the first handshake circuit section 6 includes a source pulse input terminal 42 connected to the source pulse output terminal 34 of the first circuit section 4, a receiving pulse output terminal 44 connected to the receiving pulse input terminal 36, a blocking signal input terminal 46 connected to the blocking signal output terminal 38, and an overflow signal output terminal 48 connected to the overflow signal input terminal 40.

[0112] Equivalently, the second circuit section 8 includes a source pulse output terminal 50, a receiving pulse input terminal 52, a blocking signal output terminal 54, and an overflow signal input terminal 56, and the second handshake circuit section 10 includes a source pulse input terminal 58, a receiving pulse output terminal 60, a blocking signal input terminal 62, and an overflow signal output terminal 64.

[0113] Now refer to Figure 2 and Figure 3 The timing diagram shown describes the operation of SoC 2.

[0114] Figure 2 Timing diagram 100 is shown, illustrating the operation of the first handshake circuit section 6 as the receiving end (i.e., receiving a handshake request to facilitate data transmission from the second circuit section 8 to the first circuit section 4).

[0115] Figure 2 The status of the clock signal 102 "ck" of the first clock 3, the receiving end pulse output terminal 44 "sinkRx", the receiving end request signal input terminal 22 "sinkReq", the receiving end confirmation signal output terminal 24 "sinkAck", and the blocking signal input terminal 46 "blockSinkAck" are shown.

[0116] In use, the second handshake section 10 initiates the handshake process for transferring data from the second circuit section to the first circuit section by asserting the source request signal (i.e., setting the source request signal output 30 high - not shown). This occurs at time t1 at the receiver request signal input 22 and is detected by the first handshake circuit section 6. Because the first clock 3 is not synchronized with the second clock 15, this is unlikely to occur along with the rising edge of the first clock signal 102.

[0117] At t2, on the next rising edge of the first clock signal 102, the first handshake circuit section 6 immediately acknowledges the request by asserting an acknowledgment signal (setting logic high) on the received-end acknowledgment signal output terminal 24. The second handshake circuit section 10 detects the acknowledgment signal and decrements the request signal 22. At t3, this decrementing of the request signal 22 triggers a received-end pulse on the received-end pulse output terminal 44 on the next rising edge. This received-end pulse is received by the first circuit section 4 (via the received-end pulse input terminal 36) and causes the first circuit section 4 to sample the data present on the data bus 16. Also at t3, the first handshake circuit section 6 decrements the received-end acknowledgment signal 24, and the handshake process is complete.

[0118] Also at t3, in response to receiving the receiving pulse 44 via the receiving pulse input 36 and thus knowing that the handshake process is complete, the first circuit section 4 asserts a blocking signal at its blocking signal output 38, which appears at the blocking signal input 46 of the first handshake circuit section 6. Alternatively (shown in dashed lines), the first circuit section 4 may assert the blocking signal at its blocking signal output 38 at a later time t4 on the falling edge of the receiving pulse 44. This further ensures that the blocking signal does not interfere with the previous handshake process. Preferably, the blocking signal is set within a few clock cycles of the receiving pulse being triggered or immediately thereafter to ensure that confirmation of potential new requests is blocked.

[0119] The blocking signal indicates that the first circuit section 4 is processing data received as a result of a previous handshake process. Its presence at the blocking signal input 46 prevents the first handshake circuit section 6 from acknowledging any further request signals (i.e., delaying any future handshake process). For example, at a later time t5, while the blocking signal is still asserted, the first handshake section 6 receives another request signal at the receiving end request signal input 22. However, due to the blocking signal, this request is not immediately acknowledged. Instead, when the blocking signal 46 is de-emphasized, the first handshake circuit section 6 only asserts an acknowledgment signal at the receiving end acknowledgment signal output 24 at a later time t6.

[0120] By delaying the confirmation until the blocking signal decreases, data transmission becomes more reliable because the first handshake portion 6 ensures that the first circuit portion 4 is ready to receive the data associated with the request before confirming the request.

[0121] Figure 3 Timing diagram 200 is shown, illustrating the operation of the second handshake circuit section 6 as the source end (i.e., sending a handshake request to facilitate data transmission from the second circuit section 8 to the first circuit section 4).

[0122] Figure 3The status of the clock signal 202 "ck" of the second clock 15, the source pulse input terminal 58 "sourceTx", the source request signal output terminal 30 "sourceReq", the source confirmation signal input terminal 32 "sourceAck_a", and the overflow signal output terminal 64 "sourceOverflow" are shown.

[0123] Figure 3 It also shows a request confirmation signal “sourceAcked”, which indicates when the confirmation signal is no longer asserted, and a handshake active signal “sourceActive”, which indicates when the handshake process is in progress.

[0124] In use, the second handshake section 10 initiates a handshake process to transfer data from the second circuit section to the first circuit section in response to a source pulse (i.e., a transmission command) sent by the second circuit section 8 to the source pulse input terminal 58. At time t1, in response to the source pulse, the second handshake section 10 asserts a source request signal at the source request signal output terminal 30.

[0125] Subsequently, at time t2, the second circuit section 8 sends another source-end pulse. However, the source-end request signal on the source-end request signal output terminal 30 triggered by the previous pulse remains valid, and no acknowledgment has been received. Therefore, another source-end request signal cannot be sent yet (i.e., another handshake process cannot be initiated). However, to avoid errors in the second circuit section 8, the second handshake circuit section 10 asserts the overflow signal on the overflow signal output terminal 64 to indicate to the second circuit section 8 that a new request signal cannot be sent yet. The second circuit section 8 can then respond accordingly, potentially avoiding errors and / or data loss.

[0126] At a later time t3, the first handshake circuit section 6 confirms the source request signal by asserting an acknowledgment signal at the receiver acknowledgment signal output terminal 24 (as previously referenced). Figure 2 As described, the source request signal appears on the source acknowledgment signal input 32. Then, at time t4, on the next rising edge, the second handshake circuit section 10 lowers the source request signal 30.

[0127] Also at time t4, the second circuit section 8 sends another source pulse to the source pulse input terminal 58. However, as before, the previous handshake process is still in progress (the confirmation signal is still asserted). Therefore, the second handshake circuit section 10 asserts another overflow signal at the overflow signal output terminal 64 to indicate to the second circuit section 8 that a new request signal cannot be sent yet.

[0128] At a later time t5, the first handshake circuit section 6 detects the decreased request signal on the source request signal output terminal 30 and decreases the acknowledgment signal on the source acknowledgment signal input terminal 32, ending the handshake process. At time t6, the second circuit section 8 sends another source pulse to the source pulse input terminal 58. Since the previous handshake process is now complete, the second handshake section 10 responds by asserting the source request signal again on the source request signal output terminal 30, and the handshake process restarts.

[0129] Figure 4 A schematic diagram of a handshake circuit portion 400 according to another embodiment of the present invention is shown. For example, the handshake circuit portion 400 may replace the reference diagram. Figures 1 to 3 The first handshake portion 6 or the second handshake portion 10 of the described embodiment is effective.

[0130] As in the previously described embodiments, the handshake circuit section 400 facilitates pulse transmission between the power / clock domains. This is performed via request and acknowledgment signals. The handshake circuit section 400 is generally connected in pairs, from the source end to the receiver end. Figure 4 As shown, the left side can connect to the paired handshake circuit portion, while the right side can connect to the parent circuit portion. The handshake circuit portion 400 can provide multiple source (transmitter) and receiver connections. In the diagram, NSRC represents the total number of source connections, and NSINK represents the total number of receiver connections.

[0131] The handshake circuit section 400 includes four handshake connections for interfacing with another handshake circuit section. These are a receive-end request input 402, a receive-end acknowledgment output 404, a source-end request output 406, and a source-end acknowledgment input 408. A synchronizer 409 (SSED) is provided on the receive-end request input 402 and the source-end acknowledgment input 408 to ensure correct reception of request and acknowledgment signals from different domains (e.g., different clocks or domains) (i.e., to avoid metastability issues). The synchronizer 409 may, for example, include one or more flip-flops arranged in series.

[0132] The handshake circuit section 400 also includes multiple connections for interfacing with the associated "parent" circuit section. These connections are the receiving pulse output 410, the blocking signal input 412, the source pulse input 414, the source refresh input 416, the source overflow output 418, the source active output 420, the protocol error output 422, the source acknowledgment output 424, and various clock and power connections 426.

[0133] In use, when a pulse sourceTx[N] is transmitted through the source connection N, sourceReq[N] is set high until sourceAck_a[N] is received, indicating that the request has been acknowledged by the other party. sourceActive is a status signal set when the source connection is busy. The status is busy when sourceReq[N] is set and / or the synchronous sourceAck_a[N] is set. powerReq is set as long as the connection is active. This can be used to request power for the handshake circuit section 400 itself and the receiving end pair.

[0134] Figure 5 This is a more detailed schematic diagram of a part of the handshake circuit section 400. Figure 5 As can be seen, the received-end acknowledgment output 404 (sinkAck[N]) includes the output of an AND gate 428 characterized by its inputs being the inverted form of the received-end request input 402 (sinkReq_a[N]) and the blocking signal input 412 (blockSinkAck[N]). This can be referenced above. Figure 2 The described implementation of the blocking function.

[0135] Figure 6 This is a more detailed schematic diagram of a part of the handshake circuit section 400. Figure 5 As can be seen, the source overflow output 418 (sourceOverflow[N]) output includes the output of an AND gate 430 characterized by source active output 420 (sourceActive[N]) and source pulse input 414 (sourceTx[N]) as inputs. This provides a reference to the above. Figure 3 The implementation of the described overflow function.

[0136] like Figure 6 As shown, synchronizer 431 (SSED) is also set on source flush input 416 (sourceFlush_a[N]).

[0137] Now refer to Figure 7 The timing diagram 700 shown describes Figures 4 to 6 The operation of the handshake circuit shown.

[0138] In operation, the handshake circuit section 400 receives a source pulse (i.e., a transmission command) via a source pulse input 414 (e.g., from an associated circuit section). The source pulse is stored in a flip-flop 432, which sets the source request output 406 (i.e., detected by the paired handshake circuit section acting as the receiver). This flip-flop 423 is cleared by an acknowledgment signal received at the source acknowledgment input 408 (sourceAck_a[N]) (i.e., from the paired handshake circuit section) or a refresh signal at the source refresh input 416 (sourceFlush_a[N]). The source connection is active when the source request is set (i.e., when the request signal is asserted at the source request output 406) or when the synchronization acknowledgment signal is set (i.e., when an acknowledgment signal is detected at the acknowledgment signal input 408). If the source connection is active, a new source pulse received at the source pulse input 414 causes an overflow signal to be sent via the source overflow output 418. An active source connection prompts the powerReq output to be asserted, indicating that the handshake circuit section 400 requires power.

[0139] like Figure 7 As seen, when a source request is asserted at the source request output terminal 406 or a source pulse is received at the source pulse input terminal 414 and a refresh signal is detected at the source refresh input terminal 416, a protocol error signal (protocolError[N]) is generated at the protocol error output terminal 422. When the acknowledgment signal at the acknowledgment signal input terminal 408 decreases, it indicates that the transmission has been completed, and a pulse is generated at the source acknowledgment output terminal 424.

[0140] When the handshake circuit section 400 is used between two domains that can be independently forced to close (e.g., between two independent blocks that do not have state control over each other), a flush by sourceFlush_a[N] (e.g., by the associated circuit section) can optionally be performed to clear any ongoing transmissions and block new transmissions. In this way, the handshake circuit section 400, acting as the source, will abandon its request and thus be able to enter a sleep state, and future source pulses will be blocked. When the handshake circuit section 400 is used between slave power domains, the source refresh input 416 signal can be permanently assigned to "0". If a refresh signal is detected during a handshake process or at the start of a new handshake, a pulse is generated on protocolError[n]. The refresh signal aborts the source request and sets the protocol error signal, and a new source pulse also sets the protocol error.

[0141] Although the invention has been described in detail with reference to only a limited number of embodiments, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions, or equivalent arrangements not previously described but equivalent to the scope of the invention. Furthermore, while various embodiments of the invention have been described, it should be understood that aspects of the invention may include only some of the embodiments described. Therefore, the invention should not be considered as limited by the foregoing description, but only by the scope of the appended claims.

Claims

1. A handshake circuit portion for performing a handshake process to facilitate data reception of an associated circuit portion, comprising: The request signal input is used to detect a request signal from another handshake circuit section associated with another circuit section; The confirmation signal output terminal is used to assert a confirmation signal for the other handshake circuit section. The blocking signal input terminal is used to detect the blocking signal from the associated circuit section; The handshake circuit section is arranged as follows: The request signal is detected via the request signal input terminal; Determine whether a blocking signal exists at the input terminal of the blocking signal; If a blocking signal is present, then prevent the acknowledgment signal from being sent; and If there is no blocking signal at the blocking signal input terminal, the request signal is responded to by asserting the confirmation signal via the confirmation signal output terminal.

2. The handshake circuit portion according to claim 1 includes an AND logic gate, which uses the inverted form of the request signal input terminal and the blocking signal input terminal as input terminals and the acknowledgment signal output terminal as output terminal.

3. The handshake circuit portion according to claim 1 or 2, comprising one or more synchronization components disposed on the request signal input terminal.

4. A circuit system, comprising: First circuit section; The first handshake circuit portion, as described in claim 1 and associated with the first circuit portion; The second circuit section is connected to the first circuit section via one or more data lines; as well as The second handshake circuit section is associated with the second circuit section; The first and second handshake circuit sections are arranged to perform a handshake process including request and acknowledgment signals to facilitate data transmission from the second circuit section to the first circuit section using the one or more data lines.

5. The circuit system according to claim 4, wherein, The first handshake circuit portion and the first circuit portion operate in a first domain, and the second handshake circuit portion and the second circuit portion operate in different second domains.

6. The circuit system of claim 4 or 5, comprising a first clock having a first frequency, arranged to clock a first clock domain including the first handshake circuit portion and the first circuit portion; and a second clock having a second frequency, arranged to clock a second clock domain including the second handshake circuit portion and the second circuit portion.

7. The circuit system according to claim 4 or 5, wherein, The first circuit section is used to transmit data to the second circuit section using one or more data lines.

8. The circuit system according to claim 7, wherein, The second handshake circuit section further includes a handshake circuit section, which includes a blocking signal input terminal for detecting a blocking signal from the second circuit section.

9. The circuit system according to claim 4 or 5, wherein, The first circuit section and the second circuit section are connected via multiple data lines.

10. The circuit system according to claim 4 or 5, wherein, The second handshake circuit includes: The request signal output terminal is used to assert the request signal in the first handshake circuit section. The confirmation signal input terminal is used to detect the confirmation signal from the first handshake circuit section; The source command input terminal is used to receive transmission commands from the second circuit section; The overflow signal output terminal is used to send an overflow signal to the second circuit section. The second handshake circuit section is arranged as follows: Upon receiving a transmission command from the second circuit section via the source command input, a handshake process with the first handshake circuit section is performed by asserting the request signal via the request signal output and detecting the acknowledgment signal via the acknowledgment signal input; and If a further transmission command is received via the source command input before the handshake process is completed, an overflow signal is sent to the second circuit section via the overflow signal output.

11. The circuit system according to claim 4 or 5, wherein, The second handshake circuit portion is configured to reduce the request signal when the acknowledgment signal is detected.

12. The circuit system according to claim 11, wherein, The first handshake circuit section is arranged to lower the acknowledgment signal after the request signal is lowered.

13. The circuit system according to claim 4 or 5, wherein, The second handshake circuit section is arranged to provide an indication of when the handshake process is in progress.

14. The circuit system according to claim 10, wherein, The second handshake circuit section includes a handshake active signal output terminal for asserting the handshake active signal.

15. The circuit system according to claim 14, wherein, The second handshake circuit section is configured to assert the handshake active signal when the request signal is detected at the request signal output terminal and / or when the acknowledgment signal is detected at the acknowledgment signal input terminal.

16. The circuit system according to claim 15, wherein, The second handshake circuit includes an AND logic gate, which uses the handshake active signal output terminal and the source command input terminal as input terminals and the overflow signal output terminal as output terminal.

17. The circuit system according to claim 4 or 5, wherein, The second handshake circuit portion is arranged to indicate to the second circuit portion when the confirmation signal is detected.

18. The circuit system according to claim 4 or 5, wherein, The second handshake circuit includes a synchronization component on the confirmation signal input terminal.

19. The circuit system according to claim 4 or 5, wherein, The first handshake circuit includes: The request signal output terminal is used to assert the request signal in the second handshake circuit section. The confirmation signal input terminal is used to detect the confirmation signal from the second handshake circuit section; The source command input terminal is used to receive transmission commands from the first circuit section; The overflow signal output terminal is used to send an overflow signal to the first circuit section. The first handshake circuit section is arranged as follows: The source command input terminal receives the transmission command from the first circuit section. The handshake process with the second handshake circuit is performed by asserting the request signal via the request signal output terminal and detecting the acknowledgment signal via the acknowledgment signal input terminal; and If a further transmission command is received via the source command input before the handshake process is completed, an overflow signal is sent to the first circuit section via the overflow signal output.

20. The circuit system according to claim 4 or 5, wherein, The second handshake circuit includes: The request signal input terminal is used to detect the request signal from the first handshake circuit section; The confirmation signal output terminal is used to assert a confirmation signal for the first handshake circuit section. The blocking signal input terminal is used to detect the blocking signal from the second circuit section; The handshake circuit section is arranged as follows: The request signal is detected via the request signal input terminal; Determine whether a blocking signal exists at the input terminal of the blocking signal; and If there is no blocking signal at the blocking signal input terminal, the request signal is responded to by asserting an acknowledgment signal via the acknowledgment signal output terminal.

21. A method for transferring data from a second circuit portion associated with a second handshake circuit portion to a first circuit portion associated with a first handshake circuit portion, the method comprising the steps of: The second circuit section asserts the data signal; The first and second handshake circuit sections perform the handshake process; as well as The first circuit section receives the data signal; The handshake process includes: The second handshake circuit section asserts the request signal; The first handshake circuit section detects the request signal; The first handshake circuit section determines whether the first circuit section is ready to receive the data signal; If the first circuit section is not ready to receive the data signal, the first handshake circuit section prevents the confirmation signal from being sent; and If the first circuit section is ready to receive the data signal, the first handshake circuit section asserts an acknowledgment signal.

22. The method according to claim 21, wherein, The first handshake circuit section determines whether the first circuit section is ready to receive the data signal by detecting whether the first circuit section asserts a blocking signal.

23. The method according to claim 21 or 22, further comprising the step of: The second handshake circuit section responds to a transmission command from the second circuit section by initiating the handshake process by asserting the request signal; The second handshake circuit section receives further transmission commands from the second circuit section; as well as If the further transmission command is received before the handshake process is completed, the second handshake circuit section sends an overflow signal to the second circuit section.

24. A handshake circuit portion for facilitating data transmission between associated circuit portions, comprising: The request signal output is used to assert a request signal for another handshake circuit section. The confirmation signal input terminal is used to detect the confirmation signal from the other handshake circuit section; The source input terminal is used to receive transmission commands from the associated circuit section; The overflow signal output terminal is used to send an overflow signal to the associated circuit section; The handshake circuit section is arranged as follows: Receive transmission commands via the source input terminal; The handshake process with the other handshake circuit section is performed by asserting the request signal via the request signal output terminal and detecting the confirmation signal via the confirmation signal input terminal. as well as If a further transmission command is received via the source input before the handshake process is completed, an overflow signal is sent via the overflow signal output.

25. A circuit system comprising: First circuit section; The first handshake circuit section is associated with the first circuit section; The second circuit section is connected to the first circuit section via one or more data lines; as well as The second handshake circuit portion, as described in claim 24 and associated with the second circuit portion; The first and second handshake circuit sections are arranged to perform a handshake process including request and acknowledgment signals to facilitate data transmission from the second circuit section to the first circuit section using one or more data lines.

Images