Small size pixels and display devices comprising small size pixels

Abstract

An apparatus comprising a pixel array; a row driver configured to generate a plurality of control signals, drive a plurality of rows of the pixel array using the plurality of control signals, and generate a plurality of clock signals; a row multiplexer configured to receive the plurality of clock signals and transmit one of the plurality of clock signals; a data driver configured to transmit a plurality of data signals to the pixel array in column units, each of the plurality of pixels comprising: a light emitting device; a shift register configured to receive the selectively transmitted clock signal from the row multiplexer; and generate a width-adjusted pulse width modulation (PWM) signal based on a desired brightness level of the light emitting device; and a transistor configured to transmit a drive current to the light emitting device based on the PWM signal.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2021-0050742, filed with the Korean Intellectual Property Office on April 19, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various exemplary embodiments of the present invention relate to pixels, and more specifically, to pixels having a small size, display devices including the pixels having a small size, and / or methods of operating display devices including pixels having a small size. Background Technology

[0004] With the development of the information society, the demand for display devices for displaying images has increased, and various types of display devices have been used, such as liquid crystal displays (LCDs), plasma displays, and organic light-emitting diode displays (OLEDs). In particular, there has been a recent increase in interest in display devices using micro light-emitting diodes (μLEDs) (hereinafter referred to as "micro-display devices").

[0005] Due to the expectation and / or need for improved display device characteristics to enable virtual reality (VR), augmented reality (AR), and / or mixed reality (MR) technologies, miniature light-emitting diodes (LEDs) on silicon or active-matrix organic light-emitting diodes (AMOLEDs) on silicon are increasingly being developed. In particular, to achieve high-resolution images for these applications, it is necessary to reduce pixel size. Summary of the Invention

[0006] Various exemplary embodiments of the present invention relate to pixels, display devices including the pixels, and / or methods of operating the display devices, and more specifically, at least one exemplary embodiment provides small-sized pixels by simplifying the structure of the associated pixel circuitry.

[0007] According to at least one exemplary embodiment of the present invention, an apparatus is provided, comprising: a pixel array including a plurality of rows, and each of the plurality of rows including a plurality of pixels; a row driver configured to generate a plurality of control signals, drive the plurality of rows of the pixel array using the plurality of control signals, and generate a plurality of clock signals; a row multiplexer configured to receive the plurality of clock signals and selectively transmit one of the plurality of clock signals to the pixel array; and a data driver configured to transmit a plurality of data signals to the pixel array column by column, and each of the plurality of pixels including: a light-emitting device; a shift register configured to receive the selectively transmitted clock signal from the row multiplexer; and a pulse width modulation (PWM) signal with width adjustment based on a desired brightness level of the light-emitting device; and a transistor configured to transmit a drive current to the light-emitting device based on the PWM signal.

[0008] According to at least one exemplary embodiment of the present invention, an apparatus is provided, comprising: a pixel array including a plurality of pixels arranged in multiple rows and columns, each of the plurality of pixels including a light-emitting device and a storage element; a row driver configured to generate a plurality of control signals and a plurality of clock signals, and to drive the pixel array row-wise using the plurality of control signals, the plurality of clock signals including a first clock signal, the row driver further configured to adjust the width of the first clock signal to control the brightness of at least one of the plurality of light-emitting devices; and a data driver configured to output a plurality of data signals column-wise to the pixel array.

[0009] In another aspect of at least one exemplary embodiment of the present invention, a pixel is provided, comprising: a light-emitting device; a NOR gate configured to receive a clock signal for controlling the light-emitting device; a capacitor configured to store the output from the NOR gate; and a switch configured to selectively disconnect the electrical connection between the NOR gate and the capacitor based on the clock signal. Attached Figure Description

[0010] Various exemplary embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a diagram schematically illustrating at least one example embodiment of a display device according to a concept of the present invention;

[0012] Figure 2 This is a diagram illustrating pixels of at least one example embodiment of the concept according to the present invention;

[0013] Figure 3 This is a diagram schematically illustrating at least one example embodiment of a display device according to a concept of the present invention;

[0014] Figure 4 It is a timing diagram illustrating the operation of at least one example embodiment of the concept according to the present invention;

[0015] Figure 5 It is a timing diagram illustrating the operation of at least one example embodiment of the concept according to the present invention;

[0016] Figure 6 It is a timing diagram illustrating the operation of at least one example embodiment of the concept according to the present invention;

[0017] Figure 7 This is a diagram illustrating pixels of at least one example embodiment of the concept according to the present invention;

[0018] Figure 8 This is a diagram schematically illustrating at least one example embodiment of a display device according to a concept of the present invention;

[0019] Figure 9 It is a timing diagram illustrating the operation of at least one example embodiment of the concept according to the present invention;

[0020] Figure 10 This is a diagram illustrating pixels of at least one example embodiment of the concept according to the present invention;

[0021] Figure 11 It is a timing diagram illustrating the operation of at least one example embodiment of the concept according to the present invention;

[0022] Figure 12 This is a diagram illustrating pixels of at least one example embodiment of the concept according to the present invention;

[0023] Figure 13 This is a diagram illustrating pixels of at least one example embodiment of the concept according to the present invention;

[0024] Figure 14 This is a diagram illustrating pixels of at least one example embodiment of the concept according to the present invention;

[0025] Figure 15 It is a timing diagram illustrating the operation of at least one example embodiment of the concept according to the present invention; and

[0026] Figure 16 This is a diagram schematically illustrating the manufacturing process of a display device according to at least one example embodiment of the concept of the present invention. Detailed Implementation

[0027] In the following description, various exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings. In the description with reference to the drawings, the same or corresponding components are given the same reference numerals, and repeated descriptions thereof are omitted.

[0028] Figure 1This is a diagram schematically illustrating a display device 30 according to at least one example embodiment of the concept of the present invention.

[0029] refer to Figure 1 The display device 30 may include a pixel array 110 and / or a pixel driver 120, etc., but the example embodiment is not limited thereto. For example, the display device 30 may include more or fewer components, etc.

[0030] Pixel array 110 can be based on displaying 1 to 2 n The example embodiment uses an n-bit digital image signal, such as grayscale, to display at least one image, but is not limited to this. The pixel array 110 may include a plurality of pixels PX arranged in various patterns, such as a specific pattern (e.g., a desired pattern), such as a matrix type and / or a sawtooth type, but is not limited thereto. Pixel PX may emit light (and / or a light signal) of one color and / or may emit a light signal of one color, such as red, blue, green, and / or white, but is not limited thereto. For example, pixel PX may emit a light signal of a color different from red, blue, green, and white.

[0031] A pixel (PX) may include at least one light-emitting device. The light-emitting device may be a self-emissive device. For example, the light-emitting device may be a light-emitting diode (LED), but is not limited thereto. The light-emitting device may be an LED having a micrometer to nanometer unit scale (and / or size), but is not limited thereto. The light-emitting device may emit light with a single peak wavelength and / or emit light with multiple peak wavelengths.

[0032] The pixel PX may also include pixel circuitry connected to the light-emitting device. The pixel circuitry may include at least one thin-film transistor (TFT) and / or at least one capacitor, but the example embodiments are not limited thereto. The pixel circuitry may be implemented using a semiconductor stacked structure on a substrate, but is not limited thereto.

[0033] Pixel PX may include a storage element for receiving and / or storing data (e.g., a data signal) from data driver 121 in response to a data clock signal D_CLK. The storage element may also output the stored data as a pulse-width modulation (PWM) signal in response to a PWM clock signal P_CLK, but the example embodiments are not limited thereto. In some example embodiments, the storage element may include, for example, a shift register, a flip-flop, a 1-bit memory, a 2-bit memory, and / or a capacitor, but is not limited thereto. Furthermore, pixel PX may include devices associated with characteristics of at least one example embodiment based on the selective application of VDDH and / or VDDL voltages, but is not limited thereto.

[0034] Pixel driver 120 can drive and / or control pixel array 110, etc. Pixel driver 120 may include, but is not limited to, data driver 121 and / or row driver 123, etc. Data driver 121 can drive pixel array 110 on a column-by-column basis. Row driver 123 can drive pixel array 110 on a row-by-row basis.

[0035] Data driver 121 may receive at least one frame of image data from an external source (e.g., an external source, a graphics controller, etc.), extract gray levels for each pixel PX, and / or convert the extracted gray levels into digital data with a specific (e.g., desired) number of bits, but is not limited thereto. According to at least one example embodiment, the digital data may be corrected by using a gamma value set using a gamma curve, but is not limited thereto.

[0036] Data driver 121 can be connected to multiple pixels PX of pixel array 110 via multiple data lines DL. Data driver 121 can provide digital data (e.g., multiple data signals) to each pixel PX in columns or similar manner. Data driver 121 can send digital data (from most significant bit (MSB) to least significant bit (LSB)) to each pixel PX in a specific and / or desired order, but is not limited thereto. Data driver 121 can provide bit values ​​of digital data to each pixel PX for each frame. Bit values ​​can have low or high levels (e.g., "0" or "1" values).

[0037] A frame may include multiple subframes. When the display device 30 displays n-bit image data, a frame may include n subframes, each of which may correspond to each bit of the n-bit image data, but the example embodiment is not limited thereto. The period of each subframe may be different, but is not limited thereto; for example, one or more subframes may have the same period. For example, the period (e.g., time period) of the subframe corresponding to the MSB of the digital data may be set to the longest, while the period of the subframe corresponding to the LSB may be set to the shortest, but the example embodiment is not limited thereto. The order of the MSB to LSB of the digital data may correspond to the order of the first subframe to the nth subframe, respectively, but the example embodiment is not limited thereto; for example, the order of the subframes may be set in various (other) ways.

[0038] The row driver 123 can generate control signals and / or clock signals for driving and / or controlling the pixel array 110, etc. The control signals may include, but are not limited to, enable signals for controlling pixels PX. For example, the control signals may be signals for sequentially driving multiple rows of the pixel array 110, etc.

[0039] The control signals may include a write enable signal W_EN for enabling data to be written to the storage element of pixel PX, a clock select signal C_SEL for selecting the clock signal input to pixel PX, and / or a PWM enable signal P_EN for controlling the drive current flowing through the light-emitting device using a PWM signal, etc. The control signals may activate pixel array 110 on a row-by-row basis. Multiple row lines RL may be used to send control signals to pixel array 110. Row driver 123 may generate a control signal CS for controlling data driver 121 and / or send the generated control signal CS to data driver 121, but is not limited thereto. For example, the control signal CS for controlling data driver 121 may include a signal for selecting one of data lines DL, etc.

[0040] The row driver 123 may also include, but is not limited to, a clock generator 124 for generating clock signals. The clock generator 124 may generate a data clock signal D_CLK for receiving and / or storing data from the data driver 121, and / or a PWM clock signal P_CLK for outputting the stored data as a PWM signal, but the example embodiments are not limited to this. According to at least one example embodiment, the clock generator 124 may toggle the PWM clock signal P_CLK for each subframe during a frame, but the example embodiments are not limited to this. The toggle period may be equal to the period of the corresponding subframe (e.g., a desired time period), etc. The clock generator 124 may send a clock signal to each pixel PX using the row line RL, but is not limited to this.

[0041] Each component of the pixel driver 120 may be formed as a separate integrated circuit (IC) chip, or two or more components of the pixel driver 120 may be formed as a single IC chip, etc. The pixel driver 120 may be directly mounted on a substrate on which the pixel array 110 is formed, or it may be mounted on a flexible printed circuit film, attached to the substrate as a tape-on-a-carrier package (TCP), and / or directly formed on the substrate, etc. In at least one example embodiment, the data driver 121 may be connected to the pixel array 110 as an IC chip, and the row driver 123 may be directly formed on the substrate, but the example embodiment is not limited thereto.

[0042] Figure 2 This is a circuit diagram illustrating at least one example embodiment of a pixel PX1 according to the concept of the present invention. Figure 2 It shows Figure 1 An example of a pixel PX (e.g., pixel PX1).

[0043] refer to Figure 2According to at least one example embodiment, pixel PX1 may include a write multiplexer (e.g., a multiplexer) Mux_W, a shift register SR_F, a pixel AND gate A_P, a transistor T1, a current source I1, and / or a light-emitting device LED, etc., but the example embodiment is not limited thereto. Pixel PX1 may be electrically connected to a row multiplexer Mux_R, which may receive output from the row AND gate A_R, etc.

[0044] The shift register SR_F can sequentially store and / or output data, including data from, for example, via the data line DL. Figure 1 The data driver 121 receives bits of data DT, but the example embodiment is not limited thereto. The shift register SR_F can store the bit values ​​of data DT from MSB to LSB in a specific and / or desired order, depending on (e.g., based on) a particular and / or desired order. For example, the shift register SR_F can store data DT in MSB to LSB order, but the example embodiment is not limited thereto. The shift register SR_F can receive data serially and / or output data serially. However, the example embodiments of the inventive concept are not limited thereto, and can input and / or output data in parallel, etc. The shift register SR_F can store at least one bit of data. In at least one example embodiment, the shift register SR_F can be an n-bit memory, where n is an integer of 1 or greater. The shift register SR_F can be implemented as N flip-flops F1 to FN. N can be an integer of 1 or greater. For example, the shift register SR_F can include 8 flip-flops (N = 8), but the example embodiment is not limited thereto. The MSB of data DT can be stored in the Nth flip-flop FN, and the LSB of data DT can be stored in the first flip-flop F1. In at least one example embodiment, the MSB of the data DT can be stored in the first flip-flop F1, and the LSB of the data DT can be stored in the Nth flip-flop FN, etc. The Nth flip-flop FN can be a flip-flop for outputting the PWM signal P_SIG, but is not limited thereto.

[0045] Data DT can be input to shift register SR_F via and / or using the write multiplexer Mux_W. The write multiplexer Mux_W can receive data DT and feedback data FB, which is already stored in the Nth flip-flop FN of shift register SR_F and provided as feedback from shift register SR_F. The write multiplexer Mux_W can also receive data from the row driver (e.g., ) via the row line RL. Figure 1The row driver 123, etc., receives the write enable signal W_EN, but the example embodiment is not limited thereto. The write enable signal W_EN can be a signal for selecting one of the data DT and the feedback data FB. Therefore, the data DT and the feedback data FB may not overlap, and one of the data DT or the feedback data FB may be input to the shift register SR_F at once, but the example embodiment is not limited thereto.

[0046] The shift register SR_F can receive a clock signal through a row multiplexer Mux_R located outside pixel PX1 (e.g., outside pixel PX1). The row multiplexer Mux_R can receive the PWM clock signal P_CLK and / or the data clock signal D_CLK, and can output a clock signal selected from the PWM clock signal P_CLK and / or the data clock signal D_CLK, and / or based on the PWM clock signal P_CLK and / or the data clock signal D_CLK, etc.

[0047] The data clock signal D_CLK can be a clock signal used to store the data DT in flip-flops F1 to FN. The PWM clock signal P_CLK can be a clock signal used to generate the PWM signal P_SIG, which is the output signal of the shift register SR_F. The PWM clock signal P_CLK can be switched for each subframe during a frame, but is not limited to this. (See reference...) Figure 5 Provide a detailed description of the PWM signal P_SIG.

[0048] According to at least one example embodiment, the output signal of the horizontal AND gate A_R can be input to the horizontal multiplexer Mux_R. The horizontal AND gate A_R can be controlled by the data clock signal D_CLK and / or the write enable signal W_EN. Therefore, when both the data clock signal D_CLK and the write enable signal W_EN are high, the horizontal AND gate A_R will output a high-level signal to the horizontal multiplexer Mux_R. The write enable signal W_EN and the clock selection signal C_SEL can be control signals generated by the horizontal driver 123, but the example embodiment is not limited to this.

[0049] The clock selection signal C_SEL can be a control signal used to select one of the PWM clock signal P_CLK and the data clock signal D_CLK. Therefore, the PWM clock signal P_CLK and the data clock signal D_CLK can be non-overlapping (e.g., not output simultaneously) and can be input to the shift register SR_F.

[0050] The output from the line multiplexer Mux_R can be sent to the shift register SR_F. The output from the line multiplexer Mux_R can be sent to each of the flip-flops F1 through FN, but the example embodiment is not limited thereto. Therefore, each of the flip-flops F1 through FN can store data DT and / or generate a PWM signal P_SIG in response to a control signal received from the line multiplexer Mux_R. The shift register SR_F can store the bit value of data DT for each frame during the data write cycle and can generate the PWM signal P_SIG based on the bit value stored during the illumination cycle and the PWM clock signal P_CLK, etc.

[0051] The PWM signal P_SIG output from the shift register SR_F can be input to and / or sent to the pixel AND gate A_P. The pixel AND gate A_P can also receive the PWM enable signal P_EN. Therefore, when both the PWM signal P_SIG and the PWM enable signal P_EN are high, the output from the pixel AND gate A_P can be high.

[0052] The output from the pixel AND gate A_P can be connected to the gate of transistor T1. One end of transistor T1 can be connected to current source I1, and the other end of transistor T1 can be connected to the light-emitting device (LED). Current source I1 can be connected to a high-level source voltage VDDH to provide drive current, but is not limited thereto. Transistor T1 can be turned on or off according to and / or based on the PWM signal P_SIG to transmit or cut off the drive current to the LED. When transistor T1 is on, the drive current output from transistor T1 can be transmitted to the LED, causing the LED to emit light; when transistor T1 is off, the drive current output from transistor T1 is cut off, and the LED does not emit light, etc. The light-emitting time of the LED can be adjusted according to and / or based on the on-time and / or off-time of transistor T1 (e.g., based on the duty cycle of transistor T1, etc.). During a frame, the light-emitting time and non-light-emitting time of the LED are controlled by and / or based on the on-time and off-time of transistor T1, thereby representing the color depth of pixel PX1, etc. Transistor T1 can be a P-type transistor or an N-type transistor. like Figure 2 As shown, transistor T1 can be a P-type transistor. Therefore, transistor T1 can be turned on by a low-level voltage, but the example embodiment is not limited to this.

[0053] In at least one example embodiment, by forming a pixel PX1 including a shift register SR_F that selectively receives one of a data clock signal D_CLK and a PWM clock signal P_CLK, the pixel circuitry may include transistors operated and / or controlled by low-level voltages. Because transistors operating at low-level voltages are smaller than those operating at high-level voltages, the physical area of ​​the pixel PX1 can be reduced. Therefore, when the pixel array has the same layout area (e.g., the same physical area and / or the same physical dimensions, etc.), a pixel circuitry including transistors operating at low-level voltages can provide a display device with higher resolution and / or higher pixel density and lower power consumption compared to a pixel circuitry including transistors operating at high-level voltages.

[0054] Furthermore, because the PWM signal P_SIG can be generated without separate counter and comparator circuits, the number of devices and / or components used, as well as the number of signal lines used to send control signals, can be reduced. Therefore, the structure of the pixel circuit can be simplified, and the manufacturing yield of the pixel circuit can be increased, and / or the cost of manufacturing pixels, pixel arrays, and / or display panels can be reduced.

[0055] Figure 3 This is a circuit diagram schematically illustrating at least one example embodiment of a display device according to the concept of the present invention. Figure 3 It shows including Figure 2 The example embodiment shows a display device 31 with pixel PX1, but is not limited thereto.

[0056] refer to Figure 3 The display device 31 may include a data driver 121, a data multiplexer 122, a row driver 123, a clock generator 124, a row multiplexer Mux_R, a row AND gate A_R, and / or multiple pixels PX1, etc., but the example embodiment is not limited thereto, and for example, the display device 31 may include more or fewer components.

[0057] According to at least one example embodiment, the data driver 121 may also include a data multiplexer 122, etc. The data multiplexer 122 can send data to the pixels PX1 column by column. That is, the pixels PX1 can share the data line DL, etc., column by column. The data sent by the data multiplexer 122 column by column (e.g., first data to Nth data D1, D2, ..., DN) can sequentially include data to be stored in each row, but the example embodiment is not limited thereto. For example, the first data D1 can be serially output via the data line DL and can be sequentially stored in each pixel PX1 of the first column C1, etc., in units of N bits. When the pixel PX1 includes, for example, an 8-bit shift register, the first data D1 can be sequentially stored in each pixel of the first column C1 in units of 8 bits, but the example embodiment is not limited thereto; other numbers of bits can be used for the shift register, etc. When the pixel PX1 includes a 1-bit memory, the first data D1 can be sequentially stored in each pixel PX1 of the first column C1, etc., in units of 1 bit.

[0058] Row driver 123 can generate multiple control signals CS. These multiple control signals CS can activate data driver 121 and / or pixel PX1, etc. Control signals CS sent to data driver 121 may include data write signals for controlling data driver 121 to write data and / or column select signals used by data driver 121 to select the column for sending data, etc. Control signals CS sent to pixel PX1 may include write enable signal W_EN, PWM enable signal P_EN, and / or clock select signal C_SEL, etc. (see reference). Figure 2 (as described), but the example embodiments are not limited thereto.

[0059] Clock generator 124 can generate multiple clock signals. These clock signals may include a data clock signal D_CLK and / or a PWM clock signal P_CLK, etc. Clock generator 124 can send the data clock signal D_CLK to a row AND gate A_R and the PWM clock signal P_CLK to a row multiplexer Mux_R, etc. The row multiplexer Mux_R can selectively send either the data clock signal D_CLK output from the row AND gate A_R or the PWM clock signal P_CLK output from clock generator 124 to pixel PX1. The data clock signal D_CLK can be sent sequentially to the rows, but the example embodiment is not limited to this. Therefore, rows can sequentially store the bit values ​​of data, etc. The PWM clock signal P_CLK can be sent sequentially to the rows. Therefore, rows can sequentially output the PWM signal P_SIG.

[0060] Multiple pixels PX1 in a pixel array can share a row multiplexer Mux_R and a row AND gate A_R, but are not limited to this. Therefore, a row of the pixel array can include one row multiplexer Mux_R and one row AND gate A_R, etc. For example, pixels PX1 located in the first row R1 can share the row multiplexer Mux_R and the row AND gate A_R, etc.

[0061] Figure 4 This is a timing diagram illustrating the operation of at least one example embodiment of the concept according to the present invention. Figure 4 This is a timing diagram showing the PWM clock signal P_CLK and the PWM signal P_SIG, and it shows the timing of the PWM clock signal P_CLK and the PWM signal P_SIG within one frame period, but the example embodiment is not limited to this.

[0062] refer to Figure 4 According to at least one example embodiment, a single frame (e.g., a single image frame, etc.) may include multiple subframes S1 to SN (e.g., first subframe to Nth subframe), where N is an integer greater than zero. Subframes S1 to SN may operate during a first period T, but are not limited thereto. The first period T may refer to the period during which the light-emitting device LED emits light within a frame, etc.

[0063] The number of subframes S1 to SN can be the same as the number of flip-flops N included in the shift register SR_F, but is not limited to this. For example, when there are 8 flip-flops (N=8), the number of subframes can also be 8, but the embodiments are not limited to this.

[0064] The lengths of one or more periods of subframes S1 to SN may differ from each other, but the example embodiment is not limited thereto. The period of each of subframes S1 to SN may be equal to the period of the first period T divided by 2. n The obtained period T / 2 n However, the example embodiments are not limited thereto. The first period T may refer to the period during which the light-emitting device LED emits light (e.g., on-cycle) or does not emit light (e.g., off-cycle) via the PWM clock signal P_CLK during a frame. According to at least one example embodiment, "n" may be 1 or greater, and may be an integer equal to or less than the number of flip-flops (N), but the example embodiments are not limited thereto. Furthermore, for each subframe and / or the flip-flops included in the shift register SR_F, "n" may increment from 1 to N in increments of 1. For example, when there are 8 flip-flops (N=8), the first subframe S1 may have a period by dividing the first period T by 2. 1 The obtained period T / 2, and the second subframe S2 can have this by dividing the first period T by 2. 2The obtained period T / 4, etc., is not limited to this example embodiment. In this way, according to at least one example embodiment, the eighth subframe S8 can have a period T divided by 2. 8 The obtained period is T / 256, but the example embodiment is not limited to this.

[0065] For each subframe, the PWM clock signal P_CLK can be switched, for example, by clock generator 124 and / or line driver 123, but the example embodiments are not limited thereto. The PWM clock signal P_CLK can be switched at the end of each subframe, but is not limited thereto. In at least one example embodiment, the PWM clock signal P_CLK can be switched at the beginning of each subframe, but is not limited thereto. Switching is defined as the operation of the clock signal transitioning from low to high and then back to low. The switching period of the PWM clock signal P_CLK can be the same as the period of the subframe, but is not limited thereto. Therefore, the PWM clock signal P_CLK can be switched by dividing the first period T by 2. n And each value obtained is T / 2 n Switching can be performed. For example, the first switch can be performed after time T / 2, and the second switch can be performed after time T / 4 (T / 2+T / 4) has elapsed from time T / 2. The PWM clock signal P_CLK can be switched a total of N times during the first period T. For example, when the number of flip-flops is 8 (N=8), the PWM clock signal P_CLK can be switched a total of 8 times during the first period T, but the example embodiment is not limited to this.

[0066] According to at least one example embodiment, the PWM signal P_SIG can be output from the shift register SR_F, but is not limited thereto. The PWM signal P_SIG can be a signal used to control the light-emitting device based on the bit value of data DT in subframe units and the signal width of the PWM clock signal P_CLK, etc. If the bit value of data DT is 1, the output of the PWM signal P_SIG can have a high level equal to the signal width of the PWM clock signal P_CLK. If the bit value of data DT is 0, the output of the PWM signal P_SIG can have a low level equal to the signal width of the PWM clock signal P_CLK.

[0067] The output level of the PWM signal P_SIG can be determined by the data DT, and the period during which the same level is output can be determined by the time width (e.g., switching period) during which the PWM clock signal P_CLK is switched, but the example embodiment is not limited thereto. Whether the LED emits light and the light-emitting time of the LED (e.g., light-emitting period, light-emitting duration, conduction period, etc.) can be controlled based on and / or on the PWM signal P_SIG, and can correspond to and / or represent the grayscale level indicated by the data DT, but the example embodiment is not limited thereto. That is, the data DT determines whether the LED emits light, and the light-emitting time of the LED can be controlled by the PWM clock signal P_CLK, etc.

[0068] Figure 4 An example is shown where data DT is input from MSB to LSB in the order of "1, 0, ..., 0", but the example embodiment is not limited to this. Each time the PWM clock signal P_CLK is switched, the PWM signal P_SIG can be high or low depending on and / or based on the corresponding data DT, and can remain at the logic level until the PWM clock signal P_CLK is switched again, etc. For example, "1" can be input as data DT in the first subframe S1, and correspondingly, the PWM signal P_SIG can be high in the first subframe S1, etc. The high level can be maintained for T / 2 (which is the period of the first subframe S1). Subsequently, "0" can be input as data DT during the second subframe S2, and the PWM signal P_SIG can be low and can be maintained for T / 4 (which is the period of the second subframe S2), etc. In the same way, "0" can be input as data DT input in the Nth subframe SN, therefore, the PWM signal P_SIG can be low and can be maintained for T / 2. N (This is the period of the Nth subframe SN) etc.

[0069] Figure 5 This is a timing diagram illustrating the operation of at least one example embodiment of the concept according to the present invention. Figure 5 It is shown as an example Figure 2 The diagram shows the timing of the operation of pixel PX1, and is an example of a case with 8 triggers (N=8), but the example embodiment is not limited to this.

[0070] refer to Figure 5According to at least one example embodiment, a single frame period FR1 may include a data writing period P1 and a light emission period P2, but the example embodiment is not limited thereto. The data writing period P1 may be shorter than the light emission period P2, but is not limited thereto. The first period T may refer to the duration of the light emission period P2, but is not limited thereto. The light emission period P2 may include multiple subframes, such as subframes S1 to S8, but is not limited thereto. The period lengths of one or more subframes in subframes S1 to S8 may be different from each other, but the example embodiment is not limited thereto. The period of each subframe in subframes S1 to S8 can be obtained by dividing the first period T by 2. n The obtained period T / 2 n As shown in the reference above Figure 5 The examples are described, but the examples are not limited thereto. “n” is an integer greater than or equal to 1 and equal to or less than the number of triggers N, and for example, since the number of triggers is 8 in at least one example embodiment, N can refer to an integer greater than or equal to 1 and equal to or less than 8, but is not limited thereto.

[0071] During the data write cycle P1, the shift register SR_F can store multiple data bit values, such as D0 to D7. The write enable signal W_EN can be high, and the data clock signal D_CLK can switch at a constant period, but the example embodiment is not limited to this. Figure 5 As shown, for example, MSB(D7) to LSB(D0) are input as "10101010", which is an example for description and is not limited thereto. In response to the write enable signal W_EN and the data clock signal D_CLK, the data "10101010" can be stored in the shift register SR_F, etc. That is, during the data write cycle P1, the bit values ​​of MSB D7 to LSB of data D0 to D7 can be written to the shift register SR_F. The data D0 to D7 previously stored in the shift register SR_F can be used continuously for multiple frames until the data D0 to D7 is updated and / or refreshed.

[0072] During the light-emitting period P2, pixel PX1 can generate a PWM signal P_SIG based on the PWM clock signal P_CLK and data (e.g., data D0 to D7). During the light-emitting period P2, the write enable signal W_EN can be low, but is not limited to this. During the light-emitting period P2, the data clock signal D_CLK can switch at a constant period, but can be input to the shift register SR_F without the clock selection signal C_SEL; therefore, it is shown as low for convenience, but the example embodiment is not limited to this.

[0073] During the light emission period P2, the PWM clock signal P_CLK can be switched every subframe, but is not limited to this. For example, the PWM clock signal P_CLK can be switched at the end of each subframe, but is not limited to this. The shift register SR_F can generate the PWM signal P_SIG in response to stored and / or pre-stored data (e.g., data D0 to D7, etc.) and the PWM clock signal P_CLK. The PWM signal P_SIG can be switched during period T / 2 in the first subframe S1. 1 The period has a high level and can be in the period T / 2 of the second subframe S2. 2 The period is characterized by a low level, but the example embodiment is not limited to this. Similarly, the PWM signal P_SIG can be in the eighth subframe S8 at T / 2. 8 The period is characterized by a high level, but the example embodiments are not limited to this. The color depth of the light-emitting device (e.g., pixel color value, pixel value, grayscale value, etc.) can be represented by the PWM signal P_SIG.

[0074] Figure 6 This is a timing diagram illustrating the operation of a display device according to at least one example embodiment of the concept of the present invention. Figure 6 It is shown Figure 3 The timing diagram shows the operation of the pixel array, but the example embodiment is not limited thereto.

[0075] refer to Figure 6 According to at least one example embodiment, the first frame FR1 and the second frame FR2 may be consecutive, but are not limited to this. The frame synchronization signal VSYNC may be switched at the beginning of each frame, but is not limited to this. The line change signal HSYNC may be switched each time a line changes, but is not limited to this.

[0076] For example, in the first frame FR1, after the frame synchronization signal VSYNC is switched, the row change signal HSYNC can be switched and the first row R1 can be operated, but the example embodiment is not limited to this. During the data write cycle P1, data can be sequentially stored in the pixels arranged in all columns of the first row R1. The light emission cycle P2 of the first row R1 can be performed after the data write cycle P1 of the first row R1, and so on.

[0077] When the row change signal HSYNC switches again during the light emission cycle P2 of the first row R1, the data write cycle P1 and the light emission cycle P2 of the second row R2 can continue. Thus, the data write cycle P1 and the light emission cycle P2 can proceed sequentially from the first row R1 to the nth row RN.

[0078] When the frame synchronization signal VSYNC is switched, the second frame FR2 can begin, and after the light emission period P2 ends, new data can be written to the first row R1, etc. Similar to the first frame FR1, the data writing period P1 and the light emission period P2 can be performed sequentially in the first row R1 to the nth row RN according to the row change signal HSYNC, etc.

[0079] Figure 7 This is a circuit diagram illustrating pixel P2 according to at least one example embodiment of the concept according to the present invention. Figure 7 It shows Figure 1 An example of pixel PX, and omitting the example of PX. Figure 2 The description of pixel PX1 is repeated, but the example embodiment is not limited thereto.

[0080] refer to Figure 7 According to at least one example embodiment, pixel PX2 may include a write multiplexer Mux_W, a shift register SR_L, a pixel AND gate A_P, and / or a transistor T1, etc., but the example embodiment is not limited thereto.

[0081] The shift register SR_L can be sequentially stored and output via the data line DL, including from the data drive (e.g., Figure 1 The data driver 121, etc., receives bits in the data DT, but the example embodiment is not limited thereto. The shift register SR_L may include multiple (N) latches, such as L1 to LN. N may be an integer of 1 or greater. For example, the shift register SR_L may include 8 latches (N=8), but is not limited thereto. The MSB of the data DT may be stored in the Nth latch LN, and the LSB of the data DT may be stored in the first latch L1, but is not limited thereto. In at least one example embodiment, the MSB of the data DT may be stored in the first latch L1, and the LSB of the data DT may be stored in the Nth latch LN, etc.

[0082] The shift register SR_L may also include, but is not limited to, a feedback latch LF. The feedback latch LF can be an additional latch used to provide feedback on data stored in N latches L1 to LN. Therefore, the feedback latch LF can be connected to the Nth latch LN. The feedback latch LF can receive and store the bit values ​​stored in the Nth latch LN. The Nth latch LN can be a latch that outputs the PWM signal P_SIG, but the example embodiment is not limited to this.

[0083] Data DT can be input to shift register SR_L via and / or using write multiplexer Mux_W. Write multiplexer Mux_L can receive data DT and feedback data FB stored in feedback latch LF, etc. Write multiplexer Mux_W can receive a feedback select signal FB_SEL for selecting one of data DT and feedback data FB. The feedback select signal FB_SEL can be generated by line driver 123, but is not limited thereto.

[0084] The shift register SR_L can receive multiple clock signals through multiple line multiplexers Mux_R1 to Mux_RN located outside (e.g., externally) of pixel PX2, but the example embodiment is not limited thereto. Each component of the line multiplexers Mux_R1 to Mux_RN can be connected to... Figure 3 The line multiplexer Mux_R is the same, but the example embodiment is not limited thereto.

[0085] Row multiplexers Mux_R1 to Mux_RN can each correspond to N latches L1 to LN. Row multiplexers Mux_R1 to Mux_RN can each be connected to their respective N latches L1 to LN. Therefore, each of the N latches L1 to LN can receive N clock signals through its connected row multiplexers Mux_R1 to Mux_RN. Row multiplexers Mux_R1 to Mux_RN can receive PWM clock signals P_CLK1 to P_CLKN and data clock signals D_CLK1 to D_CLKN, and can send one of these selected clock signals to the shift register SR_L, but the example embodiment is not limited to this. (See reference...) Figure 10 The PWM clock signals P_CLK1 to P_CLKN and the data clock signals D_CLK1 to D_CLKN are described in detail. The shift register SR_L can store the bit value of data DT in response to the clock signals received from the row multiplexers Mux_R1 to Mux_RN, and can generate the PWM signal P-SIG, but the example embodiment is not limited thereto. The PWM signal P-SIG can be output from the Nth latch LN, etc.

[0086] The feedback latch LF can receive multiple clock signals through a feedback multiplexer Mux_RF located outside (e.g., outside) the pixel PX2. Figure 3The components of the row multiplexer Mux_R are the same, but the example embodiment is not limited thereto. The feedback multiplexer Mux_RF can receive the feedback clock signal P_CLKF and the feedback data clock signal D_CLKF, and can selectively send one of them to the feedback latch LF, etc. The feedback clock signal P_CLKF can be input before the PWM clock signals P_CLK1 to P_CLKN are input to the N latches L1 to LN, but the example embodiment is not limited thereto.

[0087] Figure 8 This is a circuit diagram schematically illustrating at least one example embodiment of a display device according to the concept of the present invention. Figure 8 It shows including as Figure 3 at least one example embodiment Figure 7 The example embodiment shows a display device 32 with pixel PX2, but is not limited to this.

[0088] refer to Figure 8 According to at least one example embodiment, the display device 32 may include a data driver 121, a line driver 123, a multiplexer group MG and / or a pixel PX2, etc., but the example embodiment is not limited thereto.

[0089] The multiplexer group MG may include, but is not limited to, multiple line multiplexers Mux_R1 to Mux_RN and multiple line AND gates A_R1 to A_RN. The line AND gates A_R1 to A_RN may each correspond to a line multiplexer Mux_R1 to Mux_RN. The multiplexer group MG may also include a feedback multiplexer Mux_RF, which can receive the output from the AND gates.

[0090] Row multiplexers Mux_R1 to Mux_RN can each correspond to N latches L1 to LN. Pixel arrays can share multiplexer groups MG on a row-by-row basis. Pixels PX2 located in one of the rows of a pixel array can share multiplexer groups MG. Therefore, a row of a pixel array can be connected to a multiplexer group, but is not limited to this. For example, because the first row R1 can share multiplexer group MG, pixels PX2 in the first row R1 can share multiplexers Mux_R1 to Mux_RN, etc., which can be included in multiplexer group MG.

[0091] Figure 9 This is a timing diagram illustrating the operation of at least one example embodiment of the concept according to the present invention. Figure 9 It is shown Figure 8 The diagram shows the timing of the operation of pixel PX2, and is an example of the case where there are eight latches (N=8), but the example embodiment is not limited to this.

[0092] refer to Figure 9 According to at least one example embodiment, a single frame period FR1 may include a data writing period P1 and a light emission period P2, etc., but is not limited thereto. The light emission period P2 may include multiple subframes, such as subframes S1 to S8, but is not limited thereto.

[0093] The period lengths of one or more subframes (e.g., subframes S1 to S8) can be different from each other, but are not limited to this. The period of each subframe in subframes S1 to S8 can be obtained by dividing the first period T by 2. n The obtained period T / 2 n As shown in the reference above Figure 5 The example embodiments are not limited thereto. The first period T can refer to the period during which the LED emits or does not emit light within a frame, controlled by the PWM clock signal P_CLK. The first period T can refer to the duration of the light emission period P2. n is an integer greater than or equal to 1 and less than or equal to the number of latches N, and can be incremented from 1 to N in increments of 1. Because at least one example embodiment describes the case with 8 latches (N=8) as an example, n can refer to an integer greater than or equal to 1 and less than or equal to 8, but the example embodiments are not limited thereto.

[0094] During the data write cycle P1, the bit values ​​of data (e.g., data D0 to D7) can be stored in the shift register SR_L. During the data write cycle P1, the write enable signal W_EN can be high, but is not limited to this.

[0095] The data clock signal D_CLK may include, for example, first data clock signals D_CLK1 to eighth data clock signals D_CLK8 respectively input to row multiplexers Mux_R1 to Mux_R8, but the example embodiment is not limited thereto. The first data clock signals D_CLK1 to eighth data clock signals D_CLK8 may be sequentially switched during a specific and / or desired period, but are not limited thereto. Sequentially switching the first data clock signals D_CLK1 to eighth data clock signals D_CLK8 during a specific and / or desired period D_ST can be defined as "serial switching of the data clock signal D_CLK". When the data clock signal D_CLK is serially switched, the first data clock signals D_CLK1 to eighth data clock signals D_CLK8 may be sequentially switched without overlap, etc. The data clock signal D_CLK may be continuously serially switched within the data write period P1, but is not limited thereto. Figure 9As shown, MSB D7 to LSB D0 are input as "10101010", which is an example for description and is not limited thereto. During the data write cycle P1, in response to the write enable signal W_EN and the data clock signal D_CLK, the bit values ​​of MSB D7 to LSB D0 of data D0 to D7 can be stored in the shift register SR_L.

[0096] During the light-emitting cycle P2, the PWM signal P_SIG can be generated based on the PWM clock signal P_CLK and data (e.g., data D0 to D7). During the light-emitting cycle P2, the write enable signal W_EN can be low, but the example embodiment is not limited to this. The data clock signal D_CLK can be serially switched during the light-emitting cycle P2 at a specific and / or desired period, but it can be input to the shift register SR_L without the clock selection signal C_SEL. Therefore, for convenience, the data clock signal D_CLK is shown as low, but the example embodiment is not limited to this.

[0097] The PWM clock signal P_CLK may include multiple PWM clock signals respectively input to multiple row multiplexers Mux_R1 to Mux_R8, such as the first PWM clock signal P_CLK1 to the eighth PWM clock signal P_CLK8, etc., but the example embodiment is not limited to this. The first PWM clock signal P_CLK1 to the eighth PWM clock signal P_CLK8 may be sequentially switched during a specific and / or desired period P_ST, but is not limited to this. For example, the seventh PWM clock signal P_CLK7 may be switched immediately after the eighth PWM clock signal P_CLK8 is switched, and the sixth PWM clock signal P_CLK6 may be switched immediately after the seventh PWM clock signal P_CLK7 is switched, but the example embodiment is not limited to this. Sequentially switching the first PWM clock signal P_CLK1 to the eighth PWM clock signal P_CLK8 during a specific and / or desired period P_ST can be defined as "serial switching of the PWM clock signal P_CLK". During the light emission period P2, the PWM clock signal P_CLK may be serially switched in different periods, but the example embodiment is not limited to this. The PWM clock signal P_CLK can be switched serially in each subframe, but is not limited to this. The PWM clock signal P_CLK can also be switched serially at the end of each subframe, but is not limited to this.

[0098] The period length of each subframe (e.g., subframes S1 to S8) can be equal to the period length of the first period T divided by 2. n The obtained period T / 2 nHowever, the example embodiments are not limited to this. "n" is 1 or greater, and can be an integer equal to or less than the number of latches N, but is not limited to this. "n" can increment from 1 to N in increments of 1, but is not limited to this. Therefore, the first frame S1 can have this achieved by dividing the first period T by 2. 1 The obtained period T / 2, and the eighth frame S8 can be achieved by dividing the first period T by 2. 8 The obtained period is T / 256, etc.

[0099] Since the serial switching period of the PWM clock signal P_CLK is the same as the period of the subframe, the PWM clock signal P_CLK can be switched by dividing the first period T by 2. n Each period T / 2 obtained n Serial switching is used, but the example embodiment is not limited to this. For example, the first serial switching can be performed after time T / 2, and the second serial switching can be performed after time T / 4 (T / 2+T / 4) elapsed from time T / 2. During the first cycle T, the PWM clock signal P_CLK can be switched a total of N times. For example, when the number of latches is 8 (N=8), the PWM clock signal P_CLK can be serially switched a total of 8 times during the first cycle T, but the example embodiment is not limited to this.

[0100] The shift register SR_L can generate a PWM signal P_SIG in response to stored and / or pre-stored data (e.g., data D0 to D7) and the PWM clock signal P_CLK. The PWM signal P_SIG can be generated in the first subframe S1 at time T / 2. 1 It has a high level during the period and can be in T / 2 of the second subframe S2. 2 The period is characterized by a low level, but the example embodiment is not limited to this. Similarly, the PWM signal can be in the T / 2 period of the eighth subframe S8. 8 The period has a high level, but is not limited to this. The color depth of the light-emitting device (e.g., pixel value, pixel color value, grayscale value, etc.) can be represented by the PWM signal P_SIG.

[0101] During the light emission period P2, the feedback PWM clock signal P_CLKF can be switched every subframe, but is not limited to this. The feedback PWM clock signal P_CLKF can be switched at the end of each subframe, but can be switched before the eighth PWM clock signal P_CLK8 is switched, but the example embodiment is not limited to this. The feedback PWM clock signal P_CLKF can be switched in each subframe, but can be switched immediately before the PWM clock signal P_CLK is serially switched, but the example embodiment is not limited to this. During the light emission period P2, the feedback PWM clock signal P_CLKF can be switched at different periods, but is not limited to this. The switching period of the feedback PWM clock signal P_CLKF can be the same as the serial switching period of the PWM clock signal P_CLK, but is not limited to this. As the feedback PWM clock signal P_CLKF is switched, the bit value stored in the uppermost latch L8 can be fed back, etc.

[0102] Figure 10 This is a circuit diagram illustrating at least one example embodiment of a pixel PX3 according to a concept of the present invention. Figure 10 It shows Figure 2 Examples of pixels PX are provided, but the example embodiments are not limited thereto.

[0103] refer to Figure 10 According to at least one example embodiment, pixel PX3 may include storage element M, level shifter LS and / or first transistor T1, etc., but the example embodiment is not limited thereto.

[0104] The storage element M can generate at least one control signal based on the input data DT to selectively cause the light-emitting device LED to emit light or not emit light in each of the subframes S1 to SN included in an image frame, and sends the generated control signal to the first transistor T1, etc. The storage element M can receive the data DT sent from the data driver 121 and the PWM clock signal P_CLK sent from the line driver 123. The PWM clock signal P_CLK can be a clock signal whose width is adjusted to control the brightness of the light-emitting device LED, but is not limited thereto. (See reference...) Figure 11 Describe the PWM clock signal P_CLK in detail.

[0105] The storage element M can store at least 1 bit value, etc. The storage element M can be implemented using one or more transistors. The storage element M can be implemented as a latch or a flip-flop, but is not limited to these. The storage element M can be implemented as a random access memory (RAM), such as an SRAM or DRAM, etc. Alternatively, the storage element M can be implemented as a 2-bit memory, etc.

[0106] The output signal from the storage element M can be input to the level shifter LS. The signal output from the level shifter LS can have a higher voltage level than the voltage level input to the level shifter LS, but the example embodiment is not limited to this. The level shifter LS can include, but is not limited to, a boost circuit that boosts the input voltage. The level shifter LS can be implemented as multiple transistors, but is not limited to this.

[0107] The output signal from the level shifter LS can be input to the gate of the first transistor T1. One end of the transistor T1 can be connected to the current source I1, and the other end can be connected to the light-emitting device LED to transmit or cut off the drive current to the light-emitting device LED, etc.

[0108] According to at least one example embodiment, since the storage element M storing a one-bit value is driven by the PWM clock signal P_CLK, the physical area of ​​the pixel PX3 can be reduced, etc.

[0109] Figure 11 This is a timing diagram illustrating the operation of pixels according to at least one example embodiment of the concept of the present invention. Figure 11 It shows including Figure 10 The operation of the pixel array of pixel PX3 is described, but the example embodiment is not limited thereto.

[0110] refer to Figure 11 According to at least one example embodiment, frame FR1 may include multiple subframes S1 to SN, etc. The number of subframes S1 to SN may be equal to the number N of bit values ​​to be represented by storage element M, and the period of subframes S1 to SN may be obtained by dividing the time T of one frame FR1 by 2. n The obtained period T / 2 n However, the example embodiments are not limited thereto. “n” is an integer that is 1 or greater and less than or equal to the number of bit values ​​to be represented by the storage element M, but is not limited thereto. “n” can be incremented from 1 to N, etc., in increments of 1.

[0111] For example, when the number of bits sequentially stored in storage element M is 8 (N=8), n can refer to an integer greater than or equal to 1 and less than or equal to 8, but the example embodiment is not limited thereto. Therefore, a frame FR1 may include a first subframe S1 to an eighth subframe S8, and the first subframe S1 to the eighth subframe S8 may have T / 2, T / 2 2 ..., T / 2 8 The cycle is as described, but the example embodiments are not limited thereto.

[0112] According to at least one example embodiment, the PWM clock signal P_CLK may include a first PWM clock signal P_CLK1 input to the first row, a second PWM clock signal P_CLK2 input to the second row, ..., and / or an Nth PWM clock signal P_CLKN input to the Nth row, etc. The first PWM clock signal P_CLK to the Nth PWM clock signal P_CLKN can be sent sequentially to each row. Therefore, rows can sequentially store data and cause the light-emitting device to emit light or not emit light.

[0113] The PWM clock signal P_CLK can be switched at all subframes S1 to SN, but the example embodiment is not limited to this. For example, the PWM clock signal P_CLK can be switched at the beginning of each subframe S1 to SN, but the example embodiment is not limited to this. Therefore, the PWM clock signal P_CLK can be switched by dividing the time T of a frame FR1 by 2. n (n is an integer greater than or equal to 1 and less than or equal to N) and obtain each T / 2 n Switching is possible, but the example embodiment is not limited to this. Since subframes S1 to SN have different periods, the PWM clock signal P_CLK can be switched with different time widths, but is not limited to this.

[0114] During the first cycle P1 when the PWM clock signal P_CLK is switched, data can be stored in the storage element M, and the light-emitting device LED can be lit or not lit during the remaining subframe cycles P2, but the example embodiment is not limited to this. In the multiple pixels PX3 arranged in each row of the pixel array, data can be stored sequentially during the first cycle P1, and the light-emitting device can be turned on or off during the second cycle P2, but the example embodiment is not limited to this.

[0115] For each subframe from S1 to SN, the first period P1 can be constant, and for each subframe from S1 to SN, the second period P2 can be different, but the example embodiment is not limited thereto. For example, the second period P2 of the first subframe S1 can be longer than the second period P2' of the second subframe S2, and the second period P2' of the second subframe S2 can be longer than the second period P2" of the Nth subframe SN, but the example embodiment is not limited thereto.

[0116] Multiple subframes S1 to SN may include data write cycles WR and / or light emission cycles LT1 to LTN, etc.

[0117] The data write cycle WR refers to the period during which data is input to all rows of the pixel array, while the emission cycles LT1 to LTN refer to the periods during which the light-emitting devices in all rows of the pixel array are turned on or off. During the data write cycle WR, rows 1 to n can sequentially receive multiple PWM clocks P_CLK1, P_CLK2, ..., P_CLKN. Therefore, during the data write cycles WR, data can be sequentially stored in pixels PX3 arranged in rows 1 to n.

[0118] The data write period WR of multiple subframes S1 to SN can be the same, and the emission periods LT1 to LTN can be different from each other, but the example embodiment is not limited to this. The emission periods LT1 to LTN of subframes S1 to SN can vary according to the periods of subframes S1 to SN, but the example embodiment is not limited to this. For example, the emission period LT1 of the first subframe S1 can be longer than the emission period LT2 of the second subframe S2, but it is not limited to this.

[0119] Figure 12 This is a circuit diagram illustrating at least one example embodiment of a pixel PX4 according to the concept of the present invention. Figure 12 It shows Figure 1 This is an example of a pixel PX, but the example embodiment is not limited thereto. Figure 12 It shows Figure 10 Another example embodiment of the pixel PX3 is described herein, and repeated descriptions thereof are omitted, but the example embodiment is not limited thereto.

[0120] refer to Figure 12 According to at least one example embodiment, pixel PX4 may include a storage element M, a current source I1, a light-emitting device LED, a transistor T1, a second transistor T2, and / or a third transistor T3, etc., but the example embodiment is not limited thereto. The second transistor T2 and the third transistor T3 may replace the "level shifter", but the example embodiment is not limited thereto.

[0121] The second transistor T2 and the third transistor T3 can be N-type transistors or P-type transistors, and they can be different types of transistors, but are not limited to these. Figure 12 As shown, the second transistor T2 can be a P-type transistor and the third transistor T3 can be an N-type transistor, but is not limited thereto.

[0122] The second transistor T2 can receive the output Q from the storage element M through its gate. One end of the second transistor T2 can receive a low-level source voltage VDDL, and the other end of the second transistor T2 can be connected to a current source I1, which generates a drive current based on a high-level source voltage VDDH.

[0123] The third transistor T3 can receive a signal Qb, complementary to the output Q, from the storage element M through its gate. A low-level source voltage VDDL is applied to one end of the third transistor T3, and the other end of the third transistor T3 can be connected to a current source I1, but the example embodiment is not limited to this.

[0124] According to at least one example embodiment, the level shifter LS includes a second transistor T2 and a third transistor T3. When the light-emitting device LED is off, a low-level source voltage VDDL can be applied to the first transistor T1. When the light-emitting device LED is on, a voltage equal to the forward voltage of the light-emitting device LED is applied to the first transistor T1, allowing the first transistor T1 to be driven at a low level. Therefore, compared to conventional light-emitting devices, the area of ​​the pixel PX4 can be reduced by using a low voltage level to drive the light-emitting device LED.

[0125] Figure 13 This is a circuit diagram illustrating at least one example embodiment of a pixel PX5 according to the concept of the present invention. Figure 13 It shows Figure 1 This is an example of a pixel PX, but the example embodiment is not limited thereto. Figure 13 It shows Figure 10 Another example embodiment of the pixel PX3 is described herein, and repeated descriptions thereof are omitted, but the example embodiment is not limited thereto.

[0126] refer to Figure 13 According to at least one example embodiment, pixel PX5 may include a first storage element M1, a second storage element M2, a first inverter INV1 and a second inverter INV2, an AND gate AG and / or a first transistor T1 to a third transistor T3, etc., but the example embodiment is not limited thereto.

[0127] The first storage element M1 can receive the first clock signal CLK1 and the first data DT1, but is not limited thereto. The second storage element M2 can receive the second clock signal CLK2 and the second data DT2, but is not limited thereto. The output from the second storage element M2 can be input to the first inverter INV1, etc.

[0128] The AND gate AG can receive the output from the first storage element M1 and the output from the first inverter INV1. The output from the AND gate AG can be sent to the gate of the first transistor T1, the gate of the second inverter INV2, and / or the gate of the third transistor T3, but is not limited thereto. The output signal from the second inverter INV2 can be sent to the gate of the second transistor T2, etc.

[0129] One end of the first transistor T1 can be connected to a current source I1 with a high level, and the other end of the first transistor T1 can be connected to a light-emitting device such as an LED. One end of the second transistor T2 and one end of the third transistor T3 can be connected to the current source I1, and a low-level voltage can be applied from the other end of the third transistor T3.

[0130] According to at least one example embodiment, by using a first storage element M1 and a second storage element M2, the time for the clock signal to transition from a low level to a high level can be maintained for a longer period. Therefore, because the time available for writing data is increased, device characteristics, etc., can be improved.

[0131] Figure 14 This is a circuit diagram illustrating at least one example embodiment of a pixel PX6 according to the concept of the present invention. Figure 14 It shows Figure 1 This is an example of a pixel PX, but the example embodiment is not limited thereto.

[0132] refer to Figure 14 According to at least one example embodiment, the pixel PX6 may include an inverter INV, a NOR gate, a switch SW, a capacitor CAP, and / or a transistor TR, etc., but the example embodiment is not limited thereto.

[0133] The inverter INV can receive the clock signal CLK1 as input. The output of the inverter INV can be sent to NOR gates and switches such as SW.

[0134] A NOR gate can receive data DT and the output from an inverter INV, and accumulate charge in capacitors such as CAP. Because a NOR gate outputs a high-level signal (e.g., value = "1") when all inputs are low (e.g., value = "0"), it can output a high-level signal when both data DT and the output from the inverter INV are low.

[0135] The switch SW can be located between the NOR gate and the capacitor CAP to disconnect or connect the electrical connection between the NOR gate and the capacitor CAP, etc. According to some example embodiments, the switch SW is controlled by the output of the inverter INV, etc., but the example embodiments are not limited to this.

[0136] The capacitor CAP can store charge based on and / or on the output from the NOR gate. Even when the electrical connection of the NOR gate is disconnected by a switch SW, the capacitor CAP can still use the previously accumulated charge to signal the transistor TR.

[0137] The transistor TR can be an N-type transistor or a P-type transistor. In at least one example embodiment, the transistor TR can be a P-type transistor, but it is not limited thereto. Therefore, when a low-level signal is input to the gate of the transistor TR, the transistor TR can be turned on. Therefore, when the transistor TR is turned on, the light-emitting device LED can emit light, and when the transistor TR is turned off, the light-emitting device LED does not emit light.

[0138] According to at least one example embodiment, the area of ​​pixel PX6 can be reduced by forming a pixel PX6 including a capacitor CAP.

[0139] Figure 15 This is a timing diagram illustrating the operation of pixels according to at least one example embodiment of the concept of the present invention. Figure 15 It shows including Figure 14 The operation of the pixel array of pixel PX6 is described, however, the example embodiment is not limited thereto.

[0140] refer to Figure 15 According to at least one example embodiment, a single frame may include multiple subframes S1 to SN, etc., but the example embodiment is not limited thereto. The number of subframes S1 to SN may be 2. n n can be greater than or equal to 1, and can be an integer less than or equal to the number of bits N to be represented, but is not limited to this. For example, when the number of bits to be represented is 8 (N = 8), the number of subframes can be 2. 8 wait.

[0141] The duration of the display and / or execution periods of subframes S1 to SN can be the same, but is not limited to this. The period of displaying and / or executing each of subframes S1 to SN can be calculated by dividing the period T of executing one frame by the number of subframes 2. n The obtained period T / 2 n wait.

[0142] The pixels arranged in the first row of the first column of the pixel array can receive a first clock signal CLK1 as a control signal, and a first drive current ILED1 can flow through the light-emitting device, but the example embodiment is not limited thereto. The pixels arranged in the second row of the first column of the pixel array can receive a second clock signal CLK2 as a control signal, and a second drive current ILED2 can flow through the light-emitting device, but are not limited thereto.

[0143] The first clock signal CLK1 can be switched during each period of subframes S1 to SN, but is not limited to this. The second clock signal CLK2 can be switched during each period of subframes S1 to SN, but is not limited to this. The first clock signal CLK1 and the second clock signal CLK2 can be sequentially input to the pixels connected to them, but are not limited to this. For example, immediately after the first clock signal CLK1 is input to the pixels arranged in the first row of the first column, the second clock signal CLK2 can be input to the pixels arranged in the second row of the first column, etc. In this way, control signals can be input to the pixels arranged in the nth row of the first column, etc.

[0144] Data DT can be input row by row. In at least one example embodiment, the data DT input to subframes S1 to SN can sequentially include data input to pixels arranged in the first row of the first column and data input to pixels arranged in the second row of the first column, but the example embodiment is not limited thereto. For example, in the first subframe S1, the data DT can be a signal for inputting 1 to pixels arranged in the first row of the first column and 0 to pixels arranged in the second row of the first column, etc.

[0145] Multiple pixels PX6 can selectively cut off the drive currents ILED1 and / or ILED2 flowing through the light-emitting device by combining control signals CLK1 and CLK2 with data DT. For example, since the input first clock signal CLK1 and the input data DT are "1" in the first subframe S1 of the pixels arranged in the first row of the first column, the first drive current ILED1 can flow through the light-emitting device when the first subframe S1 is executed and / or displayed. Subsequently, since the input first clock signal CLK1 and the input data DT are "0" during the second frame S2, the first drive current ILED1 can be cut off in the light-emitting device when the second subframe S2 is executed and / or displayed.

[0146] In the pixels arranged in the second row of the first column, the value of the first clock signal CLK1 and the input data DT during the first subframe S1 is "0", and the second clock signal CLK2 is switched after the first clock signal CLK1 is switched. Therefore, after the first drive current ILED1 flows, the second drive current ILED2, etc., can be cut off, but the example embodiment is not limited to this.

[0147] Figure 16 This is a diagram schematically illustrating the process of manufacturing a display device 30 according to at least one exemplary embodiment of the concept of the present invention.

[0148] refer to Figure 16The display device 30 according to at least one example embodiment may include, but is not limited to, an array of light-emitting devices 10 and / or a driving circuit board 20, etc. The array of light-emitting devices 10 may be coupled to the driving circuit board 20, etc.

[0149] The light-emitting device array 10 may include multiple light-emitting devices. These devices may be LEDs, but are not limited to them. They may be LEDs with a micrometer to nanometer scale, etc. At least one light-emitting device array 10 can be manufactured by growing multiple LEDs on a semiconductor wafer, but the example embodiments are not limited to this. Therefore, the display device 30 can be manufactured by combining the light-emitting device array 10 with the driving circuit board 20, without having to separately transfer the LEDs to the driving circuit board 20, etc.

[0150] The driver circuit board 20 may be equipped with pixel circuits corresponding to the LEDs on the light-emitting device array 10. The LEDs on the light-emitting device array 10 may be electrically connected to the pixel circuits on the driver circuit board 20 to form pixels PX, etc.

[0151] Although the inventive concept has been specifically shown and described with reference to various exemplary embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A display device, comprising: A pixel array comprising multiple rows, and each of the multiple rows comprising multiple pixels; The line driver is configured as follows: Generate multiple control signals, The plurality of rows of the pixel array are driven using the plurality of control signals, and Generate multiple clock signals; A line multiplexer is configured to receive the plurality of clock signals and selectively send one of the plurality of clock signals to the pixel array; as well as A data driver is configured to send multiple data signals to the pixel array in columns; Each of the plurality of pixels includes: Light-emitting devices A shift register is configured to receive selectively transmitted clock signals from the line multiplexer and generate a pulse-width modulated (PWM) signal with width adjustment based on the desired brightness level of the light-emitting device. A transistor is configured to transmit drive current to the light-emitting device based on the PWM signal.

2. The display device according to claim 1, wherein, The row driver is also configured to: Generate a data clock signal and a PWM clock signal, wherein the data clock signal and the PWM clock signal are included in the plurality of clock signals; and The shift register is also configured to: During the data write cycle, the plurality of data signals are stored based on the data clock signal, and The PWM signal is output based on the width adjustment of the PWM clock signal during the light emission cycle.

3. The display device according to claim 1, wherein, The plurality of pixels, including those in each of the plurality of rows, are configured to share a common row multiplexer.

4. The display device according to claim 1, wherein, The row driver is configured to drive the plurality of rows during a frame period, the frame period including a data write period and a light emission period; and The shift register includes multiple flip-flops, each of which is numbered from 1 to N, where N is an integer greater than 1.

5. The display device according to claim 4, wherein, The emission period includes multiple sub-frame periods, each of which has a different duration. and The row driver is also configured to switch the PWM clock signal in each subframe cycle based on the desired emission time of the light-emitting device.

6. The display device according to claim 5, wherein, The number of subframe periods in the plurality of subframe periods is the same as the number of triggers included in the shift register; The duration of each of the plurality of subframe periods is equal to the duration of the emission period divided by 2. n ;and n increases from 1 to N in increments of 1.

7. The display device according to claim 4, wherein, Each of the plurality of pixels also includes: A write multiplexer is configured to select a data signal from the plurality of data signals or a desired bit value stored in the plurality of flip-flops, and output the selected data signal or bit value to the shift register, wherein the desired flip-flop is configured to store the PWM signal.

8. The display device according to claim 1, wherein, Each of the plurality of pixels is further configured to be driven during a frame period, the frame period including a data write period and a light emission period; and The shift register includes multiple latches, each of which is numbered from 1 to N.

9. The display device according to claim 8, wherein, The row multiplexer includes multiple multiplexers corresponding to the multiple latches; and The plurality of multiplexers are configured to select one of the plurality of clock signals and send the selected clock signal to the plurality of latches corresponding to the plurality of multiplexers.

10. The display device according to claim 8, wherein, The shift register further includes a feedback latch, which is configured to store a bit value stored in a desired latch among the plurality of latches, the desired latch being configured to output the PWM signal; and Each of the plurality of pixels further includes a write multiplexer configured to select a data signal from the plurality of data signals or a bit value stored in the feedback latch, and output the selected data signal or bit value to the shift register.

11. The display device according to claim 8, wherein, The emission period includes multiple sub-frame periods, each with a different duration; and The line driver is also configured to serially switch the PWM clock signal in each of the plurality of subframe cycles, and to control the light emission time of the light-emitting device based on the PWM clock signal.

12. The display device according to claim 11, wherein, The line driver is also configured to switch the feedback PWM clock signal in each of the plurality of subframe cycles, and to switch the feedback PWM clock signal before serially switching the PWM clock signal.

13. The display device according to claim 1, wherein, The shift register is configured to store multiple bit values.

14. A display device, comprising: A pixel array, comprising a plurality of pixels arranged in multiple rows and columns, wherein each pixel comprises a light-emitting device and a storage element; A row driver is configured to generate multiple control signals and multiple clock signals, and to drive the pixel array row by row using the multiple control signals, the multiple clock signals including a first clock signal. The line driver is also configured to adjust the width of the first clock signal to control the brightness of at least one of the plurality of light-emitting devices; as well as A data driver is configured to output multiple data signals column-by-column to the pixel array. The row driver is further configured to drive each of the plurality of pixels during a frame period, the frame period comprising a plurality of subframe periods, and to switch the first clock signal once in each of the plurality of subframe periods.

15. The display device according to claim 14, wherein, The duration of each of the plurality of subframe periods is equal to the frame period divided by 2. n , where n increases from 1 to N in increments of 1.

16. The display device according to claim 14, wherein, The storage element is any one of a latch, flip-flop, or static random access memory (SRAM) configured to store bit values; and Each of the plurality of pixels includes: A level shifter is configured to receive at least one signal output from the storage element and convert the received at least one signal into a corresponding voltage level. The first transistor is configured to control the light-emitting device of the pixel to be turned on or off based on the output from the level shifter.

17. The display device according to claim 16, wherein, The at least one signal output from the storage element includes a first signal and a second signal, wherein the second signal is complementary to the first signal; and The level shifter includes: An N-type transistor is configured to receive the first signal; as well as A P-type transistor is configured to receive the second signal, and Both the N-type transistor and the P-type transistor are configured to receive a low-level source voltage at their first terminals and a high-level source voltage at their second terminals, respectively.

18. The display device according to claim 14, wherein, The storage element includes: The shift register is configured as follows: Receive a selected clock signal from the plurality of clock signals, and A pulse width modulation (PWM) signal is generated, and the width of the PWM signal is adjusted based on the desired brightness of the light-emitting device.

19. A pixel, comprising: Light-emitting devices; The NOR gate is configured to receive a clock signal for controlling the light-emitting device; as well as A capacitor is configured to store the output from the NOR gate; as well as A switch is configured to selectively disconnect the NOR gate from the capacitor based on the clock signal.

20. The pixel according to claim 19, wherein, The clock signal switches repeatedly at desired time intervals.

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