Data input buffer and semiconductor device including the same

Abstract

The present application relates to a data input buffer and a semiconductor device including the same. A data input buffer includes a plurality of buffer units configured to receive a first impedance calibration code and a second impedance calibration code, wherein each of the plurality of buffer units outputs a detected offset in a case where a first input terminal and a second input terminal thereof are short-circuited as write data, and wherein a buffer unit among the plurality of buffer units corresponding to a current value of the first impedance calibration code is configured to correct the offset according to the second impedance calibration code.

Description

Technical Field

[0001] Various implementations generally relate to semiconductor circuits, and more specifically, to data input buffers and semiconductor devices including the data input buffers. Background Technology

[0002] Semiconductor devices include data input buffers for receiving data received from outside the semiconductor device. The data input buffer identifies data bits as "0" or "1" by comparing the input data with a reference voltage. However, due to variations in PVT (power, voltage, and temperature), a shift occurs in the output signal of the data input buffer, which degrades the operational reliability of the data input buffer and ultimately degrades the operational performance of the semiconductor device including the data input buffer. Summary of the Invention

[0003] Various implementations relate to a data input buffer capable of removing offsets from the data input buffer and a semiconductor device including the data input buffer.

[0004] In one embodiment, a data input buffer may include: a plurality of buffer units configured to receive a first impedance calibration code and a second impedance calibration code, wherein each of the plurality of buffer units outputs an offset detected when its first and second input terminals are short-circuited as write data, and wherein a buffer unit among the plurality of buffer units corresponding to the current value of the first impedance calibration code is configured to correct the offset according to the second impedance calibration code.

[0005] In one embodiment, a semiconductor device may include: an impedance calibration circuit configured to perform an offset correction operation that calibrates the value of an impedance calibration code based on written data in response to an impedance calibration command and mode register setting information; and a data input buffer configured to detect an offset, output the detected offset information as written data, and correct the offset based on the impedance calibration code.

[0006] When the mode register setting information is set to the first logic level, the controller can control the impedance calibration circuit according to the impedance calibration command, causing the impedance calibration circuit to perform offset correction and impedance calibration operations sequentially. When the mode register setting information is set to the second logic level, the controller can control the impedance calibration circuit according to the impedance calibration command, causing the impedance calibration circuit to perform only impedance calibration operations.

[0007] In one embodiment, a semiconductor device may include: a data input buffer comprising a plurality of buffer units receiving a first impedance calibration code and a second impedance calibration code, wherein each of the plurality of buffer units outputs an offset detected when its first and second input terminals are short-circuited, as write data, and wherein a buffer unit among the plurality of buffer units corresponding to the current value of the first impedance calibration code is configured to correct the offset according to the second impedance calibration code; a data output buffer configured to drive read data with an output impedance calibrated according to the first and second impedance calibration codes, so as to output the driven read data through a data input / output unit; and an impedance calibration circuit configured to perform an impedance calibration operation based on an external resistor to calibrate the output impedance of the data output buffer in response to an impedance calibration command, by calibrating the value of at least one of the first and second impedance calibration codes according to the write data; and to perform an offset correction operation based on a mode register setting information and an impedance calibration command to correct the offset of the data input buffer.

[0008] The impedance calibration circuit can be configured to perform offset correction and impedance calibration operations sequentially according to the impedance calibration command when the mode register setting information is set to the first logic level, and to perform only impedance calibration operation according to the impedance calibration command when the mode register setting information is set to the second logic level. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating the configuration of a semiconductor system according to an embodiment.

[0010] Figure 2 This is a diagram illustrating the configuration of a semiconductor device according to an embodiment.

[0011] Figure 3 This is an example Figure 2 A diagram showing the configuration of the impedance calibration circuit.

[0012] Figure 4 This is an example Figure 3 A diagram showing the configuration of the controller.

[0013] Figure 5 This is an example Figure 3 The calibration is complete. The diagram shows the configuration of the detection circuit.

[0014] Figure 6 This is an example Figure 2 A diagram showing the configuration of the data input buffer.

[0015] Figure 7 This is an example Figure 6A diagram showing the configuration of the buffer unit.

[0016] Figure 8 This is an example Figure 7 The circuit configuration diagram of the first amplifier circuit and the second amplifier circuit is shown.

[0017] Figure 9 This is a schematic illustration of the configuration of the impedance calibration circuit and data input buffer according to an embodiment. Detailed Implementation

[0018] In the following description, various embodiments of a data input buffer and a semiconductor device including the data input buffer will be described with reference to the accompanying drawings.

[0019] Figure 1 This is a diagram illustrating the configuration of semiconductor system 1 according to an embodiment.

[0020] Reference Figure 1 The semiconductor system 1 may include a memory controller 2 and a semiconductor device 10.

[0021] The memory controller 2 can provide the semiconductor device 10 with a power supply voltage, data DQ, a reference voltage VREF, and / or a control signal CTRL. The power supply voltage, serving as the power source for the operation of the semiconductor device 10, will be referred to hereinafter as the external voltage VCCQ. The control signal CTRL can include multiple signals, namely, commands, addresses, and various signals for controlling data reception of the semiconductor device 10. Depending on the operating mode of the semiconductor device 10, the various signals for controlling data reception can have different values. For example, according to the specifications of the semiconductor device 10, such as low-speed mode, high-speed mode, etc., the various signals for controlling data reception can have different values, which will be described later. The memory controller 2 can receive data DQ from the semiconductor device 10.

[0022] Semiconductor device 10 can receive data DQ from memory controller 2 according to control signal CTRL and write the received data DQ into a memory region in semiconductor device 10, or it can read data DQ written into memory region in semiconductor device 10 according to control signal CTRL and provide the read data DQ to memory controller 2. Semiconductor device 10 can detect and correct the offset of data input buffer by using a code signal for impedance calibration of data output buffer, which will be described later.

[0023] Figure 2 This is a diagram illustrating the configuration of a semiconductor device 10 according to an embodiment.

[0024] Reference Figure 2The semiconductor device 10 may include a memory region 11, a data input / output unit 13, an impedance calibration circuit 100, a data input buffer 200, and a data output buffer 300.

[0025] Memory region 11 can output read data RDATA<0:N> according to a read command, and store write data WDATA<0:N> input to the memory region according to a write command. Memory region 11 may include at least one of volatile memory and non-volatile memory. Examples of volatile memory may include SRAM (Static RAM), DRAM (Dynamic RAM), and SDRAM (Synchronous DRAM). Examples of non-volatile memory may include ROM (Read-Only Memory), PROM (Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), EPROM (Electrically Programmable ROM), flash memory, PRAM (Phase Change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), and FRAM (Ferroelectric RAM).

[0026] The data input / output unit 13 may include a plurality of data input / output pads DQ. Data input / output between the semiconductor device 10 and an external device (e.g., memory controller 2) can be performed through the data input / output unit 13.

[0027] Impedance calibration circuit 100 can perform an impedance calibration operation in response to impedance calibration command ZQC, calibrating at least one of the values ​​of a first impedance calibration code PUCODE<0:N> and a second impedance calibration code PDCODE<0:N> based on the impedance of an external resistor RZQ. The impedance calibration operation can be performed by calibrating at least one of the first impedance calibration code PUCODE<0:N> and the second impedance calibration code PDCODE<0:N> to match the output impedance of the semiconductor device 10 with the impedance of the external resistor RZQ. The impedance calibration operation can be performed during a time period separate from the read operation period and write operation period (e.g., an initialization period) of the semiconductor device 10.

[0028] Impedance calibration circuit 100 can perform an offset correction operation in response to impedance calibration command ZQC and mode register setting information CNF_OCC, calibrating at least one of the values ​​of a first impedance calibration code PUCODE<0:N> and a second impedance calibration code PDCODE<0:N> based on written data WDATA<0:N>. The offset correction operation can be performed during a time period independent of the impedance calibration operation. Impedance calibration circuit 100 can generate an offset correction enable signal OCC_EN in response to impedance calibration command ZQC and mode register setting information CNF_OCC. Mode register setting information CNF_OCC can define whether, based on impedance calibration command ZQC, only the impedance calibration operation is performed, or the offset correction operation and impedance calibration operation are performed sequentially. For example, when mode register setting information CNF_OCC is set to high, impedance calibration circuit 100 can perform the offset correction operation and impedance calibration operation sequentially according to impedance calibration command ZQC. When mode register setting information CNF_OCC is set to low, impedance calibration circuit 100 can perform only the impedance calibration operation according to impedance calibration command ZQC.

[0029] During a write operation of the semiconductor device 10, the data input buffer 200 can generate write data WDATA<0:N> by receiving data input through the data input / output unit 13. The data input buffer 200 can detect offset in response to the offset correction enable signal OCC_EN and output the detected offset information as write data WDATA<0:N>. The data input buffer 200 can correct the offset based on the first impedance calibration code PUCODE<0:N> and the second impedance calibration code PDCODE<0:N>. The data input buffer 200 may include multiple buffer units RX corresponding to multiple data input / output pads DQ of the data input / output unit 13.

[0030] The output impedance of the data output buffer 300 can be changed according to the first impedance calibration code PUCODE<0:N> and the second impedance calibration code PDCODE<0:N>. The data output buffer 300 can drive the read data RDATA<0:N> with the output impedance determined according to the first impedance calibration code PUCODE<0:N> and the second impedance calibration code PDCODE<0:N>, and can output the driven read data RDATA<0:N> through the data input / output unit 13. The data output buffer 300 may include a plurality of pre-pull-up drivers 301, a plurality of pre-pull-down drivers 302, a plurality of main pull-up drivers 401, and a plurality of main pull-down drivers 402. The plurality of pre-pull-up drivers 301 can generate a pull-up control signal PU<0:M> by driving the read data RDATA<0:N> according to the first impedance calibration code PUCODE<0:N>. The plurality of pre-pull-down drivers 302 can generate a pull-down control signal PD<0:M> by driving the read data RDATA<0:N> according to the second impedance calibration code PDCODE<0:N>. Multiple master pull-up drivers 401 can drive the data input / output unit 13 with an impedance determined according to the pull-up control signal PU<0:M>. Multiple master pull-down drivers 402 can drive the data input / output unit 13 with an impedance determined according to the pull-down control signal PD<0:M>.

[0031] Figure 3 This is an example Figure 2 A diagram showing the configuration of the impedance calibration circuit 100.

[0032] Reference Figure 3 The impedance calibration circuit 100 may include a controller 101, a timer / counter 102, an impedance calibration code generator 103, a multiplexer 104, and a calibration completion detection circuit 105.

[0033] Controller 101 can generate multiple internal commands ZQINIT and ZQOPER that define the performance of the impedance calibration operation in response to the impedance calibration command ZQC. According to the operating standards of semiconductor device 10, the impedance calibration command ZQC can be generated by a combination of CS (Chip Select), RAS (Row Access Strobe), CAS (Column Access Strobe), and WE (Write Enable). Controller 101 can generate an offset correction enable signal OCC_EN in response to the impedance calibration command ZQC, the mode register setting information CNF_OCC, the first impedance calibration code PUCODE<0:N>, the first code status signal BB_HOLD, and the second code status signal CODE_FULL. For example, when the mode register setting information CNF_OCC is set high, controller 101 can cause the impedance calibration circuit 100 to sequentially perform an offset correction operation and an impedance calibration operation according to the impedance calibration command ZQC. When the mode register setting information CNF_OCC is set to low, the controller 101 can keep the offset correction enable signal OCC_EN in the disabled state according to the impedance calibration command ZQC, so that the impedance calibration circuit 100 can only perform impedance calibration operation.

[0034] The timer counter 102 can generate the operation control signal CAL_OPER, which is used to set the impedance calibration operation time corresponding to each of the multiple internal commands ZQINIT and ZQOPER, by using the clock signal CLK.

[0035] The impedance calibration code generator 103 can generate a first impedance calibration code PUCODE<0:N> and a second impedance calibration code PDCODE<0:N> by performing an impedance calibration operation according to the operation control signal CAL_OPER. The impedance calibration code generator 103 can also generate the first impedance calibration code PUCODE<0:N> and the second impedance calibration code PDCODE<0:N> by performing an offset correction operation according to the offset correction enable signal OCC_EN, the timing signal OCC_CLK, and the counting control signal CNT_UPDN. The timing signal OCC_CLK can be used to change the buffer unit to... Figure 2 The signal that performs offset correction operation between multiple buffer units RX of the data input buffer 200.

[0036] The impedance calibration code generator 103 may include a first comparator 110, a first counter 120, a first digital-to-analog converter 140, a second comparator 150, a second counter 160, a second digital-to-analog converter 180, and a third digital-to-analog converter 190.

[0037] The first comparator 110 can compare the first reference voltage VREF1 and the voltage of the first node NA during the activation period of the operation control signal CAL_OPER according to the impedance calibration command ZQC, and thus output the comparison result. The first node NA can be connected to the external resistor RZQ via the external resistor pad ZQ.

[0038] The first counter 120 can calibrate the value of the first impedance calibration code PUCODE<0:N> by performing up / down counting based on the output of the first comparator 110. The first counter 120 can calibrate the value of the first impedance calibration code PUCODE<0:N> according to changing the timing signal OCC_CLK. The first counter 120 can initialize the value of the first impedance calibration code PUCODE<0:N> according to the offset correction enable signal OCC_EN.

[0039] The first digital-to-analog converter 140 can convert the first impedance calibration code PUCODE<0:N> into an analog voltage level and apply the analog voltage level to the first node NA. The first digital-to-analog converter 140 may include multiple PMOS transistors and resistors. The multiple PMOS transistors may be connected between a terminal of the power supply voltage VDDQ and one end of the resistor. The other end of the resistor may be connected to an external resistor pad ZQ. The first digital-to-analog converter 140 may have a circuit configuration obtained by replicating multiple master pull-up drivers 401 of the data output buffer 300. The first digital-to-analog converter 140 can be connected to an external resistor RZQ via the external resistor pad ZQ.

[0040] The second comparator 150 can compare the voltage of the first reference voltage VREF1 and the voltage of the second node NB during the activation period of the operation control signal CAL_OPER according to the impedance calibration command ZQC, and thus output the comparison result.

[0041] The second counter 160 can calibrate the value of the second impedance calibration code PDCODE<0:N> by performing up / down counting based on the output of the second comparator 150. The second counter 160 can calibrate the value of the second impedance calibration code PDCODE<0:N> according to the counting control signal CNT_UPDN. The second counter 160 can initialize the value of the second impedance calibration code PDCODE<0:N> by changing the timing signal OCC_CLK.

[0042] The second digital-to-analog converter 180 can convert the first impedance calibration code PUCODE<0:N> into an analog voltage level and apply this analog voltage level to the second node NB. The second digital-to-analog converter 180 may include multiple PMOS transistors and resistors. The multiple PMOS transistors may be connected between a terminal of the power supply voltage VDDQ and one end of the resistor. The other end of the resistor may be connected to the second node NB. The second digital-to-analog converter 180 may have a circuit configuration obtained by replicating multiple master pull-up drivers 401 of the data output buffer 300.

[0043] The third digital-to-analog converter 190 can convert the second impedance calibration code PDCODE<0:N> into an analog voltage level and apply that analog voltage level to the second node NB. The third digital-to-analog converter 190 may include multiple NMOS transistors and resistors. The multiple NMOS transistors may be connected between a terminal of the ground terminal and one end of the resistor. The other end of the resistor may be connected to the second node NB. The third digital-to-analog converter 190 may have a circuit configuration obtained by replicating multiple master pull-down drivers 402 of the data output buffer 300.

[0044] The multiplexer 104 can select one of the write data WDATA<0:N> according to the first impedance calibration code PUCODE<0:N>, and output one of the selected write data WDATA<0:N> as the counting control signal CNT_UPDN.

[0045] The calibration completion detection circuit 105 can generate a first code status signal BB_HOLD, a second code status signal CODE_FULL, and a timing change signal OCC_CLK based on the count control signal CNT_UPDN and the second impedance calibration code PDCODE<0:N>. The calibration completion detection circuit 105 can generate the first code status signal BB_HOLD based on the count control signal CNT_UPDN. The calibration completion detection circuit 105 can generate the second code status signal CODE_FULL based on the second impedance calibration code PDCODE<0:N>. The calibration completion detection circuit 105 can generate the timing change signal OCC_CLK by combining the first code status signal BB_HOLD and the second code status signal CODE_FULL. As the offset corrected by the offset correction operation approaches "0" within the error tolerance, the first code status signal BB_HOLD can be activated (e.g., to a high level) when the value of the count control signal CNT_UPDN is detected to repeat "0" (logic low) and "1" (logic high) at least a preset number of times. The second code status signal CODE_FULL can be activated when it is detected that the value of the second impedance calibration code PDCODE<0:N> has reached its limit. The fact that the value of the second impedance calibration code PDCODE<0:N> has reached its limit can indicate either the case where the value of the second impedance calibration code PDCODE<0:N> has become its maximum value and therefore cannot be increased further, or the case where the value of the second impedance calibration code PDCODE<0:N> has become its minimum value and therefore cannot be decreased further.

[0046] Figure 4 This is an example Figure 3 A diagram showing the configuration of controller 101.

[0047] Reference Figure 4 The controller 101 may include a flip-flop 101-1 and first logic gates 101-2 to seventh logic gates 101-8.

[0048] Flip-flop 101-1 can receive the power supply voltage VCC through input terminal D based on the input to clock terminal CK, receive the offset correction completion signal OCC_DONEB through reset terminal RST, and output the offset correction enable signal OCC_EN through output terminal Q. Flip-flop 101-1 can output the level of the power supply voltage VCC as the offset correction enable signal OCC_EN based on the rising edge of the signal input through clock terminal CK. Flip-flop 101-1 can initialize the value of the offset correction enable signal OCC_EN based on the offset correction completion signal OCC_DONEB. The first logic gate 101-2 and the second logic gate 101-3 can perform a logical AND operation on the impedance calibration command ZQC and the mode register setting information CNF_OCC, thereby inputting the result of the logical AND operation to the clock terminal CK of flip-flop 101-1. The third logic gate 101-4 can output the result of a logical NAND operation performed on each bit of the second impedance calibration code PDCODE<0:N>. When all bits of the second impedance calibration code PDCODE<0:N> are "1", that is, when the last buffer cell for offset correction is selected among the multiple buffer cells RX of the data input buffer 200, the third logic gate 101-4 can output a low-level signal. The fourth logic gate 101-5 can output the result of a logical NOR operation performed on the first code status signal BB_HOLD and the second code status signal CODE_FULL. When either the first code status signal BB_HOLD or the second code status signal CODE_FULL is high, that is, when the offset correction of the corresponding buffer cell is completed, the fourth logic gate 101-5 can output a low-level signal. The fifth logic gate 101-6 and the sixth logic gate 101-7 can output the result of a logical OR operation performed on the output of the third logic gate 101-4 and the output of the fourth logic gate 101-5, as the offset correction completion signal OCC_DONEB. When the offset correction operation for all buffer cells RX of the data input buffer 200 is completed, the fifth logic gate 101-6 and the sixth logic gate 101-7 can output an offset correction completion signal OCC_DONEB with a low level. The seventh logic gate 101-8 can invert the offset correction enable signal OCC_EN, thereby generating an inverted offset correction enable signal OCC_ENB.

[0049] Figure 5 This is an example Figure 3 The diagram shows the configuration of the calibration completion detection circuit 105.

[0050] Reference Figure 5The calibration completion detection circuit 105 may include a shift register 105-1, a first decoder 105-2, a second decoder 105-3, an inverter array 105-4, a third decoder 105-5, a first logic gate 105-6, and a second logic gate 105-7.

[0051] Shift register 105-1 can output a multi-bit signal by shifting the counting control signal CNT_UPDN according to the clock signal CLK. For example, shift register 105-1 can be designed to output 2. An N-bit signal is used to detect the counting control signal CNT_UPDN repeating "01" N times and "10" N times. The fact that the output signal of shift register 105-1 repeats "01" N times and "10" N times indicates that the offset corrected by the offset correction operation is close to "0" within the error tolerance.

[0052] The first decoder 105-2 can generate the first code status signal BB_HOLD by decoding the output signal of the shift register 105-1. For example, when the shift register 105-1 is designed to output a 4-bit signal, the first decoder 105-2 can output a high-level first code status signal BB_HOLD when the output signal of the shift register 105-1 is "0101" and when the output signal of the shift register 105-1 is "1010".

[0053] The second decoder 105-3 can decode and output the second impedance calibration code PDCODE<0:N>. The second decoder 105-3 can detect the maximum value of the second impedance calibration code PDCODE<0:N>. When the value of the second impedance calibration code PDCODE<0:N> is the maximum value, that is, when all bits are "1", the second decoder 105-3 can output a high-level signal.

[0054] The inverter array 105-4 can invert and output the second impedance calibration code PDCODE<0:N>.

[0055] The third decoder 105-5 can decode and output the output of the inverter array 105-4. The third decoder 105-5 can detect the minimum value of the second impedance calibration code PDCODE<0:N>. When the value of the second impedance calibration code PDCODE<0:N> is the minimum value, that is, when all bits are "0", the third decoder 105-5 can output a high-level signal.

[0056] The first logic gate 105-6 can perform a logical OR operation on the output of the second decoder 105-3 and the output of the third decoder 105-5, and output the result as the second code status signal CODE_FULL.

[0057] The second logic gate 105-7 can output the result of performing a logical OR operation on the first code status signal BB_HOLD and the second code status signal CODE_FULL, which is used as the change timing signal OCC_CLK.

[0058] Figure 6 This is an example Figure 2 A diagram showing the configuration of the data input buffer 200.

[0059] Reference Figure 6 The data input buffer 200 may include multiple buffer units 201-0 to 201-N.

[0060] Multiple buffer units 201-0 to 201-N can generate write data WDATA<0:N> by comparing the voltage levels of their corresponding data input / output pads DQ<0:N> with a reference voltage VREFQ. For example, the first buffer unit 201-0 can generate write data WDATA<0:N> by comparing the voltage levels of its corresponding data input / output pads DQ<0:N> with a reference voltage VREFQ. <0> The voltage level is compared with the reference voltage VREFQ to generate the write data WDATA. <0> Multiple buffer units 201-0 to 201-N can jointly receive the offset correction enable signal OCC_EN, the first impedance calibration code PUCODE<0:N>, and the second impedance calibration code PDCODE<0:N>. The multiple buffer units 201-0 to 201-N can detect the offset between the first input terminal (+) and the second input terminal (-) in response to the offset correction enable signal OCC_EN, and can output the detected offset information as write data WDATA<0:N>. The multiple buffer units 201-0 to 201-N can correct the offset based on the first impedance calibration code PUCODE<0:N> and the second impedance calibration code PDCODE<0:N>.

[0061] Figure 7 This is an example Figure 6 A diagram showing the configuration of buffer unit 201-0.

[0062] Reference Figure 7 The buffer unit 201-0 may include a first receiver 210, a connector 220, a decoder 230, a second receiver 240, a multiplexer 250, and a driver 260.

[0063] The first receiver 210 can amplify the signal transmitted through the data input / output pads DQ. <0> The difference between the voltage level of the input data and the reference voltage VREF is output. The first receiver 210 can correct its offset according to offset correction codes CDAC<0:M> and CDACB<0:M>. The first receiver 210 may include one or more amplifier circuits, such as a first amplifier circuit 211, a second amplifier circuit 212, and a third amplifier circuit 213. The offset correction codes CDAC<0:M> and CDACB<0:M> can be input to at least one of the first amplifier circuits 211, 212, and 213, such as the first amplifier circuit 211. The offset of the first receiver 210 can be corrected by calibrating the load resistance value of the first amplifier circuit 211 according to the offset correction codes CDAC<0:M> and CDACB<0:M>. The first receiver 210 can be used when the semiconductor device 10 is operating in a high-speed mode.

[0064] Connector 220 can short-circuit the first input terminal (+) and the second input terminal (-) of the first amplifier circuit 211 according to the offset correction enable signal OCC_EN and the inverting offset correction enable signal OCC_ENB. Connector 220 may include a transmission gate configured to short-circuit the first input terminal (+) and the second input terminal (-) according to the offset correction enable signal OCC_EN and the inverting offset correction enable signal OCC_ENB. As connector 220 short-circuits the first input terminal (+) and the second input terminal (-) of the first amplifier circuit 211, the third amplifier circuit 213 can output a signal with a logic level corresponding to the offset of buffer unit 201-0.

[0065] Decoder 230 can latch a second impedance calibration code PDCODE<0:N> based on the first impedance calibration code PUCODE<0:N>, and can decode the latched code to generate offset correction codes CDAC<0:M> and CDACB<0:M>. Decoder 230 can also latch the second impedance calibration code PDCODE<0:N> when the first impedance calibration code PUCODE<0:N> has a corresponding value (e.g., "000"), and can decode the latched code to generate offset correction codes CDAC<0:M> and CDACB<0:M>.

[0066] When the semiconductor device 10 operates in a low-speed mode, which operates at a relatively slower operating frequency compared to the high-speed mode, a second receiver 240 can be used as a component that operates at a relatively low speed compared to the first receiver 210. The second receiver 240 may include an inverter chain 241 and a level shifter 242. The level shifter 242 can convert a signal output from the inverter chain 241 with an external power supply voltage VCCQ to an internal power supply voltage VCCI and output it.

[0067] Multiplexer 250 generates output signal BUFOUT by selecting one of the outputs of first receiver 210 and second receiver 240 according to the multiplexing control signal EN_VREF. The multiplexing control signal EN_VREF can have different values ​​(high level / low level) depending on the operating mode (high speed mode / low speed mode) setting of semiconductor device 10. Multiplexer 250 can select and output the output of first receiver 210 when the multiplexing control signal EN_VREF is high, and can select and output the output of second receiver 240 when the multiplexing control signal EN_VREF is low.

[0068] Driver 260 can generate write data WDATA by using the output signal BUFOUT of driver multiplexer 250. <0> .

[0069] Figure 8 This is an example Figure 7 A diagram showing the circuit configuration of the first amplifier circuit 211 and the second amplifier circuit 212.

[0070] Reference Figure 8 The first amplifier circuit 211 may include a plurality of transistors 301 to 305 and a plurality of variable loads 306 and 307.

[0071] The first transistor 301 can operate as a current source, calibrating the current amount according to the internal power supply voltage VCCI in response to a first bias voltage VB1. The internal power supply voltage VCCI can be applied to the source terminal of the first transistor 301, and the first bias voltage VB1 can be input to the gate terminal of the first transistor 301. The source terminals of the second transistor 302 and the third transistor 303 can be connected to the drain terminal of the first transistor 301. A differential pair can be configured by the second transistor 302 and the third transistor 303. A reference voltage VREF can be input to the gate terminal of the second transistor 302, and a first output signal can be generated through the drain terminal of the second transistor 302. Data input / output pad DQ <0> The first variable load 302 can be connected to the gate terminal of the third transistor 303, and a second output signal complementary to the first output signal can be generated through the drain terminal of the third transistor 303. The drain terminal of the second transistor 302 can be connected to the drain terminal of the fourth transistor 304, and an enable signal EN can be input to the gate terminal of the fourth transistor 304. One end of the first variable load 306 can be connected to the source terminal of the fourth transistor 304, and the other end of the first variable load 306 can be connected to the ground terminal. The first variable load 306 may include a plurality of transistors 311-0 to 311-M. The plurality of transistors 311-0 to 311-M may have a drain terminal commonly connected to the source terminal of the fourth transistor 304, a source terminal connected to the ground terminal, and gate terminals respectively input with offset correction code CDAC<0:M>. The resistance value of the first variable load 306 can be calibrated according to the offset correction code CDAC<0:M>. The drain terminal of the third transistor 303 can be connected to the drain terminal of the fifth transistor 305, and the enable signal EN can be input to the gate terminal of the fifth transistor 305. One end of the second variable load 307 can be connected to the source terminal of the fifth transistor 305, and the other end of the second variable load 307 can be connected to the ground terminal. The second variable load 307 can be configured in the same manner as the first variable load 306, and the resistance value of the second variable load 307 can be calibrated according to the offset correction code CDACB<0:M>. The first amplifier circuit 211 can amplify the data input / output pad DQ according to the reference voltage VREF during the activation period (e.g., high level period) of the enable signal EN. <0> The input data can be output. The first amplifier circuit 211 can remove the offset of the data input buffer 200 by calibrating the resistance values ​​of the first variable load 306 and the second variable load 307 according to the offset correction codes CDAC<0:M> and CDACB<0:M>.

[0072] The second amplifier circuit 212 generates a differential output signal OUT / OUTB by amplifying the difference between the first output signal and the second output signal of the first amplifier circuit 211. The second amplifier circuit 212 can be configured in the same manner as the first amplifier circuit 211. The first and second variable loads of the second amplifier circuit 212 can have their resistance values ​​set according to separate codes, not based on offset correction codes CDAC<0:M> and CDACB<0:M>. The codes applied to the first and second variable loads can be set by a mode register group, etc.

[0073] Figure 9 This is a diagram that schematically illustrates the configuration of the impedance calibration circuit 100 and the data input buffer 200 according to an embodiment.

[0074] The following will refer to Figure 9 The offset correction operation of the data input buffer 200 according to the implementation method is described.

[0075] In the impedance calibration operation according to the embodiment, the first impedance calibration code PUCODE<0:N> and the second impedance calibration code PDCODE<0:N> can be used for output impedance calibration of the data output buffer 300. In the offset correction operation according to this embodiment, the first impedance calibration code PUCODE<0:N> can be used to sequentially select buffer units 201-0 to 201-N of the data input buffer 200, and the second impedance calibration code PDCODE<0:N> can be used for offset correction of each of the buffer units 201-0 to 201-N.

[0076] With the impedance calibration command ZQC and the mode register setting information CNF_OCC input at a high level, the controller 101 outputs a high-level offset correction enable signal OCC_EN.

[0077] With the offset correction enable signal OCC_EN output at a high level, the connector 220 of each of the buffer units 201-0 to 201-N can short-circuit the first input terminal (+) and the second input terminal (-) of the first amplifier circuit 211, and the third amplifier circuit 213 can output a logic level corresponding to the offset of each of the buffer units 201-0 to 201-N as each written data WDATA<0:N>.

[0078] With the offset correction enable signal OCC_EN outputting a high level, the first counter 120 can initialize the first impedance calibration code PUCODE<0:N>, and the multiplexer 104 can write data WDATA according to the initialized first impedance calibration code PUCODE<0:N> output. <0> The written data WDATA<0:N> serves as the count control signal CNT_UPDN, thereby enabling the start of offset correction operations for any of the buffer units 201-0 to 201-N (e.g., buffer unit 201-0).

[0079] The second counter 160 can increase or decrease the value of the second impedance calibration code PDCODE<0:N> according to the counting control signal CNT_UPDN. When the counting control signal CNT_UPDN is high, the second counter 160 can increase the value of the second impedance calibration code PDCODE<0:N>, and when the counting control signal CNT_UPDN is low, the second counter 160 can decrease the value of the second impedance calibration code PDCODE<0:N>.

[0080] The decoder 230 of buffer unit 201-0, which corresponds to the value of the initialized first impedance calibration code PUCODE<0:N>, can calibrate the values ​​of offset correction codes CDAC<0:M> and CDACB<0:M> by latching and decoding the second impedance calibration code PDCODE<0:N>. The resistance value of the first amplifier circuit 211 can be calibrated according to the offset correction codes CDAC<0:M> and CDACB<0:M>.

[0081] When the offset of buffer unit 201-0 is corrected within the error tolerance by repeatedly calibrating the resistance value of the first amplifier circuit 211 using the calibration offset correction codes CDAC<0:M> and CDACB<0:M>, the least significant bit of the second impedance calibration code PDCODE<0:N> repeats "0" and "1". When the calibration completion detection circuit 105 detects that the least significant bit of the second impedance calibration code PDCODE<0:N> repeats "0" and "1" a preset number of times and outputs a high-level first code status signal BB_HOLD, the offset correction operation for buffer unit 201-0 is completed. Furthermore, when the calibration completion detection circuit 105 outputs a high-level second code status signal CODE_FULL when the value of the second impedance calibration code PDCODE<0:N> becomes its maximum or minimum value, the offset correction operation for buffer unit 201-0 is completed. When either the first code status signal BB_HOLD or the second code status signal CODE_FULL is high, the calibration completion detection circuit 105 can generate a high-level change timing signal OCC_CLK.

[0082] As the timing signal OCC_CLK goes high, the first counter 120 increments the value of the first impedance calibration code PUCODE<0:N>. As the value of the first impedance calibration code PUCODE<0:N> increases, the multiplexer 104 outputs the write data WDATA from the write data WDATA<0:N>. <1> The count control signal CNT_UPDN initiates the offset correction operation for the next-level buffer unit 201-1. The offset correction operation for buffer unit 201-1 is completed when either the first code status signal BB_HOLD or the second code status signal CODE_FULL goes high.

[0083] By incrementing the value of the first impedance calibration code PUCODE<0:N> each time the timing signal OCC_CLK is generated at a high level, offset correction operations can be sequentially performed for the remaining buffer units 201-2 to 201-N. When the offset correction operation for the last buffer unit 201-N is completed, the value of the first impedance calibration code PUCODE<0:N> is at its maximum value, and one of the first code status signal BB_HOLD and the second code status signal CODE_FULL is at a high level. Therefore, the controller 101 can complete the offset correction operation for all buffer units 201-0 to 201-N by generating the offset correction enable signal OCC_EN at a low level.

[0084] While various implementations have been described above, those skilled in the art will understand that the described implementations are merely examples. Therefore, the data input buffers described herein and the semiconductor devices including such data input buffers should not be limited based on the described implementations.

[0085] Cross-references to related applications

[0086] This application claims priority to Korean Application No. 10-2021-0050574, filed with the Korean Intellectual Property Office on April 19, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A data input buffer, the data input buffer comprising: Multiple buffer units, wherein the multiple buffer units receive a first impedance calibration code and a second impedance calibration code, The offset detected when the output of each of the plurality of buffer units is short-circuited at its first and second input terminals is used as the written data. Among them, the buffer unit corresponding to the current value of the first impedance calibration code among the plurality of buffer units corrects the offset according to the second impedance calibration code.

2. The data input buffer according to claim 1, wherein, Each of the plurality of buffer units includes: A first receiver outputs a signal by amplifying the voltage level difference between the first input terminal and the second input terminal, and corrects the offset according to an offset correction code. A connector that short-circuits the first and second input terminals based on an offset correction enable signal; and The decoder latches the second impedance calibration code based on the first impedance calibration code and generates the offset correction code by decoding the latched code.

3. The data input buffer according to claim 2, wherein, The first receiver includes a first amplifier circuit and a second amplifier circuit, and At least one of the first amplifier circuit and the second amplifier circuit corrects the offset according to the offset correction code.

4. The data input buffer according to claim 2, wherein, Each of the plurality of buffer units further includes: A second receiver, which operates at a relatively lower speed compared to the first receiver; and A multiplexer generates an output signal by selecting one of the outputs of the first receiver and the second receiver according to a multiplexing control signal.

5. A semiconductor device, the semiconductor device comprising: An impedance calibration circuit receives write data, an impedance calibration command, and mode register setting information as inputs, and performs an offset correction operation to calibrate the value of the impedance calibration code according to the write data in response to the impedance calibration command and the mode register setting information. as well as A data input buffer detects offset, outputs the detected offset information as the written data, and corrects the offset according to the impedance calibration code.

6. The semiconductor device according to claim 5, wherein, The impedance calibration circuit, in response to the impedance calibration command, performs an impedance calibration operation to calibrate the value of the impedance calibration code based on the impedance of an external resistor.

7. The semiconductor device according to claim 6, further comprising: A data output buffer drives the read data with an output impedance calibrated according to the impedance calibration code, and outputs the driven read data through a data input / output unit.

8. The semiconductor device according to claim 6, wherein, The impedance calibration circuit includes: A controller that generates an offset correction enable signal in response to the impedance calibration command, the mode register setting information, the first impedance calibration code, the first code status signal, and the second code status signal, wherein the first impedance calibration code and the second impedance calibration code are included in the impedance calibration code. A first counter, which calibrates the value of the first impedance calibration code according to a change in the timing signal; A second counter calibrates the value of the second impedance calibration code according to a counting control signal; A multiplexer that outputs the counting control signal by selecting one of the written data according to the first impedance calibration code; and The calibration completion detection circuit generates a first code status signal, a second code status signal, and a change timing signal based on the count control signal and the second impedance calibration code.

9. The semiconductor device according to claim 8, wherein, The controller includes: A trigger that, based on an input to the clock terminal, outputs the offset correction enable signal through the output terminal, and initializes the output terminal based on the offset correction complete signal; The first logic gate and the second logic gate generate a combination result by logically combining the impedance calibration command and the mode register setting information, and input the combination result to the clock terminal of the flip-flop; The third logic gate outputs the result of logically combining the bits of the second impedance calibration code; A fourth logic gate, the output of which is the result of logically combining the first code state signal and the second code state signal; and The fifth and sixth logic gates, whose outputs logically combine the outputs of the third and fourth logic gates, serve as the offset correction completion signal.

10. The semiconductor device according to claim 8, wherein, The calibration completion detection circuit includes: A shift register that outputs a signal with multiple bits by shifting the counting control signal according to a clock signal; A first decoder generates the first code state signal by decoding the output signal of the shift register; The second decoder outputs the result by decoding the second impedance calibration code; An inverter array that outputs by inverting the second impedance calibration code; A third decoder outputs an output by decoding the output of the inverter array; A first logic gate, the output of which logically combines the output of the second decoder and the output of the third decoder as the second code state signal; and The second logic gate outputs the result of logically combining the first code state signal and the second code state signal, which serves as the change timing signal.

11. The semiconductor device according to claim 9, wherein, When the mode register setting information is set to the first logic level, the controller controls the impedance calibration circuit according to the impedance calibration command, so that the impedance calibration circuit performs the offset correction operation and the impedance calibration operation in sequence.

12. The semiconductor device according to claim 9, wherein, When the mode register setting information is set to the second logic level, the controller controls the impedance calibration circuit according to the impedance calibration command, so that the impedance calibration circuit only performs the impedance calibration operation.

13. The semiconductor device according to claim 5, wherein, The data input buffer includes: Multiple buffer units, wherein the multiple buffer units receive the impedance calibration code, the impedance calibration code including a first impedance calibration code and a second impedance calibration code, The offset detected when the output of each of the plurality of buffer units is short-circuited at its first and second input terminals is used as the written data. Among them, the buffer unit corresponding to the current value of the first impedance calibration code among the plurality of buffer units corrects the offset according to the second impedance calibration code.

14. The semiconductor device according to claim 13, wherein, Each of the plurality of buffer units includes: A first receiver outputs a signal by amplifying the voltage level difference between the first input terminal and the second input terminal, and corrects the offset according to an offset correction code. A connector that short-circuits the first and second input terminals based on an offset correction enable signal; and The decoder latches the second impedance calibration code based on the first impedance calibration code and generates the offset correction code by decoding the latched code.

15. A semiconductor device, the semiconductor device comprising: A data input buffer includes a plurality of buffer units that receive a first impedance calibration code and a second impedance calibration code, wherein each of the plurality of buffer units outputs an offset detected when its first and second input terminals are short-circuited as write data, and wherein the buffer unit among the plurality of buffer units corresponding to the current value of the first impedance calibration code corrects the offset according to the second impedance calibration code. A data output buffer that drives the read data with an output impedance calibrated according to the first impedance calibration code and the second impedance calibration code, and outputs the driven read data through a data input / output unit; and An impedance calibration circuit, in response to an impedance calibration command, performs an impedance calibration operation based on an external resistor to calibrate the output impedance of the data output buffer by calibrating the value of at least one of the first impedance calibration code and the second impedance calibration code; and in response to mode register setting information and the impedance calibration command, performs an offset correction operation based on the written data to calibrate the value of at least one of the first impedance calibration code and the second impedance calibration code to correct the offset of the data input buffer.

16. The semiconductor device according to claim 15, wherein, When the mode register setting information is set to the first logic level, the impedance calibration circuit sequentially performs the offset correction operation and the impedance calibration operation according to the impedance calibration command; and when the mode register setting information is set to the second logic level, it only performs the impedance calibration operation according to the impedance calibration command.

17. The semiconductor device according to claim 15, wherein, Each of the plurality of buffer units includes: A first receiver outputs a signal by amplifying the voltage level difference between the first input terminal and the second input terminal, and corrects the offset according to an offset correction code. A connector that short-circuits the first and second input terminals based on an offset correction enable signal; and The decoder latches the second impedance calibration code based on the first impedance calibration code, and generates the offset correction code by decoding the latched code.

18. The semiconductor device according to claim 15, wherein, The impedance calibration circuit includes: A controller that generates an offset correction enable signal in response to the impedance calibration command, the mode register setting information, the first impedance calibration code, the first code status signal, and the second code status signal. A first counter, which calibrates the value of the first impedance calibration code according to a change in the timing signal; A second counter calibrates the value of the second impedance calibration code according to a counting control signal; A multiplexer that outputs the counting control signal by selecting one of the written data according to the first impedance calibration code; and The calibration completion detection circuit generates a first code status signal, a second code status signal, and a change timing signal based on the count control signal and the second impedance calibration code.

19. The semiconductor device according to claim 18, wherein, The controller includes: A trigger that, based on an input to the clock terminal, outputs the offset correction enable signal through the output terminal, and initializes the output terminal based on the offset correction complete signal; The first logic gate and the second logic gate generate a combination result by logically combining the impedance calibration command and the mode register setting information, and input the combination result to the clock terminal of the flip-flop; The third logic gate outputs the result of logically combining the bits of the second impedance calibration code; A fourth logic gate, the output of which is the result of logically combining the first code state signal and the second code state signal; and The fifth and sixth logic gates, whose outputs logically combine the outputs of the third and fourth logic gates, serve as the offset correction completion signal.

20. The semiconductor device according to claim 18, wherein, The calibration completion detection circuit includes: A shift register that outputs a signal with multiple bits by shifting the counting control signal according to a clock signal; A first decoder generates the first code state signal by decoding the output signal of the shift register; The second decoder outputs the result by decoding the second impedance calibration code; An inverter array that outputs by inverting the second impedance calibration code; A third decoder outputs the output by decoding the output of the inverter array; A first logic gate, the output of which logically combines the output of the second decoder and the output of the third decoder as the second code state signal; and The second logic gate outputs the result of logically combining the first code state signal and the second code state signal, which serves as the change timing signal.

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