Shift register and control method thereof, gate driving circuit and display panel

Abstract

The application discloses a shift register and a control method thereof, a gate driving circuit and a display panel. The shift register comprises an input circuit, an intermediate circuit, an output circuit and a discharge circuit. The input circuit is configured to charge a pull-up node under the control of a first initial signal provided by a first initial signal terminal. The intermediate circuit is configured to adjust the potential of the pull-up node. The output terminal of the output circuit outputs a gate driving signal through a first clock signal provided by a first clock signal terminal under the control of the potential of the pull-up node. The discharge circuit is configured to discharge the output terminal of the output circuit under the control of a second clock signal provided by a second clock signal terminal and a third clock signal provided by a third clock signal terminal after the output of the gate driving signal is completed. The discharge circuit is configured to discharge after the output of the gate scanning signal by the output circuit is completed, so that the discharge capacity of the shift register for the gate scanning signal is enhanced, thereby ensuring the stability and normal driving of the gate driving unit.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a shift register and its control method, a gate driving circuit and a display panel. Background Technology

[0002] In related technologies, the RC load of a row of pixels varies for display panels of different sizes. When the RC load of a row of pixels is large, a single-sided driving scheme is used. To achieve a pixel charging rate of over 90%, the W value (channel width) of the output circuit transistor in the shift register is generally set to a large value (1200µm) in simulation. Generally, the output circuit transistor has a better gate RC charging capability than a discharging capability. To obtain a smaller output gate scan signal TF value (rise time), the W value of the output circuit transistor is generally increased (1500µm). Therefore, the parasitic capacitance Cgs of the output circuit transistor increases, resulting in an increase in the Ripple voltage of the pull-up node. To reduce the Ripple voltage of the pull-up node, a larger bootstrap capacitor C is generally used. However, due to layout space limitations, the bootstrap capacitor cannot reach a reasonable range. At the same time, the increase in the parasitic capacitance Cgs of the output circuit transistor increases the power consumption of the clock (CK) signal, which is detrimental to the development of low-power products. Summary of the Invention

[0003] The embodiments of this application provide a shift register and its control method, a gate driving circuit, and a display panel.

[0004] The shift register of this application includes an input circuit, an intermediate circuit, an output circuit, and a discharge circuit. The input circuit is connected to a pull-up node and a first initial signal terminal, and is used to charge the pull-up node under the control of a first initial signal provided by the first initial signal terminal. The intermediate circuit is connected to the pull-up node and is used to adjust the potential of the pull-up node. The output circuit is connected to the pull-up node and a first clock signal terminal. The output terminal of the output circuit outputs a gate drive signal under the control of the potential of the pull-up node and a first clock signal provided by the first clock signal terminal. The discharge circuit is connected to the output terminal of the output circuit, a second clock signal terminal, and a third clock signal terminal. After the gate drive signal is output, the output terminal of the output circuit is discharged under the control of a second clock signal provided by the second clock signal terminal and a third clock signal provided by the third clock signal terminal.

[0005] In some embodiments, the discharge circuit includes a first transistor and a second transistor, the gate of the first transistor is connected to the second clock signal terminal, the first terminal of the first transistor is connected to the output terminal of the output circuit, the second terminal of the first transistor is connected to the first terminal of the second transistor, the gate of the second transistor is connected to the third clock signal terminal, and the second terminal of the second transistor is connected to the first low-voltage power supply terminal.

[0006] In some implementations, the second clock signal is delayed by one unit time relative to the first clock signal, and the third clock signal is delayed by three units time relative to the first clock signal.

[0007] In some implementations, the input circuit includes a third transistor whose gate and first terminal are connected to the first initial signal terminal, and whose second terminal is connected to the pull-up node.

[0008] In some embodiments, the intermediate circuit includes a first pull-down control module, a second pull-down control module, a first pull-down module, a second pull-down module, and a third pull-down module; the first pull-down control module is connected to a first power supply voltage input terminal and a first pull-down node; the second pull-down control module is connected to a second power supply voltage input terminal and a second pull-down node; the control terminal of the first pull-down module is connected to the first pull-down node and the second pull-down node, a first terminal of the first pull-down module is connected to the pull-up node, and a second terminal of the first pull-down module is connected to a second low-voltage power supply terminal; the control terminal of the second pull-down module is connected to the pull-up node and the first initial signal terminal, a second terminal of the second pull-down module is connected to the first pull-down node, and a third terminal of the second pull-down module is connected to the second low-voltage power supply terminal; the control terminal of the third pull-down module is connected to the pull-up node and the first initial signal terminal, a second terminal of the third pull-down module is connected to the second pull-down node, and a third terminal of the third pull-down module is connected to the second low-voltage power supply terminal.

[0009] In some embodiments, the first pull-down control module includes a fourth transistor, the gate and first terminal of which are connected to the first power supply voltage input terminal, and the second terminal of which is connected to the first pull-down node; the second pull-down control module includes a fifth transistor, the gate and first terminal of which are connected to the second power supply voltage input terminal, and the second terminal of which is connected to the second pull-down node; the first pull-down module includes a sixth transistor and a seventh transistor, the gate of which is connected to the first pull-down node, the first terminal of which is connected to the pull-up node, and the second terminal of which is connected to the second low-voltage power supply terminal; the gate of which is connected to the second pull-down node, the first terminal of which is connected to the pull-up node, and the second terminal of which is connected to the second low-voltage power supply terminal; the second pull-down module... The third pull-down module includes an eighth transistor and a ninth transistor. The gate of the eighth transistor is connected to the pull-up node, the first terminal of the eighth transistor is connected to the first pull-down node, and the second terminal of the eighth transistor is connected to the second low-voltage power supply terminal. The gate of the ninth transistor is connected to the first initial signal terminal, the first terminal of the ninth transistor is connected to the first pull-down node, and the second terminal of the ninth transistor is connected to the second low-voltage power supply terminal. The third pull-down module includes a tenth transistor and an eleventh transistor. The gate of the tenth transistor is connected to the pull-up node, the first terminal of the tenth transistor is connected to the first pull-down node, and the second terminal of the tenth transistor is connected to the second low-voltage power supply terminal. The gate of the eleventh transistor is connected to the first initial signal terminal, the first terminal of the eleventh transistor is connected to the second pull-down node, and the second terminal of the eleventh transistor is connected to the second low-voltage power supply terminal.

[0010] In some embodiments, the intermediate circuit includes a first noise reduction module, the control terminal of the first noise reduction module is connected to the first pull-down node and the second pull-down node, the first terminal of the first noise reduction module is connected to the output terminal of the output circuit, and the second terminal of the first noise reduction module is connected to the first low-voltage power supply terminal.

[0011] In some embodiments, the first noise reduction module includes a twelfth transistor and a thirteenth transistor. The gate of the twelfth transistor is connected to the first pull-down node, the first terminal of the twelfth transistor is connected to the output terminal of the output circuit, and the second terminal of the twelfth transistor is connected to the first low-voltage power supply terminal. The gate of the thirteenth transistor is connected to the second pull-down node, the first terminal of the thirteenth transistor is connected to the output terminal of the output circuit, and the second terminal of the thirteenth transistor is connected to the first low-voltage power supply terminal.

[0012] In some implementations, the intermediate circuit includes a cascaded output module connected to the pull-up node, and the output of the cascaded output module is used to output a cascaded signal or a second initial signal.

[0013] In some embodiments, the cascaded output module includes a fourteenth transistor, the gate of which is connected to the pull-up node, the first terminal of which is connected to the first clock signal terminal, and the second terminal of which is connected to the output terminal of the cascaded output module.

[0014] In some embodiments, the intermediate circuit includes a second noise reduction module connected to the output terminal of the cascaded output module, and the second noise reduction module is used to reduce noise in the cascaded output module.

[0015] In some embodiments, the second noise reduction module includes a fifteenth transistor and a sixteenth transistor. The gate of the fifteenth transistor is connected to the first pull-down node, the first terminal of the fifteenth transistor is connected to the output terminal of the cascaded output module, and the second terminal of the fifteenth transistor is connected to the second low-voltage power supply terminal. The gate of the sixteenth transistor is connected to the second pull-down node, the first terminal of the sixteenth transistor is connected to the output terminal of the cascaded output module, and the second terminal of the sixteenth transistor is connected to the second low-voltage power supply terminal.

[0016] In some implementations, the intermediate circuit includes a reset module connected to the pull-up node, the reset module being used to reset the potential of the pull-up node.

[0017] In some embodiments, the reset module includes a seventeenth transistor, the first terminal of which is connected to the pull-up node, the gate of which is connected to the reset signal terminal, and the second terminal of which is connected to a second low-voltage power supply terminal.

[0018] In some implementations, the intermediate circuit includes a pre-frame discharge module, the control terminal of which is connected to a second initial signal terminal, the first terminal of which is connected to the pull-up node, and the second terminal of which is connected to a second low-voltage power supply terminal.

[0019] In some implementations, the eighteenth transistor of the pre-frame discharge module has its gate connected to the second initial signal terminal, its first terminal connected to the pull-up node, and its second terminal connected to the second low-voltage power supply terminal.

[0020] In some embodiments, the output circuit includes a nineteenth transistor, a twentieth transistor, and a storage capacitor. The gate of the nineteenth transistor is connected to the pull-up node, the first terminal of the nineteenth transistor is connected to a third clock signal terminal, and the second terminal of the nineteenth transistor is connected to the output terminal of the output circuit. The gate of the twentieth transistor is connected to a second initial signal terminal, the first terminal of the twentieth transistor is connected to the output terminal of the output circuit, and the second terminal of the twentieth transistor is connected to a first low-voltage power supply terminal. The first terminal of the storage capacitor is connected to the pull-up node, and the second terminal of the storage capacitor is connected to the output terminal of the output circuit.

[0021] The gate driving circuit of this application includes M cascaded shift registers and N clock signal lines. The shift registers are the shift registers described in any of the above embodiments. The first clock signal terminals of each of the N adjacent shift registers are respectively connected to the N clock signal lines. Wherein, N is an even number greater than or equal to 4; M is an integer greater than or equal to N. Wherein, the second clock signal terminal of the i-th shift register in the N adjacent shift registers is connected to the clock signal line corresponding to the first clock signal terminal of the (i+1)-th shift register; the third clock signal terminal of the i-th shift register in the N adjacent shift registers is connected to the clock signal line corresponding to the first clock signal terminal of the (i+3)-th shift register, where i is an integer and 0 < i ≤ N-3.

[0022] The display panel of this application embodiment includes the gate driving circuit of this application embodiment.

[0023] The control method of this application embodiment is used to control the shift register described in any of the above embodiments. The control method includes: in the charging phase, providing a first initial signal to the first initial signal terminal to increase the potential of the pull-up node; in the pull-up phase, providing a first clock signal to the first clock signal terminal to cause the output terminal of the output circuit to output the gate drive signal; in the discharging phase, providing a second clock signal to the second clock signal terminal and a third clock signal to the third clock signal terminal to discharge the output terminal of the output circuit; and in the holding phase, periodically providing a second clock signal to the second clock signal terminal and a third clock signal to the third clock signal terminal to maintain the potential of the output terminal of the output circuit.

[0024] In the shift register, gate driving circuit, display panel, and control method of this application, the shift register discharges after the gate scanning signal is output from the output circuit by setting a discharge circuit, thereby enhancing the discharge capability of the shift register to the gate scanning signal, increasing the effective data writing charging time, ensuring a high pixel charging rate for the product, reducing noise at the pull-up node and output terminal, and thus ensuring the stability and normal driving of the gate driving unit.

[0025] Additional aspects and advantages of embodiments of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of embodiments of this application. Attached Figure Description

[0026] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, wherein:

[0027] Figure 1 This is a schematic diagram of the circuit structure of the shift register according to an embodiment of this application.

[0028] Figure 2 This is a schematic diagram of the gate driving circuit according to an embodiment of this application.

[0029] Figure 3 This is a control timing diagram of the gate drive circuit according to an embodiment of this application.

[0030] Figure 4 This is a flowchart illustrating the control method of an embodiment of this application. Detailed Implementation

[0031] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0032] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0033] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0034] Please see Figure 1 This application provides a shift register 10 including an input circuit 11, an intermediate circuit 12, an output circuit 13, and a discharge circuit 14. The input circuit 11 is connected to a pull-up node UP and a first initial signal terminal STV1, and is used to charge the pull-up node UP under the control of a first initial signal provided by the first initial signal terminal STV1. The intermediate circuit 12 is connected to the pull-up node UP and is used to adjust the potential of the pull-up node UP. The output circuit 13 is connected to the pull-up node UP and a first clock signal terminal CLK1, and its output terminal Gn outputs a gate drive signal through a first clock signal provided by the first clock signal terminal CLK1 under the control of the potential of the pull-up node UP. The discharge circuit 14 is connected to the output terminal Gn of the output circuit 13, a second clock signal terminal CLK2, and a third clock signal terminal CLK3, and is used to discharge the output terminal Gn of the output circuit 13 under the control of a second clock signal provided by the second clock signal terminal CLK2 and a third clock signal provided by the third clock signal terminal CLK3 after the gate drive signal is output.

[0035] In this embodiment, the shift register 10 is configured to discharge after the output circuit 13 outputs the gate scan signal by setting the discharge circuit 14. This enhances the discharge capability of the shift register 10 to the gate scan signal, thereby increasing the effective data writing charging time, ensuring a high pixel charging rate for the product, reducing the noise of the pull-up node UP and the output end, and thus ensuring the stability and normal driving of the gate drive circuit 100.

[0036] In some embodiments, the discharge circuit 14 includes a first transistor M1 and a second transistor M2. The gate of the first transistor M1 is connected to the second clock signal terminal CLK2, the first terminal of the first transistor M1 is connected to the output terminal Gn of the output circuit 13, the second terminal of the first transistor M1 is connected to the first terminal of the second transistor M2, the gate of the second transistor M2 is connected to the third clock signal terminal CLK3, and the second terminal of the second transistor M2 is connected to the first low-voltage power supply terminal VGL.

[0037] Thus, the discharge circuit 14 connects the output terminal Gn of the output circuit 13 and the first low-voltage power supply terminal VGL in series through the first transistor M1 and the second transistor M2. After the output circuit 13 outputs the gate scan signal, the first transistor M1 can be turned on under the action of the second clock signal provided by the second clock signal terminal CLK2 and the second transistor M2 can be turned on under the action of the third clock signal provided by the third clock signal terminal CLK3, thereby releasing the voltage of the output terminal Gn of the output circuit 13 to the first low-voltage power supply terminal VGL.

[0038] It should be noted that the transistors described in this application are N-channel transistors, where the first terminal can be the source and the second terminal can be the drain. However, in practical applications, the types of the first transistor M1 and the second transistor M2 are not limited to this; for example, they can also be P-type transistors. Furthermore, all transistors described herein can be P-type transistors, or some transistors can be P-type transistors, but this is not a limitation.

[0039] In some implementations, the input circuit 11 includes a third transistor M3, the gate and first terminal of the third transistor M3 are connected to the first initial signal terminal STV1, and the second terminal of the third transistor M3 is connected to the pull-up node UP.

[0040] Thus, the third transistor M3 in the input circuit 11 is used to receive the first initial signal and charge the pull-up node UP under the control of the first initial signal.

[0041] In some implementations, the intermediate circuit 12 includes a first pull-down control module 120, a second pull-down control module 121, a first pull-down module 122, a second pull-down module 123, and a third pull-down module 124.

[0042] The first pull-down control module 120 is connected to the first power supply voltage input terminal VDDA and the first pull-down node PD1. The first pull-down control module 120 can be used to control the potential of the first pull-down node PD1.

[0043] The second pull-down control module 121 is connected to the second power supply voltage input terminal VDDB and the second pull-down node PD2. The second pull-down control module 121 can be used to control the potential of the second pull-down node PD2.

[0044] The control terminal of the first pull-down module 122 is connected to the first pull-down node PD1 and the second pull-down node PD2. The first terminal of the first pull-down module 122 is connected to the pull-up node UP, and the second terminal of the first pull-down module 122 is connected to the second low-voltage power supply terminal LVGL. The first pull-down module 122 pulls the potential of the pull-up node UP low according to the potential of the first pull-down node PD1 and the second pull-down node PD2.

[0045] The control terminal of the second pull-down module 123 is connected to the pull-up node UP and the first initial signal terminal STV1. The second terminal of the second pull-down module 123 is connected to the first pull-down node PD1, and the third terminal of the second pull-down module 123 is connected to the second low-voltage power supply terminal LVGL. The second pull-down module 123 pulls the potential of the first pull-down node PD1 low according to the potential of the pull-up node UP and the first initial signal terminal STV1.

[0046] The control terminal of the third pull-down module 124 is connected to the pull-up node UP and the first initial signal terminal STV1. The second terminal of the third pull-down module 124 is connected to the second pull-down node PD2, and the third terminal of the third pull-down module 124 is connected to the second low-voltage power supply terminal LVGL. The third pull-down module 124 pulls the potential of the second pull-down node PD2 low according to the potential of the pull-up node UP and the first initial signal terminal STV1.

[0047] In some embodiments, the first pull-down control module 120 includes a fourth transistor M4. The gate and first terminal of the fourth transistor M4 are connected to the first power supply voltage input terminal VDDA, and the second terminal of the fourth transistor M4 is connected to the first pull-down node PD1. The fourth transistor M4 is turned on under the control of the first power supply voltage input terminal VDDA to charge the first pull-down node PD1, thereby controlling the potential of the first pull-down node PD1.

[0048] The second pull-down control module 121 includes a fifth transistor M5. The gate and first terminal of the fifth transistor M5 are connected to the second power supply voltage input terminal VDDB, and the second terminal of the fifth transistor M5 is connected to the second pull-down node PD2. Accordingly, the fifth transistor M5 is turned on under the control of the second power supply voltage input terminal VDDB to charge the second pull-down node PD2, thereby controlling the potential of the second pull-down node PD2.

[0049] The first pull-down module 122 includes a sixth transistor M6 and a seventh transistor M7. The gate of the sixth transistor M6 is connected to the first pull-down node PD1, the first terminal of the sixth transistor M6 is connected to the pull-up node UP, and the second terminal of the sixth transistor M6 is connected to the second low-voltage power supply terminal LVGL. The gate of the seventh transistor M7 is connected to the second pull-down node PD2, the first terminal of the seventh transistor M7 is connected to the pull-up node UP, and the second terminal of the seventh transistor M7 is connected to the second low-voltage power supply terminal LVGL. When the first pull-down node PD1 controls the sixth transistor M6 to be turned on, the sixth transistor M6 pulls the potential of the pull-up node UP low. When the second pull-down node PD2 controls the seventh transistor M7 to be turned on, the seventh transistor M7 pulls the potential of the pull-up node UP low.

[0050] The second pull-down module 123 includes an eighth transistor M8 and a ninth transistor M9. The gate of the eighth transistor M8 is connected to the pull-up node UP, the first terminal of the eighth transistor M8 is connected to the first pull-down node PD1, and the second terminal of the eighth transistor M8 is connected to the second low-voltage power supply terminal LVGL. The gate of the ninth transistor M9 is connected to the first initial signal terminal STV1, the first terminal of the ninth transistor M9 is connected to the first pull-down node PD1, and the second terminal of the ninth transistor M9 is connected to the second low-voltage power supply terminal LVGL. When the potential of the pull-up node UP controls the eighth transistor M8 to be turned on, the eighth transistor M8 pulls the potential of the first pull-down node PD1 low; or when the potential of the first initial signal terminal STV1 controls the ninth transistor M9 to be turned on, the ninth transistor M9 pulls the potential of the first pull-down node PD1 low.

[0051] The third pull-down module 124 includes a tenth transistor M10 and an eleventh transistor M11. The gate of the tenth transistor M10 is connected to the pull-up node UP, the first terminal of the tenth transistor M10 is connected to the first pull-down node PD1, and the second terminal of the tenth transistor M10 is connected to the second low-voltage power supply terminal LVGL. The gate of the eleventh transistor M11 is connected to the first initial signal terminal STV1, the first terminal of the eleventh transistor M11 is connected to the second pull-down node PD2, and the second terminal of the eleventh transistor M11 is connected to the second low-voltage power supply terminal LVGL. When the potential of the pull-up node UP controls the tenth transistor M10 to be turned on, the tenth transistor M10 pulls the potential of the second pull-down node PD2 low; or when the potential of the first initial signal terminal STV1 controls the eleventh transistor M11 to be turned on, the eleventh transistor M11 pulls the potential of the second pull-down node PD2 low.

[0052] In this way, the potential control of the pull-up node UP, the first pull-down node PD1, and the second pull-down node PD2 is achieved, ensuring that the shift register 10 works normally.

[0053] In some embodiments, the intermediate circuit 12 includes a first noise reduction module 125. The control terminal of the first noise reduction module 125 is connected to the first pull-down node PD1 and the second pull-down node PD2. The first terminal of the first noise reduction module 125 is connected to the output terminal Gn of the output circuit 13, and the second terminal of the first noise reduction module 125 is connected to the first low-voltage power supply terminal VGL.

[0054] Thus, the first noise reduction module 125 can reduce noise in the output circuit 13 according to the potential of the first pull-down node PD1 and the second pull-down node PD2.

[0055] In some embodiments, the first noise reduction module 125 includes a twelfth transistor M12 and a thirteenth transistor M13. The gate of the twelfth transistor M12 is connected to the first pull-down node PD1, the first terminal of the twelfth transistor M12 is connected to the output terminal Gn of the output circuit 13, and the second terminal of the twelfth transistor M12 is connected to the first low-voltage power supply terminal VGL. The gate of the thirteenth transistor M13 is connected to the second pull-down node PD2, the first terminal of the thirteenth transistor M13 is connected to the output terminal Gn of the output circuit 13, and the second terminal of the thirteenth transistor M13 is connected to the first low-voltage power supply terminal VGL.

[0056] Thus, when the first pull-down node PD1 controls the twelfth transistor M12 to turn on, the twelfth transistor M12 pulls the output terminal Gn potential of the output circuit 13 low; or when the second pull-down node PD2 controls the thirteenth transistor M13 to turn on, the thirteenth transistor M13 pulls the output terminal Gn potential of the output circuit 13 low.

[0057] In some implementations, the intermediate circuit 12 includes a cascaded output module 126 connected to the pull-up node UP, and the output terminal Out_C of the cascaded output module 126 is used to output a cascaded signal or a second initial signal.

[0058] When the output terminal Out_C of the cascade output module 126 is connected to the first initial signal terminal STV1 of other shift registers 10, the output terminal Out_C of the cascade output module 126 is used to output a cascaded signal as the second initial signal of the other shift registers 10. When the output terminal Out_C of the cascade output module 126 is connected to the second initial signal terminal STV2 of other shift registers 10, the output terminal Out_C of the cascade output module 126 is used to output a second initial signal as the second initial signal of the other shift registers 10.

[0059] In some embodiments, the cascaded output module 126 includes a fourteenth transistor M14, the gate of which is connected to the pull-up node UP, the first terminal of which is connected to the first clock signal terminal CLK1, and the second terminal of which is connected to the output terminal Out_C of the cascaded output module 126.

[0060] Thus, when the pull-up node UP controls the fourteenth transistor M14 to turn on, the fourteenth transistor M14 outputs the first clock signal as a cascaded signal or a second initial signal through the output terminal Out_C of the cascaded output module 126.

[0061] In some embodiments, the intermediate circuit 12 includes a second noise reduction module 127. The control terminal of the second noise reduction module 127 is connected to the first pull-down node PD1 and the second pull-down node PD2. The second noise reduction module 127 is connected to the output terminal Out_C of the cascaded output module 126. The second noise reduction module 127 is used to reduce noise in the cascaded output module 126.

[0062] Thus, the second noise reduction module 127 can reduce noise in the cascaded output module 126 based on the potentials of the first pull-down node PD1 and the second pull-down node PD2.

[0063] In some embodiments, the second noise reduction module 127 includes a fifteenth transistor M15 and a sixteenth transistor M16. The gate of the fifteenth transistor M15 is connected to the first pull-down node PD1, the first terminal of the fifteenth transistor M15 is connected to the output terminal Out_C of the cascaded output module 126, and the second terminal of the fifteenth transistor M15 is connected to the second low-voltage power supply terminal LVGL. The gate of the sixteenth transistor M16 is connected to the second pull-down node PD2, the first terminal of the sixteenth transistor M16 is connected to the output terminal Out_C of the cascaded output module 126, and the second terminal of the sixteenth transistor M16 is connected to the second low-voltage power supply terminal LVGL.

[0064] Thus, when the first pull-down node PD1 controls the fifteenth transistor M15 to turn on, the fifteenth transistor M15 pulls the output terminal Out_C potential of the cascaded output module 126 low; or when the second pull-down node PD2 controls the sixteenth transistor M16 to turn on, the sixteenth transistor M16 pulls the output terminal Out_C potential of the cascaded output module 126 low, thereby reducing noise in the cascaded output module 126.

[0065] In some implementations, the intermediate circuit 12 includes a reset module 128 connected to the pull-up node UP, which is used to reset the potential of the pull-up node UP.

[0066] In some embodiments, the reset module 128 includes a seventeenth transistor M17, the first terminal of the seventeenth transistor M17 is connected to the pull-up node UP, the gate of the seventeenth transistor M17 is connected to the reset signal terminal TRST, and the second terminal of the seventeenth transistor M17 is connected to the second low-voltage power supply terminal LVGL.

[0067] Thus, when the reset signal terminal TRST provides a reset signal to control the seventeenth transistor M17 to turn on, the seventeenth transistor M17 pulls the potential of the pull-up node UP low, thereby resetting the potential of the pull-up node UP.

[0068] In some implementations, the intermediate circuit 12 includes a pre-frame discharge module 129, the control terminal of which is connected to the second initial signal terminal STV2, the first terminal of which is connected to the pull-up node UP, and the second terminal of which is connected to the second low-voltage power supply terminal LVGL.

[0069] Thus, the pre-frame discharge module 129 can discharge the flash node at the beginning of each frame according to the control of the second initial signal provided by the second initial signal terminal STV2.

[0070] In some implementations, the eighteenth transistor M18 of the pre-frame discharge module 129 has its gate connected to the second initial signal terminal STV2, its first terminal connected to the pull-up node UP, and its second terminal connected to the second low-voltage power supply terminal LVGL.

[0071] Thus, when the second initial signal terminal STV2 controls the eighteenth transistor M18 to turn on, the eighteenth transistor M18 pulls the potential of the pull-up node UP low.

[0072] In some embodiments, the output circuit 13 includes a nineteenth transistor M19, a twentieth transistor M20, and a storage capacitor C. The gate of the nineteenth transistor M19 is connected to the pull-up node UP, its first terminal is connected to the third clock signal terminal CLK3, and its second terminal is connected to the output terminal Gn of the output circuit 13. The gate of the twentieth transistor M20 is connected to the second initial signal terminal STV2, its first terminal is connected to the output terminal Gn of the output circuit 13, and its second terminal is connected to the first low-voltage power supply terminal VGL. The first terminal of the storage capacitor C is connected to the pull-up node UP, and its second terminal is connected to the output terminal Gn of the output circuit 13.

[0073] Thus, when the pull-up node UP controls the nineteenth transistor M19 to turn on, the nineteenth transistor M19 outputs the first clock signal as a gate scan signal. When the first initialization signal terminal controls the twentieth transistor M20 to turn on, the twentieth transistor M20 pulls the output terminal Gn potential of the output circuit 13 low.

[0074] Please see Figure 2 and Figure 3The gate drive circuit 100 of this application includes M cascaded shift registers and N clock signal lines. The shift registers are shift registers 10 as described in any of the above embodiments. The first clock signal terminal CLK1 of each of the N adjacent shift registers 10 is connected to the N clock signal lines. N is an even number greater than or equal to 4, and M is an integer greater than or equal to N. The second clock signal terminal CLK2 of the i-th shift register 10 among the N adjacent shift registers 10 is connected to the clock signal line corresponding to the first clock signal terminal CLK1 of the (i+1)-th shift register 10. The third clock signal terminal CLK3 of the i-th shift register 10 among the N adjacent shift registers 10 is connected to the clock signal line corresponding to the first clock signal terminal CLK1 of the (i+3)-th shift register 10. i is an integer and 0 < i ≤ N-3.

[0075] Thus, in the gate drive circuit 100 of this application embodiment, the shift register 10 discharges after the output circuit 13 outputs the gate scan signal by setting the discharge circuit 14, thereby enhancing the discharge capability of the shift register 10 to the gate scan signal, thereby increasing the effective data writing charging time, ensuring a high pixel charging rate of the product, reducing the noise of the pull-up node UP and the output end, and thus ensuring the stability and normal driving of the gate drive circuit 100.

[0076] It should be noted that the valid signals of the N clock signal lines are transmitted to the corresponding shift register 10 with a delay of one unit time H.

[0077] This embodiment is described using N=8 as an example. The first clock signal terminal CLK1 of each of the eight adjacent shift registers 10 in the gate drive circuit 100 is connected to eight clock signal lines (clk1-clk8). In this case, the first clock signal line clk1 is connected to the first clock signal terminal CLK1 of the first-stage shift register 10, the second clock signal line clk2 is connected to the second clock signal terminal CLK2 of the first-stage shift register 10, and the fourth clock signal line clk4 is connected to the third clock signal terminal CLK3 of the first-stage shift register 10. Similarly, the second clock signal line clk2 is connected to the first clock signal terminal CLK1 of the second-stage shift register 10, the third clock signal line (not shown) is connected to the second clock signal terminal CLK2 of the second-stage shift register 10, the fifth clock signal line clk5 is connected to the third clock signal terminal CLK3 of the second-stage shift register 10, and so on.

[0078] In other words, in the embodiments of this application, the second clock signal is delayed by one unit time H relative to the first clock signal, and the third clock signal is delayed by three unit time H relative to the first clock signal.

[0079] At this time, the period of each clock signal can be 8 units of time H, and the effective signal of the clock signal is 3 units of time H. That is to say, the duty cycle of each clock signal is 37.5%.

[0080] In some implementations, the first initial signal terminal STV1 of the first four shift registers 10 of the gate drive circuit 100 is connected to the initial signal line stv, and the first initial signal terminal STV1 of the nth shift register 10 after the fourth shift register 10 is connected to the output terminal Out_C of the cascaded output module 126 in the (n-4)th shift register 10.

[0081] In some implementations, before the last four shift registers 10, the second initial signal terminal STV2 of the nth shift register 10 is connected to the output terminal Out_C of the cascaded output module 126 in the (n+4)th shift register 10, and the last four shift registers 10 of the gate drive circuit 100 are connected to the reset signal line (not shown in the figure).

[0082] The display panel (not shown) of this application embodiment includes the gate driving circuit 100 of this application embodiment.

[0083] Thus, in the display panel of this application embodiment, the shift register 10 discharges after the output circuit 13 outputs the gate scan signal by setting the discharge circuit 14, thereby enhancing the discharge capability of the shift register 10 to the gate scan signal, thereby increasing the effective data writing charging time, ensuring a high pixel charging rate of the product, reducing the noise of the pull-up node UP and the output end, thereby ensuring the stability and normal driving of the gate drive circuit 100.

[0084] Please see Figure 4 The control method of this application embodiment is used to control the shift register 10 of any of the above embodiments, and the control method includes:

[0085] 01. During the charging phase, a first initial signal is provided to the first initial signal terminal STV1 to increase the potential of the pull-up node UP.

[0086] 03. During the pull-up phase, a first clock signal is provided to the first clock signal terminal CLK1 so that the output terminal Gn of the output circuit 13 outputs a gate drive signal.

[0087] 05. During the discharge phase, a second clock signal is provided to the second clock signal terminal CLK2 and a third clock signal is provided to the third clock signal terminal CLK3 to discharge the output terminal Gn of the output circuit 13.

[0088] 07. During the holding phase, a second clock signal is periodically provided to the second clock signal terminal CLK2 and a third clock signal is provided to the third clock signal terminal CLK3 to maintain the potential of the output terminal Gn of the output circuit 13.

[0089] The control method of this application controls the shift register 10 of this application embodiment. After the output circuit 13 of the shift register 10 outputs the gate scan signal, it discharges, thereby enhancing the discharge capability of the shift register 10 to the gate scan signal. This increases the effective data writing charging time, ensures a high pixel charging rate for the product, reduces the noise of the pull-up node UP and the output end, and thus ensures the stability and normal driving of the gate drive unit.

[0090] Please combine Figure 3 Specifically, during the charging phase t1, the third transistor M3 is turned on, and the first initial signal terminal STV1 charges the storage capacitor C, increasing the voltage of the pull-up node UP. Consequently, the eighth transistor M8 and the tenth transistor M10 are turned on, pulling the potentials of the first pull-down node PD1 and the second pull-down node PD2 low; the first clock signal terminal CLK1 is at a low level, so the output terminal Gn of the output circuit 13 has no output.

[0091] During the pull-up phase t2, the first clock signal terminal CLK1 is at a high level. Due to the bootstrap effect of the storage capacitor C, the voltage of the pull-up node UP continues to rise. The nineteenth transistor M19 remains on, and the output terminal Gn of the output circuit 13 outputs the gate scan signal. At this time, the first transistor M1 is on while the second transistor M2 is off, so there will be no leakage current in the output terminal Gn of the output circuit 13 when outputting the gate scan signal.

[0092] During the discharge phase t3, the first clock signal terminal CLK1 is at a low level. Due to the charge stored in the storage capacitor C, the pull-up node UP voltage remains high within a unit time H. At this time, the nineteenth transistor M19 is turned on, and the output terminal Gn of the output circuit 13 begins to discharge to the low level of the first clock signal terminal CLK1. Simultaneously, during this phase, the second clock signal terminal CLK2 and the third clock signal terminal CLK3 are at a high level, the first transistor M1 and the second transistor M2 are turned on, and the output terminal Gn of the output circuit 13 also begins to discharge to the first low-voltage power supply terminal VGL.

[0093] During the low-level holding phase t4, the eighteenth transistor M18 is turned on, and the voltage at the pull-up node UP begins to discharge to the second low-voltage signal terminal, thus making the potential of the pull-up node UP low. Simultaneously, the first pull-down node PD1 is high, discharging to a low level through the sixth transistor M6 and the twelfth transistor M12, affecting both the pull-up node UP and the output terminal Gn of the output circuit 13. Furthermore, the second clock signal terminal CLK2 and the third clock signal terminal CLK3 are periodically high, exhibiting a simultaneous high-level state. Consequently, the first transistor M1 and the second transistor M2 are periodically simultaneously turned on, ensuring that the output terminal Gn of the output circuit 13 remains stably low.

[0094] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0095] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A shift register, characterized in that, include: An input circuit is provided, which is connected to a pull-up node and a first initial signal terminal, and is used to charge the pull-up node under the control of a first initial signal provided by the first initial signal terminal. An intermediate circuit, connected to the pull-up node, is used to adjust the potential of the pull-up node; An output circuit is provided, which is connected to the pull-up node and the first clock signal terminal. The output terminal of the output circuit outputs a gate drive signal through the first clock signal provided by the first clock signal terminal under the control of the potential of the pull-up node. The discharge circuit includes a first transistor and a second transistor. The gate of the first transistor is connected to the second clock signal terminal of the output circuit. The first terminal of the first transistor is connected to the output terminal of the output circuit. The second terminal of the first transistor is connected to the first terminal of the second transistor. The gate of the second transistor is connected to the third clock signal terminal of the output circuit. The second terminal of the second transistor is connected to the first low-voltage power supply terminal in the shift register. The discharge circuit is used to discharge the output terminal of the output circuit under the control of the second clock signal provided by the second clock signal terminal and the third clock signal provided by the third clock signal terminal after the gate drive signal is output.

2. The shift register according to claim 1, characterized in that, The first clock signal, the second clock signal, and the third clock signal all have a period of 8 units of time, and the effective signal of the first clock signal, the second clock signal, and the third clock signal is 3 units of time. The second clock signal is delayed by one unit time relative to the first clock signal, and the third clock signal is delayed by three units time relative to the first clock signal. The high-level times of the second clock signal and the third clock signal overlap to control the first transistor and the second transistor to be turned on simultaneously.

3. The shift register according to claim 1, characterized in that, The input circuit includes a third transistor, the gate and first terminal of which are connected to the first initial signal terminal, and the second terminal of which is connected to the pull-up node.

4. The shift register according to claim 1, characterized in that, The intermediate circuit includes a first pull-down control module, a second pull-down control module, a first pull-down module, a second pull-down module, and a third pull-down module; The first pull-down control module is connected to the first power supply voltage input terminal and the first pull-down node; The second pull-down control module is connected to the second power supply voltage input terminal and the second pull-down node; The control terminal of the first pull-down module is connected to the first pull-down node and the second pull-down node, the first terminal of the first pull-down module is connected to the pull-up node, and the second terminal of the first pull-down module is connected to the second low-voltage power supply terminal. The control terminal of the second pull-down module is connected to the pull-up node and the first initial signal terminal, the second terminal of the second pull-down module is connected to the first pull-down node, and the third terminal of the second pull-down module is connected to the second low-voltage power supply terminal. The control terminal of the third pull-down module is connected to the pull-up node and the first initial signal terminal, the second terminal of the third pull-down module is connected to the second pull-down node, and the third terminal of the third pull-down module is connected to the second low-voltage power supply terminal.

5. The shift register according to claim 4, characterized in that, The first pull-down control module includes a fourth transistor, the gate and first terminal of the fourth transistor are connected to the first power supply voltage input terminal, and the second terminal of the fourth transistor is connected to the first pull-down node; The second pull-down control module includes a fifth transistor, the gate and first terminal of which are connected to the second power supply voltage input terminal, and the second terminal of which is connected to the second pull-down node; The first pull-down module includes a sixth transistor and a seventh transistor. The gate of the sixth transistor is connected to the first pull-down node, the first terminal of the sixth transistor is connected to the pull-up node, and the second terminal of the sixth transistor is connected to the second low-voltage power supply terminal. The gate of the seventh transistor is connected to the second pull-down node, the first terminal of the seventh transistor is connected to the pull-up node, and the second terminal of the seventh transistor is connected to the second low-voltage power supply terminal. The second pull-down module includes an eighth transistor and a ninth transistor. The gate of the eighth transistor is connected to the pull-up node, the first terminal of the eighth transistor is connected to the first pull-down node, and the second terminal of the eighth transistor is connected to the second low-voltage power supply terminal. The gate of the ninth transistor is connected to the first initial signal terminal, the first terminal of the ninth transistor is connected to the first pull-down node, and the second terminal of the ninth transistor is connected to the second low-voltage power supply terminal. The third pull-down module includes a tenth transistor and an eleventh transistor. The gate of the tenth transistor is connected to the pull-up node, the first terminal of the tenth transistor is connected to the first pull-down node, and the second terminal of the tenth transistor is connected to the second low-voltage power supply terminal. The gate of the eleventh transistor is connected to the first initial signal terminal, the first terminal of the eleventh transistor is connected to the second pull-down node, and the second terminal of the eleventh transistor is connected to the second low-voltage power supply terminal.

6. The shift register according to claim 4, characterized in that, The intermediate circuit includes a first noise reduction module. The control terminal of the first noise reduction module is connected to the first pull-down node and the second pull-down node. The first terminal of the first noise reduction module is connected to the output terminal of the output circuit, and the second terminal of the first noise reduction module is connected to the first low-voltage power supply terminal.

7. The shift register according to claim 6, characterized in that, The first noise reduction module includes a twelfth transistor and a thirteenth transistor. The gate of the twelfth transistor is connected to the first pull-down node, the first terminal of the twelfth transistor is connected to the output terminal of the output circuit, and the second terminal of the twelfth transistor is connected to the first low-voltage power supply terminal. The gate of the thirteenth transistor is connected to the second pull-down node, the first terminal of the thirteenth transistor is connected to the output terminal of the output circuit, and the second terminal of the thirteenth transistor is connected to the first low-voltage power supply terminal.

8. The shift register according to claim 4, characterized in that, The intermediate circuit includes a cascaded output module, which is connected to the pull-up node. The output terminal of the cascaded output module is used to output a cascaded signal or a second initial signal.

9. The shift register according to claim 8, characterized in that, The cascaded output module includes a fourteenth transistor, the gate of which is connected to the pull-up node, the first terminal of which is connected to the first clock signal terminal, and the second terminal of which is connected to the output terminal of the cascaded output module.

10. The shift register according to claim 9, characterized in that, The intermediate circuit includes a second noise reduction module, which is connected to the output terminal of the cascaded output module and is used to reduce noise in the cascaded output module.

11. The shift register according to claim 10, characterized in that, The second noise reduction module includes a fifteenth transistor and a sixteenth transistor. The gate of the fifteenth transistor is connected to the first pull-down node, the first terminal of the fifteenth transistor is connected to the output terminal of the cascaded output module, and the second terminal of the fifteenth transistor is connected to the second low-voltage power supply terminal. The gate of the sixteenth transistor is connected to the second pull-down node, the first terminal of the sixteenth transistor is connected to the output terminal of the cascaded output module, and the second terminal of the sixteenth transistor is connected to the second low-voltage power supply terminal.

12. The shift register according to claim 1, characterized in that, The intermediate circuit includes a reset module connected to the pull-up node, which is used to reset the potential of the pull-up node.

13. The shift register according to claim 12, characterized in that, The reset module includes a seventeenth transistor, the first terminal of which is connected to the pull-up node, the gate of which is connected to the reset signal terminal, and the second terminal of which is connected to the second low-voltage power supply terminal.

14. The shift register according to claim 1, characterized in that, The intermediate circuit includes a pre-frame discharge module, the control terminal of which is connected to the second initial signal terminal, the first terminal of which is connected to the pull-up node, and the second terminal of which is connected to the second low-voltage power supply terminal.

15. The shift register according to claim 14, characterized in that, The eighteenth transistor of the pre-frame discharge module has its gate connected to the second initial signal terminal, its first terminal connected to the pull-up node, and its second terminal connected to the second low-voltage power supply terminal.

16. The shift register according to claim 1, characterized in that, The output circuit includes a nineteenth transistor, a twentieth transistor, and a storage capacitor. The gate of the nineteenth transistor is connected to the pull-up node, the first terminal of the nineteenth transistor is connected to the third clock signal terminal, and the second terminal of the nineteenth transistor is connected to the output terminal of the output circuit. The gate of the twentieth transistor is connected to the second initial signal terminal, the first terminal of the twentieth transistor is connected to the output terminal of the output circuit, and the second terminal of the twentieth transistor is connected to the first low-voltage power supply terminal. The first terminal of the storage capacitor is connected to the pull-up node, and the second terminal of the storage capacitor is connected to the output terminal of the output circuit.

17. A gate driving circuit, characterized in that, The system comprises M cascaded shift registers and N clock signal lines, wherein the shift registers are the shift registers described in any one of claims 1-16; the first clock signal terminals of each of the N adjacent shift registers are respectively connected to the N clock signal lines; wherein N is an even number greater than or equal to 4; and M is an integer greater than or equal to N; wherein, The second clock signal terminal of the i-th shift register among the N adjacent shift registers is connected to the clock signal line corresponding to the first clock signal terminal of the (i+1)-th shift register; The third clock signal terminal of the i-th shift register among the N adjacent shift registers is connected to the clock signal line corresponding to the first clock signal terminal of the (i+3)-th shift register, where i is an integer and 0 < i ≤ N-3; The clock signal output from the N clock signal lines has a period of 8 units of time, and the effective signal of each clock signal is 3 units of time. The clock signals of two adjacent clock signal lines are delayed by one unit of time. The high-level periods of the second and third clock signals of each stage of the shift register overlap to control the discharge circuit to operate.

18. A display panel, characterized in that, Includes the gate drive circuit as described in claim 17.

19. A control method for controlling the shift register according to any one of claims 1-16, characterized in that, The control method includes: During the charging phase, a first initial signal is provided to the first initial signal terminal to increase the potential of the pull-up node; During the pull-up phase, a first clock signal is provided to the first clock signal terminal so that the output terminal of the output circuit outputs the gate drive signal. During the discharge phase, a second clock signal is provided to the second clock signal terminal and a third clock signal is provided to the third clock signal terminal to discharge the output terminal of the output circuit. During the holding phase, a second clock signal is periodically provided to the second clock signal terminal and a third clock signal is provided to the third clock signal terminal to maintain the potential of the output terminal of the output circuit.

Images