Semiconductor structure and method of manufacturing the same

Abstract

Semiconductor structures and methods of fabricating the same are provided. A semiconductor structure includes a substrate and a first nanostructure and a second nanostructure formed above the substrate. The semiconductor structure also includes a gate structure including a first portion encasing the first nanostructure and a second portion encasing the second nanostructure. The semiconductor structure also includes a dielectric component interposed between the first portion and the second portion of the gate structure. Further, the dielectric component includes a bottom portion and a top portion located above the bottom portion, and the top portion of the dielectric component includes a shell layer and a core portion surrounded by the shell layer.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of manufacturing the same. Background Technology

[0002] The electronics industry is experiencing a growing demand for smaller and faster electronic devices capable of implementing a large number of increasingly complex and sophisticated functions. Consequently, there is a persistent trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by shrinking the size of semiconductor ICs (e.g., the smallest component size), thereby increasing production efficiency and reducing associated costs. However, this miniaturization introduces greater complexity into semiconductor manufacturing processes. Therefore, continued advancements in semiconductor ICs and devices require similar advancements in semiconductor manufacturing processes and technologies.

[0003] Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reducing off-state current, and minimizing short-channel effect (SCE). However, the fabrication and integration of multi-gate devices can be challenging. Summary of the Invention

[0004] Some embodiments of this application provide a semiconductor structure including: a substrate; a first nanostructure and a second nanostructure formed over the substrate; a gate structure including a first portion enclosing the first nanostructure and a second portion enclosing the second nanostructure; and a dielectric member sandwiched between the first portion and the second portion of the gate structure, wherein the dielectric member includes: a bottom portion; and a top portion located above the bottom portion, wherein the top portion of the dielectric member includes a shell and a core portion surrounded by the shell.

[0005] Other embodiments of this application provide a semiconductor structure including: a substrate; a nanostructure formed on the substrate; a gate structure enclosing the nanostructure; and a first dielectric component dividing the gate structure into a first portion and a second portion, wherein the first dielectric component includes: a bottom portion; and a top portion located above the bottom portion, wherein the top portion of the first dielectric component includes a shell made of a first dielectric material and a core portion made of a second dielectric material, wherein the dielectric constant of the first dielectric material is higher than the dielectric constant of the second dielectric material.

[0006] Further embodiments of this application provide a method for manufacturing a semiconductor structure, comprising: forming a fin structure protruding from a substrate, wherein the fin structure includes alternately stacked first and second semiconductor material layers; forming an isolation structure surrounding the fin structure; forming a dielectric component over the isolation structure, comprising: forming a bottom portion of the dielectric component over the isolation structure; forming a shell layer over the bottom portion of the dielectric component; forming a core portion surrounded by the shell layer over the shell layer; recessing the shell layer and the core portion to form a groove; and forming a capping layer in the groove; removing the first semiconductor material layer of the fin structure to form a nanostructure having a second semiconductor material layer; and forming a gate structure encapsulating the nanostructure. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figure 1 A schematic top view of a semiconductor structure according to some embodiments is shown.

[0009] Figures 2A to 2Z A schematic perspective view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments is shown.

[0010] Figure 3A The following are shown according to some embodiments. Figure 1 The cross-sectional view of the semiconductor structure shown by line A-A' in the figure.

[0011] Figure 3B The following are shown according to some embodiments. Figure 1 The cross-sectional view of the semiconductor structure shown by line B-B' in the figure.

[0012] Figure 3C The following are shown according to some embodiments. Figure 1 The cross-sectional view of the semiconductor structure shown by line C-C' in the figure.

[0013] Figure 3D The following are shown according to some embodiments. Figure 1 The cross-sectional view of the semiconductor structure shown by line D-D' in the figure.

[0014] Figure 4 A schematic perspective view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments is shown.

[0015] Figure 5A and Figure 5BA cross-sectional view of a semiconductor structure according to some embodiments is shown.

[0016] Figures 6A to 6D A cross-sectional view of a semiconductor structure according to some embodiments is shown.

[0017] Figure 7 A cross-sectional view of a semiconductor structure according to some embodiments is shown.

[0018] Figure 8 A cross-sectional view of a semiconductor structure according to some embodiments is shown.

[0019] Figure 9A and Figure 9B A cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments is shown.

[0020] Figure 10A and Figure 10B A cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments is shown.

[0021] Figure 11 A cross-sectional view of a semiconductor structure according to some embodiments is shown.

[0022] Figure 12 A cross-sectional view of a semiconductor structure according to some embodiments is shown.

[0023] Figure 13 A cross-sectional view of a semiconductor structure according to some embodiments is shown.

[0024] Figure 14A and Figure 14B A cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments is shown.

[0025] Figure 15A and Figure 15B A cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments is shown.

[0026] Figure 16A and Figure 16B A cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments is shown. Detailed Implementation

[0027] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0028] Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. It should be understood that additional operations may be provided before, during, and after the method, and some of the described operations may be replaced or eliminated for other embodiments of the method.

[0029] The nanostructure transistors described below (e.g., nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon FETs, gate-all-around (GAA) transistor structures) can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller spacing than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern a GAA structure.

[0030] Embodiments of semiconductor structures and methods for forming the same are provided. The semiconductor structure may include a nanostructure formed on a substrate and a gate structure enclosing the nanostructure. Dielectric components may be formed to separate the gate structure into different portions. Furthermore, the dielectric components may include a bottom portion and a top portion, and the top portion may include a core portion and a shell surrounding the core portion. The core portion of the dielectric component may be made of a low-k dielectric material, which can therefore help reduce capacitance and improve the speed and performance of the resulting device.

[0031] Figure 1 A schematic top view of a semiconductor structure 100 according to some embodiments is shown. For clarity, it has been simplified. Figure 1To better understand the inventive concept of this invention, additional components may be added to the semiconductor structure 100, and some of the components described below may be replaced, modified, or eliminated.

[0032] Semiconductor structure 100 may include multi-gate devices and may be included in a microprocessor, memory, or other IC device. For example, semiconductor structure 100 may be part of an IC chip, which includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof.

[0033] Figures 2A to 2Z A schematic perspective view is shown of an intermediate stage in the fabrication of a semiconductor structure 100 according to some embodiments. More specifically, Figures 2A to 2R Manufacturing process is shown Figure 1 A schematic perspective view of an intermediate stage of the semiconductor structure 100 shown in the dashed box C1, and Figures 2S to 2Z Manufacturing according to some embodiments is shown. Figure 1 A schematic perspective view of an intermediate stage of the semiconductor structure 100 shown in the dashed box C2.

[0034] First, according to some embodiments, a semiconductor stack including a first semiconductor material layer 106 and a second semiconductor material layer 108 is formed over a substrate 102, such as... Figure 2A As shown in the diagram. Substrate 102 may be a semiconductor wafer, such as a silicon wafer. Optionally or additionally, substrate 102 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0035] In some embodiments, a first semiconductor material layer 106 and a second semiconductor material layer 108 are alternately stacked over a substrate 102 to form a semiconductor stack. In some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 are made of different semiconductor materials. In some embodiments, the first semiconductor material layer 106 is made of SiGe, and the second semiconductor material layer 108 is made of silicon. It should be noted that although in Figure 2A The diagram shows three first semiconductor material layers 106 and three second semiconductor material layers 108, but the semiconductor structure may include more or fewer first semiconductor material layers 106 and second semiconductor material layers 108. For example, the semiconductor structure may include two to five first semiconductor material layers 106 and two to five second semiconductor material layers 108.

[0036] The first semiconductor material layer 106 and the second semiconductor material layer 108 can be formed using low-pressure chemical vapor deposition (LPCVD), epitaxial growth processes, another suitable method, or a combination thereof. In some embodiments, the epitaxial growth process includes molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE).

[0037] According to some embodiments, after the first semiconductor material layer 106 and the second semiconductor material layer 108 are formed as a semiconductor material stack above the substrate 102, the semiconductor material stack is patterned to form fin structures 104-1 and 104-2, such as Figure 2B As shown in the diagram. Furthermore, according to some embodiments, fin structures 104-1 and 104-2 extend along the X direction, as shown in the diagram. Figure 2B As shown in the figure. In some embodiments, fin structures 104-1 and 104-2 include a base fin structure 105 and a semiconductor material stack formed on the base fin structure 105, the semiconductor material stack including a first semiconductor material layer 106 and a second semiconductor material layer 108.

[0038] In some embodiments, the patterning process includes: forming a mask structure 110 over a semiconductor material stack; and etching the semiconductor material stack and the underlying substrate 102 through the mask structure 110. In some embodiments, the mask structure 110 is a multilayer structure including a pad oxide layer 112 and a nitride layer 114 formed over the pad oxide layer 112. The pad oxide layer 112 may be made of silicon oxide, which may be formed by thermal oxidation or CVD, and the nitride layer 114 may be made of silicon nitride, which may be formed by CVD, such as LPCVD or plasma-enhanced CVD (PECVD).

[0039] According to some embodiments, after forming fin structures 104-1 and 104-2, layers such as pads 115 and 117 are formed to cover fin structures 104-1 and 104-2, such as... Figure 2C As shown in the figure. In some embodiments, pads 115 and 117 are made of different dielectric materials. In some embodiments, pad 115 is made of oxide and pad 117 is made of nitride. In some embodiments, pad 115 is omitted.

[0040] Next, according to some embodiments, an insulating layer 119 is formed around the fin structures 104-1 and 104-2 above the pad 117, such as Figure 2D As shown in the figure. In some embodiments, the insulating layer 119 is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), another suitable insulating material, or a combination thereof.

[0041] Subsequently, according to some embodiments, the insulating layer 119 and the gaskets 115 and 117 are recessed to form the insulating structure 116, such as... Figure 2E As shown in the figure. According to some embodiments, the isolation structure 116 is configured as an active region of an electrically isolated semiconductor structure (e.g., fin structures 104-1 and 104-2) and is also referred to as a shallow trench isolation (STI) component.

[0042] According to some embodiments, after the isolation structure 116 is formed, a covering layer 118 is formed above the top surface and sidewalls of the fin structures 104-1 and 104-2 above the isolation structure 116, such as... Figure 2F As shown in the figure. In some embodiments, the cladding layer 118 is made of a semiconductor material. In some embodiments, the cladding layer 118 is made of silicon germanium (SiGe). In some embodiments, the cladding layer 118 and the first semiconductor material layer 106 are made of the same semiconductor material.

[0043] The cladding layer 118 can be formed by performing an epitaxial process, such as VPE and / or UHV CVD, molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. After depositing the cladding layer 118, an etching process can be performed to remove portions of the cladding layer 118 not formed on the sidewalls of the fin structures 104-1 and 104-2, for example, using a plasma dry etching process. In some embodiments, the etching process partially or completely removes portions of the cladding layer 118 formed on the top surfaces of the fin structures 104-1 and 104-2, such that the thickness of the cladding layer 118 above the top surfaces of the fin structures 104-1 and 104-2 is thinner than the thickness of the cladding layer 118 on the sidewalls of the fin structures 104-1 and 104-2.

[0044] Prior to the formation of the cladding layer 118, a semiconductor pad (not shown) may be formed over the fin structures 104-1 and 104-2. The semiconductor pad may be a Si layer and may be incorporated into the cladding layer 118 during the epitaxial growth process used to form the cladding layer 118.

[0045] Next, according to some embodiments, a liner layer 120 is formed over the covering layer 118 and the isolation structure 116, such as Figure 2GAs shown in the figure. In some embodiments, the pad layer 120 is made of a low-k dielectric material having a k value of less than 7. In some embodiments, the pad layer 120 is made of SiN, SiCN, SiOCN, SiON, etc. The pad layer 120 can be deposited using CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof. In some embodiments, the pad layer 120 has a thickness ranging from about 2 nm to about 8 nm.

[0046] According to some embodiments, after the liner layer 120 is formed, a filler layer 122 is formed above the liner layer 120 to completely fill the gap between adjacent fin structures 104-1 and 104-2, and a polishing process is performed until the top surface of the overlay layer 118 is exposed, such as... Figure 2H As shown in the image.

[0047] In some embodiments, both the filler layer 122 and the liner layer 120 are made of oxides, but formed by different methods. In some embodiments, the filler layer 122 is made of SiN, SiCN, SiOCN, SiON, etc. The filler layer 122 can be deposited using a flowable CVD (FCVD) process, which includes, for example, depositing a flowable material (such as a liquid compound) and converting the flowable material into a solid material by suitable techniques (such as thermal annealing and / or ultraviolet radiation treatment).

[0048] Next, according to some embodiments, a groove 124 is formed between fin structures 104-1 and 104-2, such as... Figure 2I As shown in the figure. In some embodiments, the filler layer 122 and the padding layer 120 are recessed by performing an etching process. In some embodiments, the filler layer 122 is formed using a flowable CVD process such that after the etching process is performed, the resulting filler layer 122 can have a relatively flat top surface.

[0049] Subsequently, according to some embodiments, a shell layer 126 and a core portion 128 are formed in the groove 124, such as Figure 2JAs shown in the diagram. In some embodiments, a shell 126 is formed on the bottom surface and sidewalls of a recess 124, and a core portion 128 is formed above and surrounded by the shell 126. In some embodiments, the bottom surface and sidewalls of the core portion 128 are covered by the shell 126. In some embodiments, the shell 126 has a height H1 ranging from about 25 nm to about 50 nm. In some embodiments, the thickness of the shell 126 ranges from about 1 nm to about 6 nm. The thickness of the shell 126 can be controlled to be sufficiently thick to protect the core portion 128 and the bottom portion in a subsequent etching process, so that the subsequently formed source / drain structures can be properly separated without merging. On the other hand, the shell 126 cannot be too thick, otherwise the capacitance of the resulting device may increase.

[0050] In some embodiments, the shell 126 and the core portion 128 are made of different materials, and the material used to form the shell 126 has a higher dielectric constant than the material used to form the core portion 128. The core portion 128 can help reduce the k-value of the structure and can have a denser structure (fewer voids). In some embodiments, an annealing process is performed to remove voids formed in the core portion 128.

[0051] In some embodiments, the shell 126 is made of a high-k dielectric material, and the core portion 128 is made of a low-k dielectric material. In some embodiments, the shell 126 is made of a dielectric material having a k value greater than 7, and the core portion 128 is made of a dielectric material having a k value less than 7. In some embodiments, the shell 126 is made of HfO2, ZrO2, or HfAlO2. x HfSiO x It is made of materials such as Al2O3. In some embodiments, the core portion 128 is made of materials such as SiO2, SiN, SiCN, SiOC, SiOCN, etc. In some embodiments, the core portion 128 and the pad layer 120 are made of the same dielectric material. In some embodiments, the core portion 128 has a thickness in the range of about 8 nm to about 30 nm.

[0052] The dielectric material used to form the shell 126 and the core portion 128 can be formed by performing ALD, CVD, PVD, oxidation-based deposition processes, other suitable processes, or combinations thereof. According to some embodiments, after forming the core portion 128, a CMP process is performed until the mask structure 110 is exposed.

[0053] According to some embodiments, after performing the CMP process, the top portion of the core portion 128 is removed to form the groove 130, such as... Figure 2K As shown in the figure. In some embodiments, the core portion 128 is etched to form a groove 130, without etching or only slightly etching the shell layer 126.

[0054] Subsequently, according to some embodiments, a cover layer 132 is formed in the groove 130, thereby forming a dielectric component 134, such as... Figure 2L As shown in the figure. In some embodiments, dielectric component 134 includes dielectric components 134-1, 134-2, and 134-3 located on opposite sides of fin structures 104-1 and 104-2. In some embodiments, capping layer 132 and shell layer 126 are made of the same dielectric material. In some embodiments, capping layer 132 is made of a high-k dielectric material, such as HfO2, ZrO2, or HfAlO2. x HfSiO x Materials such as Al2O3. The dielectric material used to form the capping layer 132 can be formed by performing ALD, CVD, PVD, oxidation-based deposition processes, other suitable processes, or combinations thereof. According to some embodiments, after the capping layer 132 is formed, a CMP process is performed until the mask structure 110 is exposed.

[0055] In some embodiments, the dielectric component 134 includes a bottom portion 134B and a top portion 134T located above the bottom portion 134B. According to some embodiments, the bottom portion 134B includes a pad layer 120 and a fill layer 122, and the top portion 134T includes a shell layer 126, a core portion 128, and a capping layer 132. The capping layer 132 may be configured to protect the dielectric component during a subsequent etching process. In some embodiments, the capping layer 132 has a height H2 in the range of about 5 nm to about 20 nm. The capping layer 132 should be thick enough to protect the dielectric component 134 during a subsequent etching process, such that the dielectric component can be used to separate adjacent source / drain structures subsequently formed.

[0056] Because the spacing between the dielectric component 134 and the fin structures 104-1 and 104-2 is self-aligned, a complex alignment process is not required when forming the dielectric component 134. Furthermore, the width of the dielectric component 134 can be determined by the width of the spacing between the fin structures 104-1 and 104-2 and the thickness of the overlay layer 118. In some embodiments, the dielectric components 134 have substantially the same width. Meanwhile, in some embodiments, the spacing between the fin structures 104-1 and 104-2 has different widths, and the dielectric components 134 also have different widths. Figure 1 As shown, according to some embodiments, dielectric component 134 is formed between and substantially parallel to fin structures 104-1 and 104-2.

[0057] Next, according to some embodiments, the top portion of the mask structure 110 and the cladding layer 118 above the fin structures 104-1 and 104-2 is removed to expose the top surface of the topmost second semiconductor material layer 108, such as... Figure 2M As shown in the figure. In some embodiments, the top surface of the cladding layer 118 is substantially flush with the top surface of the topmost second semiconductor material layer 108.

[0058] The mask structure 110 and the cladding layer 118 can be recessed by performing one or more etching processes with a higher etching rate than that of the dielectric component 134, thereby causing only a slight etching of the dielectric component 134 during the etching process. The selective etching process can be dry etching, wet drying, reactive ion etching, or other suitable etching methods.

[0059] Subsequently, according to some embodiments, a pseudo-gate structure 136 is formed across the fin structures 104-1 and 104-2 and the dielectric component 134, such as Figure 2N As shown in the diagram, the pseudo-gate structure 136 can be used to define the source / drain region and the channel region of the resulting semiconductor structure 100.

[0060] In some embodiments, the dummy gate structure 136 includes a dummy gate dielectric layer 138 and a dummy gate electrode layer 140. In some embodiments, the dummy gate dielectric layer 138 is made of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), HfO2, HfZrO, HfSiO, HfTiO, HfAlO, or combinations thereof. In some embodiments, the dummy gate dielectric layer 138 is formed using thermal oxidation, CVD, ALD, physical vapor deposition (PVD), another suitable method, or combinations thereof.

[0061] In some embodiments, the dummy gate electrode layer 140 is made of a conductive material comprising polysilicon (poly-Si), polysilicon germanium (poly-SiGe), or a combination thereof. In some embodiments, the dummy gate electrode layer 140 is formed using CVD, PVD, or a combination thereof.

[0062] In some embodiments, a hard mask layer 142 is formed over the dummy gate structure 136. In some embodiments, the hard mask layer 142 includes multiple layers, such as an oxide layer 144 and a nitride layer 146. In some embodiments, the oxide layer 144 is silicon oxide and the nitride layer 146 is silicon nitride.

[0063] The formation of the dummy gate structure 136 may include conformally forming a dielectric material as a dummy gate dielectric layer 138. Subsequently, a conductive material may be formed over the dielectric material as a dummy gate electrode layer 140, and a hard mask layer 142 may be formed over the conductive material. Next, the dielectric and conductive materials may be patterned using the hard mask layer 142 to form the dummy gate structure 136.

[0064] According to some embodiments, after forming the dummy gate structure 136, gate spacers 148 covering the opposite sidewalls of the dummy gate structure 136 are formed along the opposite sidewalls of the dummy gate structure 136, such as... Figure 2O As shown in the figure. In some embodiments, the gate spacer 148 also covers a portion of the top surface and sidewalls of the dielectric member 134.

[0065] Gate spacer 148 may be configured to separate the source / drain structure (formed subsequently) from the dummy gate structure 136. In some embodiments, gate spacer 148 is made of a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), and / or combinations thereof.

[0066] According to some embodiments, after the gate spacer 148 is formed, a source / drain recess 150 is formed adjacent to the gate spacer 148, such as... Figure 2O As shown in the diagram. More specifically, according to some embodiments, the fin structures 104-1 and 104-2, which are not covered by the dummy gate structure 136 and the gate spacer 148, and the cladding layer 118 are recessed. Furthermore, according to some embodiments, the top portion 134T of the dielectric member 134 is also recessed to have a recessed portion 134T_R at the source / drain region. In some embodiments, the cladding layer 132 is completely removed. In some embodiments, the top portions of the shell layer 126 and the core portion 128 are also partially removed to form the recessed portion 134T_R at the source / drain region.

[0067] In some embodiments, the fin structures 104-1 and 104-2 and the cladding layer 118 are recessed by performing an etching process. The etching process can be an anisotropic etching process, such as dry plasma etching, and during the etching process, the dummy gate structure 136 and the gate spacer 148 can be used as an etching mask.

[0068] According to some embodiments, after forming the source / drain trench 150, the first semiconductor material layer 106 and the cladding layer 118 exposed by the source / drain trench 150 are laterally recessed to form a notch 154, such as... Figure 2P As shown in the image.

[0069] In some embodiments, an etching process is performed to laterally recess the first semiconductor material layer 106 and the cladding layer 118 of the fin structures 104-1 and 104-2 from the source / drain recess 150. In some embodiments, during the etching process, the first semiconductor material layer 106 and the cladding layer 118 have an etching rate (or etching amount) greater than that of the second semiconductor material layer 108, thereby forming notches 154 between adjacent second semiconductor material layers 108 and around the second semiconductor material layer 108. In some embodiments, the etching process is isotropic etching, such as dry chemical etching, remote plasma etching, wet chemical etching, another suitable technique, and / or a combination thereof.

[0070] Next, according to some embodiments, internal spacers 156 are formed in the recesses 154 between and around the second semiconductor material layers 108, such as... Figure 2Q As shown in the diagram. The internal spacer 156 can be configured to separate the source / drain structure and the gate structure formed in a subsequent manufacturing process. In some embodiments, the internal spacer 156 is made of a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), or combinations thereof.

[0071] According to some embodiments, after forming the internal spacer 156, a source / drain structure 158 is formed in the source / drain recess 150, such as... Figure 2R As shown in the diagram. In some embodiments, the source / drain structure 158 is separated by dielectric members 134-1, 134-2, and 134-3. More specifically, the source / drain structure 158 is formed in the gaps between the dielectric members 134-1, 134-2, and 134-3 in the source / drain region. Furthermore, according to some embodiments, the source / drain structure 158 is in direct contact with the pad layer 120 at the bottom portion 134B of the dielectric members 134-1, 134-2, and 134-3. In some embodiments, an air gap is formed beneath the source / drain structure 158. In some embodiments, the air gap is surrounded by the source / drain structure 158, the dielectric members 134-1, 134-2, or 134-3, and the isolation structure 116. In some embodiments, the top surface of the recessed portion 134T_R of the top portion 134T of the dielectric components 134-1, 134-2 and 134-3 is higher than the top surface of the source / drain structure 158.

[0072] In some embodiments, the source / drain structure 158 is formed using an epitaxial growth process, such as MBE, MOCVD, VPE, other suitable epitaxial growth processes, or combinations thereof. In some embodiments, the source / drain structure 158 is made of any suitable material, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or combinations thereof. In some embodiments, the source / drain structure 158 is in-situ doped during the epitaxial growth process. For example, the source / drain structure 158 may be epitaxially grown SiGe doped with boron (B). For example, the source / drain structure 158 may be: epitaxially grown Si doped with carbon to form a silicon:carbon (Si:C) source / drain device; epitaxially grown Si doped with phosphorus to form a silicon:phosphorus (Si:P) source / drain device; or epitaxially grown Si doped with both carbon and phosphorus to form a silicon-carbon-phosphorus (SiCP) source / drain device. In some embodiments, the source / drain structure 158 is doped in one or more implantation processes following the epitaxial growth process.

[0073] According to some embodiments, after forming the source / drain structure 158, a contact etch stop layer (CESL) 160 is conformally formed to cover the source / drain structure 158, and an interlayer dielectric (ILD) layer 162 is formed above the contact etch stop layer 160, such as... Figure 2R As shown in the image.

[0074] In some embodiments, the contact etch stop layer 160 is made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination thereof. The dielectric material for the contact etch stop layer 160 may be conformally deposited over the semiconductor structure by performing CVD, ALD, other suitable methods, or a combination thereof.

[0075] The interlayer dielectric layer 162 may comprise a multilayer made of various dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BPSG), or other suitable low-k dielectric materials. The interlayer dielectric layer 162 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0076] According to some embodiments, after depositing the contact etch stop layer 160 and the interlayer dielectric layer 162, a planarization process such as CMP or an etch-back process is performed until the gate electrode layer 140 of the dummy gate structure 136 is exposed, and a protective layer 164 is formed over the interlayer dielectric layer 162. Figure 2RAs shown in the diagram. More specifically, after a planarization process, the interlayer dielectric layer 162 is recessed to a level below the top surface of the dummy gate electrode layer 140, and a protective layer 164 is deposited over the interlayer dielectric layer 162 to protect it from subsequent etching processes. In some embodiments, the protective layer 164 is made of the same or similar material as that in the contact etch stop layer 160. In some embodiments, the protective layer 164 is made of Si3N4, SiCN, SiOCN, SiOC, metal oxides (such as HrO2, ZrO2, hafnium alumina), and hafnium silicate, or other suitable materials. The protective layer 164 can be formed by CVD, PVD, ALD, or other suitable methods.

[0077] Figures 2S to 2Z Manufacturing according to some embodiments is shown. Figure 1 The dashed box C2 shows a schematic perspective view of an intermediate stage of the semiconductor structure 100. According to some embodiments, after forming the interlayer dielectric layer 162 and the protective layer 164, the dummy gate structure 136, the cladding layer 118, and the first semiconductor material layer 106 are removed to form a gate trench 166, as shown below. Figure 2S As shown in the diagram. More specifically, according to some embodiments, the dummy gate structure 136, the cladding layer 118, and the first semiconductor material layer 106 are removed to form a nanostructure 108' having a second semiconductor material layer 108. The removal process may include one or more etching processes. For example, when the dummy gate electrode layer 140 is polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the dummy gate electrode layer 140. Subsequently, the dummy gate dielectric layer 138 can be removed using plasma dry etching, dry chemical etching, and / or wet etching. The first semiconductor material layer 106 and the cladding layer 118 can be removed by implementing a selective wet etching process, such as an APM (e.g., an ammonia hydroxide-hydrogen peroxide-water mixture) etching process. For example, the wet etching process uses an etchant such as ammonium hydroxide (NH4OH), TMAH, ethylenediamine catechol (EDP), and / or potassium hydroxide (KOH) solution.

[0078] In some embodiments, the top portion of the gate spacer 148 is also removed (e.g., etched) to form a shortened gate spacer 148', so that the top portion of the gate trench 166 can be enlarged and the gate structure can then be more easily formed in the gate trench.

[0079] Next, according to some embodiments, a gate structure 168 encapsulating the nanostructure 108' is formed, such as... Figure 2T As shown in the figure. According to some embodiments, the gate structure 168 encloses the nanostructure 108' to form an all-around gate transistor structure. In some embodiments, the gate structure 168 includes an interface layer 170, a gate dielectric layer 172, and a gate electrode layer 174.

[0080] In some embodiments, the interface layer 170 is an oxide layer formed around the nanostructure 108' and on the exposed portion of the base fin structure 105. In some embodiments, the interface layer 170 is formed by performing a thermal process.

[0081] In some embodiments, a gate dielectric layer 172 is formed over an interface layer 170 such that the nanostructure 108' is surrounded (e.g., wrapped) by the gate dielectric layer 172. Furthermore, according to some embodiments, the gate dielectric layer 172 also covers the gate spacer 148', the inner spacer 156, and the sidewalls of dielectric components 134-1, 134-2, and 134-3. In some embodiments, the gate dielectric layer 172 is made of one or more layers of dielectric material, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, or combinations thereof. In some embodiments, the gate dielectric layer 172 is formed using CVD, ALD, other suitable methods, or combinations thereof.

[0082] In some embodiments, the gate electrode layer 174 is formed on the gate dielectric layer 172. In some embodiments, the gate electrode layer 174 is made of one or more layers of conductive material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, or combinations thereof. In some embodiments, the gate electrode layer 174 is formed using CVD, ALD, electroplating, other suitable methods, or combinations thereof. Other conductive layers, such as work function metal layers, may also be formed in the gate structure 168, but they are not shown in the figures. After the interface layer 170, the gate dielectric layer 172, and the gate electrode layer 174 are formed, planarization processes such as CMP or etch-back processes may be performed until the protective layer 164 is exposed.

[0083] According to some embodiments, after the gate structure 168 is formed, an etch-back process is performed to remove the capping layer 132 of the top portion 134T of the dielectric component 134 in the channel region and the top portion 134T of the gate structure 168. Figure 2U As shown in the diagram. More specifically, according to some embodiments, the top portion of the gate structure 168 and the cover layer 132 of the dielectric member 134 are removed to form a recess 176 between the gate spacers 148'. In some embodiments, the top surface of the gate structure 168 is substantially flush with the top surface of the dielectric member 134 at the channel region. Thus, according to some embodiments, the gate structure 168 is divided into portions 168-1 and 168-2 by the dielectric member 134, as shown in the diagram. Figure 2UAs shown in the figure. In some embodiments, after the etch-back process, the shell 126 in the channel region has a height ranging from about 6 nm to about 15 nm. In some embodiments, after the etch-back process, the core portion 128 in the channel region has a height ranging from about 5 nm to about 15 nm.

[0084] Subsequently, according to some embodiments, a metal layer 178 is conformally formed above the bottom surface and sidewalls of the groove 176, such as... Figure 2V As shown in the diagram. More specifically, according to some embodiments, the metal layer 178 covers the top surface of the gate structure 168, the top surfaces of the dielectric components 134-1, 134-2, and 134-3 in the channel region, the sidewalls of the dielectric components 134-1, 134-2, and 134-3 located below the gate spacer 148', the top surface of the protective layer 164, and the sidewalls of the CESL 160. In some embodiments, the metal layer 178 is made of Ru, W, TiN, TaN, Co, Ti, TiAl, etc. In some embodiments, the metal layer 178 comprises two metal-containing material layers, such as a bottom layer (e.g., a TiN layer) and a main layer (e.g., a W layer) formed above the bottom layer. In some embodiments, the bottom layer is thinner than about 2 nm.

[0085] Next, according to some embodiments, the metal layer 178 formed on the sidewalls of the gate spacer 148', the sidewalls of the CESL 160, and the top surface of the protective layer 164 is removed to form a patterned metal layer 178' on the gate structure 168, such as... Figure 2W As shown in the figure. In some embodiments, a wet etching process is performed to partially remove the metal layer 178'.

[0086] Metal layer 178' may be configured to electrically connect multiple portions of gate structure 168 defined by dielectric components 134-1, 134-2, and 134-3. In some embodiments, metal layer 178' has a thickness ranging from about 2 nm to about 10 nm, such as about 2 nm to about 6 nm. Metal layers 178' should be thick enough that they may break during subsequent manufacturing processes and could affect the connections between different portions of gate structure 168. On the other hand, metal layers 178' should not be too thick, otherwise the capacitance of the resulting device may increase and the speed of the resulting device may decrease.

[0087] According to some embodiments, after forming the metal layer 178', a photoresist structure 180 is formed to pattern the metal layer 178', such as... Figure 2XAs shown in the figure. In some embodiments, the photoresist structure 180 includes a bottom layer 182, an intermediate layer 184, and a top photoresist layer 186. Because advanced semiconductor manufacturing processes may reach the limits of photolithography, a thinner top photoresist layer is required to achieve a smaller process window. However, it may be tempting to remove the thin top photoresist layer during the etching process. Therefore, the intermediate layer 184 and the bottom layer 182 are formed beneath the top photoresist layer 186 to provide a more robust etch support, allowing patterning of the underlying metal layer 178' to be implemented while still providing a relatively thin top photoresist layer 186.

[0088] In some embodiments, the intermediate layer 184 includes an anti-reflective material (e.g., a back anti-reflective coating (BARC) layer) to aid exposure and focusing during the processing of the top photoresist layer 186. In some embodiments, the bottom layer 182 includes a hard mask material, such as a nitride (e.g., silicon nitride, silicon oxynitride, etc.), a polymer, an amorphous material film (e.g., an amorphous carbon film or an amorphous silicon film), polycrystalline silicon, or any other material that can be patterned and selectively removed.

[0089] According to some embodiments, an opening 188 is formed in the photoresist structure 180, and a metal layer 178' is patterned through the opening 188, such as... Figure 2X As shown in the figure. More specifically, according to some embodiments, an opening 179 is formed in the metal layer 178', and the top surface of the dielectric member 134-2 is exposed by the opening 179.

[0090] According to some embodiments, after patterning the metal layer 178' to form the opening 179, the photoresist structure 180 is removed, such as... Figure 2Y As shown in the diagram. More specifically, according to some embodiments, the metal layer 178' now includes portions 178'-1 and 178'-2 separated from each other by an opening 179. In some embodiments, portion 178'-1 covers portion 168-1 of the gate structure 168, and portion 178'-2 covers portion 168-2 of the gate structure 168.

[0091] Next, according to some embodiments, a dielectric layer 190 extending into the opening 179 is formed over the metal layer 178', such as... Figure 2Y As shown in the figure. According to some embodiments, because the opening 179 is filled with dielectric layer 190, portions 178'-1 and 178'-2 of the metal layer 178' are separated by dielectric layer 190.

[0092] The dielectric layer 190 may comprise a multilayer made of various dielectric materials, such as Al2O3, ZrO2, silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BPSG), or other suitable dielectric materials. The dielectric layer 190 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0093] According to some embodiments, after the dielectric layer 190 is formed, a conductive structure 192 is formed through the portion 178'-2 of the dielectric layer 190 and the metal layer 178', and is bonded to the portion 168-2 of the gate structure 168. Furthermore, a source / drain contact 194 is formed through the interlayer dielectric layer 162 and the protective layer 164, and is bonded to the source / drain structure 158. Figure 2Z As shown in some embodiments, a silicide layer 196 is formed over the source / drain structure 158 before the source / drain contact 194 is formed. Figure 2Z Not shown in the image, see Figure 3B ).

[0094] More specifically, the conductive structure 192 and the source / drain contact 194 can be formed in different processes. For example, a trench through the interlayer dielectric layer 162 and the protective layer 164 can be formed by an etching process to expose the source / drain structure 158. In some embodiments, the source / drain structure 158 exposed by the trench is partially etched, such that the subsequently formed source / drain contact 194 can have a larger contact surface with the source / drain structure 158. In some embodiments, the dielectric component 134-2 exposed by the trench is also partially etched.

[0095] Next, the silicide layer 196 can be formed by forming a metal layer and annealing the metal layer over the top surface of the source / drain structure 158 to react the metal layer with the source / drain structure 158 to form the silicide layer 196. Unreacted metal layers can be removed after the silicide layer 196 is formed. Then, a conductive material can be formed in the trench to form the source / drain contacts 194. The conductive material can include aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt, tantalum nitride (TaN), nickel silicide (NiS), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminum nitride (TiAl), titanium aluminum nitride (TiAlN), other suitable conductive materials, or combinations thereof. Conductive materials can be formed using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable deposition process.

[0096] Similarly, the conductive structure 192 can be formed by forming trenches exposing the metal layer 178' and forming a conductive material. In some embodiments, the conductive structure 192 and the source / drain contact 194 are made of the same conductive material. In some embodiments, the conductive structure 192 and the source / drain contact 194 are formed using the same deposition process.

[0097] A pad and / or barrier layer (not shown) may be formed prior to the conductive material forming the conductive structure 192 and the source / drain contact 194. The pad may be made of silicon nitride, but any other suitable dielectric may be used as an option. The barrier layer may be made of tantalum nitride, but other materials such as tantalum, titanium, titanium nitride, etc., may also be used.

[0098] Figure 3A The following are shown according to some embodiments. Figure 1 A cross-sectional view of the semiconductor structure 100 shown by line A-A' (i.e., along the Y direction above the channel region). Figure 3B The following are shown according to some embodiments. Figure 1 A cross-sectional view of the semiconductor structure 100 shown by line B-B' (i.e., along the Y direction above the source / drain region). Figure 3C The following are shown according to some embodiments. Figure 1 A cross-sectional view of the semiconductor structure 100 shown by line C-C' (i.e., along the X direction above dielectric component 134-2). Figure 3D The following are shown according to some embodiments. Figure 1A cross-sectional view of the semiconductor structure 100 shown by line D-D' (i.e., along the X direction above dielectric component 134-3).

[0099] like Figure 3A As shown, according to some embodiments, the gate structure 168 includes a portion 168-1 of a nanostructure 108' enclosing fin structure 104-1, a portion 168-2 of a nanostructure 108' enclosing fin structure 104-2, and a portion 168-3 of a nanostructure 108' enclosing fin structure 104-3. According to some embodiments, portions 168-1, 168-2, and 168-3 of the gate structure 168 are separated by dielectric members 134-1 and 134-2. Furthermore, according to some embodiments, a portion 178'-1 of the metal layer 178' covers portions 168-1 and 168-3 of the gate structure 168 and the dielectric member 134-1, such that portions 168-1 and 168-3 of the gate structure 168 are electrically connected through portion 178'-1 of the metal layer 178'.

[0100] Meanwhile, according to some embodiments, a portion 178'-2 of the metal layer 178' covers a portion 168-1 of the gate structure 168 and the dielectric member 134-3, but is separated from the portion 178'-1 of the metal layer 178' by the dielectric layer 190, such that the portion 178'-2 of the metal layer 178' is electrically isolated from the portions 178'-1 and 178'-3 of the metal layer 178'. In some embodiments, the dielectric layer 190 is in direct contact with the top surface of the metal layer 178' and the dielectric member 134-2. In some embodiments, the dielectric members 134-1, 134-2, and 134-3 all pass through the gate structure 168, and the dielectric member 134-2 is in direct contact with the dielectric layer 190, while the dielectric members 134-1 and 134-3 are separated from the dielectric layer 190 by the metal layer 178'.

[0101] As described above, dielectric components 134-1, 134-2, and 134-3 are inserted into the gate structure 168 and divide the gate structure 168 into different portions, and the dividing portions of the gate structure 168 are connected by a subsequently formed metal layer 178'. Therefore, the spacing between the nanostructure 108' and the dielectric component 134 can be reduced without increasing the risk of short circuits caused by misalignment during the manufacturing process.

[0102] In some embodiments, according to certain examples, the top surface of the dielectric component 134 (including dielectric components 134-1, 134-2, and 134-3) in the channel region is substantially flush with the top surface of the gate structure 168, such as... Figure 3A As shown in the figure. In some embodiments, the dielectric components 134-1, 134-2 and 134-3 in the channel region are substantially flush with each other.

[0103] On the other hand, according to some embodiments, the dielectric components 134-1, 134-2 and 134-3 at the source / drain regions are not flush with each other.

[0104] As previously described, trenches can be formed through the interlayer dielectric layer 162 and the contact etch stop layer 160 before the conductive structure 194 and the silicide layer 196 are formed, and the dielectric components 134-2 exposed by the trenches can also be partially removed. Therefore, according to some embodiments, the dielectric components 134-2 below the conductive structure 194 are lower than the dielectric components 134-1 and 134-3 at the source / drain regions, such as... Figure 3B As shown in the diagram. In some embodiments, the bottom surface of the silicide layer 196 is higher than the bottom surface of the top portion 134T of the dielectric component 134-2, as illustrated. Figure 3B As shown in the figure. Furthermore, according to some embodiments, the top surface of the silicide layer 196 is higher than the top surface of the top portion 134T of the dielectric component 134-2.

[0105] Furthermore, according to some embodiments, the dielectric component 134-2 at the source / drain region is shorter than the dielectric component 134-2 at the channel region, such as... Figure 3C As shown in the figure. In some embodiments, the height difference H3 of the dielectric component 134-2 between the channel region and the source / drain region is less than about 35 nm, such as less than 10 nm. If H3 is too high, the capacitance may increase. Meanwhile, according to some embodiments, because the conductive structure 194 is not formed above the dielectric component 134-3, the dielectric component 134-3 has substantially the same height in the channel region and the source / drain region, as shown in the figure. Figure 3D As shown in the image.

[0106] Figure 4 A schematic perspective view of an intermediate stage in the fabrication of a semiconductor structure 100a according to some embodiments is shown. According to some embodiments, the materials and processes used to fabricate the semiconductor structure 100a may be similar to or the same as those used to fabricate the semiconductor structure 100 described above, except that an additional etching process is performed when forming the source / drain trenches of the semiconductor structure 100a.

[0107] More specifically, according to some embodiments, implementation Figures 2A to 2N The process shown is such that a source / drain recess 150a is formed adjacent to the gate spacer 148, as... Figure 4 As shown in the image. Similar to... Figure 2OAs shown, according to some embodiments, the fin structures 104-1 and 104-2, the cladding layer 118, and the cover layer 132 of the dielectric components 134-1, 134-2, and 134-3, which are not covered by the dummy gate structure 136 and the gate spacer 148, are recessed. Furthermore, according to some embodiments, the cover layer 132a of the dielectric components 134-1, 134-2, and 134-3 is not completely removed, such as... Figure 4 As shown in the image.

[0108] Therefore, according to some embodiments, an additional etching process is performed to completely remove the cover layer 132a to form with Figure 2N The structures shown are similar to or the same as those shown. Then, implementation... Figures 20 to 22 The process shown is used to form a semiconductor structure, which is basically the same as... Figure 2Z and Figures 3A to 3D The semiconductor structure 100 shown is similar to or the same as that shown.

[0109] Figure 5A and Figure 5B A cross-sectional view of a semiconductor structure 100b according to some embodiments is shown. According to some embodiments, the semiconductor structure 100b may be similar to the previously described semiconductor structure 100, except that the dielectric components beneath the source / drain contacts are not recessed. More specifically, according to some embodiments, Figure 5A It is above dielectric component 134b-2 along the X direction (e.g., along) Figure 1 The line C-C' shown is similar to Figure 3C The cross-sectional view shown by the line shown in the figure, and Figure 5B It is along the Y direction in the source / drain region (e.g., along Figure 1 The line B-B' shown is similar to Figure 3B The cross-sectional view shown is illustrated by the line shown in the diagram. The materials and processes used to manufacture the semiconductor structure 100b may be similar to or the same as those used to manufacture the semiconductor structure 100 described above, and will not be repeated here.

[0110] More specifically, according to some embodiments, implementation Figures 2A to 2Y The process shown involves forming a conductive structure (e.g., the same as conductive structure 194) bonded to a gate structure (e.g., the same as gate structure 168) through a dielectric layer (e.g., the same as dielectric layer 190) and a metal layer (e.g., the same as metal layer 178'), and forming a source / drain contact 194b bonded to the source / drain structure 158 through an interlayer dielectric layer (e.g., the same as interlayer dielectric layer 162) and a protective layer (e.g., the same as protective layer 164), as shown. Figure 5A and Figure 5B As shown in the image.

[0111] Furthermore, during the formation of the source / drain contact 194b, trenches are formed through the interlayer dielectric layer and protective layer to expose the source / drain structure 158 and the dielectric component 134b-2, but the dielectric component 134b-2 exposed by the trenches is not etched. Therefore, according to some embodiments, the dielectric component 134b-2 has a substantially flat top surface, such as... Figure 5A As shown in the figure. Furthermore, according to some embodiments, dielectric components 134b-1, 134b-2, and 134b-3 have substantially the same height, as... Figure 5B As shown in the image.

[0112] The processes and materials used to form dielectric components 134b-1, 134b-2 and 134b-3 and conductive structure 194b can be the same as those used to form dielectric components 134-1, 134-2 and 134-3 and conductive structure 194, and therefore will not be repeated here.

[0113] Figures 6A to 6D A cross-sectional view of a semiconductor structure 100c according to some embodiments is shown. According to some embodiments, the semiconductor structure 100c may be similar to the previously described semiconductor structure 100, except that the bottom portion of the dielectric component is made of a single material. More specifically, Figure 6A This is a cross-sectional view along the Y direction in the trench area. Figure 6B This is a cross-sectional view along the Y direction at the source / drain region. Figure 6C It is a cross-sectional view along the X direction at dielectric component 134c-2, and Figure 6D This is a cross-sectional view along the X direction at dielectric component 134c-3 (similar to...). Figure 3A , Figure 3B , Figure 3C and Figure 3D (See the cross-sectional view shown). The materials and processes used to manufacture the semiconductor structure 100c may be similar to or the same as those used to manufacture the semiconductor structure 100 described above, and will not be repeated here.

[0114] More specifically, according to some embodiments, implementation Figures 2A to 2F The process shown is such that the space between fin structures 104-1 and 104-2 is completely filled with dielectric layer 120c. In some embodiments, dielectric layer 120c is made of a low-k dielectric material, such as SiN, SiCN, SiOCN, SiON, etc. Dielectric layer 120c can be deposited using CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof.

[0115] According to some embodiments, the polishing dielectric layer 120c extends up to the cladding layer (e.g., ...). Figure 2FAfter the top surface of the covering layer 118 shown is exposed, the following is implemented. Figures 2I to 2Z The process shown is used to form semiconductor structure 100c, such as Figures 6A to 6D As shown. Figures 6A to 6D As shown, according to some embodiments, the bottom portions of dielectric components 134c-1, 134c-2 and 134c-3 are formed by dielectric layer 120c, and the top portions including shell layer 126, core portion 128 and cover layer 132 are formed above dielectric layer 120c.

[0116] Figure 7 A cross-sectional view of a semiconductor structure 100d along the Y direction at the channel region according to some embodiments is shown. According to some embodiments, the semiconductor structure 100d may be similar to the semiconductor structure 100, except that the interface between the top and bottom portions of the dielectric component is substantially flush with the nanostructure. The materials and processes used to manufacture the semiconductor structure 100d may be similar to or the same as those described above for manufacturing the semiconductor structure 100, and will not be repeated here.

[0117] More specifically, according to some embodiments, implementation Figures 2A to 2H The process shown is followed by recessing the dielectric pad 120 and dielectric fill layer 122 to form the bottom portions 134dB of dielectric components 134d-1, 134d-2, and 134d-3. According to some embodiments, after recessing the dielectric pad 120 and dielectric fill layer 122, the top surface of the bottom portions 134dB of the dielectric components 134d-1, 134d-2, and 134d-3 is substantially flush with the top surface of the topmost second semiconductor material layer (e.g., second semiconductor material layer 108). Next, according to some embodiments, the process is implemented... Figures 2J to 2Z The process shown is used to form a semiconductor structure 100d.

[0118] like Figure 7 As shown, according to some embodiments, the interface between the top portion 134dT and the bottom portion 134dB is substantially flush with the top surface of the topmost nanostructure 108' in the channel region. The processes and materials used to form dielectric components 134d-1, 134d-2, and 134d-3 can be the same as those used to form dielectric components 134-1, 134-2, and 134-3, and therefore will not be repeated here.

[0119] Figure 8A cross-sectional view of a semiconductor structure 100e shown along the Y direction at the channel region according to some embodiments is illustrated. According to some embodiments, the semiconductor structure 100e may be similar to the semiconductor structure 100, except that the interface between the top and bottom portions of the dielectric component is relatively low. The materials and processes used to manufacture the semiconductor structure 100e may be similar to or the same as those described above for manufacturing the semiconductor structure 100, and will not be repeated here.

[0120] More specifically, according to some embodiments, implementation Figures 2A to 2H The process shown involves recessing the dielectric pad 120 and dielectric fill layer 122 to form the bottom portions 134eB of the dielectric components 134e-1, 134e-2, and 134e-3. According to some embodiments, after recessing the dielectric pad 120 and dielectric fill layer 122, the top surface of the bottom portions 134eB of the dielectric components 134e-1, 134e-2, and 134e-3 is slightly lower than the top surface of the topmost second semiconductor material layer (e.g., second semiconductor material layer 108). Next, according to some embodiments, the process is implemented... Figures 2J to 2Z The process shown is used to form semiconductor structure 100e.

[0121] like Figure 8 As shown, according to some embodiments, the interface between the top portion 134eT and the bottom portion 134eB is below the top surface of the topmost nanostructure 108' in the channel region. In some embodiments, the interface between the top portion 134eT and the bottom portion 134eB is above the bottom surface of the topmost nanostructure 108' in the channel region. The processes and materials used to form dielectric components 134e-1, 134e-2, and 134e-3 can be the same as those used to form dielectric components 134-1, 134-2, and 134-3, and therefore will not be repeated here.

[0122] Figure 9A and Figure 9B A cross-sectional view of an intermediate stage of a semiconductor structure 100f, shown along the Y direction, at the fabrication channel region according to some embodiments is shown. According to some embodiments, the semiconductor structure 100f may be similar to the semiconductor structure 100, except that the dielectric components in the semiconductor structure 100f at the channel region are higher than the gate structure. The materials and processes used to fabricate the semiconductor structure 100f may be similar to or the same as those described above for fabricating the semiconductor structure 100, and will not be repeated here.

[0123] More specifically, according to some embodiments, implementation Figures 2A to 2T The process shown is followed by an etch-back process to remove the top portion of the gate structure 168f and the top portions of the dielectric components 134f-1, 134f-2, and 134f-3 in the channel region, as illustrated. Figure 9AAs shown in the figure. In some embodiments, the gate structure 168f and dielectric components 134f-1, 134f-2, and 134f-3 are etched at different rates during the etch-back process, and therefore, the top surfaces of the gate structure 168f and dielectric components 134f-1, 134f-2, and 134f-3 are not flush. In some embodiments, the top surface of the gate structure 168f is lower than the top surface of the top portion 134fT of the dielectric components 134f-1, 134f-2, and 134f-3. In some embodiments, the height difference between the top surface of the gate structure 168f and the top surface of the top portion 134fT of the dielectric components 134f-1, 134f-2, and 134f-3 in the channel region is less than about 3 nm, such that the subsequently formed metal layer can still connect the portions of the gate structure 168f separated by the dielectric components 134f-1, 134f-2, and 134f-3.

[0124] Subsequently, according to some embodiments, implementation Figures 2V to 2Z The process shown is used to form semiconductor structure 100f, as... Figure 9B As shown in the diagram. According to some embodiments, because the top surfaces of the gate structure 168f and the dielectric components 134f-1, 134f-2, and 134f-3 are not flush, the metal layer 178f' formed above them is not flat. In some embodiments, the metal layer 178f' has portions 178f'-1 and 178f'-2 (with protrusions above the dielectric components 134f-1 and 134f-3). The processes and materials used to form the gate structure 168f, the dielectric components 134f-1, 134f-2, and 134f-3, and the metal layer 178f' can be the same as those used to form the gate structure 168f, the dielectric components 134-1, 134-2, and 134-3, and the metal layer 178f', and therefore will not be repeated here.

[0125] Figure 10A and Figure 10B A cross-sectional view of an intermediate stage of a semiconductor structure 100g, shown along the Y direction, at a fabrication channel region according to some embodiments is shown. According to some embodiments, the semiconductor structure 100g may be similar to the semiconductor structure 100, except that the openings in the metal layer are wider than the dielectric components exposed by the openings. The materials and processes used to fabricate the semiconductor structure 100g may be similar to or the same as those described above for fabricating the semiconductor structure 100, and will not be repeated here.

[0126] More specifically, according to some embodiments, implementation Figures 2A to 2W The process shown is followed by patterning a metal layer 178g' through an opening 188g in the photoresist structure 180g, as illustrated. Figure 10AAs shown in the diagram. In some embodiments, the opening 188g of the photoresist structure 180g is wider than the dielectric component 134-2. Therefore, according to some embodiments, the opening 179g of the metal layer 178g' is also wider than the dielectric component 134-2, such that portions 168g-1 and 168g-2 of the gate structure 168g are also partially exposed by the opening 179g of the metal layer 178g'. In some embodiments, the edge of the opening 179g of the metal layer 178g' is not aligned with the edge of the dielectric component 134-2.

[0127] Subsequently, according to some embodiments, implementation Figure 2Y and Figure 2Z The process shown is used to form a semiconductor structure of 100g, such as Figure 10B As shown in the diagram. Because portions 168g-1 and 168g-2 are exposed by opening 179g, the subsequently formed dielectric layer 190g is in direct contact with the top surfaces of portions 168g-1 and 168g-2 of the gate structure 168g. According to some embodiments, although some portions of the gate structure 168g are not covered by the metal layer 178g', the nanostructure 108' is entirely vertically covered (e.g., vertically overlapped) by the metal layer 178g'. The processes and materials used to form the gate structure 168g, metal layer 178g', photoresist structure 180g, and dielectric layer 190g can be the same as those used to form the gate structure 168, metal layer 178', photoresist structure 180, and dielectric layer 190, and therefore will not be repeated here.

[0128] Figure 11 A cross-sectional view of a semiconductor structure 100h shown along the Y direction at the channel region according to some embodiments is illustrated. According to some embodiments, the semiconductor structure 100h may be similar to the semiconductor structure 100, except that the openings in the metal layer are narrower than the dielectric components exposed by the openings. The materials and processes used to manufacture the semiconductor structure 100h may be similar to or the same as those described above for manufacturing the semiconductor structure 100, and will not be repeated here.

[0129] Similar to semiconductor structure 100g, according to some embodiments, although dielectric component 134-2 is exposed by opening 179h of metal layer 178h', the edges of dielectric component 134-2 and opening 179h of metal layer 178h' are not aligned with each other. More specifically, according to some embodiments, opening 179h of metal layer 178h' is narrower than dielectric component 134-2, such that dielectric component 134-2 is partially exposed by opening 179h and partially covered by metal layer 178h'.

[0130] In some embodiments, the dielectric component 134-2 is partially covered by the dielectric layer 190h and partially covered by the metal layer 178h'. In some embodiments, portions 178h'-1 and 178h'-2 of the metal layer 178h' both extend to the top surface of the dielectric component 134-2. The processes and materials used to form the metal layer 178h' and the dielectric layer 190h can be the same as those used to form the metal layer 178' and the dielectric layer 190, and therefore will not be repeated here.

[0131] Figure 12 A cross-sectional view of a semiconductor structure 100i shown along the Y direction at the channel region according to some embodiments is illustrated. According to some embodiments, the semiconductor structure 100i may be similar to the semiconductor structure 100, except that the openings in the metal layer are not perfectly aligned with the dielectric components exposed by the openings. The materials and processes used to manufacture the semiconductor structure 100i may be similar to or the same as those described above for manufacturing the semiconductor structure 100, and will not be repeated here.

[0132] Similar to semiconductor structure 100g, according to some embodiments, although dielectric component 134-2 is exposed by opening 179i of metal layer 178i', the edge of dielectric component 134-2 and opening 179i of metal layer 178i' are not perfectly aligned with each other. More specifically, according to some embodiments, one of the sidewalls of opening 179i of metal layer 178i' is aligned with one of the sidewalls of dielectric component 134-2, while the other sidewall of opening 179i is located above the top surface of portion 168i-1 of gate structure 168i.

[0133] In some embodiments, the dielectric layer 190i formed over the metal layer 178i' is in direct contact with portions 168i-1 and dielectric components 134-2 of the gate structure 168i, while portions 168i-2 and 168i-3 of the gate structure 168i and dielectric components 134-1 and 134-3 are separated from the dielectric layer 190i by the metal layer 178i'. The processes and materials used to form the metal layer 178i' and the dielectric layer 190i can be the same as those used to form the metal layer 178' and the dielectric layer 190, and therefore will not be repeated here.

[0134] Figure 13 A cross-sectional view of a semiconductor structure 100j shown along the Y direction at the channel region according to some embodiments is illustrated. According to some embodiments, the semiconductor structure 100j may be similar to the semiconductor structure 100, except that the openings in the metal layer are not aligned with the dielectric components exposed by the openings. The materials and processes used to manufacture the semiconductor structure 100j may be similar to or the same as those described above for manufacturing the semiconductor structure 100, and will not be repeated here.

[0135] Similar to semiconductor structure 100g, according to some embodiments, although dielectric component 134-2 is exposed by opening 179j of metal layer 178j', the edges of dielectric component 134-2 and opening 179j of metal layer 178j' are not aligned with each other. More specifically, according to some embodiments, one of the sidewalls of opening 179j of metal layer 178j' is located above the top surface of dielectric component 134-2, while the other sidewall of opening 179j is located above the top surface of portion 168j-1 of gate structure 168j.

[0136] In some embodiments, the dielectric layer 190j formed over the metal layer 178j' is in direct contact with portions 168j-1 and dielectric components 134-2 of the gate structure 168j, while portions 168j-2 and 168j-3 of the gate structure 168j and dielectric components 134-1 and 134-3 are separated from the dielectric layer 190j by the metal layer 178j'. Furthermore, according to some embodiments, portion 178j'-2 of the metal layer 178j' extends over the top surface of the dielectric component 134-2. The processes and materials used to form the metal layer 178j' and the dielectric layer 190j can be the same as those used to form the metal layer 178' and the dielectric layer 190, and therefore will not be repeated here.

[0137] Figure 14A and Figure 14B A cross-sectional view of an intermediate stage of a semiconductor structure 100k shown along the Y direction at a fabrication channel region according to some embodiments is shown. According to some embodiments, the semiconductor structure 100k may be similar to the semiconductor structure 100, except that the dielectric components exposed by openings in the metal layer are partially removed. The materials and processes used to fabricate the semiconductor structure 100k may be similar to or the same as those described above for fabricating the semiconductor structure 100, and will not be repeated here.

[0138] More specifically, according to some embodiments, implementation Figures 2A to 2W The process shown involves patterning a metal layer with an opening 188k through a photoresist structure 180k to form a patterned metal layer 178k' with an opening 179k, as illustrated. Figure 14AAs shown in the figure. In some embodiments, the dielectric component 134k-2 below the opening 179k of the metal layer 178k' is also etched to form a groove 135k during the etching process for patterning the metal layer. In some embodiments, the bottom portion of the groove 135k is lower than the top surface of the gate structure 168. In some embodiments, the top portion of the core portion 128k-2 of the dielectric component 134k-2 is removed (e.g., etched) such that the top surface of the core portion 128k-2 of the dielectric component 134k-2 is lower than the top surface of the core portion 128k-1 of the dielectric component 134k-1 and the top surface of the core portion 128k-3 of the dielectric component 134k-3. In some embodiments, the top portion of the shell layer 126k-2 of the dielectric component 134k-2 is higher than the top surface of the core portion 128k-2 and substantially flush with the top portions of the shell layers 126k-1 and 126k-3 of the dielectric components 134k-1 and 134k-3.

[0139] Subsequently, according to some embodiments, implementation Figure 2Y and Figure 2Z The process shown is used to form a semiconductor structure of 100k, such as Figure 14B As shown in some embodiments, because the core portion 128k-2 of dielectric member 134k-2 is partially removed, the dielectric layer 190k formed above the metal layer 178k' has an extension portion 191k extending into the groove 135k above the dielectric member 134k-2. In some embodiments, the extension portion 191k of the dielectric layer 190k is surrounded by a shell layer 126k-2. Furthermore, according to some embodiments, the bottom surface of the extension portion 191k of the dielectric layer 190k (or the top surface of the core portion 128k-2 of the dielectric member 134k-2) is lower than the top surface of the gate structure 168k, the top surfaces of dielectric members 134k-1 and 134k-3, and the bottom surface of the metal layer 178k'. The processes and materials used to form dielectric components 134k-1, 134k-2 and 134k-3, metal layer 178k', photoresist structure 180k and dielectric layer 190k can be the same as those used to form dielectric components 134k-1, 134k-2 and 134k-3, metal layer 178', photoresist structure 180 and dielectric layer 190, and therefore will not be repeated here.

[0140] Figure 15A and Figure 15B A cross-sectional view of an intermediate stage of a semiconductor structure 100l shown along the Y direction at a fabrication channel region according to some embodiments is shown. According to some embodiments, the semiconductor structure 100l may be similar to the semiconductor structure 100, except that the dielectric components exposed by openings in the metal layer are partially removed. The materials and processes used to fabricate the semiconductor structure 100l may be similar to or the same as those described above for fabricating the semiconductor structure 100, and will not be repeated here.

[0141] More specifically, according to some embodiments, implementation Figures 2A to 2W The process shown involves patterning a metal layer through openings 188l in the photoresist structure 180l to form a patterned metal layer 178l' with openings 179l, as illustrated. Figure 15A As shown in the figure. In some embodiments, the dielectric component 134l-2 below the opening 179l of the metal layer 178l' is also etched to form a groove 135l in the core portion 128l-2 of the dielectric component 134l-2 during the etching process for patterning the metal layer. In some embodiments, the width of the groove 135l, measured at the top surface of the core portion 128l-2 of the dielectric component 134l-2, is smaller than the width of the core portion 128l-2 of the dielectric component 134l-2.

[0142] Subsequently, according to some embodiments, implementation Figure 2Y and Figure 2Z The process shown is used to form semiconductor structure 100l, such as Figure 15B As shown in the figure. According to some embodiments, because the core portion 128l-2 of the dielectric member 134l-2 has a groove 135l formed therein, the dielectric layer 190l formed above the metal layer 178l' has an extension portion 191l extending into the groove 135l of the dielectric member 134l-2. In some embodiments, the extension portion 191l of the dielectric layer 190l is surrounded by the core portion 128l-2. Furthermore, according to some embodiments, the bottom surface of the extension portion 191l of the dielectric layer 190l is lower than the top surface of the gate structure 168l, the top surfaces of the dielectric members 134l-1, 134l-2 and 134l-3, and the bottom surface of the metal layer 178l'. The processes and materials used to form dielectric components 134l-1, 134l-2 and 134l-3, metal layer 178l', photoresist structure 180l and dielectric layer 190l can be the same as those used to form dielectric components 134l-1, 134l-2 and 134l-3, metal layer 178', photoresist structure 180 and dielectric layer 190, and therefore will not be repeated here.

[0143] Figure 16A and Figure 16B A cross-sectional view of an intermediate stage of a semiconductor structure 100m shown along the Y direction in the fabrication channel region according to some embodiments is illustrated. According to some embodiments, the semiconductor structure 100m may be similar to the semiconductor structure 100, except that the dielectric components exposed by openings in the metal layer are partially removed. The materials and processes used to fabricate the semiconductor structure 100m may be similar to or the same as those described above for fabricating the semiconductor structure 100, and will not be repeated here.

[0144] More specifically, according to some embodiments, implementation Figures 2A to 2WThe process shown involves patterning a metal layer with an opening 188m through a photoresist structure 180m to form a patterned metal layer 178m' with an opening 179m, as illustrated. Figure 16A As shown in the figure. In some embodiments, the core portion 128m-2 of the dielectric component 134m-2 is partially exposed by an opening 179m in the metal layer 178m' and is also etched to form a groove 135m during an etching process for patterning the metal layer. In some embodiments, the opening 179m in the metal layer 178m' is wider than the groove 135m in the dielectric component 134m-2.

[0145] Subsequently, according to some embodiments, implementation Figure 2Y and Figure 2Z The process shown is used to form a semiconductor structure of 100m, such as Figure 16B As shown in the figure. According to some embodiments, because the core portion 128m-2 of the dielectric component 134m-2 has a groove 135m formed therein, the dielectric layer 190m formed above the metal layer 178m' has an extension portion 191m extending into the groove 135m above the dielectric component 134m-2. In some embodiments, the extension portion 191m of the dielectric layer 190m extends into the core portion 128m-2 and contacts the shell layer 126m-2. Furthermore, according to some embodiments, the bottom surface of the extension portion 191m of the dielectric layer 190m is lower than the top surface of the gate structure 168m, the top surfaces of the dielectric components 134m-1, 134m-2 and 134m-3, and the bottom surface of the metal layer 178m'. The processes and materials used to form dielectric components 134m-1, 134m-2 and 134m-3, metal layer 178m', photoresist structure 180m and dielectric layer 190m can be the same as those used to form dielectric components 134-1, 134-2 and 134-3, metal layer 178', photoresist structure 180 and dielectric layer 190, and therefore will not be repeated here.

[0146] Typically, depending on the design of a semiconductor device, it may be necessary to divide the gate structure into multiple portions using isolation components. However, if isolation components are formed through the gate structure to divide it, additional spacing may be required when forming the isolation components to prevent misalignment issues. In some embodiments, the spacing between dielectric components (e.g., dielectric components 134, 134-1, 134-2, 134-3, 134b-1 to 134m-1, 134b-2 to 134m-2, 134b-3 to 134m-3) and fin structures (e.g., fin structures 104-1, 104-2, and 104-3, which will form nanostructure 108') is self-aligned, and thus the distance between the fin structures can be reduced. Furthermore, a metal layer (e.g., metal layer 178') is formed and patterned over the dividing portions of the gate structure to connect some portions of the gate structure while other portions of the gate structure remain unconnected. Because the connection and disconnection of different regions of the gate structure are achieved through a patterned metal layer, and the patterning of the metal layer has a large coverage offset tolerance, the device size can be further reduced. Furthermore, the nanostructure can therefore have higher density and wider dimensions.

[0147] Furthermore, the dielectric component is made of a top portion (e.g., top portion 134T) and a bottom portion (134B), and the bottom portion and core portion (e.g., core portion 128) of the dielectric component can be made of a low-k dielectric material. Therefore, the capacitance (e.g., gate-to-source / drain structure) can be reduced (e.g., 3-5%), and the speed of the resulting device can be increased (e.g., 3-5%). Additionally, power efficiency can also be improved (e.g., 4-6%).

[0148] Furthermore, although the capping layer (e.g., capping layer 132) formed above the core portion and the shell layer (e.g., shell layer 126) surrounding the core portion can be made of a high-k dielectric material, these portions will be partially removed during the manufacturing process. Therefore, the dielectric components in the resulting device can still have a relatively low k value.

[0149] Furthermore, while voids may tend to form in thick high-k structures (e.g., thicker than 4 nm), the high-k portions in dielectric components are relatively thin, and the main parts of the dielectric component are the core and bottom portions. Additionally, an extra annealing process can be performed to prevent voids from forming during the formation of the core portion. Therefore, few or no voids will form in the dielectric component, and leakage paths caused by voids can be avoided. This improves the reliability of the resulting device.

[0150] It should be understood that the elements shown in semiconductor structures 100 and 100a to 100m can be combined and / or interchanged. For example, the semiconductor structure may include at least two dielectric components shown in semiconductor structures 100 and 100a to 100m.

[0151] Furthermore, it should be pointed out that, Figures 1 to 16B The same elements in the text can be represented by the same reference numerals, and can comprise the same or similar materials, and can be formed by the same or similar processes; therefore, for the sake of brevity, such redundant details have been omitted. Furthermore, although the method is described... Figures 1 to 16B However, it should be understood that Figures 1 to 16B The structure disclosed is not limited to this method, but can exist independently of the method as a separate structure. Similarly, Figures 1 to 16B The methods shown are not limited to the disclosed structures, but can exist independently of the structures. Furthermore, according to some embodiments, the above-described nanostructures may include nanowires, nanosheets, or other suitable nanostructures.

[0152] Similarly, while the disclosed methods are shown and described below as a series of steps or events, it should be understood that the order in which such steps or events are shown may be changed in some other embodiments. For example, in addition to those steps or events shown and / or described above, some steps may occur in a different order and / or simultaneously with other steps or events. Furthermore, it may not be necessary to implement all the steps shown above to implement one or more aspects or embodiments described above. Moreover, one or more steps described above may be performed in one or more separate steps and / or stages.

[0153] Furthermore, the terms “approximately,” “basically,” “essentially,” and “about” described above take into account minor variations and can vary across different technologies, and are within the range of deviations understood by those skilled in the art. For example, when used in conjunction with an event or situation, the terms can refer to a situation where the event or situation occurred precisely or a situation where the event or situation was very close to occurring.

[0154] Embodiments for forming semiconductor structures can be provided. The semiconductor structure may include a gate structure encapsulating a nanostructure. Furthermore, dielectric components may be formed to divide the gate structure into multiple portions. The dielectric components may include a bottom portion and a top portion above the bottom portion, and the top portion may include a shell and a core portion above the shell. The formation of the dielectric components can help improve the performance of the semiconductor structure, such as speed and power efficiency, and can improve reliability.

[0155] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate and a first nanostructure and a second nanostructure formed on the substrate. The semiconductor structure also includes a gate structure comprising a first portion enclosing the first nanostructure and a second portion enclosing the second nanostructure. The semiconductor structure also includes a dielectric member sandwiched between the first and second portions of the gate structure. Furthermore, the dielectric member includes a bottom portion and a top portion located above the bottom portion, and the top portion of the dielectric member includes a shell and a core portion surrounded by the shell.

[0156] In some embodiments, the top surface of the core portion of the top portion of the dielectric member is lower than the top surface of the gate structure. In some embodiments, the top surface of the gate structure is lower than the top surface of the top portion of the dielectric member. In some embodiments, the semiconductor structure further includes: a metal layer formed over the gate structure; and a dielectric layer formed over the metal layer, wherein a portion of the dielectric layer extends through the metal layer. In some embodiments, the dielectric layer is in direct contact with the top portion of the dielectric member. In some embodiments, the dielectric layer is in direct contact with the top surface of the gate structure.

[0157] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate and a nanostructure formed on the substrate. The semiconductor structure also includes a gate structure enclosing the nanostructure and a first dielectric component separating the gate structure into a first portion and a second portion. Furthermore, the first dielectric component includes a bottom portion and a top portion located above the bottom portion. Additionally, the top portion of the first dielectric component includes a shell made of a first dielectric material and a core portion made of a second dielectric material, wherein the dielectric constant of the first dielectric material is higher than that of the second dielectric material.

[0158] In some embodiments, the semiconductor structure further includes: a metal layer formed over the gate structure; and a dielectric layer covering the top surface of the metal layer and extending into the metal layer. In some embodiments, the metal layer continuously covers the first portion of the gate structure and the top portion of the first dielectric component. In some embodiments, the top surface of the first dielectric component is partially covered by the dielectric layer and partially covered by the metal layer. In some embodiments, the metal layer includes a first portion located over the first portion of the gate structure and a second portion located over the second portion of the gate structure, and the first portion and the second portion of the metal layer are separated by the dielectric layer. In some embodiments, the semiconductor structure further includes: a source / drain structure connected to the nanostructure, wherein the source / drain structure is in direct contact with the bottom portion of the first dielectric component. In some embodiments, the semiconductor structure further includes: a second dielectric component separating a first portion of the gate structure from a third portion; a metal layer formed over the gate structure; and a dielectric layer covering the top surface of the metal layer, wherein the source / drain structure is in direct contact with the first dielectric component and the second dielectric component, and the dielectric layer is in direct contact with the first dielectric component but is separated from the second dielectric component by the metal layer.

[0159] In some embodiments, a method for manufacturing a semiconductor structure is provided. The method for manufacturing a semiconductor structure includes forming a fin structure protruding from a substrate. Furthermore, the fin structure includes alternately stacked first and second semiconductor material layers. The method for manufacturing a semiconductor structure also includes forming an isolation structure surrounding the fin structure and forming a dielectric component over the isolation structure. The step of forming the dielectric component over the isolation structure includes forming a bottom portion of the dielectric component over the isolation structure and forming a shell layer over the bottom portion of the dielectric component. The step of forming the dielectric component over the isolation structure further includes forming a core portion surrounded by the shell layer over the shell layer and recessing the shell layer and the core portion to form a groove. The step of forming the dielectric component over the isolation structure further includes forming a capping layer in the groove. The method for manufacturing a semiconductor structure also includes removing a first semiconductor material layer of the fin structure to form a nanostructure having a second semiconductor material layer and forming a gate structure encapsulating the nanostructure.

[0160] In some embodiments, the first dielectric component is inserted into the gate structure. In some embodiments, the method of manufacturing a semiconductor structure further includes: removing a top portion of the gate structure and the cover layer of the dielectric component; forming a metal layer over the gate structure and the dielectric component; patterning the metal layer to form an opening in the metal layer; and forming a dielectric layer over the metal layer and in the opening in the metal layer. In some embodiments, a portion of the dielectric component and a portion of the gate structure are exposed by the opening in the metal layer. In some embodiments, the dielectric component is partially exposed by the opening in the metal layer and partially covered by the metal layer. In some embodiments, the method of manufacturing a semiconductor structure further includes: recessing the core portion of the dielectric component to form a groove before forming the dielectric layer over the metal layer. In some embodiments, the bottom portion of the groove is lower than the top surface of the gate structure.

[0161] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor structure, comprising: Substrate; A first nanostructure and a second nanostructure are formed on the substrate; A gate structure, comprising a first portion encapsulating the first nanostructure and a second portion encapsulating the second nanostructure; as well as A dielectric component, sandwiched between the first portion and the second portion of the gate structure, wherein the dielectric component comprises: The bottom part; and The top portion, located above the bottom portion, includes a shell on the bottom portion and a core portion located on and surrounded by the shell.

2. The semiconductor structure according to claim 1, wherein, The top surface of the core portion of the top portion of the dielectric component is lower than the top surface of the gate structure.

3. The semiconductor structure according to claim 1, wherein, The top surface of the gate structure is lower than the top surface of the top portion of the dielectric component.

4. The semiconductor structure according to claim 1, further comprising: A metal layer is formed above the gate structure; as well as A dielectric layer is formed over the metal layer, wherein a portion of the dielectric layer extends through the metal layer.

5. The semiconductor structure according to claim 4, wherein, The dielectric layer is in direct contact with the top portion of the dielectric component.

6. The semiconductor structure according to claim 4, wherein, The dielectric layer is in direct contact with the top surface of the gate structure.

7. A semiconductor structure comprising: Substrate; Nanostructures are formed on the substrate; A gate structure encapsulates the nanostructure. as well as A first dielectric component divides the gate structure into a first portion and a second portion, wherein the first dielectric component includes: The bottom part; and The top portion, located above the bottom portion, includes a shell made of a first dielectric material and a core portion made of a second dielectric material, wherein the shell is located on the bottom portion, the core portion is located on the shell and surrounded by the shell, and the dielectric constant of the first dielectric material is higher than that of the second dielectric material.

8. The semiconductor structure according to claim 7, further comprising: A metal layer is formed above the gate structure; as well as A dielectric layer that covers the top surface of the metal layer and extends into the metal layer.

9. The semiconductor structure according to claim 8, wherein, The metal layer continuously covers the first portion of the gate structure and the top portion of the first dielectric component.

10. The semiconductor structure according to claim 8, wherein, The top surface of the first dielectric component is partially covered by the dielectric layer and partially covered by the metal layer.

11. The semiconductor structure according to claim 8, wherein, The metal layer includes a first portion located above a first portion of the gate structure and a second portion located above a second portion of the gate structure, and the first portion and the second portion of the metal layer are separated by the dielectric layer.

12. The semiconductor structure according to claim 7, further comprising: Source / drain structure, connected to the nanostructure, The source / drain structure is in direct contact with the bottom portion of the first dielectric component.

13. The semiconductor structure according to claim 12, further comprising: The second dielectric component separates the first portion and the third portion of the gate structure; A metal layer is formed above the gate structure; as well as A dielectric layer covering the top surface of the metal layer. The source / drain structure is in direct contact with the first dielectric component and the second dielectric component, and the dielectric layer is in direct contact with the first dielectric component but is separated from the second dielectric component by the metal layer.

14. A method for manufacturing a semiconductor structure, comprising: A fin structure protruding from a substrate is formed, wherein the fin structure comprises alternating stacked first and second semiconductor material layers; An isolation structure is formed around the fin structure; A dielectric component is formed above the isolation structure, including: The bottom portion of the dielectric component is formed above the isolation structure; A shell is formed above the bottom portion of the dielectric component; A core portion, surrounded by the shell, is formed above the shell layer; The shell and the core portion are recessed to form a groove; and A covering layer is formed in the groove; Removing the first semiconductor material layer of the fin structure to form a nanostructure having the second semiconductor material layer; and A gate structure is formed that encapsulates the nanostructure.

15. The method for manufacturing a semiconductor structure according to claim 14, wherein, The dielectric component is inserted into the gate structure.

16. The method for manufacturing a semiconductor structure according to claim 14, further comprising: Remove the top portion of the gate structure and the cover layer of the dielectric component; A metal layer is formed over the gate structure and the dielectric component; The metal layer is patterned to form openings in the metal layer; as well as A dielectric layer is formed over the metal layer and in the opening of the metal layer.

17. The method for manufacturing a semiconductor structure according to claim 16, wherein, A portion of the dielectric component and a portion of the gate structure are exposed by the opening in the metal layer.

18. The method for manufacturing a semiconductor structure according to claim 16, wherein, The dielectric component is partially exposed by the opening in the metal layer and partially covered by the metal layer.

19. The method for manufacturing a semiconductor structure according to claim 16, further comprising: Before forming the dielectric layer over the metal layer, the core portion of the dielectric component is recessed to form a groove.

20. The method for manufacturing a semiconductor structure according to claim 19, wherein, The bottom portion of the groove is lower than the top surface of the gate structure.

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