Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The application provides a semiconductor structure preparation method and a semiconductor structure, and relates to the technical field of semiconductors. The semiconductor structure preparation method comprises the following steps: providing a substrate; forming a plurality of bit line structures on the substrate, the plurality of bit line structures are parallel to each other and extend along a first direction, and a groove is formed between adjacent bit line structures; forming a first conductive layer in the groove, the first conductive layer has a gap therein; removing part of the first conductive layer to form a first recess, and the gap is exposed at the bottom of the first recess; forming an epitaxial layer on the inner wall of the first recess; and performing epitaxial growth on the epitaxial layer to form an extension, and the extension fills the gap. The epitaxial layer is formed on the inner wall of the first recess, and the extension is formed by epitaxial growth of the epitaxial layer, so that the gap in the conductive structure can be filled, the compactness of the conductive structure is improved, the resistance of the conductive structure is reduced, and the conductivity of the conductive structure and the performance of the semiconductor structure are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure thereof. Background Technology

[0002] Dynamic random access memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data and is widely used in data storage devices or apparatuses.

[0003] In related technologies, dynamic random access memory (DRAM) consists of many repeating memory cells. Each memory cell typically includes a capacitor structure and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor structure. A conductive plunger is disposed on the substrate, and one end of the conductive plunger is connected to the drain to read data information stored in the capacitor structure through the bit line, or to write data information into the capacitor structure for storage through the bit line.

[0004] However, during the formation of the conductive plunger, voids can easily form inside the conductive plunger. These voids increase the resistance of the conductive plunger and reduce the performance of the semiconductor structure. Summary of the Invention

[0005] In view of the above problems, embodiments of the present invention provide a method for preparing a semiconductor structure and a semiconductor structure, which are used to reduce the resistance of the conductive plunger and improve the performance of the semiconductor structure.

[0006] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0007] A first aspect of this invention provides a method for fabricating a semiconductor structure, comprising:

[0008] A substrate is provided, the substrate comprising a plurality of active regions;

[0009] Multiple bit line structures are formed at intervals on the substrate, the multiple bit line structures are parallel to each other and extend along a first direction, and a groove is formed between adjacent bit line structures.

[0010] A first conductive layer is formed in the trench, and the first conductive layer has voids.

[0011] The portion of the first conductive layer located within the trench is removed, and the remaining first conductive layer forms a conductive structure. The conductive structure and the bit line structure form a first groove, and the bottom of the first groove exposes the void.

[0012] An epitaxial layer is formed on the inner wall of the first groove;

[0013] The epitaxial layer is epitaxially grown to form an extension, which fills the void.

[0014] The method for fabricating a semiconductor structure as described above, wherein the step of forming an epitaxial layer on the inner wall of the first groove includes:

[0015] An epitaxial layer is formed on the inner wall of the first groove using a low-pressure vapor deposition process. The epitaxial layer covers the top surface of the bit line structure. Both the epitaxial layer and the first conductive layer are made of polycrystalline silicon.

[0016] In the semiconductor structure fabrication method described above, the thickness of the epitaxial layer is between 1 and 5 nm.

[0017] The semiconductor structure fabrication method described above, wherein the epitaxial growth step of the epitaxial layer includes:

[0018] The epitaxial growth reaction temperature is 400–600°C, and the epitaxial growth reaction gas is at least one of SiCl4, SiHCl3, SiH4, and SiH2Cl2.

[0019] The semiconductor structure fabrication method described above, wherein, before the step of forming an epitaxial layer on the inner wall of the first trench, and after the step of removing a portion of the first conductive layer located within the trench, the fabrication method further includes:

[0020] Chlorine or hydrogen gas is introduced into the first groove to pretreat the top surface of the conductive structure.

[0021] In the semiconductor structure fabrication method described above, the ratio of the depth of the first groove to the depth of the trench is 1:5 to 1:3.

[0022] The method for fabricating a semiconductor structure as described above, wherein the step of forming a plurality of spaced bit line structures on the substrate includes:

[0023] Bit lines are formed on the substrate, and intermediate trenches are formed between adjacent bit lines;

[0024] Isolation sidewalls are formed on the sides of the bit line facing the intermediate trench. The isolation sidewalls include a first dielectric layer, a second dielectric layer and a third dielectric layer stacked in sequence. The first dielectric layer contacts the side of the intermediate trench, and the third dielectric layer covers the bottom wall of the intermediate trench and the top surface of the bit line. The third dielectric layers located in the same intermediate trench form the trench.

[0025] The semiconductor structure fabrication method described above, wherein after the step of forming isolation sidewalls on the sides of the bit lines facing the intermediate trench and before the step of forming a first conductive layer in the trench, the fabrication method further includes;

[0026] The third dielectric layer located on the bottom wall of the trench is removed, exposing the active region within the trench;

[0027] The portion of the active area exposed within the trench is removed to form a receiving groove within the active area, and the first conductive layer fills the receiving groove.

[0028] The method for fabricating a semiconductor structure as described above, wherein the step of removing a portion of the active region exposed within the trench to form a receiving trench within the active region includes:

[0029] The active region exposed within the trench is removed by dry etching, wherein the etching gas used in the dry etching is at least one of SF6, NF3, and Cl2, the etching pressure of the dry etching is 5 mTorr to 100 mTorr, and the radio frequency power of the dry etching is 200 W to 1000 W.

[0030] The semiconductor structure fabrication method described above, wherein after the step of removing a portion of the first conductive layer located within the trench and before the step of forming an epitaxial layer on the inner wall of the first trench, the fabrication method further includes:

[0031] The third dielectric layer located on the top surface of the bit line and on the side wall of the first groove is removed, and the top surface of the remaining third dielectric layer is flush with the top surface of the conductive structure.

[0032] In the semiconductor structure fabrication method described above, the bit line includes a second conductive layer, a barrier layer, a third conductive layer, and an insulating layer stacked sequentially.

[0033] The semiconductor structure fabrication method described above, wherein after the step of epitaxial growth of the epitaxial layer to form the extension, the fabrication method further includes:

[0034] A filling layer is formed in the first groove, the filling layer fills the first groove and covers the top surface of the bit line structure;

[0035] A plurality of etched grooves are formed at intervals within the filler layer, and the extending direction of the etched grooves is perpendicular to the first direction.

[0036] The filler layer and the conductive structure exposed in the etched groove are removed, the remaining conductive structure forms a conductive plunger, and the area of ​​the removed filler layer and the conductive structure forms a second groove, the second groove exposing the substrate;

[0037] A fourth dielectric layer is formed within the second groove, and the fourth dielectric layer fills the second groove.

[0038] After removing the filler layer, the conductive plunger and the fourth dielectric layer form a third groove.

[0039] The semiconductor structure fabrication method described above, wherein after the step of removing the filling layer, the fabrication method further includes:

[0040] A pad is formed in the third groove. One end of the pad is connected to the conductive plunger, and the other end of the pad is used to connect to a capacitor.

[0041] In the semiconductor structure fabrication method described above, the filling layer is made of silicon oxide.

[0042] A second aspect of the present invention provides a semiconductor structure, which is obtained by the semiconductor structure preparation method described above.

[0043] In the semiconductor structure preparation method and semiconductor structure provided in the embodiments of the present invention, an epitaxial layer is formed on the inner wall of the first groove, and an extension is formed by epitaxial growth using the epitaxial layer. The extension can fill the gaps in the conductive structure, improve the compactness of the conductive structure, thereby reducing the resistance of the conductive structure and improving the conductivity of the conductive structure and the performance of the semiconductor structure.

[0044] In addition to the technical problems solved by the embodiments of the present invention, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, the semiconductor structure preparation method and semiconductor structure provided by the embodiments of the present invention, other technical problems that can be solved by the semiconductor structure, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific embodiments. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of the structure that forms the bit line structure in related technologies;

[0047] Figure 2 This is a schematic diagram of the structure that forms the sacrificial layer in related technologies;

[0048] Figure 3 This is a schematic diagram of the structure used to form etched holes in related technologies;

[0049] Figure 4 This is a schematic diagram of the structure in which a silicon nitride layer is formed in related technologies;

[0050] Figure 5 This is a schematic diagram of the structure forming a contact hole in related technologies;

[0051] Figure 6 A process flow diagram of the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0052] Figure 7 This is a schematic diagram of the structure forming bit lines in the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0053] Figure 8 This is a schematic diagram of the bit line structure formation process in the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0054] Figure 9 This is a schematic diagram of the structure forming the receiving groove in the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0055] Figure 10 A schematic diagram of the structure for forming the first conductive layer in the semiconductor structure fabrication method provided in this embodiment of the invention. Figure 1 ;

[0056] Figure 11 A schematic diagram of the structure for forming the first conductive layer in the semiconductor structure fabrication method provided in this embodiment of the invention. Figure 2 ;

[0057] Figure 12 A schematic diagram of the semiconductor structure fabrication method provided in this embodiment of the invention, showing the formation of the first groove and the conductive structure. Figure 1 ;

[0058] Figure 13 A schematic diagram of the semiconductor structure fabrication method provided in this embodiment of the invention, showing the formation of the first groove and the conductive structure. Figure 2 ;

[0059] Figure 14 This is a schematic diagram of the semiconductor structure fabrication method provided in the embodiments of the present invention, in which part of the third dielectric layer is removed;

[0060] Figure 15 This is a schematic diagram of the structure forming the epitaxial layer in the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0061] Figure 16 A schematic diagram of the structure forming the filling layer in the semiconductor structure fabrication method provided in this embodiment of the invention. Figure 1 ;

[0062] Figure 17 A schematic diagram of the structure forming the filling layer in the semiconductor structure fabrication method provided in this embodiment of the invention. Figure 2 ;

[0063] Figure 18 This is a schematic diagram of the structure forming the etching groove in the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0064] Figure 19 This is a schematic diagram of the structure for forming the second groove in the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0065] Figure 20 This is a schematic diagram of the structure forming the fourth dielectric layer in the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0066] Figure 21 This is a schematic diagram of the structure forming the third groove in the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0067] Figure 22 This is a schematic diagram of the structure for forming pads in the semiconductor structure fabrication method provided in an embodiment of the present invention.

[0068] Figure label:

[0069] 10: Substrate; 11: Active region;

[0070] 12: Isolation structure; 13: Receiving groove;

[0071] 20: Bitline structure; 21: Bitline;

[0072] 211: Second conductive layer; 212: Barrier layer;

[0073] 213: Third conductive layer; 214: Insulating layer;

[0074] 22: Intermediate trench; 23: Isolation sidewall;

[0075] 231: First dielectric layer; 232: Second dielectric layer;

[0076] 233: Third dielectric layer; 30: Trench;

[0077] 40: First conductive layer; 41: Void;

[0078] 42: Conductive structure; 421: Conductive plunger;

[0079] 50: First groove; 60: Epitaxial layer;

[0080] 70: Filler layer; 71: Etched groove;

[0081] 80: Second groove; 90: Fourth dielectric layer;

[0082] 100: Third groove; 110: Solder pad;

[0083] 120: Sacrificial layer; 121: Etched via;

[0084] 130: Silicon nitride layer; 140: Contact hole. Detailed Implementation

[0085] like Figures 1 to 5 As shown, when forming a conductive plunger, it is usually necessary to first form a plurality of spaced bit line structures 20 on the substrate 10, and form a sacrificial layer 120 between adjacent bit line structures 20. Then, the sacrificial layer 120 is patterned to form a plurality of spaced etch holes 121 in the sacrificial layer 120, and the length direction of each etch hole 121 is perpendicular to the extension direction of the bit line structure 20.

[0086] After the etched hole 121 is formed, a silicon nitride layer 130 is formed in the etched hole 121 using a deposition process. Then, the sacrificial layer 120 is removed, and a contact hole 140 is formed in the area where the sacrificial layer 120 is located. After that, the silicon nitride layer on the bottom wall of the contact hole 140 is removed so that part of the active region of the contact hole 140 is exposed. Finally, a conductive plunger is formed in the contact hole 140 to realize the electrical connection between the conductive plunger and the drain of the active region. However, in the process of forming the conductive plunger, since the conductive plunger is formed in the contact hole 140, the opening area of ​​the contact hole 140 is small and the depth is deep, which makes it easy to form voids when forming the conductive plunger. These voids will increase the resistance of the conductive plunger and reduce the performance of the semiconductor structure.

[0087] To address the aforementioned technical problems, embodiments of the present invention provide a method for fabricating a semiconductor structure and a semiconductor structure. By forming an epitaxial layer on the inner wall of a first groove and using the epitaxial layer for epitaxial growth to form an extension, the extension can fill the gaps in the conductive structure, thereby improving the compactness of the conductive structure, reducing the resistance of the conductive structure, and thus improving the performance of the semiconductor structure.

[0088] To make the above-mentioned objectives, features, and advantages of the embodiments of the present invention more apparent and understandable, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0089] Figure 6 This is a flowchart of a method for fabricating a semiconductor structure provided in an embodiment of the present invention. Figures 7-22 The diagram below illustrates the various stages of semiconductor structure fabrication. Figures 6-22 The methods for fabricating semiconductor structures are described in detail.

[0090] Step S100: Provide a substrate, the substrate including a plurality of active regions. For example, such as... Figure 7 and Figure 8 As shown, the substrate 10 serves as a support component for the memory, supporting other components disposed thereon. The substrate 10 may be made of a semiconductor material, which may be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds.

[0091] The substrate 10 has a plurality of active regions 11 and an isolation structure 12 for separating each active region 11. When forming the isolation structure 12, an isolation trench can be formed in the substrate first, and then an insulating material can be deposited into the isolation trench. The insulating material constitutes the isolation structure 12.

[0092] Step S200: A plurality of bit line structures are formed on the substrate at intervals, the plurality of bit line structures are parallel to each other and extend along a first direction, and a groove is formed between adjacent bit line structures.

[0093] It should be noted that the first direction can be... Figure 1 and Figure 7 The Y direction is the direction perpendicular to the plane of the paper and pointing inwards.

[0094] For example, continue to refer to Figure 7 First, a plurality of spaced bit lines 21 are formed on the substrate 10, and an intermediate trench 22 is formed between adjacent bit lines 21. Each bit line 21 includes a second conductive layer 211, a barrier layer 212, a third conductive layer 213 and an insulating layer 214 stacked in sequence, wherein the second conductive layer 211 is disposed on the substrate 10.

[0095] In this embodiment, the material of the second conductive layer 211 may include conductive materials such as polycrystalline silicon, the material of the barrier layer 212 may include conductive materials such as silicon nitride, the material of the third conductive layer 213 may include conductive materials such as tungsten, and the material of the insulating layer 214 may include insulating materials such as silicon nitride.

[0096] Secondly, such as Figure 8 As shown, after the bit line 21 is formed, isolation sidewalls 23 are formed on the surface of the bit line 21 facing the intermediate trench 22, that is, with Figure 8 Taking the orientation shown as an example, isolation sidewalls 23 are formed on the left and right sides of the position line 21. The position line 21 and the isolation sidewalls 23 set on the position line 21 constitute the position line structure 20. The isolation sidewalls 23 form a groove 30 in the same intermediate groove 22.

[0097] It should be noted that the formation process and structure of the bitline structure in this embodiment are similar to those in related technologies, and specific figures can also be found in the diagrams. Figure 1 .

[0098] In this embodiment, the isolation sidewall 23 may include a first medium layer 231, a second medium layer 232 and a third medium layer 233 stacked sequentially. The first medium layer 231 contacts the sidewall of the intermediate trench 22, the second medium layer 232 covers the first medium layer 231, and the third medium layer 233 covers the bottom wall of the intermediate trench 22 and the top surface of the position line 21. The third medium layer 233 located in the same intermediate trench 22 forms a trench 30.

[0099] For example, an atomic layer deposition process can be used to form a silicon nitride layer on the inner wall of the intermediate trench 22. The silicon nitride layer extends to the outside of the intermediate trench 22 and covers the top surface of the bit line 21. Then, an etching solution or etching gas is used to remove the silicon nitride layer located on the bottom wall of the intermediate trench 22 and the top surface of the bit line 21, leaving the silicon nitride layer located on the side wall of the intermediate trench 22 to form the first dielectric layer 231.

[0100] Then, an atomic layer deposition process is used to form a silicon oxide layer on the sidewall of the first dielectric layer 231 and the bottom wall of the intermediate trench 22. The silicon oxide layer on the bottom wall of the intermediate trench 22 is removed by an etching solution or etching gas, while the silicon oxide layer on the sidewall of the first dielectric layer 231 is retained to form the second dielectric layer 232.

[0101] Subsequently, an atomic layer deposition process is used to form a silicon nitride layer on the sidewall of the second dielectric layer 232 and the bottom wall of the intermediate trench 22. The silicon nitride layer extends to the outside of the intermediate trench 22 and covers the top surface of the bit line 21. The silicon nitride layer constitutes the third dielectric layer 233, wherein the third dielectric layer 233 located in the same intermediate trench 22 forms a trench 30.

[0102] After the isolation sidewall structure is formed, such as Figure 9 As shown, the method for fabricating a semiconductor structure further includes: removing the third dielectric layer 233 on the bottom wall of the trench 30 using an etching solution or etching gas, so that the active region 11 is exposed in the trench 30. After the active region 11 is exposed, the portion of the active region 11 exposed in each trench 30 can be further removed to form a receiving trench 13 in the active region 11.

[0103] For example, when forming the receiving trench 13, a portion of the active region 11 exposed in the trench 30 can be removed by dry etching, wherein the etching gas for dry etching is at least one of SF6, NF3 and Cl2, the etching pressure for dry etching is 5 mTorr to 100 mTorr, and the radio frequency power for dry etching is 200 W to 1000 W.

[0104] Step S300: A first conductive layer is formed in the trench, and the first conductive layer has voids.

[0105] like Figure 10 As shown, a first conductive layer 40 is formed in the trench 30 by physical vapor deposition or chemical vapor deposition. The first conductive layer 40 extends outside the trench and covers the top surface of the bit line structure 20. The first conductive layer 40 is filled in the receiving groove 13, that is, the end of the first conductive layer 40 near the substrate 10 is filled in the receiving groove 13.

[0106] Typically, the trench 30 has a high aspect ratio, and during the deposition of the first conductive layer 40, voids 41 are easily formed within the first conductive layer 40, wherein the diameter of the voids 41 is approximately 0 to 1.5 nm.

[0107] In this embodiment, by forming a receiving groove in the active region, when the first conductive layer is deposited in the groove, the first conductive layer can fill the receiving groove to increase the contact area between the first conductive layer and the active region, thereby improving the conductivity between the first conductive layer and the active region.

[0108] It should be noted that after the first conductive layer is formed, chemical mechanical polishing (CMP) can be used to flatten the top surface of the first conductive layer, thus improving its structure. Figure 11 As shown.

[0109] Step S400: Remove part of the first conductive layer located in the trench, the remaining first conductive layer forms a conductive structure, the conductive structure and the bit line structure form a first groove, and the bottom of the first groove exposes a gap.

[0110] For example, a first photoresist layer (not shown in the figure) can be formed on a first conductive layer by a coating process, and then the first photoresist layer can be patterned by an exposure, development or etching process, so that the first photoresist layer forms a plurality of spaced first protrusions and a first opening located between adjacent first protrusions. The extension direction of the first protrusions is the same as the extension direction of the bit line structure, and the first protrusions are used to block the bit line structure.

[0111] Then, as Figure 12 and Figure 13 As shown, an etching solution or etching gas is used to remove the first conductive layer 40 exposed in the first opening 51. The removed first conductive layer 40 includes the first conductive layer 40 located on the top surface of the bit line structure 20 and a portion of the first conductive layer 40 located in the trench 30. The retained first conductive layer 40 constitutes the conductive structure 42.

[0112] The conductive structure 42 and the bit line structure 20 form a first groove 50, and the bottom of the first groove 50 exposes a gap 41. The ratio of the depth of the first groove 50 to the depth of the trench 30 is between 1:5 and 1:3.

[0113] If the ratio of the depth of the first groove 50 to the depth of the trench 30 is less than 1:5, the depth of the first groove will be too small, making it difficult to expose the gaps and fill them. If the ratio of the depth of the first groove 50 to the depth of the trench 30 is greater than 1:3, the height of the conductive structure will be reduced, thereby reducing the conductivity of the conductive structure. Therefore, in this embodiment, by making the ratio of the depth of the first groove to the depth of the trench between 1:5 and 1:3, the conductivity of the conductive structure can be guaranteed, and the gaps can be exposed so that subsequent processes can fill the gaps and reduce the resistance of the conductive structure.

[0114] like Figure 14 As shown, after the conductive structure 42 is formed, the third dielectric layer 233 located on the top surface of the bit line and on the side wall of the first groove 50 can be removed, and the top surface of the retained third dielectric layer 233 is flush with the top surface of the conductive structure 42.

[0115] For example, etching gas can be used to remove the third dielectric layer 233 located on the top surface of the bit line and on the sidewall of the first groove 50, thereby increasing the area of ​​the first groove 50, so as to increase the area of ​​the subsequent pads in the first groove, thereby improving the performance of the semiconductor structure.

[0116] In this embodiment, the etching gas may include CH3F or H2.

[0117] Step 500: An epitaxial layer is formed on the inner wall of the first groove.

[0118] like Figure 15As shown, by way of example, an epitaxial layer 60 is formed on the inner wall of the first groove 50 using a low-pressure vapor deposition process. The epitaxial layer 60 covers the top surface of the bit line structure 20. That is, the epitaxial layer 60 can cover the top surface of the bit line and the second dielectric layer 232. The epitaxial layer 60 and the first conductive layer 40 are both made of polycrystalline silicon.

[0119] This embodiment also limits the thickness of the epitaxial layer. For example, the thickness of the epitaxial layer 60 is between 1 and 5 nm, so that the epitaxial layer is directly oxidized to form silicon oxide during the subsequent deposition of the filling layer. This avoids the need for additional processes to remove the epitaxial layer and simplifies the semiconductor structure fabrication process.

[0120] It should be noted that, prior to the step of forming the epitaxial layer on the inner wall of the first trench, and after the step of removing a portion of the first conductive layer located within the trench, the semiconductor structure fabrication method further includes:

[0121] Chlorine or hydrogen gas is introduced into the first groove 50 to pre-treat the top surface of the conductive structure 42, thereby removing impurities located in the first groove 50 and improving the growth interface of the epitaxial layer 60 to facilitate the growth of the epitaxial layer.

[0122] Step S600: The epitaxial layer is epitaxially grown to form an extension, which fills the gaps.

[0123] In this embodiment, the reaction temperature in the reaction chamber needs to be controlled to be between 400°C and 600°C to provide the reaction temperature for the growth of the epitaxial layer. After the reaction temperature in the reaction chamber reaches the above requirements, hydrogen (H2) is used to carry the reaction gas into the reaction chamber. The reaction gas is at least one of silicon tetrachloride (SiCl4), trichlorosilane (SiHCl3), silane (SiH4), and dichlorosilane (SiH2Cl2). The above-mentioned reaction gas and the epitaxial layer are reduced or thermally decomposed under high temperature conditions to form silicon atoms. The silicon atoms grow in the gaps to form extensions.

[0124] In this embodiment, the extension fills the gaps, making the conductive structure dense, thereby reducing the resistance of the conductive structure and improving the conductivity of the conductive structure and the performance of the semiconductor structure.

[0125] After the extension is formed, the semiconductor structure fabrication method also includes the following steps:

[0126] First, such as Figure 16 and Figure 17As shown, a filling layer 70 is formed in the first groove 50, filling the first groove 50 and covering the top surface of the bit line structure 20. The filling layer 70 is made of insulating materials such as silicon oxide. In this way, during the formation of the filling layer, the epitaxial layers located on the sidewalls of the first groove and on the top surface of the bit line structure can directly form silicon oxide in a high-temperature environment, so that the silicon oxide is bonded to the filling layer. This avoids the need for additional processes to remove the epitaxial layers located on the sidewalls of the first groove and on the top surface of the bit line structure, thus simplifying the semiconductor structure fabrication process.

[0127] Next, a second photoresist layer (not shown in the figure) is formed on the filler layer 70, and the second photoresist layer is patterned to form spaced-apart second openings on the photoresist layer. The filler layer 70 exposed in the second openings is removed using an etching solution or etching gas to form a plurality of spaced-apart etching grooves 71 in the filler layer 70, the structure of which is as follows. Figure 18 As shown, the extension direction of the etched groove 71 is perpendicular to the first direction, that is, the length direction of the etched groove 71 is the X direction.

[0128] Then, as Figure 19 As shown, the filling layer 70 and conductive structure 42 exposed in the etched groove 71 are removed, and the remaining conductive structure forms a conductive plunger 421. The area where the filling layer 70 and conductive structure 42 were removed forms a second groove 80, and the second groove 80 exposes the substrate 10.

[0129] After that, as Figure 20 As shown, a fourth dielectric layer 90 is formed in the second groove 80 using a deposition process. The fourth dielectric layer 90 fills the second groove 80. The fourth dielectric layer may include insulating materials such as silicon nitride.

[0130] Finally, as Figure 21 As shown, the remaining filler layer 70 is removed by a cleaning process, and the conductive plunger 421 and the fourth dielectric layer 90 form a third groove 100.

[0131] It should be noted that after the step of removing the filler layer, the semiconductor structure fabrication method also includes:

[0132] like Figure 22 As shown, a pad 110 is formed in the third groove 100. One end of the pad 110 is connected to the conductive plunger 421, and the other end of the pad 110 is used to connect to the capacitor.

[0133] This embodiment first forms bit line structures on a substrate, deposits conductive structures within trenches formed by adjacent bit line structures, and finally etches the conductive structures to form multiple conductive plungers through multiple etching processes. Compared to the prior art, which first forms a sacrificial layer between bit line structures, then forms multiple spaced etching holes in the sacrificial layer, fills the etching holes with a silicon nitride layer, removes the filling layer to form multiple contact holes on the substrate, and finally forms conductive plungers within the contact holes, the trench volume is larger than the contact hole volume, making it easier to deposit conductive structures within the trench. This results in smaller gaps in the conductive structures compared to the gaps in the conductive plungers formed within the contact holes. Subsequent epitaxial growth fills these gaps, resulting in seamless and dense conductive plungers, thereby improving the performance of the semiconductor structure. Furthermore, the method for forming conductive plungers in this embodiment is simpler, simplifying the semiconductor structure manufacturing process.

[0134] This invention also provides a semiconductor structure, which is obtained by the semiconductor structure preparation method described in any of the above embodiments.

[0135] The semiconductor structure provided in this embodiment is prepared by the method described in the above embodiment. Therefore, voids in the conductive structure of the semiconductor structure can be avoided, thereby improving the compactness of the conductive structure, reducing the resistance of the conductive structure, and improving the conductivity of the conductive structure and the performance of the semiconductor structure.

[0136] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0137] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of the present invention.

[0138] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0139] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The steps include the following: A substrate is provided, the substrate comprising a plurality of active regions; Multiple bit line structures are formed at intervals on the substrate, the multiple bit line structures are parallel to each other and extend along a first direction, and a groove is formed between adjacent bit line structures. A first conductive layer is formed in the trench, and the first conductive layer has voids. The portion of the first conductive layer located within the trench is removed, and the remaining first conductive layer forms a conductive structure. The conductive structure and the bit line structure form a first groove, and the bottom of the first groove exposes the void. An epitaxial layer is formed on the inner wall of the first groove; The epitaxial layer is epitaxially grown to form an extension, which fills the void; A filling layer is formed in the first groove, the filling layer fills the first groove and covers the top surface of the bit line structure; A plurality of etched grooves are formed at intervals within the filler layer, and the extending direction of the etched grooves is perpendicular to the first direction. The filler layer and the conductive structure exposed in the etched groove are removed, the remaining conductive structure forms a conductive plunger, and the area of ​​the removed filler layer and the conductive structure forms a second groove, the second groove exposing the substrate; A fourth dielectric layer is formed within the second groove, and the fourth dielectric layer fills the second groove. After removing the filler layer, the conductive plunger and the fourth dielectric layer form a third groove.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of forming an epitaxial layer on the inner wall of the first groove includes: An epitaxial layer is formed on the inner wall of the first groove using a low-pressure vapor deposition process. The epitaxial layer covers the top surface of the bit line structure. Both the epitaxial layer and the first conductive layer are made of polycrystalline silicon.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The thickness of the epitaxial layer is between 1 and 5 nm.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The epitaxial growth step of the epitaxial layer includes: The epitaxial growth reaction temperature is 400–600°C, and the epitaxial growth reaction gas is at least one of SiCl4, SiHCl3, SiH4, and SiH2Cl2.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, Before the step of forming an epitaxial layer on the inner wall of the first groove, and after the step of removing a portion of the first conductive layer located within the groove, the fabrication method further includes: Chlorine or hydrogen gas is introduced into the first groove to pretreat the top surface of the conductive structure.

6. The method for preparing a semiconductor structure according to any one of claims 1-5, characterized in that, The ratio of the depth of the first groove to the depth of the trench is 1:5 to 1:

3.

7. The method for preparing a semiconductor structure according to any one of claims 1-5, characterized in that, The step of forming a plurality of spaced bit line structures on the substrate includes: Bit lines are formed on the substrate, and intermediate trenches are formed between adjacent bit lines; Isolation sidewalls are formed on the sides of the bit line facing the intermediate trench. The isolation sidewalls include a first dielectric layer, a second dielectric layer and a third dielectric layer stacked in sequence. The first dielectric layer contacts the side of the intermediate trench, and the third dielectric layer covers the bottom wall of the intermediate trench and the top surface of the bit line. The third dielectric layers located in the same intermediate trench form the trench.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, After the step of forming isolation sidewalls on the sides of the bit lines facing the intermediate trench, and before the step of forming the first conductive layer in the trench, the preparation method further includes; The third dielectric layer located on the bottom wall of the trench is removed, exposing the active region within the trench; The portion of the active area exposed within the trench is removed to form a receiving groove within the active area, and the first conductive layer fills the receiving groove.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The step of removing a portion of the active region exposed within the trench to form a receiving groove within the active region includes: The active region exposed within the trench is removed by dry etching, wherein the etching gas used in the dry etching is at least one of SF6, NF3, and Cl2, the etching pressure of the dry etching is 5 mTorr to 100 mTorr, and the radio frequency power of the dry etching is 200 W to 1000 W.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, After the step of removing a portion of the first conductive layer located within the trench, and before the step of forming an epitaxial layer on the inner wall of the first trench, the preparation method further includes: Remove the third dielectric layer located on the top surface of the bit line and on the side wall of the first groove, leaving the top surface of the retained third dielectric layer flush with the top surface of the conductive structure.

11. The method for preparing a semiconductor structure according to any one of claims 8-10, characterized in that, The bit line includes a second conductive layer, a barrier layer, a third conductive layer, and an insulating layer stacked in sequence.

12. The method for preparing a semiconductor structure according to claim 1, characterized in that, After the step of removing the filler layer, the preparation method further includes: A pad is formed in the third groove. One end of the pad is connected to the conductive plunger, and the other end of the pad is used to connect to a capacitor.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, The filler layer is made of silicon oxide.

14. A semiconductor structure, characterized in that, The semiconductor structure is obtained by the method for preparing a semiconductor structure as described in any one of claims 1-13.

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