Integrated circuit package with decoupling capacitor

Abstract

An IC package includes a substrate having a first surface, a circuit die coupled to the first surface of the substrate, a decoupling capacitor coupled to the first surface of the substrate, and a power trace coupled to the first surface of the substrate and connected to the circuit die and the decoupling capacitor. A method of manufacturing an IC package includes: providing a substrate having a first surface; forming a power trace on the first surface of the substrate, wherein the power trace is a portion of a conductive power path; mounting a circuit die on the first surface, the circuit die being electrically connected to the power trace; and mounting a decoupling capacitor on the first surface of the substrate, wherein the decoupling capacitor is electrically connected to the power trace and the circuit die.

Description

Technical Field

[0001] This application generally relates to integrated circuit packaging and methods of manufacturing the same, and more specifically to integrated circuit packaging including decoupling capacitors. Background Technology

[0002] Decoupling capacitors can be used to improve the electrical performance of integrated circuit (IC) packages, for example, by storing the voltage from V when the gate voltage turns off the power transistor. in The charge of the power source to maintain V out This is to increase switching speed. Sometimes, decoupling capacitors are located on the bottom side of the substrate holding the IC die in the IC package. Summary of the Invention

[0003] One aspect of this disclosure provides an integrated circuit package. The integrated circuit package may include a substrate having a first surface, a circuit die coupled to the first surface of the substrate, a decoupling capacitor coupled to the first surface of the substrate, and a power trace coupled to the first surface of the substrate and connected to the circuit die and the decoupling capacitor.

[0004] In any such embodiment, the decoupling capacitor may have a conductive charge storage for the circuit die.

[0005] In any such embodiment, the power trace may be part of a conductive power path, which includes a through-substrate via passing through the substrate.

[0006] Any such embodiment may further include a first set of decoupling capacitors, wherein the power trace is electrically connected to each of the decoupling capacitors in the first set to form a first power island. Some such embodiments may further include a second set of decoupling capacitors, wherein the second power trace is electrically connected to each of the decoupling capacitors in the second set to form a second power island. For some such embodiments, the second power trace may be electrically connected to a conductive power path via a second through-substrate via through the substrate.

[0007] In any such embodiment, the conductive power path may include a through-substrate via connected to a decoupling capacitor and passing through the substrate and connected to microbumps located on a second surface of the substrate. In some such embodiments, the through-substrate via connecting to the decoupling capacitor is located in a peripheral portion of the substrate not covered by a circuit die on a first surface of the substrate.

[0008] Any such embodiment may also include multiple sets of decoupling capacitors, wherein different power traces of these power traces may each be electrically connected to decoupling capacitors that are portions of different decoupling capacitors in the multiple sets of decoupling capacitors, to form multiple power islands. In some such embodiments, the decoupling capacitor banks may be distributed around the circuit die located on the first surface.

[0009] In any such embodiment, the circuit die covers the central portion of the first surface of the substrate.

[0010] Any such embodiment may also include a printed circuit board, wherein the printed circuit board includes a conductive power routing layer as part of a conductive power path. In some such embodiments, microbumps located on a second surface of the substrate may be electrically connected to the conductive power routing layer.

[0011] Any such embodiment may also include two or more circuit dies located on the first surface, wherein each of these circuit dies is connected to separate power islands, each of these separate power islands comprising different sets of decoupling capacitors and different power traces electrically connected to different sets of decoupling capacitors. In some such embodiments, the separate power islands may be portions of different conductive power paths.

[0012] Any such embodiment may also include a second type of decoupling capacitor mounted to the second surface of the substrate in an opening in the second surface of the substrate. In some such embodiments, a second power trace may be electrically connected to a circuit die and electrically connected to a second power type decoupling capacitor. In some such embodiments, the second type of decoupling capacitor has a conductive charge storage for the circuit die, and the second power trace may be part of a conductive power path. In some such embodiments, the second power trace is electrically connected to a second circuit die in the circuit die and electrically connected to a second type of decoupling capacitor, whereby the second decoupling capacitor has a conductive charge storage for the second circuit die, and the second power trace is part of a second conductive power path.

[0013] Any such embodiment may also include one or more memory modules on the first surface of the substrate.

[0014] In another aspect, a method for manufacturing an integrated circuit package is disclosed. The method may include providing a substrate having a first surface and forming power traces on the first surface of the substrate. The method may include: mounting a circuit die on the first surface, wherein the circuit die is electrically connected to the power traces; and mounting a decoupling capacitor on the first surface of the substrate, wherein the decoupling capacitor is electrically connected to both the power traces and the circuit die. Any such embodiment may further include mounting a second type of decoupling capacitor on the second surface of the substrate in an opening in the second surface. Attached Figure Description

[0015] The following description, taken in conjunction with the accompanying drawings, now refers to:

[0016] Figure 1 A cross-sectional view of an exemplary embodiment of an integrated circuit package of the present disclosure, including a top-side decoupling capacitor, is presented.

[0017] Figure 2 The integrated circuit package of this disclosure (such as...) is presented Figure 1 A top view of the integrated circuit package depicted in the image;

[0018] Figure 3 A cross-sectional view of another exemplary embodiment of the integrated circuit package disclosed herein is presented, which is similar to Figure 1 The integrated circuit package described herein also includes printed circuit boards (PCBs);

[0019] Figure 4 A cross-sectional view of another exemplary embodiment of the integrated circuit package disclosed herein is presented, which is similar to Figure 3 The integrated circuit package described herein also includes a bottom-side decoupling capacitor;

[0020] Figure 5 The integrated circuit package of this disclosure (such as...) is presented Figure 4 A top view of the integrated circuit package depicted in the image;

[0021] Figure 6 A cross-sectional view of another exemplary embodiment of the integrated circuit package disclosed herein is presented, which is similar to Figure 4 The integrated circuit package described herein also includes a top-side memory module; and

[0022] Figure 7 A flowchart illustrating exemplary embodiments of a method for manufacturing an integrated circuit package according to the principles of this disclosure is presented, including, as in... Figures 1 to 6 Any of the encapsulations disclosed in the context of the document. Detailed Implementation

[0023] The embodiments of this disclosure follow our understanding of several disadvantages of existing packages (and specifically, integrated circuit packages including high-speed (high-frequency) signaling circuit dies) with decoupling capacitors placed on the back side of the integrated circuit package. When such a circuit die is mounted to a PCB, the PCB layer beneath the circuit die can be cut through multiple connections to through-circuit vias (TCVs) to provide conductive power paths to the back-mounted decoupling capacitors. Therefore, for high-speed signaling, it may be difficult to provide an integrated reference (ground) plane in this area, which can in turn lead to poor signal integrity. With multiple back-mounted decoupling capacitors present, the amount of space available for routing data signal lines (e.g., data to and from the circuit die carrying TCVs and traces) beneath the circuit die can become limited, thereby limiting signaling speed and throughput. The presence of the back-mounted decoupling capacitors, the power-carrying TCVs, and the power-carrying traces to and from the decoupling capacitors (power traces) can also introduce parasitic inductance and resistance, which can in turn affect power decoupling and limit signaling speed. The need to provide a large number of such power carrier TCVs in a PCB can increase PCB manufacturing costs and reduce PCB manufacturing yield. There may also be increased redesign costs associated with each new integrated circuit package project, for example, to provide an appropriate number of decoupling capacitors and associated power carrier TCVs and power traces, and to balance this with the need for an appropriate number of data signaling carrier TCVs and traces, even when using the same circuit die design.

[0024] To help mitigate these drawbacks, we have developed an integrated circuit package in which decoupling capacitors can be mounted on the top side of a substrate holding the integrated circuit die. Power traces, also located on the top side of the substrate, connect the decoupling capacitors to each other and to the circuit die, and in some embodiments, the decoupling capacitors interconnect each other and to the circuit die. Positioning at least some of the decoupling capacitors on the top side of the substrate helps free up space under the circuit die for data signal line connections and also reduces parasitic inductance and resistance. Embodiments of the circuit die and substrate can be mounted and connected to a standardized trace design layout on the surface of a PCB design without requiring TCVs to be formed in the PCB, thereby advantageously reducing design and manufacturing costs and increasing manufacturing yield.

[0025] Positioning the decoupling capacitor structure on the top side of the IC package substrate (as disclosed herein) is not obvious, at least because it would compromise a much simpler conventional IC packaging manufacturing process. For example, some conventional manufacturing processes mount the decoupling capacitor on the back side of the PCB and then use vias to bring the chip power island to the system PCB. These procedures are easier to implement than those disclosed herein and still provide sufficient decoupling for low-speed applications (e.g., signaling speeds of 250 kHz, 500 kHz, 900 kHz, or less). However, we anticipate that using circuit dies capable of higher signaling speeds (e.g., 1, 2, 3, 4, or 5 GHz or more in some embodiments) leads to the disadvantages discussed above and motivates us to modify our IC package design and its fabrication, as further disclosed below.

[0026] One aspect of this disclosure is integrated circuit packaging. Figure 1-6 Cross-sectional and plan views of various embodiments of the IC package 100 according to the present invention are shown. (Continue to see...) Figure 1-6 Any IC package 100 embodiment includes a substrate 110 having a first surface (e.g., a top surface 105 or a bottom surface 155, wherein the substrate is inverted compared to the orientation shown in the figures), a circuit die 102 coupled to the first surface 105 of the substrate 110 (e.g., located on the top surface 105 or the bottom surface 155), a decoupling capacitor 112 coupled to the first surface of the substrate (e.g., located on the top or bottom surface of the substrate), and a power trace 115 coupled to the first surface of the substrate and connected to the circuit die and the decoupling capacitor (e.g., located on the top or bottom surface of the substrate).

[0027] As used herein, the term circuit die refers to any one of a central processing unit (CPU), graphics processing unit (GPU), memory chip, or other integrated circuit die or chip or combination thereof familiar to those skilled in the art.

[0028] In various embodiments, the decoupling capacitor 112 may have a conductive charge storage for the circuit chip 102. In various embodiments, a power trace may be electrically connected to the circuit chip and electrically connected to the decoupling capacitor, and the power trace may be a portion of a conductive power path 120 connecting the decoupling capacitor and the circuit chip 102. The conductive power path 120 connects the decoupling capacitor and the circuit die to a power source (not shown). As a non-limiting example, the power source may be deployed on a packaged PCB (e.g., Figure 3 One or more DC-DC converters on PCB 305, wherein each converter is connected to supply power to circuit die (e.g., die 102) or multiple circuit dies via different power traces.

[0029] In some embodiments of the IC package 100, the conductive power path 120 includes through-substrate vias (e.g., one or more TSV125a) extending through the substrate. In some such embodiments, power microbumps (e.g., microbump 130, solder bumps) can connect a circuit die to the conductive power carrying path, and signal microbumps (e.g., microbump 132, solder bumps) can connect a circuit die to a conductive signal carrying path (not shown).

[0030] Some embodiments of the IC package 100 may further include a first set of decoupling capacitors 112 (e.g., set 140), and a power trace 115 may be electrically connected to each decoupling capacitor in the first set 140 to form a first power island (e.g., power island 142) and as a portion of the power trace 115. Some such embodiments may further include a second set of decoupling capacitors (e.g., set 145), wherein a second power trace (e.g., power trace 147) may be electrically connected to each decoupling capacitor in the second set 145 to form a second power island (e.g., power island 150). Furthermore, in some such embodiments, the second power trace may be electrically connected to a conductive power path 120 via a second through-substrate via (e.g., one or more TSV125b) through the substrate 110.

[0031] In some embodiments of the IC package 100, the conductive power path 120 may include a TSV (e.g., typically TSV 125) connected to a decoupling capacitor 112 and passing through the substrate 110 to a microbump (e.g., typically bottom-side microbump 152) located on a second surface (e.g., bottom surface 155 or top surface 105) of the substrate 110. For example, the conductive power path 120 may include microbumps 152a and 152b respectively connected to TSVs 125a and 125b, and TSVs 125a and 125b may be connected to decoupling capacitor 112 in a first or second set of decoupling capacitors (e.g., decoupling groups 140 and 145, respectively).

[0032] In some such embodiments, a through-substrate via 125 that passes through the substrate and connects to a decoupling capacitor may be located in one or more peripheral portions (e.g., portion 160) of the substrate 110 that are not covered by the circuit die 102 on the first surface 105 of the substrate.

[0033] like Figure 1 As shown, some embodiments of IC package 100 may further include multiple sets of decoupling capacitors (e.g., sets 140, 145), and different power traces (e.g., traces 115, 147) may each be electrically connected to decoupling capacitor 112, which is part of a different set of sets 140, 145, to form multiple power islands (e.g., power islands 142, 150).

[0034] In some such embodiments, such as Figure 2 As shown, multiple sets of decoupling capacitor banks (e.g., banks 140, 145) may be distributed around a circuit die 102 located on a first surface of substrate 110. For example, in some embodiments, the circuit die 102 may cover a central portion of substrate 110 such that the die is not within 5%, 10%, 20%, or 30% of the periphery relative to the total width 161 and / or height 162 of the substrate 110 surface 105. For example, in some embodiments, one or more peripheral portions 160 where the decoupling capacitors are located may be within 5%, 10%, 20%, or 30% of the periphery relative to the total width 161 and / or height 162 of the substrate 110 surface 105.

[0035] like Figure 3 As shown, some embodiments of IC package 100 may further include a printed circuit board (PCB 305), wherein the printed circuit board includes a conductive power routing layer (e.g., routing layer 310) as part of a conductive power path (e.g., power path 120).

[0036] In some such embodiments, microbumps (e.g., microbumps 152) located on a second surface (e.g., bottom surface 155 or top surface 105) of substrate 110 may be electrically connected to conductive power routing layer 310.

[0037] like Figure 4 and Figure 5 As shown, some embodiments of the IC package 100 may further include two or more circuit dies (e.g., dies 102a, 102b) located on a first surface (e.g., top surface 105 or bottom surface 155) of the substrate 110.

[0038] In some such embodiments, each of the circuit dies may be connected to separate power islands (e.g., die 102a connected to power island 142, die 102b connected to power island 150), and each of the separate power islands may include different groups of decoupling capacitors (e.g., groups 140 and 145, respectively), and different power traces (e.g., traces 115 and 147, respectively) may be electrically connected to different groups of decoupling capacitors (e.g., trace 115 connected to group 140, trace 147 connected to group 145). In some such embodiments, the separate power islands 142 and 150 may be portions of different conductive power paths (e.g., paths 120 and 420 connected to different power supplies, respectively). In some such embodiments, the printed circuit board 305 may include separate conductive power routing layers (e.g., power routing layers 310 and 410), which are portions of the different conductive power paths (e.g., power paths 120 and 420).

[0039] like Figure 4 As shown, some embodiments of the IC package 100 may further include a second type of decoupling capacitor (e.g., one or more second decoupling capacitors 412), which may be mounted to the second surface of the substrate in an opening in the second surface of the substrate (e.g., each decoupling capacitor 412 is mounted in one of the openings 430, 450 in the second surface 155 or in a similar opening formed in the top surface 105).

[0040] In some such embodiments, a second power trace (e.g., trace 435) may be electrically connected to a circuit die (e.g., die 102a) and a second type of decoupling capacitor 412. In some such embodiments, the second type of decoupling capacitor has a conductive charge storage for circuit die 102a, and the second power trace 435 is part of the conductive power path 120. In some such embodiments, the conductive charge storage for circuit die 102a provided by one or more second-type decoupling capacitors 412 may be greater than, less than, or equal to the conductive charge storage for circuit die 102a provided by one or more first-type decoupling capacitors 112. In some embodiments, the first and second types of decoupling capacitors 112, 412 may be of the same type (e.g., ceramic or electrolytic capacitors), while in other embodiments, the first and second types of decoupling capacitors 112, 412 may be of different types.

[0041] In some such embodiments, the second power trace 455 may be electrically connected to a second circuit die (e.g., die 102b) in the circuit die and the second power trace 455 may be electrically connected to a second type of decoupling capacitor 412, wherein the second decoupling capacitor has a conductive charge storage for the second circuit die 102b and the second power trace 455 is part of the second conductive power path 420.

[0042] For example, when IC package 100 includes two or more circuit dies (e.g., dies 102a, 102b), there may be different groups of second-type decoupling capacitors 412 (e.g., groups 440 and 445, respectively) in the same opening or separate openings (e.g., openings 430 and / or 450, respectively) in the second surface of substrate 110 (e.g., bottom surface 155 or top surface 105), and separate power traces (e.g., first trace 435 and second trace 455, respectively) can electrically connect the different groups (e.g., groups 440 and 445, respectively) of the second-type decoupling capacitors to the two or more circuit dies (e.g., first circuit die 102a and second circuit die 102b, respectively).

[0043] like Figure 6 As shown, some embodiments of the IC package 100 may further include one or more memory modules 610 on a first surface of the substrate 110 (e.g., top surface 105 or bottom surface 155). As a non-limiting example, the memory module 610 may be or include double data rate dynamic random access memory (DDR SDRAM), such as synchronous dynamic random access memory (SDRAM) designed for GPU circuit dies (e.g., 102a, 102b). For example, in some embodiments, by providing some decoupling capacitors 412 on the back side of the substrate 110 and some decoupling capacitors 112 on the first side of the substrate 110, an additional portion 160 of the first surface 105 can be used for such memory modules. However, in some embodiments, the IC package 100 may have only top-side mounted decoupling capacitors 112 without back-side mounted decoupling capacitors 412 and still accommodate such memory modules or other device features.

[0044] Another aspect of this disclosure is a method for manufacturing integrated circuit packages. Figure 7 The flowchart illustrates selected steps in a method 700 for manufacturing an integrated circuit package according to this disclosure, the method including manufacturing in... Figures 1 to 6 Any of the embodiments of the encapsulation 100 discussed in the context of the present invention.

[0045] See also Figure 1-7 ,like Figure 7 As shown, embodiments of method 700 may include providing a substrate having a first surface (e.g., in step 705, substrate 110, or in some embodiments, a silicon substrate, on a top surface 105 or a bottom surface 155) and forming power traces on the first surface of the substrate, the power traces being portions of conductive power paths (e.g., power trace 115, or in some embodiments, a metal trace, on the top surface 105 or the bottom surface 155). Method 700 may include mounting circuit dies on the first surface of substrate 110 (e.g., in step 715, one or more circuit dies 102a, 102b on the top surface 105 or the bottom surface 155), wherein the circuit dies are electrically connected to the power traces. Method 700 may include mounting decoupling capacitors on the first surface of the substrate, the decoupling capacitors being electrically connected to the power traces and connected to the circuit dies (e.g., in some embodiments, in step 720, one or more decoupling capacitors 112, prefabricated ceramic and / or electrolytic capacitors).

[0046] In some embodiments, forming power traces on a first surface of the substrate (step 710) may further include forming power islands (e.g., step 725, one or more power islands 142, 150), including forming mounting pads as portions of the power islands (step 727). In some embodiments, forming power traces (step 710) may further include forming power microbumps on the first surface of the substrate (e.g., step 730, one or more power microbumps 130), which are electrically connected to the power islands (e.g., at least one of islands 142 or 150).

[0047] In some embodiments, the power trace may be part of a conductive power path. For example, in some embodiments of method 700, forming a power trace (step 710) may be a step of forming a conductive power path (e.g., step 735, power path 120). In some embodiments, forming a conductive power path (step 735) may further include forming a ground plane on a second surface of the substrate (e.g., bottom surface 155 or top surface 105 of substrate 110) (step 740). In some embodiments, forming a conductive power path (step 735) may further include forming a through-substrate via (e.g., step 742, one or more TSVs 125, through-silicon vias in some embodiments), which may be electrically connected to the power island and the ground plane. In some embodiments, forming a conductive power path (step 735) may further include forming microbumps on the second surface of the substrate, wherein at least some of the bottom-side microbumps are connected to the through-substrate vias electrically connected to the power island (e.g., bottom-side microbumps 152 connected to TSVs 125 in step 745).

[0048] In some embodiments, mounting the circuit die (step 715) may include contacting the circuit die with power microbumps located on a first surface of the substrate, power microbumps electrically connected to power islands (e.g., step 750, at least one power microbump 130 on the first surface 105 of the substrate 110 and connected to at least one of the islands 142 or 150). In some embodiments, mounting the circuit die (step 715) may include mounting the die to a central circuit die mounting portion of the substrate (e.g., step 752, mounting one or more dies 102a, 102b to a central portion 165 of the substrate 110).

[0049] In some embodiments, mounting the decoupling capacitor to a first surface of the substrate (step 720) includes contacting the decoupling capacitor with mounting pads on the power islands (step 755, mounting one or more decoupling capacitors 112 to one or more mounting pads on at least one of the islands 142 or 150). In some embodiments, mounting the decoupling capacitor to the first surface of the substrate (step 720) includes mounting the decoupling capacitor to a peripheral portion of the substrate (e.g., step 757, mounting one or more decoupling capacitors 112 to pads on at least one of the islands 142 or 150 in a peripheral portion 160 of the substrate 110).

[0050] Some embodiments of method 700 may further include, for example, as part of forming a conductive signal path (step 760), forming signal microbumps on a first surface of the substrate (e.g., step 762, signal microbump 132), the signal microbumps being located on a circuit die mounting portion (e.g., portion 165) of the substrate 110 such that the signal microbumps are connected to a signal TSV formed in the substrate (step 764), and forming signal microbumps on a second surface of the substrate, at least some of which may form bottom-side signal microbumps (step 766, bottom-side signal microbump 170). The top-side and bottom-side microbumps 132, 170 are connected such that once the circuit die mounted in step 715 can contact the signal microbumps (step 768, top-side signal microbump 132), data signals can be transmitted through the substrate to and from the circuit die.

[0051] Embodiments of method 700 may further include mounting a second type of decoupling capacitor (e.g., in some embodiments, one or more decoupling capacitors 412, ceramic and / or electrolytic capacitors) on a second surface of a substrate in an opening in the bottom surface (step 770, bottom surface 155 or top surface 105 of substrate 110, at least one of openings 430, 450). For some such embodiments, method 700 may include forming a second power trace on the second surface (e.g., step 772, power trace 435 on bottom surface 155 or top surface 105) such that the second power trace is electrically connected to the circuit die and electrically connected to the second type of decoupling capacitor when the second type of decoupling capacitor is mounted (step 770), thereby providing an additional conductive charge storage to the circuit die. In some such embodiments, forming the second power trace (step 772) may include forming a second power island with mounting pads and mounting the second type of decoupling capacitor 412 to such mounting pads, similar to what is discussed in the context of steps 725 and 755. Such embodiments may also include forming openings in a second surface of the substrate (e.g., step 775, one or more openings 430, 450). Some embodiments of forming openings (step 775) may include etching the surface of the substrate (e.g., the bottom surface 155 or top surface 105 of the monolithic silicon substrate 110) using procedures familiar to those skilled in the art. Some embodiments of forming openings (step 775) may include providing a base substrate (e.g., step 705, Figure 4 Provide a base substrate 110a) and couple an intermediate layer substrate to the base substrate to form an opening (e.g., couple an intermediate layer substrate 110b).

[0052] Those skilled in the art to which this application pertains will understand that other and further additions, deletions, substitutions, and modifications can be made to the described embodiments.

Claims

1. An integrated circuit package comprising: a substrate having a first surface; a circuit die coupled to the first surface of the substrate; a decoupling capacitor coupled to the first surface of the substrate; a power trace coupled to the first surface of the substrate and connected to the circuit die and to the decoupling capacitor; a second type of decoupling capacitor mounted to a second surface of the substrate in an opening in the second surface of the substrate; and a first group of the decoupling capacitors, wherein the power trace is electrically connected to each of the decoupling capacitors in the first group to form a first power island. The power trace is part of a conductive power pathway that includes a through-substrate via through the substrate.

2. The package of claim 1, wherein, A second power trace is electrically connected to each of the decoupling capacitors in the second group to form a second power island.

3. The package of claim 1, further comprising a second set of the decoupling capacitors, wherein, 4. The package of claim 3, wherein the second power trace is electrically connected to the conductive power pathway by a second through-substrate via through the substrate.

5. The package of claim 2, wherein the conductive power pathway includes a plurality of through-substrate vias connected to the decoupling capacitor and through the substrate and connected to micro-bumps on a second surface of the substrate. The plurality of through-substrate vias through the substrate and connected to the decoupling capacitor are located in a peripheral portion of the substrate that is not covered by the circuit die on the first surface of the substrate.

6. The package of claim 5, wherein, Different ones of the power traces are each electrically connected to the decoupling capacitors that are part of different ones of the groups of decoupling capacitors to form a plurality of power islands.

7. The package of claim 1, further comprising multiple sets of the decoupling capacitors, wherein, Each group of decoupling capacitors is distributed around the circuit die on the first surface.

8. The package of claim 7, wherein, The circuit die covers a central portion of the first surface of the substrate.

9. The package of claim 1, wherein, 10. The package of claim 1, further comprising a printed circuit board, wherein the printed circuit board includes a conductive power routing layer that is part of a conductive power pathway.

11. The package of claim 10, wherein micro-bumps on a second surface of the substrate are electrically connected to the conductive power routing layer. Each of the circuit dies is connected to a separate power island, each of the separate power islands includes a different group of the decoupling capacitors, and a different power trace is electrically connected to the different group of the decoupling capacitors.

12. The package of claim 1, further comprising two or more of the circuit dies on the first surface, wherein: The separate power islands are part of different conductive power pathways.

13. The package of claim 12, wherein, A second power trace is electrically connected to the circuit die and to the second type of decoupling capacitor.

14. The package of claim 1, wherein, A second power trace is electrically connected to a second one of the circuit dies and to the second type of decoupling capacitor, whereby the second type of decoupling capacitor has a conductive charge reservoir for the second circuit die and the second power trace is part of a second conductive power pathway.

15. The package of claim 1, wherein, ​ 16. The package of claim 1, further comprising one or more memory modules on the first surface of the substrate.

17. A method of manufacturing an integrated circuit package, comprising: providing a substrate having a first surface; forming power traces on the first surface of the substrate; mounting a circuit die on the first surface, wherein the circuit die is electrically connected to the power traces; mounting a decoupling capacitor on the first surface of the substrate, wherein the decoupling capacitor is electrically connected to the power traces and to the circuit die; mounting a second type of decoupling capacitor on a second surface of the substrate in an opening in the second surface; and providing a first group of the decoupling capacitors, wherein the power traces are electrically connected to each of the decoupling capacitors in the first group to form a first power island.

18. The method of claim 17, wherein the second type of decoupling capacitor is mounted on the second surface of the substrate in the opening in the second surface.

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