System for backside signal routing, integrated circuit device and method of generating integrated circuit layout

Abstract

A backside signal routing system and method includes a substrate having a first side and a second side opposite the first side; a unit on the substrate, the unit having a first pin on the first side or on the second side and a second pin on the second side; a first signal routing connected to the first pin; and a second signal routing connected to the second pin.

Description

Technical Field

[0001] This disclosure relates to a system and method for back-side signal routing. Background Technology

[0002] This disclosure generally relates to signal routing, and more particularly to signal routing on the back side of a semiconductor substrate.

[0003] Integrated circuits are widely used in various applications. Designing an integrated circuit is a multi-step process. Specifically, integrated circuit design begins with a description of the required functionality of the integrated circuit. Based on the functional description, transistor-level circuitry is designed, and a network interconnect table is developed to define the connections between various transistors in the circuit. The network interconnect table can be simulated and tested to verify that the circuit implements the required functionality and to predict operating parameters. The network interconnect table is then used to generate a standard cell layout for the circuit. The standard cell layout includes the placement of standard components or standard cells from a standard cell library, and signal routing to show how these cells are interconnected. However, current standard cell layout techniques have limitations in signal routing. Summary of the Invention

[0004] According to some embodiments disclosed herein, a back-side signal routing system includes a substrate, a unit, a first signal route, and a second signal route. The substrate has a first surface and a second surface, wherein an active device of an integrated circuit formed on the substrate is located on the first surface and the second surface is opposite to the first surface. The unit is on the substrate, having a first pin on the first surface and a second pin on the second surface. The first signal route is connected to the first pin for routing a clock leaf signal. The second signal route is connected to the second pin for routing a clock trunk signal.

[0005] According to some embodiments disclosed herein, a back-side signal routing system includes a substrate, a unit, a first signal route, and a second signal route. The substrate has a first surface and a second surface, wherein an active device of an integrated circuit formed on the substrate is on the first surface and the second surface is opposite to the first surface. The unit is on the substrate, having a first pin on the second surface and a second pin on the second surface. The first signal route is connected to the first pin. The second signal route is connected to the second pin, wherein the first signal route is used to route a first clock trunk signal and the second signal route is used to route a second clock trunk signal.

[0006] According to some embodiments disclosed herein, a back-side signal routing system includes a substrate, a unit, a first signal route, and a second signal route. The substrate has a first surface and a second surface, wherein an active device of an integrated circuit formed on the substrate is on the first surface and the second surface is opposite to the first surface. The unit is on the substrate, having a first pin and a second pin on the second surface. The first signal route is connected to the first pin. The second signal route is connected to the second pin, wherein the first signal route routes a first feedthrough portion of a feedthrough line and the second signal route routes a second feedthrough portion of the feedthrough line.

[0007] According to some embodiments disclosed herein, a back-side signal routing system includes a substrate, a first unit, a second unit, a first signal route, a second signal route, and a third signal route. The substrate has a first surface and a second surface, wherein an active device of an integrated circuit formed on the substrate is on the first surface and the second surface is opposite to the first surface. The first unit, on the substrate, has a first pin on the first surface and a second pin on the second surface. The second unit, on the substrate, has a third pin on the first surface and a fourth pin on the second surface. The first signal route is connected to the first pin. The second signal route is connected to the second pin. The third signal route is on the first surface and connected to the third pin, wherein the first signal route is connected to the third signal route via the second signal route, such that one end of the second signal route is connected to the second pin and the other end of the second signal route is connected to the fourth pin, and wherein the second signal route is a timing-critical network.

[0008] According to some embodiments of this disclosure, a method for generating a layout of an integrated circuit includes the following steps: identifying a signal route on a first surface of a substrate to move to a second surface of the substrate, wherein an active device of the integrated circuit formed on the substrate is on the first surface and the second surface is opposite to the first surface; inserting a unit on the substrate having a first pin on the first surface or on the second surface and a second pin on the second surface; connecting the signal route to the second pin; and connecting the signal route to the other signal route by connecting another signal route to the first pin.

[0009] According to some embodiments disclosed herein, an integrated circuit device includes: a substrate having a first surface and a second surface, wherein an active device formed on the substrate is on the first surface and the second surface is opposite to the first surface; an output pin on the first surface; an input pin on the second surface; a first active region on the first surface; and a second active region on the first surface, wherein, in order to connect the input pin to the output pin: the input pin is connected to the first active region; the output pin is connected to the second active region; and the first active region is connected to the second active region.

[0010] According to some embodiments disclosed herein, a back-side signal routing system includes: a substrate, a device, a first signal route, and a second signal route. The substrate has a first surface and a second surface, wherein an active device formed on the substrate is on the first surface and the second surface is opposite to the first surface. The device includes: a first pin on the first surface, a second pin on the second surface, a first active region on the first surface, and a second active region on the first surface, wherein the first pin is connected to the second pin via the first active region, the second active region, and one or more gate structures. The first signal route is connected to the first pin for routing a clock leaf signal. The second signal route is connected to the second pin for routing a clock trunk signal.

[0011] According to some embodiments disclosed herein, a back-side signal routing system includes: a substrate, a first device, a second device, a first signal route, a second signal route, and a third signal route. The substrate has a first surface and a second surface, wherein an active device of an integrated circuit formed on the substrate is on the first surface and the second surface is opposite to the first surface. The first device is on the substrate and includes: a first pin on the first surface, a second pin on the second surface, a first active region on the first surface, and a second active region on the first surface, wherein the first pin is connected to the second pin via the first active region, the second active region, and one or more first gate structures. The second device is on the substrate and includes: a third pin on the first surface, a fourth pin on the second surface, a third active region on the first surface, and a fourth active region on the first surface, wherein the third pin is connected to the fourth pin via the third active region, the fourth active region, and one or more second gate structures. The first signal route is connected to the first pin. The second signal route is connected to the second pin. A third signal route is on the first surface and connected to the third pin, wherein the first signal route is connected to the third signal route via the second signal route, such that one end of the second signal route is connected to the second pin and the other end of the second signal route is connected to the fourth pin.

[0012] According to some embodiments of this disclosure, a back-side signal routing system includes: a substrate, a unit, a first signal route, a second signal route, and a third signal route. The substrate has a first surface and a second surface, wherein the second surface is opposite to the first surface, and an active device of an integrated circuit formed on the substrate is on the first surface. The unit is on the substrate, and the unit has a first pin on the first surface or the second surface, and a second pin on the second surface. The first signal route on the second surface routes a first power and ground signal rail. The second signal route on the second surface routes a second power and ground signal rail. The third signal route is connected to the second pin and on the second surface routes a first clock trunk signal, wherein the third signal route is between the first signal route and the second signal route.

[0013] According to some embodiments of this disclosure, a back-side signal routing system includes a substrate, a unit, a first signal route, a second signal route, and a third signal route. The substrate has a first surface and a second surface, wherein the second surface is opposite to the first surface, and an active device of an integrated circuit formed on the substrate is on the first surface. The unit is on the substrate, and the unit has a first pin and a second pin on the second surface. The first signal route on the second surface routes a first power and ground signal rail. The second signal route on the second surface routes a second power and ground signal rail. The third signal route on the second surface routes a first feedthrough line, wherein the third signal route is between the first signal route and the second signal route.

[0014] According to some embodiments disclosed herein, a back-side signal routing system includes a substrate, a first unit, a second unit, and a first signal route. The substrate has a first surface and a second surface, the second surface being opposite to the first surface, wherein an active device of an integrated circuit formed on the substrate is on the first surface. The first unit is on the substrate, the first unit having a first pin on the first surface and a second pin on the second surface. The second unit is on the substrate, the second unit having a third pin on the first surface and a fourth pin on the second surface. The first signal route is connected to the second pin on the second surface and to the fourth pin on the second surface, connecting a second signal route on the first surface to a third signal route on the first surface. Attached Figure Description

[0015] The features disclosed herein will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced for clarity of description.

[0016] Figure 1 This is an example block diagram of a computing system according to some embodiments;

[0017] Figure 2 It is an instance layout implemented according to the back clock tree of some embodiments;

[0018] Figure 3 This is another instance layout implemented according to the back clock tree of some embodiments;

[0019] Figure 4 This is an example flowchart outlining operations for performing a layout implemented by a back face clock tree, based on some embodiments.

[0020] Figure 5 These are example block diagrams illustrating feedthrough implementations according to some embodiments;

[0021] Figure 6 This is an example layout implemented according to the back feedthrough of some embodiments;

[0022] Figure 7A This is an example layout implemented according to the vertical back feedline of some embodiments;

[0023] Figure 7B This is an example layout implemented according to some embodiments of the horizontal back feedline;

[0024] Figure 8 This is another example layout implemented according to the back feedthrough of some embodiments;

[0025] Figure 9 This is an instance layout implemented according to some embodiments of back-side layer lifting;

[0026] Figure 10 This is an example flowchart illustrating operations for performing a back-side layer lifting implementation, based on an overview of some embodiments;

[0027] Figure 11A , Figure 11B ,and Figure 11C These are examples illustrating the configuration of input and output pins on a semiconductor substrate that enables back-side routing, according to some embodiments;

[0028] Figure 12A This is an example layout diagram of a buffer for facilitating back-end routing according to some embodiments;

[0029] Figure 12B and Figure 12C According to some embodiments Figure 12A The corresponding front and back layout diagrams of the buffer;

[0030] Figure 12D According to some embodiments Figure 12A A cross-sectional view of an example buffer;

[0031] Figure 13 This is an example flowchart outlining some embodiments of the present disclosure for performing back-side routing operations.

[0032] [Symbol Explanation]

[0033] 100: Computing System

[0034] 105: Main unit

[0035] 110: Memory device

[0036] 115: Input device

[0037] 120: Output device

[0038] 125A: Interface

[0039] 125B: Interface

[0040] 125C: Interface

[0041] 130A: CPU core

[0042] 130N: CPU core

[0043] 135: Standard Cell Layout Application

[0044] 140: Memory controller

[0045] 145: Memory Array

[0046] 150: Manufacturing tools

[0047] 200: Layout

[0048] 210: First Page

[0049] 215: Second page

[0050] 220A: Clock trunk signal

[0051] 220B: Clock trunk signal

[0052] 225: Through hole

[0053] 230: Clock buffer or clock gating unit

[0054] 235: Through hole

[0055] 240: Block

[0056] 245: Clock trunk signal

[0057] 250A: Time-lapse leaf signal

[0058] 250B: Time-lapse leaf signal

[0059] 255: Through hole

[0060] 260: Clock buffer or clock gating unit

[0061] 265: Through hole

[0062] 270A: Through hole

[0063] 270B: Through hole

[0064] 275: Metal interconnect layer

[0065] 280: Block

[0066] 285: Opposite side

[0067] 290: Opposite side

[0068] 300: Layout

[0069] 305: Substrate

[0070] 310: Second page

[0071] 315: Power supply and grounding signals

[0072] 320: Power and ground signals

[0073] 325A: Clock trunk signal

[0074] 325B: Clock trunk signal

[0075] 330A: Power and ground signal rail

[0076] 330B: Power and ground signal rail

[0077] 330C: Power and ground signal rail

[0078] 400: Process

[0079] 405: Operation

[0080] 410: Operation

[0081] 415: Operation

[0082] 420: Operation

[0083] 500: Top-level design

[0084] 505: Block

[0085] 510: Block

[0086] 515: Wire

[0087] 600: Layout

[0088] 605: Substrate

[0089] 610: First Page

[0090] 615: Second page

[0091] 620: Feeder line

[0092] 625: Buffer

[0093] 630: Through hole

[0094] 635: Through hole

[0095] 640: Part One

[0096] 645: Part Two

[0097] 700: Feeder line

[0098] 705: Back

[0099] 710: Substrate

[0100] 715: Repeater

[0101] 720: Input pin

[0102] 725: Output pin

[0103] 730: Feeder line

[0104] 735: Back

[0105] 740: Substrate

[0106] 745: Repeater

[0107] 750: Input pin

[0108] 755: Output pin

[0109] 800: Layout

[0110] 805: Substrate

[0111] 810: Second page

[0112] 815: Power and grounding signal rails

[0113] 820: Power and ground signal rails

[0114] 825: Feeder line

[0115] 830: Feeder line

[0116] 900: Layout

[0117] 905: Substrate

[0118] 910: First Page

[0119] 915: Second page

[0120] 920: Signal

[0121] 925: Buffer

[0122] 930: Buffer

[0123] 935: Through hole

[0124] 940: Through hole

[0125] 945: Signal

[0126] 950: Signal

[0127] 955: Through hole

[0128] 960: Through hole

[0129] 965: Arrow

[0130] 1000: Manufacturing process

[0131] 1005: Operation

[0132] 1010: Operation

[0133] 1015: Operation

[0134] 1100: Unit

[0135] 1105: Substrate

[0136] 1110: First page

[0137] 1115: Second page

[0138] 1120: Input pin

[0139] 1125: Output pin

[0140] 1200: Buffer unit

[0141] 1205: Input pin

[0142] 1210: Second page

[0143] 1215 : Substrate

[0144] 1220: Output pin

[0145] 1225: First Page

[0146] 1230A: First Active Zone

[0147] 1230B: Second Active Zone

[0148] 1235A: Gate structure

[0149] 1235B: Gate structure

[0150] 1235C: Gate structure

[0151] 1240A: Part 1

[0152] 1240B: Part Two

[0153] 1245A: First conductive layer

[0154] 1245B: Second Interconnect Layer

[0155] 1245C: Third Interconnect Layer

[0156] 1245D: Fourth Interconnect Layer

[0157] 1245E: Fifth Interconnect Layer

[0158] 1245F: Sixth Interconnect Layer

[0159] 1250A: Through hole

[0160] 1250B: Through hole

[0161] 1250C: Through hole

[0162] 1250D: Through hole

[0163] 1255A: Arrow

[0164] 1255B: Arrow

[0165] 1260A: Third Active Zone

[0166] 1260B: Fourth Active Zone

[0167] 1265: Backside interconnect metal layer

[0168] 1270: Through hole

[0169] 1300: Manufacturing process

[0170] 1305: Operation

[0171] 1310: Operation

[0172] 1315: Operation

[0173] 1320: Operation Detailed Implementation

[0174] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components and configurations will be described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, references to numbers and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0175] Furthermore, for the convenience of describing the relationship between one element or feature as illustrated in the figures and another element(s) or feature(s), spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and the like are used herein. Spatial relative terms are intended to cover different orientations of the device during use or operation other than those depicted in the figures. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted similarly accordingly.

[0176] Now for reference Figure 1According to some embodiments of this disclosure, an example block diagram of a computing system 100 is shown. The computing system 100 can be implemented using standard cell layouts by circuit or layout designers. As used herein, “circuit” or “integrated circuit” refers to the interconnection of electrical components such as resistors, transistors, switches, batteries, inductors, or other types of semiconductor devices configured to implement desired functionality. The computing system 100 includes a host device 105 associated with a memory device 110. The host device 105 can be used to receive input from one or more input devices 115 and provide output to one or more output devices 120. The host device 105 can be used to communicate with the memory device 110, the input devices 115, and the output devices 120 via appropriate interfaces 125A, 125B, and 125C, respectively. The computing system 100 can be implemented in various computing devices, such as computers (e.g., desktop computers, laptop computers, servers, data centers, etc.), tablet computers, personal digital assistants, mobile devices, other handheld or portable devices, or any other computing device suitable for performing a standard cell layout using the host device 105.

[0177] Input device 115 may include any of a variety of input technologies, such as a keyboard, stylus, touchscreen, mouse, ballpoint, keypad, microphone, voice recognition, motion recognition, remote controller, input port, one or more buttons, dial pad, joystick, and any other input peripheral associated with host device 105 that allows external sources (such as users (e.g., circuit or layout designers)) to input information (e.g., data) into the host device and send instructions to the host device. Similarly, output device 120 may include a variety of output technologies, such as external memory, printer, speaker, display, microphone, LED, headset, video device, and any other output peripheral for receiving information (e.g., data) from host device 105. "Data" input to and / or output from host device 105 may include any of a variety of text data, circuit data, signal data, semiconductor device data, graphic data, combinations thereof, or other types of analog and / or digital data suitable for processing using computing system 100.

[0178] The host device 105 includes or is associated with one or more processing units / processors, such as Central Processing Unit ("CPU") cores 130A-130N. CPU cores 130A-130N may be implemented as Application Specific Integrated Circuits ("ASICs"), Field Programmable Gate Arrays ("FPGAs"), or any other type of processing unit. Each of the CPU cores 130A-130N can be used to execute instructions for running one or more applications of the host device 105. In some embodiments, the instructions and data required to run one or more applications may be stored in memory device 110. The host device 105 can also be used to store the results of running one or more applications in memory device 110. Therefore, the host device 105 can be used to request memory device 110 to perform various operations. For example, the host device 105 may request memory device 110 to read data, write data, update or delete data, and / or perform management or other operations.

[0179] One such application that the host device 105 can run is a standard cell layout application 135. The standard cell layout application 135 may be part of a computer-aided design or electronic design automation software suite that can be used by a user of the host device 105 to generate a standard cell layout of a circuit (also referred to herein as a "layout," "layout diagram," "layout design," and the like). The standard cell layout of a circuit can show the various components and connections of the circuit to be manufactured. For example, a standard cell layout can show one or more active regions, gate electrodes, source and drain electrodes, metal lines, via contacts, openings for connection pads, one or more metal layers, power supplies, input and output signals, clock signals, etc., representing the various components of the circuit and how these components are interconnected when arranged in / on a semiconductor substrate (such as a silicon wafer). The standard cell layout can be implemented by following a design procedure that may include one or more logic designs, physical designs, or placement and routing. The standard cell layout can be represented using one or more data files (such as GDSII or DFII file formats). In other embodiments, other file formats may be used. Therefore, circuit designers can use the standard cell layout application 135 to generate a standard cell layout for the circuit. In some embodiments, the instructions required to execute or run the standard cell layout application 135 may be stored in the memory device 110. The standard cell layout application 135 may be executed by one or more of the CPU cores 130A to 130N using instructions associated with the standard cell layout application from the memory device 110.

[0180] Still referencing Figure 1 The memory device 110 includes a memory controller 140 for reading data from or writing data to the memory array 145. In some embodiments, the memory array 145 may include various volatile and / or non-volatile memory types. For example, in some embodiments, the memory array 145 may include non-flash memory cores, static random access memory (SRAM) cores, dynamic random access memory (DRAM) cores, magnetoresistive random access memory (MRAM) cores, phase change memory (PCM) cores, resistive random access memory (ReRAM) cores, 3D XPoint memory cores, ferroelectric random-access memory (FeRAM) cores, and other types of memory cores suitable for use within the memory array. Generally, memory array 145 may include various random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), hard disk drive, flash drive, memory tape, optical drive, cloud memory, or any combination of main memory and / or secondary memory suitable for performing the operations described herein.

[0181] The memories within memory array 145 can be controlled individually and independently by memory controller 140. In other words, memory controller 140 can be used to communicate individually and independently with each memory within memory array 145. By communicating with memory array 145, memory controller 140 can be used to read data from or write data to memory array in response to instructions received from host device 105. Although shown as part of memory device 110, in some embodiments, memory controller 140 may be part of host device 105 or part of another component of computing system 100 and associated with memory device. Memory controller 140 may be implemented as logic circuitry in software, hardware, firmware, or a combination thereof to perform the functions described herein. For example, in some embodiments, memory controller 140 can be used to retrieve instructions associated with standard cell layout application 135 stored in memory array 145 of memory device 110 when a request is received from host device 105.

[0182] In some embodiments, the computing system 100 may also be associated with various manufacturing tools 150. Among other things, the manufacturing tools 150 may be used to prepare and manufacture a set of masks based on a standard cell layout generated by a standard cell layout application 135. This set of masks may define the geometry for optical lithography steps used during the semiconductor fabrication of the circuit. Although the manufacturing tools 150 are shown separately from the host device 105, in some embodiments, at least some of the functionality of the manufacturing tools may be implemented by the host device, such as by the standard cell layout application 135 or another application associated with the standard cell layout application.

[0183] To prepare a set of masks, manufacturing tool 150 can be used to convert the standard cell layout of the circuit into a representative data file ("RDF"). The RDF can then be used to manufacture a set of physical masks to fabricate the circuit.

[0184] In some embodiments, preparing the set of masks may include performing optical proximity correction (OPC) using lithography techniques to compensate for image errors, such as self-diffraction, interference, other process effects, and similar image errors in a standard cell layout. In some embodiments, a mask rule checker (MRC) of the manufacturing tool 150 may check the standard cell layout that has undergone the process of applying a set of mask generation rules to an OPC. The mask generation rules may contain certain geometric and / or connectivity constraints to ensure sufficient margin, take into account variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC may modify the standard cell layout to compensate for limitations during the manufacture of the set of masks. In some embodiments, preparing the set of masks may also include resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shift masks, other suitable techniques, and the like or combinations thereof.

[0185] In some embodiments, preparing the mask may further include lithography process checking (LPC), which simulates the processes implemented to manufacture the circuit. LPC can simulate these processes based on a standard cell layout to produce a simulated manufactured circuit arrangement. LPC may consider various factors, such as virtual image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and similar or combinations thereof, to simulate circuit manufacturing. In some embodiments, after the simulated manufacturing arrangement has been generated by LPC, if the simulated arrangement does not meet certain design rules, OPC and / or MRC may be repeated to further refine the standard cell layout.

[0186] To fabricate this mask, a mask writer can convert RDF into an image on a substrate, such as a mask (master photomask) or a semiconductor wafer. In some embodiments, an electron beam (e-beam) or multiple electron beams can be used to form a mask pattern on the semiconductor wafer to form the mask. In some embodiments, the mask pattern may include one or more opaque areas and one or more transparent areas. A radiation beam, such as an ultraviolet (“UV”) beam, used to expose an image-sensitive data layer (e.g., a photoresist layer) coated on the semiconductor wafer, can be blocked by the opaque areas and transmitted through the transparent areas. In one example, the mask pattern may include a transparent substrate (e.g., fused silica) and opaque data (e.g., chromium) coated in the opaque areas to form the mask. In other embodiments, other or additional techniques may be used to fabricate the mask.

[0187] Once the mask is fabricated, a manufacturing entity (e.g., a manufacturing facility or semiconductor foundry) can use the fabricated mask to fabricate circuits. In some embodiments, fabricating circuits may involve depositing one or more materials in / on a semiconductor wafer using a mask (or multiple masks). The semiconductor wafer may include a silicon substrate or other substrate on which material layers are formed. The semiconductor wafer may further include various doped regions, dielectric features, multilevel interconnects, and the like formed using one or more of the masks.

[0188] It should be understood that although the manufacturing tool 150 is described as performing certain operations for preparing and subsequently manufacturing the set of curtains, in some embodiments, the various processes may differ from those described. In some embodiments, additional or other processes or operations may be used to prepare and manufacture the set of curtains. It should also be understood that in Figure 1 Only some components of the computing system 100 are shown and described herein. However, the computing system 100 may include other components such as various batteries and power supplies, network interfaces, routers, switches, external memory systems, controllers, etc. Generally, the computing system 100 may include any of the various hardware, software, and / or firmware components that are required or deemed necessary in performing the functions described herein. Similarly, the host device 105, input device 115, output device 120, and memory device 110 including memory controller 140 and memory array 145 may each include other hardware, software, and / or firmware components that are deemed necessary or required in performing the functions described herein.

[0189] Transfer to Figure 2According to some embodiments of this disclosure, an example layout 200 implementing a clock tree is shown. Specifically, layout 200 includes a semiconductor substrate (hereinafter simply referred to as the "substrate") 205. Substrate 205 includes a first surface 210 and a second surface 215 opposite to the first surface. In some embodiments, the first surface 210 may be considered as a top surface (or top surface) or a front surface (or front face), and the second surface 215 may be considered as a bottom surface (or bottom face) or a back surface (or rear face). The "front" or "top" surface of substrate 205 is the surface or face on which active devices of integrated circuits (e.g., transistors, resistors, etc.) are formed. The opposite surface of the "front" or "top" surface is the "back" or "bottom" surface of substrate 205. In other words, the surface or face on which active devices of integrated circuits are not formed is the "back" or "bottom" surface of substrate 205. It should be understood that substrate 205 is shown as transparent or clear only to show the components on the first surface 210 and the second surface 215 and how these components are connected. The substrate 205 is generally opaque or not very transparent. Furthermore, although... Figure 2 It is not obvious from the outside, but the substrate 205 may have a specific thickness and the shape / size of the substrate may vary from one embodiment to another.

[0190] Conventionally, all integrated circuits and associated connections are formed on the first surface 210. Therefore, conventionally, a clock tree that provides clock signals to the integrated circuits is also provided on the first surface 210. Generally, a clock tree is a clock distribution network that provides clock signals to various components of the integrated circuit. The terms "clock signal," "clock," "clock pulse signal," "clock tree signal," "clock tree," and the like are used interchangeably herein. Clock tree signals can be routed throughout the integrated circuit using signal routing or routing resources (e.g., metal layers such as M0 layers, M1 layers, etc.). Routing resources used in this disclosure can be any type of suitable signal routing used to route electrical signals from one point on the integrated circuit to another. In some embodiments, the clock tree may include one or more reference clocks. In some embodiments, one or more reference clocks may be synthesized to produce one or more output clocks. The output clocks can be routed to various synchronization components of the integrated circuit to control the operation of these components. In some embodiments, each reference clock of the clock tree can be considered a clock "trunk," and each output clock of the clock tree can be considered a clock "branch" or "leaf." The terms "clock trunk," "clock trunk signal," and the like are used interchangeably herein. Similarly, the terms "clock leaf," "clock leaf signal," and the like are used interchangeably herein. Clock trunk signals and clock leaf signals can be routed throughout the integrated circuit using routing resources. Furthermore, in some embodiments, the clock tree can be designed with various topologies, such as mesh, H-tree, etc. Conventionally, the routing resources of the clock tree, including all clock trunks and all clock leaves, are provided on the first surface 210. Moreover, the routing resources of the clock tree, including all clock trunks and clock leaves, consume a significant area on the substrate 205.

[0191] Furthermore, in some embodiments, the clock signal, and particularly the clock trunk signal, may be a high-frequency signal that can be affected by adjacent signals. Since the clock signal can be considered a critical signal and can affect wafer speed in some embodiments, shielding of the routing resources surrounding the clock signal can be used to protect it. In some embodiments, power and ground signals (e.g., VDD (high voltage) and VSS (ground) power rails) that supply power to the integrated circuit on substrate 205 can be used to provide shielding to the clock tree. In some embodiments, shielding may involve sandwiching clock signal routing resources between two power and ground signal rails. For example, in some embodiments, clock signal routing resources may be sandwiched between a power signal (e.g., the VDD signal) and a ground signal (e.g., the VSS signal). In some embodiments, the power and ground signals may be provided on the second surface 215 and feed through substrate 205 to the first surface 210. By providing power and ground signals on the second surface 215, the standard cell height can be reduced and the voltage drop (IR) at higher nodes in the integrated circuit can be improved.

[0192] When power and ground signals are on the second surface 215 of substrate 205 and clock signals are on the first surface 210 of substrate 205, the power and ground signals that would otherwise be used to shield these clock signals need to be fed from the second surface to the front surface. This feedthrough of power and ground signals to the first surface 210 results in the consumption of additional routing resources. Therefore, in some embodiments, the routing resources of at least a portion of the clock signals of the clock tree can be routed on the second surface 215. By routing at least a portion of the clock tree on the second surface 215 (e.g., by providing its routing resources), the need to feed power and ground signals for shielding from the second surface 215 to the first surface 210 is avoided. Furthermore, by routing at least a portion of the clock tree on the second surface 215, the routing resources on the first surface 210 can be freed up and used by other components that would otherwise consume these routing resources for the clock signals.

[0193] Furthermore, by routing at least a portion of the clock tree on the second surface 215, routing resources for the clock tree can be provided using low-resistance interconnect layers without via stacking. Specifically, in some embodiments, when all clock signals of the clock tree are provided on the first surface 210, these clock signals can be provided in higher interconnect layers (e.g., metal 2, metal 3, etc.) to accommodate other integrated circuit components in lower interconnect layers. The higher the interconnect layer or the farther the signal originates from the substrate 205, the lower the resistance in that layer and the lower the resistance of the signals connected by these higher interconnect layers. However, to reach higher interconnect layers, via stacking may be required. Vias can be used to provide conductive connections from one conductive interconnect layer to another. By routing at least a portion of the clock tree on the second surface 215, similar resistance can be achieved without via stacking, or at least the number of vias that would otherwise be required on the first surface 210 can be reduced.

[0194] Therefore, routing at least a portion of the clock tree on the second face 215 utilizes power and ground signals on the second face, while providing the ability to route using lower resistance interconnect layers, reducing via stacking, and freeing up routing resources on the first face 210 for other signals. In some embodiments, the clock signals of the clock tree routed on the second face 215 may include those clock signals that need to be shielded. For example, in embodiments where clock trunk signals need to be shielded, clock trunk signals (including H-trees and meshes) may be routed on the second face 215, while clock leaf signals may continue to be routed on the first face 210. In other embodiments, if clock leaf signals need to be shielded, these clock signals may also be routed on the second face 215. In some embodiments, clock signals that do not necessarily need to be shielded may also be routed on the second face 215, and / or some clock signals that need to be shielded may continue to be routed on the first face 210 depending on the available backside resources on the second face 215. In some embodiments, the term "backside resources" may refer to backside pin connections on the second face 215. In some embodiments, the term "backside resource" may additionally or alternatively include other elements required for routing signals on the second surface 215. As discussed in more detail below, in some embodiments, the second surface 215 may not be configured with backside pin connections. In this case, bridging units (such as buffers or inverters) with pins on the second surface 215 may be inserted onto the substrate 205.

[0195] Figure 2 An example is shown where the clock trunk signal can be routed on the second face 215 and the clock leaf signal can be routed on the first face 210. Specifically, Figure 2The trunk-to-trunk interconnects on the left side of substrate 205 and the trunk-to-leaf interconnects on the right side of substrate 205 are shown. Since in some embodiments, clock trunk signals can be routed on the second surface 215, trunk-to-trunk interconnects can be formed on the second surface. Furthermore, since in some embodiments, clock trunk signals can be routed on the second surface 215 and clock leaf signals can be routed on the first surface 210, trunk-to-leaf interconnects can be formed by feeding clock trunk signals from the second surface to connect to clock leaf signals on the first surface. It should be understood that the trunk-to-trunk interconnects and trunk-to-leaf interconnects are shown only in separate portions of substrate 205 for ease of illustration. In other embodiments, trunk-to-trunk interconnects and trunk-to-leaf interconnects may be provided together or on separate substrates.

[0196] To form a trunk-to-trunk interconnect, routing resources of at least two clock tree signals (e.g., clock trunk signals 220A and 220B) may be interconnected. In some embodiments, clock trunk 220A (e.g., routing resources associated with clock trunk 220A) may be connected via via via 225 to a clock buffer or clock gate unit 230 that provides clock distribution and power consumption. Similarly, clock trunk 220B (e.g., routing resources associated with clock trunk 220B) may be connected via via 235 to the clock buffer or clock gate unit 230. Thus, the clock buffer or clock gate unit 230 provides an interconnection between the routing resources of clock trunk signals 220A and 220B via vias 225 and 235. In some embodiments, to provide an interconnection between multiple clock trunk signals, the clock buffer or clock gate unit 230 may be oriented / connected to have input and output pins on the same surface (e.g., second surface 215). In some embodiments, if the substrate 205 is configured with back-side pin connections on the second surface 215, the clock trunk signals 220A and 220B can be directly connected to those back-side pin connections without requiring a clock buffer or clock gate unit 230 or vias 225, 235. Furthermore, in some embodiments, the routing resources for the clock trunk signals 220A and 220B can be side-connected on either surface via a shield 240. In some embodiments, the shield 240 may be part of the power and ground signals provided on the second surface 215.

[0197] To form a trunk-to-leaf interconnect, the routing resources of the clock trunk signal on the second face 215 may need to be fed through and connected to the routing resources of one or more clock leaf signals on the first face 210. For example, the routing resources of the clock trunk signal 245 on the second face 215 may be connected to the routing resources of the clock leaf signals 250A and 250B on the first face 210. The routing resources of the clock trunk signal 245 may be connected to the clock buffer or clock gate unit 260 on the second face 215 via via 255. The routing resources of the clock leaf signals 250A and 250B may also be connected to the clock buffer or clock gate unit 260 on the first face 210 via one or more vias 265, 270A, 270B and one or more metal interconnect layers 275. Therefore, the clock buffer or clock gate unit 260 provides a conductive connection between the second face 215 and the first face 210.

[0198] In some embodiments, to facilitate the connection between clock signals on the first surface 210 and clock signals on the second surface 215, a clock buffer or clock gating unit 260 may include input pins on one surface (e.g., the second surface) and output pins on the other surface (e.g., the first surface). Examples of buffer units having input and output pins on opposite surfaces are discussed below. Therefore, clock buffers or clock gating units (e.g., clock buffers and gating units 230, 260) can be used to provide trunk-to-trunk interconnects and trunk-to-leaf interconnects. Furthermore, similar to clock trunk signals 220A and 220B with shield 240, clock trunk signal 245 may have shield 280. In some embodiments, shield 280 may be formed from power and ground signals on the second surface 215.

[0199] It should be understood that Figure 2 The trunk-to-trunk and trunk-to-leaf interconnect configurations shown are merely examples, and several variations are envisioned and considered within the scope of this disclosure. For example, although in Figure 2 The diagram illustrates only two clock trunk signals (e.g., clock trunk signals 220A and 220B) forming a trunk-to-trunk interconnect. However, in other embodiments, more than two clock trunk signals may be provided and interconnected to form a large trunk-to-trunk interconnect or multiple trunk-to-trunk interconnects. In other embodiments, a single clock trunk signal may be provided. Similarly, although each of clock trunk signals 220A and 220B is shown connected to the clock buffer or clock gating unit 230 via a single via (e.g., vias 225 and 235), in other embodiments, any or both of these clock trunk signals may be connected to the clock buffer or clock gating unit via one or more vias stacked on top of each other and / or via one or more back interconnect layers and a combination of one or more vias. The back interconnect layers will be described in more detail below.

[0200] Furthermore, although not shown, each of clock trunk signals 220A and 220B can be connected to one or more clock leaf signals on the first surface 210 to also form one or more trunk-to-leaf interconnects. For example, in some embodiments, clock trunk signal 220A can be connected via a via on the opposite surface 285 to a clock buffer or clock gating unit (similar to clock buffer or clock gating unit 260) to form one or more trunk-to-leaf interconnects, as explained above. Clock trunk signal 220B can similarly form one or more trunk-to-leaf interconnects. Furthermore, clock trunk signal 245 can be connected to other clock trunk signals to also form trunk-to-trunk interconnects. For example, clock trunk signal 245 can be connected via a via on the opposite surface 290 to a clock buffer or clock gating unit (similar to clock buffer or clock gating unit 230) to form one or more trunk-to-trunk interconnects, as explained above. It should also be understood that in other embodiments, the orientation, size, and shape of each of the clock trunk signals 220A, 220B, and 245 may differ from the orientation, size, and shape shown. Furthermore, although in Figure 2 The clock trunk signals 220A and 220B are shown generally in parallel, but in other embodiments, each of these clock trunk signals may be oriented in other directions and / or angles.

[0201] Additionally, although clock trunk signal 245 is shown as forming two trunk-to-leaf interconnects via connections to two clock leaf signals (e.g., clock leaf signals 250A and 250B), in other embodiments, the clock trunk signal may be connected to a single clock leaf signal or two or more clock leaf signals. In other embodiments, the shape, size, and orientation of each of the clock leaf signals 250A and 250B may differ. Furthermore, although each of the clock leaf signals 250A and 250B is shown as being connected to the clock buffer or clock gate unit 260 via specific connections of vias (e.g., vias 265, 270A, 270B) and metal layers (e.g., metal interconnect layer 275), in other embodiments, the number of vias and / or the number of metal layers may differ.

[0202] Furthermore, despite Figure 2 An example is described where the clock trunk signal is on the second surface 215 of the substrate 205 and the clock leaf signal is on the first surface 210 of the substrate 205. However, in other embodiments, one or more clock trunk signals may be on the first surface and / or one or more clock leaf signals may be on the second surface.

[0203] Now turn to Figure 3 According to some embodiments of this disclosure, another example layout 300 of a clock tree implementation is shown. Layout 300 shows a substrate 305. Figure 3The back side or second surface 310 of substrate 305 is shown. Second surface 310 is similar to second surface 215 of substrate 205. As shown above, in some embodiments, power and ground signals may be provided on the second surface of the substrate. Also as described above, in some embodiments, clock trunk signals may be provided on the second surface, and the power and ground signals may provide shielding to the clock trunk signals. In some embodiments, the power and ground signals and the clock trunk signals may be routed such that no additional routing resources are required to provide shielding to the clock trunk signals.

[0204] For example, such as Figure 3 As shown, in some embodiments, power and ground signals may be routed via a backside interconnect layer. Similar to the conductive interconnect layers (e.g., metal 0, metal 1, metal 2, etc.) on the first side (referred to herein as "frontside interconnect layer," "frontside metal layer," and the like), the second side 215 may have conductive interconnect layers or routing resources, referred to herein as "backside interconnect layer," "backside metal layer," and the like (e.g., backside metal 0, backside metal 1, backside metal 2, etc.). In some embodiments, the backside interconnect layer is the same as or substantially similar to the frontside interconnect layer in terms of manufacture and operation. In some embodiments, the backside interconnect layer may be slightly wider than the frontside interconnect layer. Because a wider interconnect layer has lower resistance, by using a wider backside interconnect layer on the second side 310, lower-level backside interconnect layers can be used on the second side to achieve the same or similar resistance as higher-level frontside interconnect layers.

[0205] Therefore, when power and ground signals are provided on the second surface 310, they can be routed via the back interconnect layer. For example, in some embodiments, power and ground signals 315 can be routed via back metal layer 1 and power and ground signals 320 can be routed via back metal layer 2. In some embodiments, power and ground signals 315 and 320 extend in an intersecting direction. Although power and ground signals 315 are shown extending in a generally vertical direction and power and ground signals 320 are shown extending in a generally horizontal direction, in other embodiments, these power and ground signals can extend in other directions. Furthermore, although power and ground signals 315 and 320 are shown to be routed via a specific level of back interconnect layer (e.g., back metal layer 1 and back metal layer 2), in other embodiments, these power and ground signals can be routed via other levels of back metal layers (e.g., back metal layer 0, back metal layer 3, etc.) and / or via additional or fewer back metal layers.

[0206] In some embodiments, clock trunk signals can be routed between two power and ground signal rails for natural shielding. For example, routing resources for clock trunk signal 325A can be provided between power and ground signal rails 330A and 330B. Similarly, routing resources for clock trunk signal 325B can be provided between power and ground signal rails 330B and 330C, and so on. Thus, clock trunk signals can be used alternately with power and ground signals, such that each clock trunk signal is separated from another clock trunk signal via shielded power and ground signal rails. Thus, clock trunk signal 325A can be shielded by power and ground signal rails 330A and 330B, and so on. Furthermore, routing resources for clock trunk signals 325A, 325B, and any other clock trunk signals extending in the same direction as power and ground signal rails 330A and 330B can be provided by a back-side interconnect layer of the same level. For example, if the power and ground signals 315 are provided by the back metal layer 1, then the routing resources for clock trunk signals 325A, 325B, etc., can also be provided by the back metal layer 1. Similarly, in some embodiments, the back metal layer 2 can be used for the clock trunk signal between the power signal and the ground signal 320. In some embodiments, instead of using a single power and ground signal track to separate the clock signals, more than one clock signal can be provided between two power and ground signal tracks. Similarly, in some embodiments, the two clock signals can be separated by more than one power and ground signal track.

[0207] refer to Figure 4 According to some embodiments of this disclosure, an example flowchart outlining a process 400 for performing a clock tree implementation layout as described above is shown. Process 400 may include other or additional operations depending on the embodiment. Process 400 may be implemented by a standard cell placement application 135. The clock tree implementation layout process 400 begins with a placement operation 405. During the clock tree implementation placement operation 405, the locations of various circuit components may be specified while various design constraints are optimized. Prior to placement operation 405, a netlist and design constraints may be entered into the standard cell placement application 135. The netlist may be a functionally equivalent logic gate-level circuit description provided via a synthesis process. The synthesis process forms a functionally equivalent logic gate-level circuit description by matching one or more behaviors and / or functions with (standard) cells in a set of cell libraries. Behaviors and / or functions may be specified based on various signals or stimuli of input applied to the overall design of the integrated circuit and may be written in a suitable language, such as a hardware description language. Similarly, design constraints can specify timing, process parameters, and other suitable constraints that must be followed once the network interconnects are physically formed into an integrated circuit.

[0208] At placement operation 405, the synthesized netlist and design constraints can be used to assign positions to various cells identified by the synthesized netlist. To minimize the wiring length and area requirements of the resulting integrated circuit, the placement of cells within a cell column and the placement of each cell column relative to other cell columns can be guided via a cost function. Placement can be performed automatically or manually, allowing the user to manually insert one or more cells into a cell column.

[0209] At operation 410, a clock tree synthesis operation is performed. During clock tree synthesis, clock signals may be distributed to synchronization components via integrated circuit design, and the clock tree may be synthesized using clock buffers or clock gating units. In some embodiments, clock tree synthesis may include routing clock signals to minimize wiring length and reduce area requirements to optimize clock signal routing. At operation 415, the clock trunk signal of the clock tree may be provided on the second surface 215 of substrate 205, and the clock leaf signal may be provided on the first surface 210. In some embodiments, the clock trunk signal may be alternated with power and ground signals on the second surface 215 to provide automatic shielding, as described above. Figure 3 As all instances of the cell and clock are placed, at operation 420, various signal connections can be routed using the front interconnect layer and the back interconnect layer, as described above. Routing using routing resources can be performed while taking into account time effects and minimizing violations of design rule checks.

[0210] After routing is completed, process 400 can determine whether the actual physical design of the entire integrated circuit matches the expected design requirements. Various design requirements can be checked by performing one or more simulations using a circuit simulator (e.g., a Simulation Program with Integrated Circuit Emphasis, SPICE), such as timing quality, power quality, and the presence of local congestion issues in the actual physical design of the entire integrated circuit. If all design requirements are met, process 400 can then manufacture, via manufacturing tool 150, a material to produce, for example, an optical lithography mask, which can be used to physically fabricate the physical design.

[0211] refer to Figure 5 According to some embodiments of this disclosure, examples of feedthrough lines on a semiconductor substrate are shown. The top-level design of an integrated circuit or wafer may include one or more blocks, which represent a hierarchical structure below the top-level design. Each block itself may include one or more sets of integrated circuits (e.g., combinations of standard cells) with a specified function. A feedthrough line is a signal line that enters the block from one edge and exits the block from the other edge, without actually connecting to any component on the integrated circuit block. For example, Figure 5 A top-level design 500 is shown, on which blocks 505 and 510 may exist. It should be understood that although two blocks (e.g., blocks 505 and 510) are shown on the top-level design 500, in other embodiments, the top-level design may have more or fewer than two blocks. Wires 515 can be considered feedthroughs of block 505, as these wires are not connected to any component of the block. More precisely, wires 515 connect to block 510 and simply pass through or cut through block 505.

[0212] Typically, feedthroughs (e.g., conductors 515) are routed using routing resources on the front side (e.g., first side 210) of a semiconductor substrate (e.g., substrate 205). Depending on the length of the feedthrough and other factors that may affect signal integrity, in some embodiments, one or more repeaters may be used to overcome the resistance of long conductors and maintain signal integrity. Feedthroughs also consume higher-resistance routing resources on the front side of the substrate that could otherwise be used for routing and connecting other components of the top-level design 500. In some embodiments, and as discussed below, at least some of the feedthroughs (e.g., conductors 515) may be routed using routing resources on the back side of the substrate (e.g., second side 215). By routing at least some feedthroughs on the back side of the substrate, routing resources on the front side can be freed up for use by other components. Furthermore, as mentioned above, a wider back-side interconnect metal layer with lower resistance can be used to provide routing resources on the back side. Therefore, by routing at least some feedthroughs on the back side of the substrate, the resistance of the feedthroughs on the back side is naturally reduced, thus requiring fewer repeaters to reduce the total repeater count in the top-level design 500. Repeaters themselves help reduce resistance. Therefore, by using a combination of repeaters and a low-resistance back-side interconnect metal layer, the total resistance of the feedthrough on the back side can be significantly reduced compared to the resistance of the conductors on the front side. Alternatively, and similar to clock tree implementations, power and ground signals can be used as shielding to reduce noise or crosstalk with other adjacent signals.

[0213] Transfer to Figure 6 According to some embodiments of this disclosure, an example layout 600 of a feedthrough line is shown. Layout 600 shows a substrate 605 having a first side 610 and a second side 615. The first side 610 is similar to the first side 210, and the second side 615 is similar to the second side 215. In other words, the first side 610 is the front side of the substrate 605, such that integrated circuits are formed on the first side, while the second side 615 is the back side of the substrate. Furthermore, it should be understood that the substrate 605 is made transparent to show the components on the second side 615 of the substrate. In other embodiments, the substrate 615 may be opaque. Additionally, in some embodiments, power and ground signals may be provided / routed on the second side 615, as described above. In some embodiments, a feedthrough line may also be provided / routed on the second side 615.

[0214] For example, and such Figure 6 As shown, a feedthrough 620 (e.g., feedthrough routing resources) may be provided on the second surface 615, thereby freeing up routing resources on the first surface 610. In some embodiments, a repeater may be used to route the feedthrough 620. In some embodiments, a buffer 625 (or inverter) may be used as a repeater. The buffer 625 may include input and output pins on the second surface 615 to which the feedthrough 620 may be connected. In some embodiments, the routing resources of the feedthrough 620 may be connected to the buffer 625 via vias 630 and 635. Specifically, in some embodiments, a first portion 640 of the routing resources of the feedthrough 620 may be connected to an input pin of the buffer 625 via via via 630, and a second portion 645 of the routing resources of the feedthrough may be connected to an output pin of the buffer via via 635, thereby maintaining continuity of conductive connection in the first and second portions of the feedthrough.

[0215] Although a single instance of buffer 625 has been shown herein, in other embodiments, multiple such buffers may be used as needed. In some embodiments, it may be desirable to have a buffer at each predetermined length of the routing resources of feeder 620. In other embodiments, other criteria may be used to determine where instances of buffer 625 are needed or desired. Furthermore, although Figure 6 The diagram shows routing resources for a single instance of feeder line 620, but it should be understood that in other embodiments, all or at least multiple feeders may be provided / routed on the second face 615 or otherwise on the first face 610.

[0216] Transfer to Figure 7A and Figure 7B According to some embodiments disclosed herein, the vertical and horizontal orientations of feedthrough lines are shown respectively. Specifically, the orientation of the input and output pins on the repeater may vary depending on the orientation of the feedthrough line's routing resources. In some embodiments, for feedthrough lines routed vertically or substantially vertically (e.g., from top to bottom), the repeater may have input and output pins also oriented in a vertical or substantially vertical direction. For example, and as... Figure 7A As shown, feedthrough 700 is routed on the back side (e.g., second side) 705 of substrate 710 using routing resources in a vertical or generally vertical orientation. Repeater 715 (e.g., buffer) can be used to route feedthrough 700. Repeater 715 may include input pin 720 and output pin 725. Input pin 720 and output pin 725 may be aligned in a vertical or generally vertical direction (e.g., stacked on top of each other) to allow the routing resources of feedthrough 700 to be routed vertically or generally vertically.

[0217] In some embodiments, for feedthroughs routed horizontally or substantially horizontally (e.g., from left to right), the repeater may have input and output pins that are also horizontally or substantially horizontally aligned. For example, and as Figure 7B As shown, the feedthrough line 730 can be routed using routing resources that extend horizontally or substantially horizontally on the back side (e.g., the second side) 735 of the substrate 740. A repeater 745 used with the feedthrough line 730 may include an input pin 750 and an output pin 755. The input pin 750 and the output pin 755 may also be aligned horizontally or substantially horizontally (e.g., side-by-side) to allow the routing resources of the feedthrough line 730 to be routed horizontally or substantially horizontally.

[0218] Now turn to Figure 8 According to some embodiments of this disclosure, another example layout 800 of a feedthrough implementation is shown. Layout 800 shows a substrate 805, and in particular, a back surface or second surface 810 of the substrate. The second surface 810 is similar to the second surface 615 of the substrate 605. As shown above, in some embodiments, power and ground signals may be provided along the feedthrough on the second surface 615 of the substrate 605. In some embodiments, the power and ground signals and routing resources of the feedthrough may be configured / routed on the second surface 810 such that no additional routing resources are required to provide shielding to the feedthrough via the power and ground signals.

[0219] Specifically, and as described above, when power and ground signals are provided on the second surface 810 of substrate 805, these signals can be routed via back-side interconnect layers (e.g., back-side metal 0, back-side metal 1, back-side metal 2, etc.). For example, in some embodiments, power and ground signal tracks 815 can be routed via a first back-side interconnect metal layer, and power and signal tracks 820 can be routed via a second back-side interconnect metal layer. In some embodiments, the first and second back-side interconnect metal layers extend in the intersection direction of different layers. Furthermore, although power and ground signal tracks 815 and 820 are shown as being routed via only two back-side interconnect metal layers, in other embodiments, power and ground signals can be routed via fewer or more than two back-side interconnect metal layers.

[0220] Furthermore, in some embodiments, the feedthrough line can be routed between the two power and ground signal rails using the same interconnect level / backside interconnect metal layer that extends in the same direction as the feedthrough line. For example, routing resources for feedthrough line 825 can be provided to alternate with power and ground signal rail 815 using a first backside interconnect metal layer. Similarly, routing resources for feedthrough line 830 can be provided to alternate with power and ground signal rail 820 using a second backside interconnect metal layer. Thus, each feedthrough line can be alternated with power and ground signals, such that each feedthrough line is separated from another feedthrough line by providing shielded power and ground signal rails. In some embodiments, instead of using power and ground signal rails to separate the feedthrough lines, more than one feedthrough line can be provided between two power and ground signal rails. Similarly, in some embodiments, two feedthrough lines can be separated by more than one power and ground signal rail.

[0221] refer to Figure 9 According to some embodiments of this disclosure, an example layout 900 of a back-side layer lift-up implementation is shown. Using a back-side layer lift-up implementation, timing critical nets can be moved from the front side of the substrate to the back side of the substrate. In conventional implementations, timing critical connections are typically lifted to a higher metal layer on the front side of the substrate to reduce the resistance of these critical connections. To lift timing critical connections to a higher metal layer, via stacking is used, such that multiple vias can be stacked on top of each other to reach a higher metal layer. In some embodiments, instead of using via stacking to reach a lower resistance metal layer, back-side resources on the substrate can be used. Specifically, in some embodiments, timing critical nets can be moved to the back side of the substrate to achieve resistance that is the same as, similar to, or even lower than that on the front side of the substrate.

[0222] Therefore, as Figure 9As shown, substrate 905 includes a first surface 910 and a second surface 915. First surface 910 is similar to first surface 210 and corresponds to the front side of substrate 905. Second surface 915 is similar to second surface 215 and corresponds to the back side of substrate. Substrate 905 is shown as transparent only to illustrate the characteristics of the back side of substrate. In other embodiments, substrate 905 does not need to be transparent. As described above, the back interconnect layer used on the second surface 915 of substrate 905 may be a wider metal layer than the front interconnect layer used on the first surface 910 of substrate 905. Due to its greater width, the back interconnect metal layer may be a lower resistance layer. Therefore, using a back interconnect layer on the second surface 915 can achieve the same, similar, or even lower resistance compared to using a front interconnect layer on the first surface 910, making the back interconnect layer a suitable choice for timing-critical interconnects. Furthermore, compared to the higher metal layer required on the first surface 910, a lower-level back interconnect layer can be used on the second surface 915 to achieve the same, similar, or even lower timing-critical interconnect resistance. Therefore, via stacking can be completely avoided, or at least a lower via stacking may be required to achieve the same, similar, or lower resistance on the second side 915 as on the first side 910.

[0223] For example, routing resources for signal 920 may be provided on the second surface 915. In some embodiments, signal 920 may be a timing critical connection typically provided on the first surface 910 using a higher metal layer to achieve lower resistance. In other embodiments, signal 920 may be another type of critical or non-critical connection or long connection that typically uses a higher metal layer to provide on the first surface 910, or requires lower or lower resistance compared to other connections on the first surface. Signal 920 may be fed through to connect to other connections on the first surface 910. In some embodiments, buffers 925 and 930 may be used to feed signal 920 to the first surface 910. In some embodiments, the ends of the routing resources of signal 920 may be connected to buffers 925 and 930 on the second surface 915 using vias 935 and 940, respectively. Similarly, on the first surface 910, buffers 925 and 930 may be connected to routing resources of other signals 945 and 950 using vias 955 and 960, respectively. Therefore, buffers 925 and 930 can facilitate the feedthrough of signal 920 from the second surface 915 to the first surface 910, while providing the ability to achieve a low-resistance metal layer without via stacking.

[0224] For example, to allow current to flow from signal 945 to signal 950 using signal 920, buffers 925 and 930 and their respective routing resources, in some embodiments, buffer 925 may have an input pin on a first face 910 and an output pin on a second face 915, while buffer 930 may have an input pin on the second face and an output pin on the first face to provide a connection in the direction indicated by arrow 965. Similarly, in some embodiments where current is desired to flow from connection 950 to connection 945, buffer 930 may have an input pin on the first face 910 and an output pin on the second face 915, while buffer 925 may have an input pin on the second face and an output pin on the first face to provide a connection in the direction opposite to that indicated by arrow 965. Therefore, depending on the desired connection, buffers with input and output pins on appropriate faces can be used. In some embodiments, inverters may be used instead of buffers. Inverters may have a pin configuration similar to the buffers discussed above. In some embodiments, if the substrate 905 is configured with a backside resource to include pins on the second surface 915, then the buffer 925 and / or 930 may not be necessary, and the signal 920 may be directly connected to the pins of the backside resource.

[0225] Furthermore, in some embodiments, if signal 920 is used to connect to another connection also on the second surface 915, buffer 925 and / or 930 may have input and output pins on the second surface.

[0226] Transfer to Figure 10 According to some embodiments of this disclosure, an outline is shown for providing Figure 9 The diagram illustrates an example flowchart of the operation of process 1000, implemented with a back-side layer lift. Process 1000 can be implemented using a standard cell layout application 135. At operation 1005, a low-resistance connection can be identified on the first surface 910 to move to the second surface 915. It should be understood that what constitutes "low" resistance can be predefined, and connections that meet the definition of "low" resistance can be identified in this operation. For example, in some embodiments, connections on or above a specific metal layer (e.g., metal 2, metal 3, etc.) on the front side can be designated as low-resistance connections. In other embodiments, connections requiring a resistance at a certain predefined value can be considered low-resistance connections.

[0227] At operation 1010, at least a subset of low-resistance interconnects may be selected to move to the second surface 915 of substrate 905. In some embodiments, timing critical-length interconnects may be selected to move to the second surface 915. In other embodiments, other types of low-resistance interconnects identified at operation 1005 may additionally or alternatively be selected to move to the second surface 915. At operation 1015, if the second surface 915 is configured with back-side pins, each of the timing critical-length interconnects may be connected to these pins without requiring the buffers described above to provide feedthrough to the first surface 910. If the second surface 915 of substrate 905 is not configured with back-side pins, in some embodiments, a pair of buffers (e.g., buffers 925, 930) or inverters may be inserted for each of the timing critical-length interconnects moved to the second surface 915 and connected via vias (e.g., vias 930, 935) as described above to connect the timing critical-length interconnects to other interconnects on the first surface 910.

[0228] Now for reference Figures 11A to 11C According to some embodiments of this disclosure, an example configuration of input and output pins on a unit 1100 for back-side routing of a substrate 1105 is shown. The substrate 1105 includes a first surface 1110 similar to a first surface 210 and a second surface 1115 similar to a second surface 215. Therefore, the first surface 1110 can be considered as the front side, and the second surface 1115 as the back side. Conventionally, all input and output pins of the unit 1100 are provided on the first surface 1110. However, to provide back-side routing and to bridge connections or wiring on the second surface 1115 with connections or wiring on the first surface 1110, alternative pin configurations are required. For example, in some embodiments, to bridge connections or wiring on the second surface 1115 with connections or wiring on the first surface 1110, such as... Figure 11A As shown, an input pin 1120 may be provided on the first side 1110 and an output pin 1125 may be provided on the second side 1115. Alternatively, and as... Figure 11B As shown, in some embodiments, in order to bridge the connections or wiring on the second surface 1115 with the connections or wiring on the first surface 1110, an input pin 1120 may be provided on the second surface and an output pin 1125 may be provided on the first surface.

[0229] In some embodiments, the wiring on the second surface 1115 may be connected to other wiring on the second surface. To facilitate such connection, in some embodiments, unit 1100 may include input pins 1120 and output pins 1125 both located on the second surface 1115 of the unit. In some embodiments, unit 1100 including input pins 1120 and output pins 1125 both located on the second surface 1115 of the unit may be similar to a unit having input and output pins on the first surface 1110, but may be modified to connect to the second surface instead of the first surface, such that the input and output pins extend outward from the second surface to facilitate connection. In some embodiments, unit 1100 may be a buffer unit or inverter unit as described in the above figure. In other embodiments, unit 1100 may be another type of unit that can be used to bridge connections or wiring on the second surface 1115 to connections or wiring on the first surface 1110.

[0230] Turning Figures 12A to 12D According to some embodiments of this disclosure, an example layout of a buffer unit 1200 having input pins on one side of a substrate and output pins on the other side of the substrate is shown. For example, the buffer unit 1200 is shown with input pins 1205 on a second side 1210 of a substrate 1215 and output pins 1220 on a first side 1225 of the substrate. The first side 1225 is similar to the first side 210 and is considered the front side of the substrate 1215, while the second side 1210 is similar to the second side 215 and is considered the back side of the substrate. The substrate 1215 is shown as transparent for illustrative purposes only. In other embodiments, the substrate 1215 does not need to be transparent.

[0231] Furthermore, in some embodiments, a back interconnect metal layer 0 (e.g., a back BM0 layer) may be used to provide input pins 1205 (e.g., input terminals), and a front interconnect metal layer 0 (e.g., a front BM0 layer) may be used to provide output pins 1220 (e.g., output terminals). In other embodiments, input pins 1205 and / or output pins 1220 may be provided using other back interconnect metal layers and front interconnect metal layers, respectively. Although the buffer 1200 has been shown with input pins 1205 on the second surface 1210 and output pins 1220 on the first surface 1225, in other embodiments, the buffer may be similarly provided such that it has input pins on the first surface and output pins on the second surface. When the input 1205 is on one side of the substrate 1215 (e.g., the second side 1210) and the output pin 1220 is on the other side of the substrate 1215 (e.g., the first side 1225), the buffer 1200 can be used as a bridging mechanism to route signals (e.g., from input to output) between the first side and the second side.

[0232] Figure 12BA top view of an example layout of buffer 1200 on the first surface 1225 is shown. Figure 12C A top view of an example layout of the buffer on the second surface 1210 is shown, and Figure 12D An example cross-sectional layout of the buffer is shown. The layout of the buffer 1200 on the first surface 1225 may include a first active region 1230A and a second active region 1230B to form the source and drain terminals of the transistors in the buffer 1200. The first active region 1230A and the second active region 1230B may each be a fin region of one or more three-dimensional field-effect transistors (e.g., FinFET, Gate all around (GAA) transistors), or an oxide-definition (OD) region of one or more planar metal-oxide-semiconductor field-effect transistors (MOSFETs), such that the active region can be used as a source or drain feature of the respective transistor(s). The first active region 1230A and the second active region 1230B may each extend along a cell column direction (such as the X direction). Furthermore, in some embodiments, the first active region 1230A and the second active region 1230B may be n-type or p-type.

[0233] The layout of the buffer 1200 on the first surface 1225 may also include gate structures 1235A, 1235B, and 1235C covering the first active region 1230A and the second active region 1230B. The gate structures 1235A-1235C may be formed of one or more conductive materials (e.g., polysilicon (various types), metal (various types)). The gate structures 1235A-1235C may define the gate terminals of the transistors in the buffer 1200, such that the first active region 1230A and the second active region 1230B on the left and right sides of the covering gate structures define the source and drain of the transistors in the buffer 1200. The input pin 1205 may be connected to the output pin 1220 via one or more of the first active region 1230A, the second active region 1230B, and the gate structures 1235A-1235C. For example, in some embodiments, gate structures 1235A and 1235B may extend continuously from the first active region 1230A to the second active region 1230B. In other embodiments, gate structure 1235C may be a dummy gate structure, with a first portion 1240A of gate structure 1235C extending above the first active region and a second portion 1240B of gate structure 1235C extending above the second active region, such that the first portion and the second portion are not connected. In some embodiments, the first portion 1240A may be connected to VDD (e.g., a high voltage level) and the second portion 1240B may be connected to VSS (e.g., a ground voltage level) to disable gate structure 1235C.

[0234] Furthermore, in some embodiments, the gate structure 1235A may be connected to the output pin 1220 and may be connected to the first active region 1230A via a first conductive layer 1245A (e.g., a metal 0 layer) connected to the gate structure 1235A. The first conductive layer 1245A may be connected to a second interconnect layer 1245B (e.g., a metal oxide layer) via a via 1250A. The via 1250B may connect the gate structure 1235A to a third interconnect layer 1245C (e.g., a metal 0 layer), the via 1250C may connect the third interconnect layer to a fourth interconnect layer 1245D (e.g., a metal oxide layer), the via 1250D may connect a fifth interconnect layer 1245E (e.g., a metal 0 layer) to a sixth interconnect layer 1245F (e.g., a metal oxide layer), and the via 1250E may connect the fifth interconnect layer to the polysilicon region 1235B. The connection between input pin 1205 and output pin 1220 can be established via a sixth interconnect layer to vias 1250D and 1250E to gate structure 1235B, as shown by arrow 1255A. Based on the input signal, the fourth interconnect layer 1245D may have VDD (e.g., a high voltage level) or VSS (e.g., a low voltage level), which can be passed to the transistor gate represented by gate structure 1235A, as shown by arrow 1255B. Based on the VDD or VSS voltage signal passed to gate structure 1235A, the second interconnect layer 1245B has VDD or VSS voltages respectively, serving as the output on output pin 1220.

[0235] Figure 12C An example layout of the buffer 1200 on the second surface 1210 is shown. This layout includes a third active region 1260A and a fourth active region 1260B. The third active region 1260A and the fourth active region 1260B may be fin regions of one or more three-dimensional field-effect transistors (e.g., FinFETs, Gate all around (GAA) transistors) or oxide-definition (OD) regions of one or more planar metal-oxide-semiconductor field-effect transistors (MOSFETs), such that the active regions can be used as source or drain features of the respective transistors. The third active region 1260A and the fourth active region 1260B may each extend along a cell column direction (such as the X direction). Furthermore, in some embodiments, the third active region 1260A and the fourth active region 1260B may be n-type or p-type. In some embodiments, the third active region 1260A may correspond to (e.g., be aligned with) the first active region 1230A on the first surface 1225, and the fourth active region 1260B may correspond to (e.g., be aligned with) the second active region 1230B on the first surface.

[0236] In some embodiments, the layout of the buffer 1200 on the second surface 1210 does not include any gate structure. Figure 12C The gate structures 1235A-1235C are shown only to illustrate the location of these regions on the first surface 1225. Input pin 1205 is connected to the second active region 1230B via a back interconnect metal layer (e.g., back metal layer 0) 1265 and a via 1270, as shown. Figure 12C The cross-sectional layout is shown. Figure 12C The layout also shows VDD pin 1275 and VSS pin 1280, representing the power and ground signals on the second side 1210.

[0237] Now turn to Figure 13 According to some embodiments of this disclosure, an example flowchart outlining the operation of process 1300 is shown. Process 1300 may be implemented by a standard layout application 135. Process 1300 may include other or additional operations in other embodiments. At operation 1305, one or more signals that will move from the front side of the substrate to the back side of the substrate are identified. In some embodiments, the one or more signals may be clock tree signals, feedthroughs, and / or timing critical long interconnects. In other embodiments, other or additional signals may be identified for moving from the front side of the substrate to the back side. At operation 1310, if the substrate is not configured for back-side connectivity, one or more buffers or inverters are inserted on the substrate. For example, if the substrate is not configured with back-side connectivity pins, one or more buffers or inverters with pins on the back side may be inserted. The number of buffers / inverters may vary depending on the signals that will move to the back side of the substrate and how these signals will connect to other signals. Furthermore, each buffer / inverter may need to have pins on either the front or back side of the substrate, depending on the configuration.

[0238] For example, to connect a clock trunk signal on the back side of a substrate to a clock leaf signal on the front side of the substrate, a buffer with input pins on the back side and output pins on the front side can be inserted. To connect a clock trunk signal to another clock trunk signal, a buffer with both input and output pins on the back side of the substrate can be inserted. Similarly, for feedthrough signals, a buffer with both input and output pins on the back side can be inserted. For timing-critical interconnects, a pair of buffers can be inserted, each buffer having input pins on one side and output pins on the other side, as described above.

[0239] When one or more buffers / inverters are inserted, at operations 1315 and 1320, the routing resources of the signal (e.g., the first signal) identified at operation 1305 can be connected to a pin on the back of the buffer, and another signal to which the first signal is connected can be connected to another pin of the buffer. In some embodiments, the first signal can be provided to be used alternately with power and ground signals to provide natural shielding.

[0240] Therefore, this disclosure provides a mechanism for moving or routing certain signals from the front side of a substrate to the back side of the substrate, utilizing power and ground signals on the back side of the substrate for shielding, reducing resistance, and freeing up resources on the front side of the substrate for other purposes, thereby reducing wafer area and improving speed / performance. In some embodiments, signals such as clock tree signals, feedthroughs, and / or timing-critical long interconnects may be routed on the back side of the substrate. In other embodiments, other or additional signals may be routed on the back side of the substrate. In some embodiments, the substrate may have been configured for back-side connectivity. For example, in some embodiments, the back side of the substrate may include pins on the back side to allow signal connections and feed signals from the back side of the substrate to the front side of the substrate. In other embodiments, if back-side pin connections are not provided on the back side of the substrate, a buffer or inverter having input pins on one side (e.g., front or back) and output pins on the other side (e.g., back or front) may be used to bridge signals from the back side to the front side and vice versa.

[0241] According to some embodiments of this disclosure, a system is disclosed. The system includes a substrate having a first surface and a second surface. An active device of an integrated circuit formed on the substrate is on the first surface, and the second surface is opposite to the first surface. The system also includes a cell on the substrate having a first pin on the first surface or the second surface, and a second pin on the second surface, with a first signal route connected to the first pin and a second signal route connected to the second pin. According to some embodiments of this disclosure, the first pin is on the first surface, and the first signal route is used to route a clock leaf signal and the second signal route is used to route a clock trunk signal. According to some embodiments of this disclosure, the first pin is on the second surface, and the first signal route is used to route a first clock trunk signal and the second signal route is used to route a second clock trunk signal. According to some embodiments of this disclosure, the first clock trunk signal is separated from the second clock trunk signal via a power and ground signal rail on the second surface. According to some embodiments of this disclosure, a first pin is on a second surface, and a first signal route is used to route a first feedthrough portion of a feedthrough line, and a second signal route is used to route a second feedthrough portion of the feedthrough line. According to some embodiments of this disclosure, the feedthrough line extends vertically, and the first pin and the second pin are vertically aligned. According to some embodiments of this disclosure, the feedthrough line extends horizontally, and the first pin and the second pin are horizontally aligned. According to some embodiments of this disclosure, the feedthrough line is separated from an adjacent feedthrough line by a power and ground signal rail on the second surface. According to some embodiments of this disclosure, the system further includes another unit on the substrate, the other unit having a third pin on a first surface and a fourth pin on a second surface; and a third signal route on the first surface, the third signal route being connected to the third pin, wherein the first pin is on the first surface; wherein the first signal route is connected to the third signal route via a second signal route, such that one end of the second signal route is connected to the second pin and the other end of the second signal route is connected to the fourth pin. According to some embodiments of this disclosure, the second signal route is a timing-critical network. According to some embodiments of this disclosure, the unit is a buffer or an inverter. According to some embodiments of this disclosure, a first signal route is connected to a first pin via a first via. According to some embodiments of this disclosure, a second signal route is connected to a second pin via a second via.

[0242] According to some other embodiments of this disclosure, a method is disclosed. The method includes identifying a signal route on a first surface of a substrate to move to a second surface of the substrate. An active device of an integrated circuit formed on the substrate is on the first surface, and the second surface is opposite to the first surface. The method also includes inserting a cell on the substrate having a first pin on the first surface or a second pin on the second surface, connecting a signal route to the second pin, and connecting the signal route to the other signal route by connecting another signal route to the first pin. According to some embodiments of this disclosure, the method further includes connecting the signal route to the second pin via a first via. According to some embodiments of this disclosure, the method further includes connecting the other signal route to the first pin via a second via.

[0243] According to another embodiment of this disclosure, an apparatus is disclosed. The apparatus includes a substrate having a first surface and a second surface. An active device formed on the substrate is on the first surface, and the second surface is opposite to the first surface. The apparatus also includes an output pin on the first surface, an input pin on the second surface, a first active region on the first surface, and a second active region on the first surface. To connect the input pin to the output pin, the input pin is connected to the first active region, the output pin is connected to the second active region, and the first active region is connected to the second active region. According to some embodiments of this disclosure, the apparatus further includes: a third active region on the second surface, corresponding to the first active region; and a fourth active region on the second surface, corresponding to the second active region. According to some embodiments of this disclosure, the first active region is connected to the second active region via a first gate structure and a second gate structure. According to some embodiments of this disclosure, the output pin is connected to a front metal layer 0 and the input pin is connected to a back metal layer 0.

[0244] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A system for back-side signal routing, characterized in that, Include: A substrate has a first surface and a second surface, wherein an active device of an integrated circuit formed on the substrate is on the first surface and the second surface is opposite to the first surface; A unit, on the substrate, has a first pin on a first surface and a second pin on a second surface; A first signal route, connected to the first pin for routing a clock leaf signal; and A second signal route is connected to the second pin to route a clock trunk signal.

2. The system according to claim 1, characterized in that, This unit is a buffer or an inverter.

3. The system according to claim 1, characterized in that, The first signal route is connected to the first pin via a first through-hole.

4. The system according to claim 1, characterized in that, The second signal route is connected to the second pin via a second through-hole.

5. A system for rear-side signal routing, characterized in that, Include: A substrate has a first surface and a second surface, wherein an active device of an integrated circuit formed on the substrate is on the first surface and the second surface is opposite to the first surface; A unit, on the substrate, has a first pin on the second surface and a second pin on the second surface; A first signal route is connected to the first pin; and A second signal route is connected to this second pin. The first signal route is used to route a first clock trunk signal, and the second signal route is used to route a second clock trunk signal.

6. The system according to claim 5, characterized in that, The first signal route is connected to the first pin via a first through-hole, and the second signal route is connected to the second pin via a second through-hole.

7. The system according to claim 5, characterized in that, The first clock trunk signal is separated from the second clock trunk signal via a power and ground signal track on the second surface.

8. A system for back-side signal routing, characterized in that, Include: A substrate has a first surface and a second surface, wherein an active device of an integrated circuit formed on the substrate is on the first surface and the second surface is opposite to the first surface; A unit, on the substrate, has a first pin on the second surface and a second pin on the second surface; A first signal route is connected to the first pin; and A second signal route is connected to this second pin. The first signal route is used to route a first feeder section of a feeder line, and the second signal route is used to route a second feeder section of the feeder line.

9. The system according to claim 8, characterized in that, The feedthrough extends in a vertical direction, and the first pin is perpendicularly aligned with the second pin.

10. The system according to claim 8, characterized in that, The feedthrough extends horizontally, and the first pin is horizontally aligned with the second pin.

11. The system according to claim 8, characterized in that, The feeder is separated from an adjacent feeder by a power and ground signal track on the second surface.

12. A system for back-side signal routing, characterized in that, Include: A substrate has a first surface and a second surface, wherein an active device of an integrated circuit formed on the substrate is on the first surface and the second surface is opposite to the first surface; A first unit, on the substrate, has a first pin on a first surface and a second pin on a second surface; A second unit, on the substrate, has a third pin on the first surface and a fourth pin on the second surface; A first signal route is connected to the first pin; A second signal route is connected to this second pin; A third signal route is provided on the first surface and connected to the third pin. The first signal route is connected to the third signal route via the second signal route, such that one end of the second signal route is connected to the second pin and the other end of the second signal route is connected to the fourth pin; and The second signal route is a time-critical network.

13. The system according to claim 12, characterized in that, The first and second units are a buffer or an inverter.

14. A method for generating a layout of an integrated circuit, characterized in that, Include: A signal route is identified on a first surface of a substrate to move to a second surface of the substrate, wherein an active device of the integrated circuit formed on the substrate is on the first surface and the second surface is opposite to the first surface; A unit having a first pin on the first surface or a second pin on the second surface is inserted into the substrate; Connect the signal route to this second pin; and The signal route is connected to the other signal route by connecting the other signal route to the first pin.

15. The method according to claim 14, characterized in that, It further includes: routing the signal to the second pin via a first through-hole.

16. The method according to claim 15, characterized in that, It further includes: routing the other signal to the first pin via a second via.

17. The method according to claim 14, characterized in that, This unit is a buffer or an inverter.

18. The method according to claim 14, characterized in that, The signal route contains a clock tree signal.

19. The method according to claim 14, characterized in that, The signal route includes a feeder line.

20. The method according to claim 14, characterized in that, The signal routing includes a timing critical network.

21. An integrated circuit device, characterized in that, Include: A substrate has a first surface and a second surface, wherein an active device formed on the substrate is on the first surface and the second surface is opposite to the first surface; One output pin on the first surface; An input pin on the second surface; A first active region on the first surface; and In the second active region of the first surface, In order to connect this input pin to this output pin: Connect the input pin to the first active area; Connect the output pin to the second active area; and Connect the first active region to the second active region.

22. The integrated circuit device according to claim 21, characterized in that, A third active region on the second surface, the third active region corresponding to the first active region; and a fourth active region on the second surface, the fourth active region corresponding to the second active region.

23. The integrated circuit device according to claim 21, characterized in that, The first active region is connected to the second active region through a first gate structure and a second gate structure.

24. The integrated circuit device according to claim 23, characterized in that, The first gate structure is connected to the first active region through a first conductive layer.

25. The integrated circuit device according to claim 23, characterized in that, It further includes a third gate structure, which includes a first gate portion extending over the first active region and a second gate portion extending over the second active region.

26. The integrated circuit device according to claim 25, characterized in that, The first gate portion is connected to a high voltage level and the second gate portion is connected to a ground voltage level.

27. The integrated circuit device according to claim 25, characterized in that, The first gate portion is not connected to the second gate portion.

28. The integrated circuit device according to claim 21, characterized in that, The output pin is connected to a front-side metal 0 layer.

29. The integrated circuit device according to claim 21, characterized in that, The input pin is connected to a metal layer 0 on the back.

30. A system for rear-side signal routing, characterized in that, Include: A substrate has a first surface and a second surface, wherein an active device formed on the substrate is on the first surface and the second surface is opposite to the first surface; An apparatus comprising: The first joint on the first surface; A second pin on the second surface; A first active region on the first surface; and In a second active region on the first surface, the first pin is connected to the second pin via the first active region, the second active region, and one or more gate structures; A first signal route, connected to the first pin for routing a clock leaf signal; and A second signal route is connected to the second pin to route a clock trunk signal.

31. The system according to claim 30, characterized in that, The one or more gate structures include a first gate structure and a second gate structure, and the first active region is connected to the second active region through the first gate structure and the second gate structure.

32. The system according to claim 31, characterized in that, The one or more gate structures include a third gate structure, which includes a first gate portion extending over the first active region and a second gate portion extending over the second active region.

33. The system according to claim 30, characterized in that, The device further includes: A third active region on the second surface, the third active region corresponding to the first active region; and A fourth active region on the second surface, the fourth active region corresponding to the second active region.

34. The system according to claim 30, characterized in that, The first pin is connected to a front metal layer 0 and the second pin is connected to a back metal layer 0.

35. A system for rear-side signal routing, characterized in that, Include: A substrate has a first surface and a second surface, wherein an active device of an integrated circuit formed on the substrate is on the first surface and the second surface is opposite to the first surface; A first device, on the substrate, the first device comprising: The first joint on the first surface; A second pin on the second surface; A first active region on the first surface; and In a second active region on the first surface, the first pin is connected to the second pin via the first active region, the second active region, and one or more first gate structures; A second device, on the substrate, the second device comprising: A third joint on the first surface; A fourth pin on the second surface; A third active region on the first surface; and In a fourth active region on the first surface, the third pin is connected to the fourth pin via the third active region, the fourth active region, and one or more second gate structures; A first signal route is connected to the first pin; A second signal route is connected to this second pin; A third signal route is provided on the first surface and connected to the third pin. The first signal route is connected to the third signal route via the second signal route, such that one end of the second signal route is connected to the second pin and the other end of the second signal route is connected to the fourth pin.

36. The system according to claim 35, characterized in that, The second signal route is a time-critical network.

37. The system according to claim 35, characterized in that, The one or more first gate structures include: A first continuous gate structure and a second continuous gate structure, wherein the first active region is connected to the second active region through the first continuous gate structure and the second continuous gate structure, and A third gate structure comprising a first gate portion extending over the first active region and a second gate portion extending over the second active region. The one or more second gate structures include: A third continuous gate structure and a fourth continuous gate structure, wherein the third active region is connected to the fourth active region through the third continuous gate structure and the fourth continuous gate structure, and A fourth gate structure comprising a third gate portion extending over the third active region and a fifth gate portion extending over the fourth active region.

38. The system according to claim 35, characterized in that, The first device further includes: A fifth active region on the second surface, the fifth active region corresponding to the first active region; and A sixth active region on the second surface, the sixth active region corresponding to the second active region.

39. The system according to claim 38, characterized in that, The second device further includes: A seventh active region on the second surface, the seventh active region corresponding to the third active region; and An eighth active region on the second surface, which corresponds to the fourth active region.

40. A system for back-side signal routing, characterized in that, Include: A substrate has a first surface and a second surface, wherein the second surface is opposite to the first surface, and an active device of an integrated circuit formed on the substrate is on the first surface; A unit, on the substrate, has a first pin on the first surface or the second surface, and a second pin on the second surface; A first signal route is provided on the second surface for routing a first power supply and ground signal rail; A second signal route, on the second surface, is used to route a second power supply and grounding signal rail; and A third signal route is connected to the second pin and used on the second surface to route a first clock trunk signal, wherein the third signal route is between the first signal route and the second signal route.

41. The system according to claim 40, characterized in that, The first pin is on the second surface, wherein the system further includes a fourth signal route on the second surface for routing a second clock trunk signal; and the second clock trunk signal is connected to the first pin to form a trunk-to-trunk interconnect.

42. The system according to claim 41, characterized in that, The first clock trunk signal is connected to the second pin via a first through-hole, and the second clock trunk signal is connected to the first pin via a second through-hole.

43. The system according to claim 41, characterized in that, The fourth signal route is located between the second signal route and a fifth signal route to be used on the second surface to route a third power supply and grounding signal rail.

44. The system according to claim 40, characterized in that, The first pin is on the first surface, wherein the system further includes a fourth signal route on the first surface for routing a clock leaf signal; and wherein the third signal route is connected to the second pin via a first via and the fourth signal route is connected to the first pin via a second via to form a trunk-to-leaf interconnect.

45. The system according to claim 44, characterized in that, The fourth signal route is further connected to the first pin on the first surface via one or more metal interconnect layers.

46. ​​The system according to claim 40, characterized in that, This unit contains a buffer or an inverter.

47. The system according to claim 40, characterized in that, The first signal route, the second signal route, and the third signal route are each provided using the same level of back-side interconnect metal layer.

48. The system according to claim 40, characterized in that, Further includes: A fourth signal route is provided on this second surface for routing a third power supply and ground signal rail; A fifth signal route is provided on this second surface for routing a fourth power supply and ground signal rail; and A sixth signal route is provided on the second surface for routing a second clock trunk signal. The first, second, and third signal routes extend in a first direction, while the fourth, fifth, and sixth signal routes extend in a second direction different from the first direction.

49. The system according to claim 40, characterized in that, Each of the first signal route, the second signal route, and the third signal route is provided using a back-side interconnect layer, which is wider than the front-side interconnect layer used on the first side.

50. A system for rear-side signal routing, characterized in that, Include: A substrate has a first surface and a second surface, wherein the second surface is opposite to the first surface, and an active device of an integrated circuit formed on the substrate is on the first surface; A unit, on the substrate, has a first pin on the second surface and a second pin on the second surface; A first signal route is provided on the second surface for routing a first power supply and ground signal rail; A second signal route, on the second surface, is used to route a second power supply and grounding signal rail; and A third signal route is provided on the second surface for routing a first feeder line, wherein the third signal route is between the first signal route and the second signal route.

51. The system according to claim 50, characterized in that, A first portion of the first feedthrough line is connected to the first pin, and a second portion of the first feedthrough line is connected to the second pin.

52. The system according to claim 51, characterized in that, The first portion of the first feedthrough line is connected to the first pin via a first through hole, and the second portion of the first feedthrough line is connected to the second pin via a second through hole.

53. The system according to claim 50, characterized in that, The first signal route, the second signal route, and the third signal route are each provided using the same level of back-side interconnect metal layer.

54. The system according to claim 50, characterized in that, Each of the first signal route, the second signal route, and the third signal route is provided using a back-side interconnect layer, which is wider than the front-side interconnect layer used on the first side.

55. The system according to claim 50, characterized in that, Further includes: A fourth signal route is provided on this second surface for routing a third power supply and ground signal rail; A fifth signal route, used on the second surface to route a fourth power supply and ground signal rail; and A sixth signal route, used on this second plane to route a second feeder line, The first signal route, the second signal route, and the third signal route extend in a first direction, while the fourth signal route, the fifth signal route, and the sixth signal route extend in a second direction different from the first direction.

56. The system according to claim 50, characterized in that, This unit is a buffer or an inverter.

57. A system for rear-side signal routing, characterized in that, Include: A substrate has a first surface and a second surface, the second surface being opposite to the first surface, wherein an active device of an integrated circuit formed on the substrate is on the first surface; A first unit, on the substrate, has a first pin on a first surface and a second pin on a second surface; A second unit, on the substrate, has a third pin on the first surface and a fourth pin on the second surface; A first signal route is connected to the second pin on the second surface and to the fourth pin on the second surface, so as to connect a second signal route on the first surface to a third signal route on the first surface.

58. The system according to claim 57, characterized in that, The first signal route is a time-critical network.

59. The system according to claim 57, characterized in that, The second signal route is connected to the first pin on the first surface, and the third signal route is connected to the third pin on the first surface.

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