Semiconductor structure, method of fabricating the same, memory, and storage system

Abstract

Embodiments of the present application provide a semiconductor structure, a manufacturing method thereof, a memory, and a storage system. The manufacturing method of the semiconductor structure comprises: providing a substrate; the substrate comprises a first semiconductor layer and a second semiconductor layer on the first semiconductor layer; forming a plurality of first grooves extending through the second semiconductor layer to the first semiconductor layer and arranged along a first direction; forming a plurality of second grooves extending through the second semiconductor layer and arranged along a second direction; the first grooves and the second grooves divide the second semiconductor layer into a plurality of active pillars arranged in an array; forming a first dielectric layer in the plurality of first grooves and the plurality of second grooves; removing the first semiconductor layer to expose part of the first dielectric layer; forming a third groove between two exposed parts of the first dielectric layer adjacent in the first direction; and forming a bit line structure electrically connected to the active pillars in the third groove.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, including but not limited to a semiconductor structure and its fabrication method, a memory, and a storage system. Background Technology

[0002] Transistors in semiconductor structures are widely used as switching devices or driving devices in electronic devices. For example, transistors can be used in Dynamic Random Access Memory (DRAM) to control the capacitance in each memory cell. The basic memory cell structure of DRAM consists of a transistor and a storage capacitor. Its main operating principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0003] However, there are still many problems in the process of forming transistors in related technologies that need to be improved. Summary of the Invention

[0004] To address the related technical issues, embodiments of this application propose a semiconductor structure and its fabrication method, a memory, and a storage system.

[0005] This application provides a semiconductor structure, including:

[0006] Multiple active pillars arranged in an array, the active pillars being used to form transistors;

[0007] Multiple bitline structures are provided, each of which is connected to a row of active pillars arranged in an array. The orthographic projection of the active pillars onto a preset plane is located within the orthographic projection of the bitline structure onto the preset plane. The preset plane is perpendicular to the direction in which the active pillars extend.

[0008] In the above scheme, the multiple bit line structures are non-linear.

[0009] In the above scheme, the semiconductor structure further includes a conductive contact layer located between the active pillar and the bit line structure.

[0010] In the above scheme, the semiconductor structure further includes: an air gap isolation structure and a capping layer; wherein,

[0011] The capping layer covers the air gap isolation structure and the bit line structure; the air gap isolation structure is located between two adjacent bit line structures, and the surface of the air gap isolation structure away from the capping layer is substantially flush with the surface of the conductive contact layer near the capping layer.

[0012] In the above scheme, the transistor includes:

[0013] The source electrode is located at one of the first and second ends of the active post;

[0014] The drain is located at the remaining end of the first and second ends of the active post; the first end and the second end are two opposite ends of the active post in the extension direction.

[0015] A gate structure is located on at least one side of the active pillar.

[0016] In the above scheme, the semiconductor structure further includes:

[0017] Storage cell, one end of which is coupled to the second end of the corresponding active column; and

[0018] Multiple interconnect layers, each of which is coupled to a plurality of memory cells corresponding to a row of active columns in the array of active columns, the interconnect layers being used to connect the corresponding plurality of memory cells to a reference signal.

[0019] This application provides another memory, including: a semiconductor structure as described in the above embodiments of this application.

[0020] This application provides a storage system, including: a memory as described in the above embodiments of this application; and,

[0021] A memory controller, connected to the memory and used to control the memory.

[0022] This application also provides a method for fabricating a semiconductor structure, including:

[0023] A substrate is provided; the substrate includes a first semiconductor layer and a second semiconductor layer located on the first semiconductor layer;

[0024] A plurality of first grooves are formed, extending through the second semiconductor layer into the first semiconductor layer and arranged along a first direction;

[0025] A plurality of second grooves are formed that penetrate the second semiconductor layer and are arranged along the second direction; the first groove and the second groove divide the second semiconductor layer into active pillars arranged in an array; the first direction and the second direction intersect and are both perpendicular to the extension direction of the active pillars;

[0026] A first dielectric layer is formed in a plurality of the first and second grooves;

[0027] The first semiconductor layer is removed to expose a portion of the first dielectric layer extending into the first semiconductor layer; wherein a third groove is formed between two adjacent exposed portions of the first dielectric layer along a first direction;

[0028] A bit line structure is formed in the third groove.

[0029] In the above scheme, the substrate further includes: a second dielectric layer located between the first semiconductor layer and the second semiconductor layer;

[0030] The formation of a plurality of first grooves extending through the second semiconductor layer into the first semiconductor layer and arranged along a first direction includes:

[0031] A plurality of first grooves are formed that penetrate the second semiconductor layer and the second dielectric layer and extend into the first semiconductor layer; after the first semiconductor layer is removed, the portion of the first dielectric layer extending into the first semiconductor layer and the second dielectric layer are exposed;

[0032] The method further includes:

[0033] Before forming the bit line structure, the second dielectric layer located in the third groove is removed.

[0034] The method in the above scheme further includes:

[0035] After the second dielectric layer located in the third groove is removed, the first end of the active post is exposed;

[0036] A conductive contact layer is formed at the first end of each of the active pillars;

[0037] A bit line structure is formed in the third groove, including:

[0038] The bit line structure covering the conductive contact layer is formed in the third groove.

[0039] In the above scheme, the method further includes: removing a portion of the first dielectric layer located between the plurality of bit line structures to form a plurality of fourth grooves;

[0040] A capping layer is formed to cover the fourth groove and the bit line structure; wherein, the surface of each fourth groove away from the capping layer is substantially flush with the surface of the conductive contact layer near the capping layer, and the fourth groove forms an air gap isolation structure.

[0041] In the above scheme, the active pillar is used to form a transistor; the method further includes:

[0042] Before removing the first semiconductor layer, one of a source and a drain is formed at the second end of the active pillar, wherein the second end and the first end are two opposite ends of the active pillar in the extending direction; and

[0043] A gate structure is formed on at least one side of the active pillar;

[0044] After removing the first semiconductor layer, one of the source and the drain is formed at the first end of the active pillar.

[0045] The method in the above scheme further includes:

[0046] Before removing the first semiconductor layer, a memory cell is formed, one end of which is coupled to the second end of the corresponding active pillar; and

[0047] A plurality of interconnect layers are formed along a second direction; each of the interconnect layers extends along a first direction and is coupled to the other end of the corresponding plurality of memory cells; the interconnect layers are used to connect the corresponding plurality of memory cells to a reference signal.

[0048] This application provides a semiconductor structure, a method for fabricating the same, a memory, and a storage system. In various embodiments of this application, a plurality of first grooves and a plurality of second grooves are formed to divide a second semiconductor structure into a plurality of active pillars. The plurality of first grooves are arranged along a first direction, and the plurality of second grooves are arranged along a second direction. The first and second directions intersect and are both perpendicular to the extension direction of the active pillars. Furthermore, the dimension of the first groove along the extension direction of the active pillars is set to be larger than the dimension of the second groove along the extension direction of the active pillars, such that a third groove is formed between two adjacent first grooves at the extension point. Then, conductive material is filled into the third groove to form a bit line structure. In this way, the bit line structure is directly formed between two adjacent first grooves and coupled to multiple active pillars corresponding to the two first grooves for forming transistors. The third groove where the bit line is located can be offset with the offset of the active pillars, while still ensuring coupling with the active pillars. Thus, self-alignment between the bit line structure and the transistor can be achieved, reducing the alignment offset between the bit line structure and multiple transistors and increasing the process window of the semiconductor structure. At the same time, by forming the bit line structure in the third groove, the alignment accuracy between the transistor and the bit line structure can be improved, thereby reducing the contact resistance between the transistor and the bit line structure, and further reducing the RC delay caused by poor contact between the transistor and the bit line structure. Attached Figure Description

[0049] Figure 1 This is a circuit connection diagram of a DRAM transistor provided in an embodiment of this application;

[0050] Figure 2 This is a top view schematic diagram showing an alignment misalignment between a bit line structure and a transistor, as provided in an embodiment of this application.

[0051] Figure 3 This is a flowchart illustrating the method for fabricating the semiconductor structure provided in the embodiments of this application;

[0052] Figures 4a-4o This is a cross-sectional schematic diagram illustrating the fabrication process of a semiconductor structure provided in an embodiment of this application.

[0053] Explanation of reference numerals in the attached figures:

[0054] 200-Substrate; 201-Transistor; 202-Bit line structure; 400-Substrate; 401-First semiconductor layer; 402-Second semiconductor layer; 403-First trench; 404-Second trench; 405-Active pillar; 4051-Drain; 4052-Source; 4053-Channel region; 4054-Gate structure; 4054a-Gate; 4054b-Gate oxide layer; 4055-Lightly doped drain region; 406-Second dielectric layer; 407-First dielectric layer; 408-Memory cell; 4081-First electrode; 4082-Dielectric layer; 4083-Second electrode; 409-Interconnect layer; 410-Third trench; 411-Carrier layer; 412-Conductive contact layer; 413-Bit line structure; 414-Fourth trench; 415-Capping layer.

[0055] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0056] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0057] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0058] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0059] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0060] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0061] In order to gain a more detailed understanding of the features and technical content of the embodiments of this application, the implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this application.

[0062] The semiconductor structures involved in the embodiments of this application are at least a portion of those to be used in subsequent processes to form the final device structure. Here, the final device may include a memory, including but not limited to dynamic random access memory (DRAM). The following description uses DRAM as an example only. However, it should be noted that the following descriptions of DRAM in the embodiments are for illustrative purposes only and are not intended to limit the scope of this application.

[0063] It is understandable that dynamic random access memory (DRAM) consists of multiple memory cell structures. Each memory cell structure mainly consists of a transistor and a memory cell (capacitor) controlled by the transistor. That is, DRAM includes an architecture of 1 transistor (T) and 1 capacitor (C) (1T1C). Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0064] Figure 1 This is a schematic diagram of a control circuit using a 1T1C architecture provided in an embodiment of this application. Figure 1 As shown, the drain of transistor T is electrically connected to the bit line (BL), the source region of transistor T is electrically connected to one of the electrode plates of capacitor C, and the other electrode plate of capacitor C can be connected to a reference voltage, which can be ground voltage or other voltages. The gate of transistor T is connected to the word line (WL). The transistor T is turned on or off by applying a voltage through the word line WL. The bit line BL is used to perform read or write operations on transistor T when it is turned on.

[0065] In some embodiments, a transistor is first formed on the front side of the semiconductor layer, and then a bit line groove is etched on the back side of the semiconductor layer at the position corresponding to the transistor. The bit line groove is filled with conductive material to form a bit line structure, and the bit line structure is coupled to one end of the transistor. However, in its process, due to the bonding process and the stress between the structural layers, the alignment of one end of the transistor with the bit line structure becomes a problem.

[0066] For example, refer to Figure 2 First, a preset pattern of transistors is formed on the front side of the substrate 200 using photolithography, and a preset pattern of bit line structures is formed on the back side of the substrate; second, multiple transistors along a first direction (e.g., ...) are formed on the front side of the substrate using etching and other processes. Figure 2 The X-axis direction shown in the figure) and the second direction (as shown in the figure) Figure 2 The diagram shows transistors 201 arranged in an array along the Y-axis, with one end of each transistor extending into the substrate. The substrate is then flipped, and bit line grooves are etched on the back side of the substrate 200 at positions corresponding to the transistors. Conductive material is then filled into these grooves, forming multiple bit line structures 202 arranged side-by-side along the X-axis. Theoretically, each bit line structure 202 extends along the Y-axis and can connect to one end of multiple transistors 201. However, in practice, stress from the bonding process or other structural layers causes a shift between the actual formation position of the transistors 201 and their intended position, such as... Figure 2 In this case, a row of transistors 201 along the Y-axis appears skewed. When the bitline structure 202 is formed according to its preset position, an offset occurs between the bitline structure 202 and the transistors 201. In other words, the alignment window between the bitline structure and one end of the transistor decreases, increasing the difficulty of alignment. Furthermore, when the offset distance reaches a certain level, one end of the transistor will deviate from the alignment window of the bitline structure, making it impossible for some transistors to connect to the bitline structure. Additionally, high-resistance regions are formed at locations where the bitline structure and some transistors are not connected, leading to problems such as resistance-capacitance (RC) delay.

[0067] In some embodiments, the alignment window between the bit line structure and the transistor can be increased by increasing the width of the bit line structure 202 along the first direction, thereby reducing the alignment difficulty; however, when the distance between two adjacent bit line structures is reduced, the parasitic capacitance or coupling capacitance between the bit line structures gradually increases, which in turn affects the operating speed of the memory.

[0068] In view of this, in order to solve one or more of the above problems, embodiments of this application provide a method for fabricating a semiconductor structure. Figure 3 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application. Figure 3 As shown, the method for fabricating a semiconductor structure provided in this application includes the following steps:

[0069] Step S301: Provide a substrate; the substrate includes a first semiconductor layer and a second semiconductor layer located on the first semiconductor layer;

[0070] Step S302: Form a plurality of first grooves that extend through the second semiconductor layer into the first semiconductor layer and are arranged along the first direction;

[0071] Step S303: Form a plurality of second grooves that penetrate the second semiconductor layer and are arranged along the second direction; the first groove and the second groove divide the second semiconductor layer into active pillars arranged in an array; the first direction and the second direction intersect and are both perpendicular to the extension direction of the active pillars;

[0072] Step S304: Form a first dielectric layer in the plurality of first grooves and second grooves;

[0073] Step S305: Remove the first semiconductor layer to expose a portion of the first dielectric layer; wherein a third groove is formed between two adjacent exposed portions of the first dielectric layer along the first direction;

[0074] Step S306: Form a bit line structure electrically connected to the active post in the third groove.

[0075] It should be understood that Figure 3 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 3 The steps shown can be adjusted in order according to actual needs. Figures 4a to 4o This is a cross-sectional schematic diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of this application. The following is in conjunction with... Figure 3 , Figures 4a to 4o The method for fabricating the semiconductor structure provided in the embodiments of this application will be described in detail.

[0076] refer to Figure 4a , Figure 4b Step S301 is executed to provide a substrate 400.

[0077] The substrate 400 includes a first semiconductor layer 401 and a second semiconductor layer 402; the second semiconductor layer 402 is located on the first semiconductor layer 401. The materials of the first semiconductor layer 401 and the second semiconductor layer 402 may be the same or different; preferably, the materials of the first semiconductor layer 401 and the second semiconductor layer 402 are the same. Here, the material of the first semiconductor layer 401 or the second semiconductor layer 402 may include silicon (Si), germanium (Ge), silicon germanide (SiGe), etc.

[0078] here, Figure 4a This is a sectional view of the XOZ plane. Figure 4b This is a top view of the XOY plane, where, Figure 4b for Figure 4a Top view along section AA.

[0079] refer to Figure 4a , Figure 4b Step S302 is executed to form a plurality of first grooves 403. The plurality of first grooves 403 are arranged at intervals along a first direction; each first groove 403 penetrates the second semiconductor layer 402 and extends into the first semiconductor layer 401; the method for forming the first grooves 403 includes, but is not limited to, plasma dry etching.

[0080] refer to Figure 4c Step S303 is executed to form a plurality of second grooves 404. The plurality of second grooves 404 penetrate the second semiconductor layer 402 and are arranged along a second direction. Here, the plurality of first grooves 403 and the plurality of second grooves 404 divide the second semiconductor layer 402 into a plurality of active pillars 405; the plurality of active pillars 405 are arranged in an array along a first direction and a second direction, and are used to form transistors in subsequent processes. The method for forming the second grooves 404 includes, but is not limited to, plasma dry etching.

[0081] It should be noted that in this application, the first direction and the second direction intersect, that is, the angle between the first direction and the second direction is any angle between 0 and 90 degrees. Here, both the first direction and the second direction are perpendicular to the extension direction of the active column. To clearly describe this application, the following embodiments use the example of the first direction being perpendicular to the second direction. For example, the first direction is... Figure 4a The X-axis direction shown in the figure; the second direction is Figure 4bThe Y-axis direction is shown in the figure; the extension direction of the active column is... Figure 4a The Z-axis direction is shown in the figure. It should be noted that the description of the direction in the following embodiments is for illustrative purposes only and is not intended to limit the scope of this application.

[0082] Additionally, it is understood that since the second groove 404 only penetrates the second semiconductor layer 402, the dimension of the first groove 403 along the Z-axis is greater than the dimension of the second groove 404 along the Z-axis.

[0083] In some embodiments, reference Figure 4a The substrate 400 further includes a second dielectric layer 406 located between the first semiconductor layer 401 and the second semiconductor layer 402;

[0084] The formation of a plurality of first grooves 403 extending through the second semiconductor layer 402 into the first semiconductor layer 401 and arranged along a first direction includes:

[0085] A plurality of first grooves 403 are formed that penetrate the second semiconductor layer 402 and the second dielectric layer 406 and extend into the first semiconductor layer 401.

[0086] In other words, the first groove 403 penetrates the second semiconductor layer 402 and the second dielectric layer 406, and extends into the first semiconductor layer 401, while the second groove 404 only penetrates the second semiconductor layer 402 and stops on the second dielectric layer 406; thus, the dimension of the first groove 403 along the Z-axis is greater than the dimension of the second groove 404 along the Z-axis.

[0087] Here, the second dielectric layer 406 can serve as an etching stop layer for the second groove 404. The second dielectric layer 406 can also be called a buried oxide layer, and its constituent materials include, but are not limited to, silicon oxide. In practice, when the substrate is directly provided silicon-on-insulator, the second dielectric layer 406 can be directly obtained by providing the substrate; alternatively, the second dielectric layer 406 can also be formed on the first semiconductor layer 401 using processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0088] refer to Figure 4d , Figure 4eStep 304 is executed, in which a first dielectric layer 407 is formed in the first groove 403 and the second groove 404. The material of the first dielectric layer 407 includes, but is not limited to, silicon oxide; the method of forming the first dielectric layer 407 includes, but is not limited to, PVD, CVD and other processes.

[0089] here, Figure 4d This is a sectional view of the XOZ plane. Figure 4e This is a top view of the XOY plane, where, Figure 4e for Figure 4d Top view along section BB.

[0090] In some embodiments, the active pillar is used to form a transistor, and the method further includes:

[0091] Before removing the first semiconductor layer, one of a source and a drain is formed at the second end of the active pillar, wherein the second end and the first end are two opposite ends of the active pillar in the extending direction; and

[0092] A gate structure is formed on at least one side of the active pillar;

[0093] After removing the first semiconductor layer, one of the source and the drain is formed at the first end of the active pillar.

[0094] For example, refer to Figure 4f The first end and the second end are two opposite ends of the active post 405 in the Z-axis direction; wherein, the first end of the active post is the end of the two ends of the active post that is closer to the first semiconductor layer 401; and the second end of the active post is the end of the two ends of the active post that is farther away from the first semiconductor layer 401.

[0095] In this embodiment, a source or a drain can be formed at the first end of the active pillar; a drain or the remaining source can be formed at the second end of the active pillar, and the positions of the source and drain can be interchanged. In other words, if a source is formed at the first end of the active pillar, a drain is formed at the second end; similarly, if a drain is formed at the first end of the active pillar, a source is formed at the second end. For ease of description, this embodiment uses the example of forming a drain at the first end of the active pillar and a source at the second end. The methods for forming the source and drain include, but are not limited to, ion implantation, thermal diffusion, and other processes.

[0096] To improve process operability, a source is typically formed at the second end of the active pillar before the first semiconductor layer 401 is removed; and a drain is typically formed at the first end of the active pillar after the first semiconductor layer 401 is removed.

[0097] Here, for reference Figure 4f , Figure 4g The region between the drain 4051 and the source 4052 is the channel region 4053. The gate structure 4054 can be located on one side of the channel region 4053; it can be located on opposite sides of the channel region 4053; or it can be located around the channel region 4053. The specific location can be set according to the actual needs of the transistor; in this embodiment, the gate structure 4054 is located on one side of the channel region 4053 as an example. In this embodiment, multiple gate structures 4054 are arranged along the second direction, and each gate structure 4054 extends along the first direction.

[0098] refer to Figure 4g The gate structure 4054 includes a gate 4054a and a gate oxide layer 4054b. The gate oxide layer 4054b is located between the gate 4054a and the channel region 4053, serving to electrically isolate the channel region 4053 and the gate 4054a. It is understood that the gate oxide layer in a transistor can be used to sense different electric fields and apply them to the surface of the channel region, causing minority carriers in the first semiconductor layer to be adsorbed, accumulated, and inverted on the surface of the channel region, making the gate oxide layer have the same doping type as the source and drain, thereby achieving conduction between the source and drain.

[0099] Here, the gate material may include, but is not limited to, metal (such as tungsten) or polysilicon; the gate oxide material may include, but is not limited to, silicon oxide.

[0100] In some embodiments, reference Figure 4g When a gate voltage is applied to the gate, generating a strong electric field, electrons drift and accelerate along the direction of the electric field, gaining significant kinetic energy. As these electrons travel from the source to the drain, the voltage difference causes them to collide with the gate oxide layer and be injected into it, resulting in a hot carrier effect. This hot carrier effect significantly impacts the reliability of the transistor. Therefore, a lightly doped drain region 4055 can be placed between the drain and channel regions in the transistor. This lightly doped drain region 4055 withstands part of the voltage to weaken the drain electric field and thus improve the hot carrier effect.

[0101] It should be noted that the gate structure 4054 can be formed before or after the removal of the first semiconductor layer 401. The actual operation sequence can be selected and set according to actual needs.

[0102] here, Figure 4f This is a sectional view in the YOZ plane. Figure 4g This is a top view of the YOZ plane. Figure 4hThis is a sectional view of the XOZ plane. Figure 4i This is a top view of the XOY plane, where, Figure 4f for Figure 4i Cross-sectional view along section CC. Figure 4g for Figure 4f Enlarged diagram corresponding to the dashed box in the middle. Figure 4h for Figure 4i A sectional view along section DD.

[0103] Next, continue to refer to Figure 4g , Figure 4h , Figure 4i The method further includes:

[0104] Before removing the first semiconductor layer 401, a memory cell 408 is formed, one end of which is coupled to the second end of the corresponding active pillar; and

[0105] A plurality of interconnect layers 409 are formed along a second direction; each of the interconnect layers 409 extends along a first direction and is coupled to the other end of the corresponding plurality of memory cells 408; the interconnect layers 409 are used to connect the corresponding plurality of memory cells 408 to a reference signal.

[0106] The storage unit 408 is used to store written data. In some specific embodiments, the storage unit may include a capacitor; the capacitor includes a first electrode 4081, a dielectric layer 4082 covering the first electrode, and a second electrode 4083 covering the dielectric layer. It is understood that one end of the storage unit 408 is the first electrode 4081 of the capacitor; the other end of the storage unit is the second electrode 4083 of the capacitor. Here, the first electrode 4081 of the capacitor is connected to the second end (i.e., the source) of the active post; the second electrode 4083 of the capacitor is connected to the interconnect layer 409.

[0107] Here, forming the capacitor includes forming a first electrode coupled to the second end of the active post, forming a dielectric layer covering the first electrode, and forming a second electrode covering the dielectric layer.

[0108] The materials of the first electrode 4081 and the second electrode 4083 include, but are not limited to, titanium nitride (TiN). The material of the dielectric layer 4082 includes a high-k dielectric material, which generally refers to a material with a dielectric constant higher than 3.9, and is usually significantly higher than this value. In some specific examples, the material of the dielectric layer 4082 may include, but is not limited to, hafnium oxide (HfO2). The methods for forming the first electrode, the dielectric layer, and the second electrode include, but are not limited to, PVD, CVD, ALD, and other processes.

[0109] Next, a plurality of interconnect layers 409 are formed to be connected to the second electrode of the capacitor; Reference Figure 4h , Figure 4i Multiple interconnect layers 409 are arranged in parallel along the Y-axis direction, and each interconnect layer 409 extends along the X-axis direction and is connected to the second side of multiple memory cells 408 in the X-axis direction; here, the interconnect layer 409 is used to connect the corresponding multiple memory cells to a reference signal. The reference voltage can be ground voltage or other voltages.

[0110] refer to Figure 4j , Figure 4k Step 305 is executed to remove the first semiconductor layer 401.

[0111] Specifically, after forming the interconnect layer 409, the substrate 400 is flipped and thinned; this thinning process involves removing the first semiconductor layer 401 from the substrate 400. In practice, the methods used to remove the first semiconductor layer 401 include, but are not limited to, dry etching.

[0112] It should be noted that when the second dielectric layer 406 is not disposed between the first semiconductor layer 401 and the second semiconductor layer 402, after removing the first semiconductor layer 401, a portion of the first dielectric layer 407 is exposed; wherein, the exposed portion of the first dielectric layer 407 extends into the first semiconductor layer 401; at this time, a third groove 410 is formed between two adjacent exposed portions of the first dielectric layer 407 along the first direction, for reference. Figure 4j .

[0113] In other embodiments, when a second dielectric layer 406 is disposed between the first semiconductor layer 401 and the second semiconductor layer 402, after removing the first semiconductor layer 401, a portion of the first dielectric layer 407 and the second dielectric layer 406 are exposed. (Refer to...) Figure 4k Based on this, the method further includes: before forming the bit line structure, removing the second dielectric layer 406 to form a third groove 410 between two exposed portions of the first dielectric layer 407, referring to... Figure 4k .

[0114] It should be noted that the third groove 410 is parallel to the first groove 403; specifically, a plurality of third grooves 410 are arranged along the X-axis direction, and each of the third grooves 410 extends along the Y-axis direction.

[0115] It should be noted that, in some specific embodiments, before flipping the substrate 400, a carrier layer 411 is disposed above the second semiconductor layer. The carrier layer 411 is used to protect the transistors, capacitors, interconnect layers and other structures in the second semiconductor layer 402 from being damaged.

[0116] In some embodiments, the method further includes:

[0117] After the second dielectric layer 406 located in the third groove 410 is removed, the first end of the active post is exposed;

[0118] A conductive contact layer 412 is formed at the first end of each of the active pillars.

[0119] refer to Figure 4l The conductive contact layer 412 contacts the first end (e.g., drain) of the active pillar to reduce contact resistance and improve conductivity. Forming the conductive contact layer 412 involves depositing a metal layer on the first end of the active pillar and then annealing it. In some specific embodiments, the metal layer may be made of elements such as cobalt (Co) or nickel (Ni). For example, a layer of nickel (Ni) is deposited on the first end of the active pillar, and then the active pillar with the nickel layer is subjected to high-temperature annealing. During annealing, the silicon in the active pillar reacts with the nickel to form a metal silicide, such as nickel silicide (SiNi). Here, nickel silicide is used to reduce the contact resistance between one end (e.g., drain) of the active pillar and the bit line structure.

[0120] refer to Figure 4m Step 306 is performed to form bit line structure 413 in each of the third grooves.

[0121] Specifically, forming a bit line structure in the third groove includes: forming a bit line structure covering the conductive contact layer 412 in the third groove. The bit line structure 413 may include bit lines and / or bit line contacts; for example, when no bit line contacts are formed in the semiconductor structure, the bit line structure here can be a bit line contact. When bit line contacts are formed in the semiconductor structure, the bit line structure here can be a bit line connected to the bit line contact. When no bit line contacts are formed in the semiconductor structure, the bit line structure here can be a bit line contact and a bit line; wherein, the method of forming the bit line structure includes: forming a bit line contact in each of the third grooves, and then forming a bit line connected to the bit line contact. Here, each bit line structure is connected to a row of active pillars in the array of active pillars. Furthermore, with the structural features of the third groove 410, each bit line structure 413 extends along the Y-axis direction; multiple bit line structures 413 are arranged parallel to each other along the X-axis direction. It should be noted that each bitline structure 413 can be a straight line extending along the Y-axis or a non-straight line extending along the Y-axis. Specifically,

[0122] If the external stress has little effect during the execution of the above steps, and the line connecting the first ends of the multiple active pillars formed along the Y-axis is a straight line, then the third groove formed above the first ends of the multiple active pillars is a straight line; therefore, the bit line structure formed in the third groove also extends in a straight line along the Y-axis.

[0123] If, during the execution of the above multiple steps, stress occurs due to bonding processes or other structural layers, the actual formation position of the first end of the active pillar will deviate from the preset position of the first end of the active pillar. (Refer to...) Figure 4n In other words, the line connecting the first ends of the row of active pillars can be non-linear, such as curved, which in turn makes the third groove formed above the first ends of the row of active pillars non-linear, such as curved. Based on this, the bit line structure 413 formed in the third groove is also non-linear, such as curved.

[0124] In some embodiments, the width of the bit line structure 413 in the first direction is greater than or equal to the width of the first end of the active column in the first direction. It can also be understood that the orthographic projection of the row of active columns onto a preset plane is located within the orthographic projection of the bit line structure onto the preset plane, and the preset plane is perpendicular to the direction in which the active columns extend.

[0125] It should be noted that, Figure 4j , Figure 4k , Figure 4l , Figure 4m All are sectional views in the (-X)O(-Z) plane. Figure 4n This is a top view of the XOY plane; where the -X-axis direction and the X-axis direction are two opposite extension directions on the same coordinate axis; the -Z-axis direction and the Z-axis direction are two opposite extension directions on the same coordinate axis.

[0126] Understandably, forming the bit line structure 413 directly in the third groove enables self-alignment between the first end of the active pillar and the bit line structure. This avoids the alignment process between the bit line structure and multiple transistors during the manufacturing process, reduces the positional offset between the bit line structure and multiple transistors, and increases the process window of the semiconductor structure. In practice, this reduces the probability of the bit line structure and some transistors not being connected, thereby reducing the probability of a high-resistance region forming between the transistor and the bit line structure, and thus avoiding problems such as RC delay caused by high-resistance regions.

[0127] In some embodiments, reference Figure 4o The method further includes: removing a portion of the first dielectric layer 407 located between the plurality of bit line structures to form a plurality of fourth grooves 414;

[0128] A capping layer 415 is formed to cover the fourth groove 414 and the bit line structure 413; the material of the capping layer 415 includes, but is not limited to, orthosilicate (TEOS); the method of forming the capping layer 415 includes, but is not limited to, PVD, CVD, ALD and other processes.

[0129] In each of the fourth grooves 414, the surface furthest from the cap layer 415 is substantially flush with the surface of the conductive contact layer 412 near the cap layer 415. The fourth groove 414 forms an air gap isolation structure. This air gap isolation structure may include a solid filler, such as silicon oxide, or air. Preferably, the air gap isolation structure includes air. It should be understood that air is a good dielectric with a significantly low relative permittivity. Here, providing an air gap isolation structure between two adjacent bit line structures can reduce coupling capacitance, thereby increasing the device's read / write speed and improving its electrical performance.

[0130] Based on this, in this embodiment of the application, a plurality of first grooves and a plurality of second grooves are formed to divide the second semiconductor structure into a plurality of active pillars. The plurality of first grooves are arranged along a first direction, and the plurality of second grooves are arranged along a second direction. The first direction and the second direction intersect and are both perpendicular to the extension direction of the active pillars. Furthermore, the dimension of the first groove along the extension direction of the active pillars is set to be greater than the dimension of the second groove along the extension direction of the active pillars, so that a third groove is formed between two adjacent first grooves at the extension. Then, conductive material is filled in the third groove to form a bit line structure. In this way, the bit line structure is directly formed between two adjacent first grooves and coupled to multiple active pillars corresponding to the two first grooves for forming transistors. The third groove where the bit line is located can be offset with the offset of the active pillars, while still ensuring coupling with the active pillars. Thus, self-alignment between the bit line structure and the transistor can be achieved, reducing the alignment offset between the bit line structure and multiple transistors and increasing the process window of the semiconductor structure. At the same time, by forming the bit line structure in the third groove, the alignment accuracy between the transistor and the bit line structure can be improved, thereby reducing the contact resistance between the transistor and the bit line structure, and further reducing the RC delay caused by poor contact between the transistor and the bit line structure.

[0131] This application also provides a semiconductor structure, which is obtained by the fabrication method described in the foregoing embodiments; the semiconductor structure includes:

[0132] Multiple active pillars arranged in an array, the active pillars being used to form transistors;

[0133] Multiple bitline structures are provided, each of which is connected to a row of active pillars arranged in an array. The orthographic projection of the row of active pillars onto a preset plane is located within the orthographic projection of the bitline structure onto the preset plane. The preset plane is perpendicular to the direction in which the active pillars extend.

[0134] It should be noted that the reference Figure 4n During the formation of the semiconductor structure, bonding stress and compressive stress cause the actual formation position of the active pillar 405 (or transistor) to deviate from the preset position, thereby making the bit line structure 413 formed at one end of a row of active pillars (or transistors) curved. The curved bit line structure 413 can be formed according to the actual position of the active pillar 405 (or transistor), which improves the connection reliability between the bit line structure 413 and the transistor, thereby improving the electrical performance of the device.

[0135] In some embodiments, the multiple bitline structure is non-linear.

[0136] It should be noted that in some other embodiments, in the multiple rows of active pillars (or transistors) obtained by the manufacturing method in the foregoing embodiments of this application, there is no offset of some active pillars (or transistors), and the line segment where each bit line structure is located is a straight line.

[0137] In some embodiments, the semiconductor structure further includes a conductive contact layer located between the active pillar and the bit line structure.

[0138] In some embodiments, the semiconductor structure further includes: an air gap isolation structure and a capping layer; wherein,

[0139] The capping layer covers the air gap isolation structure and the bit line structure; the air gap isolation structure is located between two adjacent bit line structures, and the surface of the air gap isolation structure away from the capping layer is substantially flush with the surface of the conductive contact layer near the capping layer.

[0140] In some embodiments, the transistor includes:

[0141] The source electrode is located at one of the first and second ends of the active post;

[0142] The drain is located at the remaining end of the first and second ends of the active post; the first end and the second end are two opposite ends of the active post in the extension direction.

[0143] A gate structure is located on at least one side of the active pillar.

[0144] In some embodiments, the semiconductor structure further includes:

[0145] Storage cell, one end of which is coupled to the second end of the corresponding active column; and

[0146] Multiple interconnect layers, each of which is coupled to a plurality of memory cells corresponding to a row of active columns in the array of active columns, the interconnect layers being used to connect the corresponding plurality of memory cells to a reference signal.

[0147] This application also provides a memory, including a semiconductor structure as described in the above embodiments of this application.

[0148] The memory fabricated by the method provided in this application is similar to the memory in the above embodiments. For technical features not disclosed in detail in this application, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0149] This application provides a storage system, including: a memory as described in the above embodiments; and,

[0150] A memory controller, connected to the memory and used to control the memory.

[0151] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0152] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0153] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Multiple active pillars arranged in an array, the active pillars being used to form transistors; Multiple bitline structures are provided, each of which is connected to a row of active pillars arranged in an array. The orthographic projection of the active pillars onto a preset plane lies within the orthographic projection of the bitline structure onto the preset plane, and the preset plane is perpendicular to the extension direction of the active pillars. The width of the bitline structure in a first direction is greater than or equal to the width of the first end of the active pillar in the first direction. The first end of the active pillar is the end where the active pillar is connected to the bitline structure. The bitline structure extends along a second direction, where the first direction and the second direction are perpendicular, and both the first direction and the second direction are perpendicular to the extension direction of the active pillars.

2. The semiconductor structure according to claim 1, characterized in that, The multiple bitline structures are non-linear.

3. The semiconductor structure according to claim 2, characterized in that, The semiconductor structure further includes a conductive contact layer located between the active pillar and the bit line structure.

4. The semiconductor structure according to claim 3, characterized in that, The semiconductor structure further includes: an air gap isolation structure and a capping layer; wherein... The capping layer covers the air gap isolation structure and the bit line structure; the air gap isolation structure is located between two adjacent bit line structures, and the surface of the air gap isolation structure away from the capping layer is substantially flush with the surface of the conductive contact layer near the capping layer.

5. The semiconductor structure according to claim 2, characterized in that, The transistor includes: The source electrode is located at one of the first and second ends of the active post; The drain is located at the remaining end of the first and second ends of the active post; the first end and the second end are two opposite ends of the active post in the extension direction. A gate structure is located on at least one side of the active pillar.

6. The semiconductor structure according to claim 5, characterized in that, The semiconductor structure also includes: Storage cell, one end of which is coupled to the second end of the corresponding active column; and Multiple interconnect layers, each of which is coupled to a plurality of memory cells corresponding to a row of active columns in the array of active columns, the interconnect layers being used to connect the corresponding plurality of memory cells to a reference signal.

7. A memory, characterized in that, include: The semiconductor structure as described in any one of claims 1 to 6.

8. A storage system, characterized in that, include: The memory as described in claim 7; as well as, A memory controller, connected to the memory and used to control the memory.

9. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; The substrate includes a first semiconductor layer and a second semiconductor layer located on the first semiconductor layer; A plurality of first grooves are formed, extending through the second semiconductor layer into the first semiconductor layer and arranged along a first direction; A plurality of second grooves are formed that penetrate the second semiconductor layer and are arranged along the second direction; the first groove and the second groove divide the second semiconductor layer into a plurality of active pillars arranged in an array; the first direction and the second direction intersect and are both perpendicular to the extension direction of the active pillars; A first dielectric layer is formed in the first groove and the second groove; The first semiconductor layer is removed to expose a portion of the first dielectric layer; wherein a third groove is formed between two adjacent exposed portions of the first dielectric layer along a first direction; A bitline structure electrically connected to the active post is formed in the third groove.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, The substrate further includes a second dielectric layer located between the first semiconductor layer and the second semiconductor layer; The formation of a plurality of first grooves extending through the second semiconductor layer into the first semiconductor layer and arranged along a first direction includes: A plurality of first grooves are formed that penetrate the second semiconductor layer and the second dielectric layer and extend into the first semiconductor layer; after the first semiconductor layer is removed, the portion of the first dielectric layer extending into the first semiconductor layer and the second dielectric layer are exposed; The method further includes: Before forming the bit line structure, the second dielectric layer located in the third groove is removed.

11. The method for fabricating a semiconductor structure according to claim 10, characterized in that, The method further includes: After the second dielectric layer located in the third groove is removed, the first end of the active post is exposed; A conductive contact layer is formed at the first end of the active post; A bit line structure is formed in the third groove, including: The bit line structure covering the conductive contact layer is formed in the third groove.

12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, The method further includes: removing a portion of the first dielectric layer located between the plurality of bit line structures to form a plurality of fourth grooves; A capping layer is formed to cover the fourth groove and the bit line structure; wherein, the surface of each fourth groove away from the capping layer is substantially flush with the surface of the conductive contact layer near the capping layer, and the fourth groove forms an air gap isolation structure.

13. The method for fabricating a semiconductor structure according to claim 10, characterized in that, The active pillar is used to form a transistor, and the method further includes: Before removing the first semiconductor layer, one of a source and a drain is formed at the second end of the active pillar, wherein the second end and the first end are two opposite ends of the active pillar in the extending direction; and A gate structure is formed on at least one side of the active pillar; After removing the first semiconductor layer, one of the source and the drain is formed at the first end of the active pillar.

14. The method for fabricating a semiconductor structure according to claim 13, characterized in that, The method further includes: Before removing the first semiconductor layer, a memory cell is formed, one end of which is coupled to the second end of the corresponding active pillar; and A plurality of interconnect layers are formed along a second direction; each of the interconnect layers extends along a first direction and is coupled to the other end of the corresponding plurality of memory cells; the interconnect layers are used to connect the corresponding plurality of memory cells to a reference signal.

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