Semiconductor device having multiple substrates and die stacks

Abstract

This document discloses a semiconductor device having multiple substrates and die stacks, as well as associated systems and methods. In some embodiments, a semiconductor device includes a package substrate and a first die stack mounted on the package substrate and including a plurality of first memory dies. The device may include a substrate mounted on the first die stack, the substrate including a plurality of routing elements. The device may also include a second die stack mounted on the substrate, the second die stack including a plurality of second memory dies. The device may further include a controller die mounted on the substrate. The controller die may be configured to communicate with the second die stack via the routing elements of the substrate. The device may include a molding material encapsulating the first die stack, the second die stack, the substrate, and the controller die.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, and more specifically, to semiconductor devices having multiple substrates for signal routing of respective die stacks. Background Technology

[0002] A packaged semiconductor die containing memory chips, microprocessor chips, and imager chips typically comprises a semiconductor die mounted on a substrate and encased in a protective cover. The semiconductor die may contain functional features, such as memory cells, processor circuitry, and imager devices, as well as bonding pads electrically connected to these functional features. The bonding pads may be electrically connected to terminals outside the protective cover to allow the semiconductor die to be connected to higher-level circuitry.

[0003] Market pressures are constantly driving semiconductor manufacturers to reduce the size of die packages to fit within the space constraints of electronic devices, while simultaneously increasing the functional capacity of each package to meet operating parameters. One method for increasing the processing power of a semiconductor package without substantially increasing the surface area covered by the package (i.e., the package's "coverage area") is to vertically stack multiple semiconductor dies on top of each other within a single package. Dies in such vertically stacked packages can be electrically coupled to each other and / or electrically coupled to the substrate via wires, interconnects, or other conductive structures. However, conventional techniques for routing signals to and from vertically stacked semiconductor dies rely on complex multilayer routing structures within a single package substrate, which can lead to reduced signal integrity, larger package size, and increased manufacturing costs. Summary of the Invention

[0004] According to an aspect of this application, a semiconductor device is provided. The semiconductor device includes: a packaging substrate; a first die stack mounted on the packaging substrate, the first die stack including a plurality of first memory dies; an intermediate substrate mounted on the first die stack, the intermediate substrate including a plurality of routing elements; a second die stack mounted on the substrate, the second die stack including a plurality of second memory dies; a controller die mounted on the substrate, wherein the controller die is configured to communicate with the second die stack via routing elements of the intermediate substrate; and a molding material encapsulating the first die stack, the second die stack, the intermediate substrate, and the controller die.

[0005] According to another aspect of this application, a semiconductor device is provided. The semiconductor device includes: a package substrate; a first die stack mounted on the package substrate, the first die stack including a plurality of DRAM dies coupled to the package substrate; an intermediate substrate directly mounted on the first die stack, the intermediate substrate including a plurality of routing elements, wherein the intermediate substrate is electrically coupled to the package substrate via one or more bonding wires; a second die stack mounted on the intermediate substrate, the second die stack including a plurality of NAND dies coupled to the intermediate substrate; a controller die mounted on the intermediate substrate, wherein the controller die is configured to communicate with the second die stack via the routing elements of the intermediate substrate; and a molding material encapsulating the first die stack, the second die stack, the intermediate substrate, and the controller die.

[0006] According to another aspect of this application, a method for manufacturing a semiconductor device is provided. The method includes: forming a first assembly by mounting a plurality of first memory dies on a first substrate; forming a second assembly by mounting a plurality of second memory dies and a controller die on a second substrate, wherein the second memory dies are electrically coupled to the controller die via routing elements in the second substrate; mounting the second assembly onto the first assembly; and encapsulating the first assembly and the second assembly with a molding material after mounting the second assembly onto the first assembly. Attached Figure Description

[0007] The following figures provide a better understanding of many aspects of the invention. The components in the figures are not necessarily drawn to scale. The focus is on clearly illustrating the principles of the invention.

[0008] Figure 1A A partial schematic side cross-sectional view of a semiconductor device configured according to an embodiment of the present invention.

[0009] Figure 1B for Figure 1A A partial schematic side cross-sectional view of the first substrate of the semiconductor device.

[0010] Figure 1C for Figure 1A A partial schematic side cross-sectional view of the second substrate of the semiconductor device.

[0011] Figure 2 A partial schematic cross-sectional view of another semiconductor device configured according to an embodiment of the present invention.

[0012] Figure 3 A partial schematic cross-sectional view of another semiconductor device configured according to an embodiment of the present invention.

[0013] Figure 4A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0014] Figure 5 A schematic diagram of a system comprising a semiconductor device or package configured according to an embodiment of the present invention. Detailed Implementation

[0015] The following describes several embodiments of a semiconductor device and specific details of associated systems and methods. In some embodiments, for example, a semiconductor device includes: a first die stack including a plurality of first memory dies (e.g., DRAM dies); a second die stack including a plurality of second memory dies (e.g., NAND dies); and a controller and / or logic die (e.g., NAND controller die) for the second die stack. The first die stack may be mounted on a package substrate. The semiconductor device may also include an intermediate substrate mounted on the first die stack, and the second die stack and the controller die may be mounted on the intermediate substrate. The semiconductor device may further include a molding material that encapsulates the first die stack, the second die stack, the intermediate substrate, and the controller die to form a single monolithic package.

[0016] In some embodiments, signal routing for the second die stack is physically separated and / or electrically isolated from signal routing for the first die stack. For example, the second die stack may communicate with the controller die via routing elements in the intermediate substrate, while the first die stack may communicate with an external device (e.g., a host device) via routing elements in the package substrate. Therefore, for example, signal routing in the package substrate can be reduced and / or simplified compared to conventional devices that route all signals through the package substrate. Thus, thinner and less complex package substrates can be used, reducing the overall package height. This approach also improves signal integrity by reducing or eliminating crosstalk that might occur when routing all die stack signals through a single substrate. Additionally, signal routing in the intermediate substrate can be modified independently of signal routing in the package substrate, reducing manufacturing costs and providing greater flexibility in device design.

[0017] Those skilled in the art will recognize that the appropriate stages of the methods described herein can be performed at the wafer level or the die level. Therefore, depending on the context, the term "substrate" can refer to a wafer-level substrate or a single die-level substrate. Furthermore, unless the context otherwise indicates, semiconductor manufacturing techniques can be used to form the structures disclosed herein. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques.

[0018] Numerous specific details are disclosed herein to provide a detailed and useful description of embodiments of the invention. However, those skilled in the art will understand that the technology may have additional embodiments, and that the technology may be described without further reference. Figure 1A-5 The described embodiments are practiced in several details. For example, some details of semiconductor devices and / or packages well known in the art have been omitted to avoid obscuring the technical aspects of the invention. Generally, it should be understood that various other devices and systems besides the specific embodiments disclosed herein are within the scope of the invention.

[0019] As used herein, the terms “vertical,” “horizontal,” “upper,” “lower,” “above,” and “below” may refer to the relative orientation or position of a feature in a semiconductor device, given the orientation shown in the figures. For example, “upper” or “topmost” may refer to a feature positioned closer to the top of a page than another feature. However, these terms should be broadly understood to include semiconductor devices with other orientations, such as inverted or tilted orientations, where top / bottom, above / below, above / below, up / down, and left / right may be interchanged depending on the orientation.

[0020] Figure 1A This is a partially schematic side cross-sectional view of a semiconductor device 100 (“Device 100”) configured according to an embodiment of the present invention. Device 100 includes: a first die stack 102 comprising a plurality of first dies 104; and a second die stack 106 comprising a plurality of second dies 108. Device 100 further includes a first substrate 110 (e.g., a package substrate) supporting the first die stack 102, and a second substrate 112 (e.g., an intermediate substrate) supporting the second die stack 106. The first die stack 102 may be mounted on the first substrate 110, the second substrate 112 may be mounted on the first die stack 102, and the second die stack 106 may be mounted on the second substrate 112. Device 100 may also include a third die 114 mounted on the second substrate 112. The third die 114 may be a controller and / or logic die (e.g., a microcontroller) configured to control the operation of the second die stack 106, as discussed in more detail below.

[0021] Each of the first die 104, the second die 108, and the third die 114 may include a semiconductor substrate (e.g., a silicon substrate, a gallium arsenide substrate, an organic laminate substrate, etc.). In some embodiments, the first die 104, the second die 108, and the third die 114 each include a front surface and / or an active surface having various types of semiconductor components. For example, any one of the first die 104, the second die 108, or the third die 114 may include memory circuitry (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), flash memory (e.g., NAND, NOR, or other types of memory circuitry), controller circuitry (e.g., DRAM controller circuitry), logic circuitry, processing circuitry, circuit elements (e.g., wires, traces, interconnects, transistors, etc.), imaging components, and / or other semiconductor features. Optionally, one or more of the first die 104 or the second die 108 may be “blank” substrates that do not contain semiconductor components and are formed of, for example, crystalline, semi-crystalline and / or ceramic substrate materials, such as silicon, polycrystalline silicon, alumina (Al2O3), sapphire and / or other suitable materials.

[0022] In such embodiments, device 100 is a memory device, and some or all of the first die 104 and the second die 108 are memory dies (e.g., NAND dies, DRAM dies, SRAM dies, etc.). The first die 104 and the second die 108 may each be of the same type of memory die. Alternatively, device 100 may be a hybrid memory device, wherein some or all of the first dies 104 are memory die types different from some or all of the second dies 108. For example, the first dies 104 may each be of a first memory die type (e.g., DRAM), and the second dies 108 may each be of a second memory die type (e.g., NAND). Optionally, the third die 114 may be a memory controller (e.g., a NAND memory controller) for the second die 108. However, in other embodiments, the first die 104, the second die 108, and / or the third die 114 may comprise other types of semiconductor dies.

[0023] In the illustrated embodiment, the first die 104 of the first die stack 102 and the second die 108 of the second die stack 106 are each arranged in a shingled or stepped configuration, wherein each die is horizontally offset from the die below to allow electrical interconnection, as discussed in more detail below. Although Figure 1AThe first die stack 102 is depicted as comprising four first dies 104, and the second die stack 106 is depicted as comprising eight second dies 108. However, in other embodiments, the first die stack 102 and / or the second die stack 106 may each independently have fewer or more dies (e.g., one, two, four, five, six, seven, eight, nine, ten, or more dies). The first dies 104 and / or the second dies 108 may be stacked “face up” with their front surfaces facing upward and away from the package substrate 110 and the intermediate substrate 112. The third die 114 may be stacked “face down” with its front surface facing downward and towards the intermediate substrate 112. However, in other embodiments, one or more of the first dies 104 and / or the second dies 108 may be configured face down, and / or the third die 114 may be configured face up.

[0024] The first substrate 110 may be or contain any component suitable for supporting the first die stack 102, such as an interposer, printed circuit board, redistribution layer (RDL), dielectric spacer, another semiconductor die (e.g., a logic die), or another suitable packaging substrate. In some embodiments, the first substrate 110 includes additional semiconductor components (e.g., doped silicon wafers or gallium arsenide wafers), non-conductive components (e.g., various ceramic substrates, such as alumina (Al2O3) etc.), aluminum nitride, and / or conductive portions (e.g., interconnect circuitry, TSVs, etc.). The first substrate 110 may be coupled to conductive elements or contacts 116 (e.g., solder balls, conductive bumps, conductive pillars, conductive epoxy, and / or other suitable conductive elements) configured to electrically couple device 100 to an external device (not shown), such as a host device further discussed below.

[0025] Figure 1BThis is a partially schematic side cross-sectional view of a first substrate 110. The first substrate 110 may comprise multiple discrete layers. In the illustrated embodiment, for example, the first substrate 110 includes three functional and / or metallic layers: a first signal routing layer 132, a power and / or ground shielding layer 134, and a second signal routing layer 136. The power and / or ground shielding layer 134 may be positioned between the first signal routing layer 132 and the second signal routing layer 136. Additionally, the first substrate 110 may include additional insulating material layers between the functional and / or metallic layers, such as a first insulating layer 133 between the first signal routing layer 132 and the power and / or ground shielding layer 134, and a second insulating layer 135 between the power and / or ground shielding layer 134 and the second signal routing layer 136. However, in other embodiments, the number and / or arrangement of layers in the first substrate 110 may be varied as needed. Some or all of the layers 132-136 of the first substrate 110 may contain various components for transmitting signals to the device 100 (e.g., the first die stack 102) and / or routing elements for transmitting signals from said various components (e.g., conductive components omitted for simplicity, such as traces, bonding pads, vias, etc.), as described in more detail below.

[0026] Refer again Figure 1A The first die stack 102 may be electrically coupled to the first substrate 110 via a plurality of first electrical connectors 118. In the illustrated embodiment, the first electrical connectors 118 are depicted as connecting individual first dies 104 to each other and / or to a plurality of bonding wires connected to the first substrate 110. Alternatively or in combination, the first electrical connectors 118 may include other types of connection elements, such as through-silicon vias (TSVs), interconnect structures (e.g., bumps, microbumps, pillars, posts, columns, etc.), and / or any other die-to-die or die-to-substrate interconnect elements known to those skilled in the art.

[0027] In some embodiments, the first die stack 102 connects to external devices (e.g., via signals routed through the first electrical connector 118, the first substrate 110, and the conductive element 116) via signals routed through the first electrical connector 118, the first substrate 110, and the conductive element 116. Figure 1A (The host device is not shown in the image) for communication. The first substrate 110 may include one or more routing elements (e.g., signal traces, bonding pads, vias, etc., as previously referenced). Figure 1B As described, signals are transmitted from the first die stack 102 and the first electrical connector 118 to the conductive element 116, and vice versa. For example, at least some of the first electrical connectors 118 can be connected to bonding pads (not shown) on the first substrate 110, and routing elements of the first substrate 110 can connect each bonding pad to a corresponding conductive element 116. The first substrate 110, conductive element 116, and electrical connector 118 can also transmit power from an external power source to the first die stack 102.

[0028] The second substrate 112 may be coupled to the first die stack 102 (e.g., coupled to the uppermost first die 104 in the first die stack 102) via a die attachment film and / or other suitable techniques known to those skilled in the art. The second substrate 112 may be directly mounted to the first die stack 102 without any intervening spacers, interposers, dies, or other support structures. The second substrate 112 may be any component suitable for supporting the second die stack 106, such as an interposer, printed circuit board, dielectric spacers, stacked RDL, another semiconductor die (e.g., a logic die), or another suitable organic or inorganic substrate. The second substrate 112 may be made of the same or similar material as the first substrate 110, or may be made of a different material. Optionally, the material of the second substrate 112 may be selected to reduce or minimize the coefficient of thermal expansion (CTE) mismatch with the first substrate 110, for example, to reduce thermomechanical stress on the device 100 during manufacturing and / or operation.

[0029] Figure 1C This is a partial schematic side cross-sectional view of the second substrate 112. The second substrate 112 may comprise multiple discrete layers. In the illustrated embodiment, for example, the second substrate 112 comprises two functional and / or metallic layers: a signal routing layer 142 and a power and / or ground shielding layer 144. The power and / or ground shielding layer 144 may be positioned below the signal routing layer 142. The second substrate 112 may further comprise an insulating layer 143 between the signal routing layer 142 and the power and / or ground shielding layer 144. However, in other embodiments, the number and / or arrangement of layers in the second substrate 112 may be varied as needed. Some or all of the layers 142-144 of the second substrate 112 may comprise various components for transmitting signals to the device 100 (e.g., the second die stack 106 and / or the third die 114) and / or routing elements for transmitting signals from said various components (e.g., traces, vias, bonding pads, etc., omitted for simplicity), as described in more detail below.

[0030] Refer again Figure 1A The second die stack 106 can be electrically coupled to the second substrate 112 via a plurality of second electrical connectors 120. The second electrical connectors 120 may be the same as or substantially similar to the first electrical connector 118. In the illustrated embodiment, for example, the second electrical connector 120 includes a plurality of bonding wires connecting individual second dies 108 to each other and / or to the second substrate 112. However, in other embodiments, other types of die-to-die or die-to-substrate interconnect technologies may be used.

[0031] The third die 114 may be mounted on the second substrate 112 via multiple interconnect structures 122 (e.g., bumps, microbumps, pillars, posts, columns, etc.). In some embodiments, the third die 114 is attached to the second substrate 112 with its face down configured, wherein the interconnect structures 122 electrically couple the active surfaces of the third die 114 to the second substrate 112. The interconnect structures 122 may optionally be composed of an underfill material (for simplicity, in...). Figure 1A (The text is omitted here.) For example, the location of the third die 114 on the second substrate 112 provides more tolerance for introducing underfill material around the interconnect structure 122 during the manufacturing process, compared to a device where the third die 114 is located on the same substrate as the first die stack 102. However, in other embodiments, the third die 114 may be mounted face-up (e.g., using a die attachment film) and may be electrically coupled to the second substrate 112 via wire bonding or other electrical connectors. Figure 1A As shown, the device 100 may not include any intervening spacers, supports, other dies, etc. between the third die 114 and the second substrate 112.

[0032] The second substrate 112 may include one or more routing elements (e.g., signal traces, bonding pads, vias, etc., as previously referenced). Figure 1C As described, signals are transmitted between the second die stack 106 and the third die 114. For example, at least some of the second electrical connector 120 and interconnect structure 122 can be connected to corresponding bonding pads (not shown) on the second substrate 112, and routing elements of the second substrate 112 can connect individual bonding pads to each other. Thus, the third die 114 can communicate with the second die stack 106 via the second substrate 112, for example, to control the operation of the second die 108.

[0033] The second substrate 112 can be electrically coupled to the first substrate 110 via at least one third electrical connector 124 (e.g., one or more bonding wires). The third electrical connector 124 can route signals from the second die stack 106 and / or the third die 114 to the first substrate 110, which can then route the signals to an external device (e.g., via routing elements of the first substrate 110 and conductive elements 116). Conversely, signals from an external device can be transmitted to the second die stack 106 and / or the third die 114 via conductive elements 116, the first substrate 110, the third electrical connector 124, and the second substrate 112. The conductive elements 116, the first substrate 110, the third electrical connector 124, and the second substrate 112 can also transmit power from an external power source to the second die stack 106 and / or the third die 114. Optionally, the first die stack 102 can communicate with the second die stack 106 and / or the third die 114 via signals routed through the first substrate 110, the third electrical connector 124, and the second substrate 112.

[0034] In some embodiments, the second substrate 112 contains most or all of the signal routing paths for communication between the second die stack 106 and the third die 114, and / or the first substrate 110 contains little or no signal routing paths for communication between the second die stack 106 and the third die 114. Similarly, in some embodiments, the first substrate 110 contains most or all of the signal routing paths for communication between the first die stack 102 and an external device, and / or the second substrate 112 contains little or no signal routing paths for communication between the first die stack 102 and an external device. Therefore, the first die stack 102 and the second die stack 106 can be electrically isolated from each other because their respective signal routing paths are decoupled from each other and distributed across different substrates.

[0035] Optionally, the first substrate 110 and / or the second substrate 112 may include signal routing paths for communication between an external device and the third die 114 and / or between an external device and the second die stack 106. These signal routing paths may be different from and / or separate from the signal routing paths for communication between the external device and the first die stack 102 (e.g., electrically isolated from said signal routing paths). For example, the first substrate 110 may include a plurality of external contacts (e.g., which may be or include conductive elements 116) for communication with the external device, the first die stack 102 may be electrically coupled to a first subset of the external contacts, and the second die stack 106 and / or the third die 114 may be electrically coupled to a second, different subset of the external contacts. In some embodiments, the third die 114 is electrically inserted between the second die stack 106 and the second substrate 112 and / or the external device. In such embodiments, the second die stack 106 does not communicate directly with the second substrate 112 and / or external devices, but rather indirectly with the second substrate 112 and / or external devices via signals routed through the third die 114.

[0036] Electrical isolation between the first die stack 102 and the second die stack 106 provides various advantages. For example, electrical isolation can reduce crosstalk and / or other interference that would otherwise occur if the signal routing paths for the first die stack 102 and the second die stack 106 were located in the same substrate. Additionally, by separating the signal routing paths across two different substrates, the amount and / or complexity of routing in each substrate can be reduced. For example, the number of routing layers in each substrate can be reduced, which can reduce the overall size (e.g., height) of the device 100. In some embodiments, the first substrate 110 and / or the second substrate 112 each independently have no more than six layers, five layers, four layers, three layers, or two layers.

[0037] Furthermore, because the signal routing paths for the first die stack 102 and the second die stack 106 are located in different substrates, the routing in each substrate can be modified independently (e.g., based on the desired arrangement and / or functionality of the corresponding die stack) with little or no effect on the routing in the other substrate. Therefore, the same or similar configurations of the first substrate 110 and the first die stack 102 can be used with many different configurations of the second substrate 112, the second die stack 106, and the third die 114; and vice versa. This modular approach improves design and manufacturing flexibility and reduces costs.

[0038] like Figure 1A As shown, device 100 may further include molding material 126 encapsulating a first substrate 110, a first die stack 102, a second substrate 112, a second die stack 106, and / or a third die 114. Molding material 140 may be a resin, epoxy resin, silicone-based material, polyimide, or any other material suitable for protecting the various components of device 100 from contaminants and / or physical damage. In some embodiments, for example, compared to a package stack (POP) configuration in which device components are individually encapsulated and then assembled into a single package, the first substrate 110, the first die stack 102, the second substrate 112, the second die stack 106, and / or the third die 114 are all encapsulated by a continuous volume of molding material 140.

[0039] Optionally, device 100 may include surface-mount components ( Figure 1A (Not shown), such as capacitors, resistors, inductors, and / or other circuit elements. Surface mount assemblies may be on the first substrate 110, the second substrate 112, or a combination thereof. The use of multiple substrates provides greater space and flexibility for positioning the surface mount assemblies. In some embodiments, the semiconductor device 100 includes other components such as external heat sinks, sleeves (e.g., thermally conductive sleeves), electromagnetic interference (EMI) shielding components, etc.

[0040] As described above, in some embodiments, device 100 is a memory device and configured to connect to a host device that utilizes memory for temporary or permanent storage of information or components thereof. The host device may be a computing device, such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, tablet computer, digital reader, digital media player), or a component thereof (e.g., a central processing unit, coprocessor, dedicated memory controller, etc.). The host device may be a networking device (e.g., a switch, router, etc.), a recorder of digital images, audio, and / or video, a vehicle, an appliance, a toy, or any of several other products. In some embodiments, the host device may be directly connected to device 100, but in other embodiments, the host device may be indirectly connected to device 100 (e.g., via a network connection or through an intermediary device).

[0041] Figure 2 and 3 This describes semiconductor devices having various die stacking configurations according to embodiments of the present invention. Figure 2 and 3 The device shown in the document is broadly similar to the one described above. Figure 1A-1C The described device 100. Therefore, similarity numbers are used to identify similar or identical components, and Figure 2 and 3 The description of the apparatus shown in the document will be limited to those different from those in the present document. Figure 1A-1C Those features of the device 100.

[0042] Figure 2 A partial schematic cross-sectional view of a semiconductor device 200 (“device 200”) configured according to an embodiment of the present invention. Device 200 may be generally similar to Figure 1A-1C The device 100 differs from the device 200 in that the device 200 includes multiple die stacks (e.g., second die stack 206a and third die stack 206b) mounted on a second substrate 212. While the illustrated embodiment shows two die stacks 206a-b on the second substrate 212, in other embodiments, the device 200 may include a larger number of die stacks on the second substrate 212, such as three, four, five, or more die stacks. The configuration of the device 200 can facilitate a reduction in overall package height while accommodating more dies.

[0043] The second die stack 206a may contain a set of second dies 208a, and the third die stack 206b may contain a set of third dies 208b. The second dies 208a may all be of the same die type as the third dies 208b, or some or all of the second dies 208a may be of a different die type than some or all of the third dies 208b. In some embodiments, the second and third dies 208a-b may be memory dies (e.g., NAND dies). The second die stack 206a may contain the same number of dies as the third die stack 206b, or the second die stack 206a may contain a different number of dies than the third die stack 206b. Although Figure 2 The second and third die stacks 206a-b are described as each having four dies, but in other embodiments, the second and third die stacks 206a-b may each have a different number of dies (e.g., one, two, three, five, six, seven, eight or more dies).

[0044] The device 200 may further include a fourth die 214, which can be coupled with Figure 1A The third die 114 is the same as or similar to the first die. For example, the fourth die 214 may be a controller and / or logic die (e.g., a memory controller die) configured to control the operation of the second die stack 206a and / or the third die stack 206b. In the illustrated embodiment, the fourth die 214 is positioned on the second substrate 212 between the second die stack 206a and the third die stack 206b. However, in other embodiments, the fourth die 214 may be located at different positions on the second substrate 212 (e.g., to positions laterally spaced from the second and / or third die stacks 206a-b).

[0045] The second and third die stacks 206a-b are electrically coupled to the second substrate 212 via a second electrical connector 220a (e.g., a second bonding wire) and a third electrical connector 220b (e.g., a third bonding wire), respectively. Therefore, the fourth die 214 can communicate with the second and third die stacks 206a-b via routing elements in the second substrate 212. Optionally, the second and third die stacks 206a-b can also communicate with each other via routing elements in the second substrate 212. In some embodiments, the second substrate 212 contains most or all of the signal routing paths for communication between the second and third die stacks 206a-b and / or the fourth die 214, and / or the first substrate 210 contains little or no signal routing paths for communication between the second and third die stacks 206a-b and / or the fourth die 214.

[0046] The second substrate 212 can be electrically coupled to the first substrate 210 via at least one fourth electrical connector 224 (e.g., one or more fourth bonding wires). The fourth electrical connector 224 can route signals from the second die stack 206a, the third die stack 206b, and / or the fourth die 214 to the first substrate 210, which can then route the signals to an external device (e.g., via routing elements of the first substrate 210 and conductive element 216). Conversely, signals from an external device can be transmitted via conductive element 216, the first substrate 210, the fourth electrical connector 224, and the second substrate 212 to the second die stack 206a, the third die stack 206b, and / or the fourth die 214. The conductive element 216, the first substrate 210, the fourth electrical connector 224, and the second substrate 212 can also transmit power from an external power source to the second die stack 206a, the third die stack 206b, and / or the fourth die 214. Optionally, the first die stack 202 may communicate with the second die stack 206a, the third die stack 206b and / or the fourth die 214 via signals routed through the first substrate 210, the fourth electrical connector 224 and the second substrate 212.

[0047] Figure 3 A partial schematic cross-sectional view of a semiconductor device 300 (“device 300”) configured according to an embodiment of the present invention. Device 300 may be generally similar to Figure 1A-1C The device 100 differs from the device 300 in that the device 300 includes multiple die stacks (e.g., a first die stack 302a and a third die stack 302b) mounted on a first substrate 310. While the illustrated embodiment shows two die stacks 302a-b on the first substrate 310, in other embodiments, the device 300 may include a larger number of die stacks on the first substrate 310, such as three, four, five, or more die stacks. The configuration of the device 300 can facilitate a reduction in overall package height while accommodating more dies.

[0048] The first die stack 302a may contain a set of first dies 304a, and the third die stack 302b may contain a set of third dies 304b. The first dies 304a may be of the same die type as the third dies 304b, or some or all of the first dies 304a may be of a different die type than some or all of the third dies 304b. In some embodiments, some or all of the first dies and the third dies 304a-b are memory dies (e.g., DRAM dies). The first die stack 302a may contain the same number of dies as the third die stack 302b, or the first die stack 302a may contain a different number of dies than the third die stack 302b. Although Figure 3The first die stack and the third die stack 302a-b are described as each having four dies, but in other embodiments, the first die stack and the third die stack 302a-b may each have a different number of dies (e.g., one, two, three, five, six, seven, eight or more dies).

[0049] In the illustrated embodiment, the second substrate 312 is mounted on and extends across both the first die stack and the third die stack 302a-b. However, in other embodiments, the second substrate 312 may be mounted on only the first die stack 302a or only the third die stack 302b. As previously referenced Figure 1A-1C As described, the second substrate 312 may support the second die stack 306 and / or the fourth die 314 (which may be connected to...). Figure 1A (The third nude film 114 is the same as or similar to it).

[0050] The first die stack and the third die stack 302a-b can be electrically coupled to the first substrate 310 via a first electrical connector 318a (e.g., a first bonding wire) and a third electrical connector 318b (e.g., a third bonding wire), respectively. Therefore, the first die stack and the third die stack 302a-b can communicate with each other via routing elements in the first substrate 310. Optionally, the first die stack and the third die stack 302a-b can communicate with external devices via routing elements in the first substrate 310 and conductive elements 316. The first substrate 310 and conductive elements 316 can also transmit power from an external power source to the first die stack and the third die stack 302a-b. In some embodiments, the first substrate 310 contains most or all of the signal routing paths for communication between the first die stack and the third die stack 302a-b, and / or the second substrate 312 contains little or no signal routing paths for communication between the first die stack and the third die stack 302a-b. Similarly, in some embodiments, the first substrate 310 contains most or all of the signal routing paths for communication between the first die stack and the third die stack 302a-b and external devices, and / or the second substrate 312 contains little or no signal routing paths for communication between the first die stack and the third die stack 302a-b and external devices.

[0051] Figure 4 This is a flowchart illustrating a method 400 for manufacturing a semiconductor device according to an embodiment of the present invention. Method 400 can be used to manufacture any of the semiconductor devices described herein, for example... Figure 1A-3 Any one of the devices 100-300.

[0052] Method 400 begins at step 410, wherein a first assembly is formed by mounting a plurality of first dies on a first substrate. The first dies (e.g., Figure 1A The first bare die 104 can be mounted on the first substrate (e.g., Figure 1A The first assembly is formed on a first substrate 110 to create a first die stack (e.g., first die stack 102) according to techniques known to those skilled in the art. In some embodiments, the first assembly includes a plurality of first memory dies (e.g., DRAM dies) arranged in a vertical stack on a package substrate. Optionally, the first dies may be assembled into a plurality of die stacks on the first substrate, for example, as previously referenced. Figure 3 As described. Step 410 may also include electrically coupling the first die to the first substrate via a bonding wire or other electrical connector. In other embodiments, the first die may be electrically coupled to the first substrate in a subsequent step of method 400 (e.g., during or after step 430 described below).

[0053] At step 420, method 400 continues to form a second assembly by mounting a plurality of second and third dies on a second substrate. The second dies (e.g., Figure 1A The second bare die 108 can be mounted on the second substrate (e.g., Figure 1A The second die is placed on a second substrate 112 to form a second die stack (e.g., second die stack 106) according to techniques known to those skilled in the art. Optionally, the second die may be assembled into multiple die stacks on the second substrate, for example, as previously referenced. Figure 2 As described. The third nude (e.g., Figure 1A The third die 114 may be mounted on the second substrate before, during, or after the second die is mounted on the second substrate. In some embodiments, the second assembly includes a plurality of second memory dies (e.g., NAND dies) arranged in a vertical stack on an intermediate substrate, and controller and / or logic dies for the second memory dies on the intermediate substrate.

[0054] Optionally, step 410 may further electrically couple a second die to a second substrate (e.g., via bonding wires and / or other electrical connectors), and / or electrically couple a third die to the second substrate (e.g., via an interconnect structure). The third die may be electrically coupled to the second substrate before, during, or after the second die is electrically coupled to the second substrate. In other embodiments, the second and / or third die may be electrically coupled to the second substrate in subsequent steps of method 400 (e.g., during or after step 430 described below).

[0055] At step 430, method 400 includes mounting the second assembly onto the first assembly. The second assembly may be coupled to the first assembly using any technique known to those skilled in the art, such as die attachment films or other suitable adhesive materials. Optionally, step 430 may further include electrically coupling the second assembly to the first assembly, for example, using bonding wires and / or other electrical connectors bridging the first and second substrates.

[0056] At step 440, method 400 includes using a molding material (e.g., according to techniques known to those skilled in the art). Figure 1A The molding material 126) encapsulates the first assembly and the second assembly. The first assembly and the second assembly can be encapsulated in a single process step, such that the final device is an integral package having the same molding material surrounding both the first assembly and the second assembly.

[0057] Compared to conventional manufacturing processes, method 400 offers various advantages. For example, because the first and second assemblies are manufactured in separate process steps, they can be tested independently before assembling the final device. Therefore, if one of the assemblies fails or is otherwise unsuitable for use, the individual assembly can be discarded and replaced, rather than the entire device. This method reduces manufacturing costs and waste.

[0058] References above Figure 1A-4 Any of the semiconductor devices and / or packages with the described features can be incorporated into any of a multitude of larger and / or more complex systems, a representative example of which is... Figure 5 The system 500 is schematically shown in the diagram. System 500 may include a processor 502, a memory 504 (e.g., SRAM, DRAM, flash memory, and / or other memory devices), an input / output device 506, and / or other subsystems or components 508. (See above reference) Figure 1A-4 The described semiconductor die and / or package may be included Figure 5The resulting system 500 can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and / or other functions. Therefore, representative examples of system 500 include, but are not limited to, computers and / or other data processors, such as desktop computers, laptop computers, networked appliances, handheld devices (e.g., handheld computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multiprocessor systems, processor-based or programmable consumer electronics devices, network computers, and microcomputers. Additional representative examples of system 500 include lamps, cameras, vehicles, etc. Regarding these and other examples, system 500 can be housed in a single unit or distributed, for example, across multiple interconnected units via a communication network. Therefore, components of system 500 can include local and / or remote memory storage devices and any of a wide variety of suitable computer-readable media.

[0059] In summary, it should be understood that specific embodiments of the present technology have been described herein for illustrative purposes, but various modifications may be made without departing from this disclosure. Therefore, the present invention is not limited to the appended claims. Furthermore, certain aspects of the new technology described in the context of specific embodiments may be combined or removed in other embodiments. Moreover, while advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments are intended to present such advantages to fall within the scope of the present technology. Therefore, this disclosure and associated technologies may cover other embodiments not explicitly shown or described herein.

Claims

1. A semiconductor device comprising: Packaging substrate; A first die stack is mounted on the packaging substrate, and the first die stack includes a plurality of first memory dies; An intermediate substrate, which is mounted on the first die stack, includes a plurality of routing elements; A second die stack is mounted on the intermediate substrate, and the second die stack includes a plurality of second memory dies; A controller die, mounted on the intermediate substrate, wherein the controller die is configured to communicate with the second die stack via the routing element of the intermediate substrate; as well as A molding material encapsulates the first die stack, the second die stack, the intermediate substrate, and the controller die. The signal routing for the second die stack is physically separated and / or electrically isolated from the signal routing for the first die stack.

2. The semiconductor device of claim 1, wherein at least some of the first memory dies are memory die types different from at least some of the second memory dies.

3. The semiconductor device of claim 2, wherein the first memory die comprises a plurality of DRAM dies, and the second memory die comprises a plurality of NAND dies.

4. The semiconductor device of claim 1, wherein the intermediate substrate is directly coupled to the uppermost first memory die in the first die stack.

5. The semiconductor device of claim 4, wherein the intermediate substrate is coupled to the uppermost first memory die via a die attachment film.

6. The semiconductor device according to claim 1, wherein: The packaging substrate includes multiple external packaging contacts. The first die stack is electrically coupled to a first subset of the external package contacts, and The second die stack and the controller die are electrically coupled to a second subset of the external package contacts.

7. The semiconductor device of claim 1, wherein the first die stack is electrically coupled to the package substrate via a plurality of first bond lines, and the second die stack is electrically coupled to the intermediate substrate via a plurality of second bond lines.

8. The semiconductor device of claim 7, further comprising at least one bonding wire coupling the intermediate substrate to the package substrate.

9. The semiconductor device of claim 7, wherein the packaging substrate comprises no more than three functional layers.

10. The semiconductor device of claim 1, further comprising a third die stack mounted on the intermediate substrate, the third die stack including a plurality of third memory dies, wherein the controller die is configured to communicate with the third die stack via the routing element of the substrate.

11. The semiconductor device of claim 1, further comprising a third die stack mounted on the package substrate, wherein the third die stack includes a plurality of third memory dies, and wherein the intermediate substrate is mounted on both the first die stack and the third die stack.

12. The semiconductor device of claim 1, wherein the controller die is electrically inserted between the second die stack and the package substrate.

13. A semiconductor device comprising: Packaging substrate; A first die stack is mounted on the package substrate, the first die stack comprising a plurality of DRAM dies coupled to the package substrate; An intermediate substrate, which is directly mounted on the first die stack, the intermediate substrate includes a plurality of routing elements, wherein the intermediate substrate is electrically coupled to the package substrate via one or more bonding wires; A second die stack is mounted on the intermediate substrate, and the second die stack includes a plurality of NAND dies coupled to the intermediate substrate; A controller die, mounted on the intermediate substrate, wherein the controller die is configured to communicate with the second die stack via the routing element of the intermediate substrate; as well as A molding material encapsulates the first die stack, the second die stack, the intermediate substrate, and the controller die. The signal routing for the second die stack is physically separated and / or electrically isolated from the signal routing for the first die stack.

14. The semiconductor device of claim 13, further comprising: Multiple first bonding lines electrically couple the first die stack to the package substrate; as well as Multiple second bonding lines electrically couple the second die stack to the intermediate substrate.

15. The semiconductor device according to claim 13, wherein: The packaging substrate includes multiple external packaging contacts. The first die stack is electrically coupled to a first subset of the external package contacts, and The second die stack and the controller die are electrically coupled to a second subset of the external package contacts.

16. The semiconductor device of claim 13, wherein the packaging substrate comprises no more than three functional layers, and the intermediate substrate comprises no more than two functional layers.

17. The semiconductor device of claim 13, wherein the controller die is electrically inserted between the second die stack and the package substrate.

18. A method for manufacturing a semiconductor device, comprising: A first assembly is formed by mounting a plurality of first memory dies on a first substrate; A second assembly is formed by mounting a plurality of second memory dies and a controller die on a second substrate, wherein the second memory dies are electrically coupled to the controller die via routing elements in the second substrate; Install the second assembly onto the first assembly; as well as After the second assembly is installed on the first assembly, the first assembly and the second assembly are encapsulated with molding material. The signal routing for the second assembly is physically separated and / or electrically isolated from the signal routing for the first assembly.

19. The method of claim 18, further comprising: The first memory die is electrically coupled to the first substrate via multiple first bonding wires; The second memory die is electrically coupled to the second substrate via multiple second bonding wires; as well as The second substrate is electrically coupled to the first substrate via one or more third bonding wires.

20. The method of claim 18, wherein the first memory die comprises a plurality of DRAM dies, and the second memory die comprises a plurality of NAND dies.

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