Common well structure, layout and method

Abstract

Common well structures, layouts, and methods are disclosed. An integrated circuit (IC) structure includes a continuous well having a first well portion to a third well portion. The continuous well is one of an n-well or a p-well, the first well portion extends in a first direction, the second well portion extends from the first well portion in a second direction perpendicular to the first direction, and the third well portion extends from the first well portion in the second direction parallel to the second well portion.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more specifically to common well structures, layouts, and methods. Background Technology

[0002] The ongoing miniaturization trend in integrated circuits (ICs) has resulted in increasingly smaller devices that consume less power but deliver more functionality at higher speeds compared to earlier technologies. This miniaturization has been achieved through design and manufacturing innovations linked to increasingly stringent specifications. Various electronic design automation (EDA) tools are used to generate, modify, and verify semiconductor device designs while ensuring compliance with IC architecture design and manufacturing specifications. Summary of the Invention

[0003] According to a first aspect of this disclosure, an integrated circuit (IC) structure is provided, comprising: a first continuous well, which is one of an n-well or a p-well, the first continuous well comprising: a first well portion extending in a first direction; a second well portion extending from the first well portion in a second direction perpendicular to the first direction; and a third well portion extending from the first well portion in the second direction parallel to the second well portion.

[0004] According to a second aspect of this disclosure, an integrated circuit (IC) structure is provided, comprising: a first through-silicon via (TSV) isolation structure and a second TSV isolation structure aligned along a first direction; a first continuous well, which is one of an n-well or a p-well, the first continuous well comprising: a first well portion adjacent to the first TSV isolation structure; and a plurality of second well portions extending from the first well portion in the first direction; and a second continuous well, which is the other of the n-well or the p-well, the second continuous well comprising: a third well portion adjacent to the second TSV isolation structure; and a plurality of fourth well portions extending from the third well portion in a second direction opposite to the first direction, wherein the plurality of second well portions alternate with the plurality of fourth well portions along a third direction perpendicular to the first direction and the second direction.

[0005] According to a third aspect of this disclosure, a method for manufacturing an integrated circuit (IC) structure is provided, the method comprising: configuring each of an n-well and a p-well in a first IC die to have the following portions: a first portion extending in a first direction; and a second portion and a third portion extending from the first portion in a second direction perpendicular to the first direction; and forming an IC device including a first pickup structure electrically connected to the n-well and a second pickup structure electrically connected to the p-well, wherein forming the IC device comprises: forming a PMOS transistor in the second or third portion of the n-well and forming an NMOS transistor in the second or third portion of the p-well. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figure 1A This is a diagram of an IC structure based on some embodiments.

[0008] Figure 1B This is a diagram of an IC structure based on some embodiments.

[0009] Figure 1C This is an illustration of an IC package according to some embodiments.

[0010] Figure 2 This is a flowchart of a method for operating an IC device according to some embodiments.

[0011] Figure 3 This is a flowchart of a method for manufacturing an IC structure according to some embodiments.

[0012] Figure 4 This is an illustration of an IC layout diagram according to some embodiments.

[0013] Figure 5 This is a flowchart of a method for generating an IC layout diagram according to some embodiments.

[0014] Figures 6A-6C This is an illustration of an IC layout diagram according to some embodiments.

[0015] Figure 7 This is a flowchart of a method for generating an IC layout diagram according to some embodiments.

[0016] Figure 8 It is a block diagram of a system generated based on IC layout diagrams of some embodiments.

[0017] Figure 9 This is a block diagram of an IC manufacturing system and associated IC manufacturing process according to some embodiments. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components, values, steps, operations, materials, arrangements, etc., are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, steps, operations, materials, arrangements, etc., are contemplated. For example, in the following description, forming a first feature above or on a second feature can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] In addition, spatially related terms (e.g., "below," "under," "down," "above," "up") may be used herein to facilitate the description of the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0020] In various embodiments, the IC structure based on the IC layout includes a well shared between more than two rows of IC devices in such a way that the well includes a first portion extending in a direction perpendicular to each row and multiple portions extending from the first portion into each row. The first portion corresponds to a border (or a location within a border) of an IC block including IC devices (e.g., a block between through-silicon vias (TSVs)). The IC block including the shared well implements latch-up protection by including a single pickup structure (e.g., a portion of a tap cell) capable of biasing each of the multiple portions, such that the shared well is biased using a smaller number of pickup structures compared to the number of portions. Compared to a method where one row or pair of rows of IC devices corresponds to a single well including at least one pickup structure, the IC block including the shared well uses fewer pickup structures, thereby increasing the space utilization of the IC devices.

[0021] Figure 1AThis is an illustration of an IC structure 100 according to some embodiments. The IC structure 100 (also referred to as IC block 100 in some embodiments) corresponds to an IC die (e.g., as described below regarding...). Figure 1B The IC structure 100D discussed refers to the circuit portion (e.g., digital circuit block) of the substrate, and in some embodiments, the IC structure 100 is also included in an IC package (e.g., as discussed below). Figure 1C The discussion focuses on the 100P IC package. Besides the 100 IC structure, Figure 1A The X and Y directions are depicted.

[0022] IC structure 100 is based on IC layout diagram (e.g., the following about Figures 6A-6C The IC layout diagrams 600A-600C discussed are executed by performing the following steps regarding... Figure 3 Non-limiting examples of IC structures manufactured using some or all of the methods discussed in 300.

[0023] Figure 1A A plan view (XY plane) of an IC structure 100 is depicted, which includes border regions 100A and 100B extending in the Y direction and an IC device 100C located between the border regions 100A and 100B. Figure 1A In the illustrated embodiment, the IC device 100C of the five rows R1-R5 extends in the X direction (also referred to as the row direction in some embodiments).

[0024] IC structure 100 includes a continuous well WA (also referred to as a shared well WA in some embodiments), which includes: a portion WAS located in border region 100A and extending in the Y direction; and portions WAP1-WAP3 extending from the portion WAS in the positive X direction within one or more corresponding rows R1-R5. A continuous well WB (also referred to as a shared well WB in some embodiments) includes: a portion WBS located in border region 100B and extending in the Y direction; and portions WBP1-WBP3 extending from the portion WBS in the negative X direction within one or more corresponding rows R1-R5. IC structure 100 also includes at least one instance of a pickup structure PA located in the continuous well WA and at least one instance of a pickup structure PB located in the continuous well WB, as described below.

[0025] Figure 1A The orientation of the IC structure 100 depicted is a non-limiting example provided for illustrative purposes. In some embodiments, border regions 100A and 100B, as well as portions of WAS and WBS, extend in the X direction, and rows R1-R5, as well as portions of WAP1-WAP3 and WBP1-WBP3, extend in the Y direction. In some embodiments, the IC structure 100 has a... Figure 1AThe orientation shown is the opposite of the orientation, which is horizontal and / or vertical.

[0026] Each figure in this article (e.g., Figure 1A (These figures are simplified for illustrative purposes.) They depict views of IC structures, dies, packages, and layouts, including and excluding various features for the convenience of the following discussion. In various embodiments, except... Figures 1A-1C , Figure 4 and Figures 6A-6C In addition to the features depicted, the depicted IC structure, die, package and / or layout diagram includes one or more features corresponding to power distribution structures, metal interconnects, contacts, vias, gate structures or other transistor elements, isolation structures, etc.

[0027] In various embodiments, the IC device 100C includes one or a combination of logic gates or other digital circuits, components of signal or application processors, memory, high-bandwidth memory (HBM), system-on-IC (SoIC), transmitters and / or receivers, application-specific integrated circuits (ASIC), large-scale integrated circuits (LSI) or very large-scale integrated circuits (VLSI), voltage or current regulators, etc.

[0028] IC device 100C includes n-type metal-oxide-semiconductor (NMOS) and p-type metal-oxide-semiconductor (PMOS) transistors (not shown). The NMOS transistor is located in one of the continuous wells WA or WB, while the PMOS transistor is located in the other of the continuous wells WA or WB.

[0029] exist Figure 1A In the illustrated embodiment, IC device 100C extends from border region 100A to border region 100B along each row R1-R5 having a height CH1 (also referred to as cell height CH1 in some embodiments). In various embodiments, IC structure 100 includes IC device 100C configured, for example, to include one or more gaps in one or more rows, and / or to partially extend between border regions 100A and 100B in one or more rows such that NMOS and PMOS transistors are located in consecutive wells WA and WB.

[0030] exist Figure 1A In the illustrated embodiment, IC device 100C corresponds to each of the five rows R1-R5 of the total number of IC structure 100. In various embodiments, IC device 100C corresponds to fewer or more of the five rows, and / or corresponds to a subset of the total number of rows of IC structure 100.

[0031] The IC structure 100 is thus configured to include a total area, which includes at least the area occupied by the IC device 100C and the border areas 100A and 100B. In some embodiments, the total area of ​​the IC structure 100 is equal to the total area occupied by the IC device 100C and the border areas 100A and 100B. In some embodiments, the total area of ​​the IC structure 100 is larger than the total area occupied by the IC device 100C and the border areas 100A and 100B, and in addition to the IC device 100C and the border areas 100A and 100B, the IC structure 100 includes one or more areas (not shown), such as one or more dummy devices.

[0032] A well (e.g., a continuous well WA or WB) is a continuous portion of a semiconductor wafer (e.g., a silicon (Si) wafer or an epitaxial Si layer) suitable for forming one or more IC devices (e.g., IC device 100C). In various embodiments, a well is a p-well based on a semiconductor portion comprising one or more acceptor dopants (e.g., boron (B) or aluminum (Al)), or an n-well based on a semiconductor portion comprising one or more donor dopants (e.g., phosphorus (P) or arsenic (As)). A continuous well WA is one of a p-well or an n-well, and a continuous well WB is the other of a p-well or an n-well.

[0033] In some embodiments, the IC structure 100 is isolated by one or more isolation structures ( Figure 1A The IC structure 100 is surrounded by one or more insulating structures (i.e., structures comprising one or more dielectric materials), such that each of the continuous wells WA and WB is electrically isolated from a substrate outside the IC structure 100. The dielectric material includes one or more of the following: silicon dioxide (SiO2), silicon nitride (Si3N4), and / or a high-k dielectric material (e.g., a dielectric material with a k value greater than 3.8 or 7.0, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), or titanium oxide (TiO2), or other suitable materials). In some embodiments, the IC structure 100 is partially surrounded by one or more insulating structures, such that one or both of the continuous wells WA or WB are continuous with one or more portions of a substrate (not shown) outside the IC structure 100.

[0034] exist Figure 1A In the illustrated embodiment, the continuous wells WA and WB comprise corresponding portions WAP1-WAP3 (WAPn) and WBP1-WBP3 (WBPn) of the same total number n. In some embodiments, the continuous wells WA and WB comprise different numbers of corresponding portions, such as WAPn and WBPn±1.

[0035] exist Figure 1AIn the illustrated embodiments, each of the continuous wells WA and WB includes corresponding portions WAPn and WBPn with a total n = 3. In various embodiments, one or both of the continuous wells WA or WB include corresponding portions WAPn or WBPn with a total n less than or greater than three.

[0036] In some embodiments, one or both of the continuous wells WA or WB include corresponding portions with a total number n from five (5) to 75. In some embodiments, one or both of the continuous wells WA or WB include corresponding portions with a total number n from 15 to 50. In some embodiments, one or both of the continuous wells WA or WB include corresponding portions with a total number n from 25 to 40.

[0037] In some embodiments, the continuous well portions WAPn and / or WBPn having a total of n cause the IC structure 100 to have dimensions corresponding to the dimensions of the IC device 100C (e.g., in the Y direction). In some embodiments, the continuous well portions WAPn and / or WBPn having a total of n cause the IC structure 100 to have one or more substrate features external to the IC structure 100 ( Figure 1A Dimensions (not shown in the image) (e.g., below regarding) Figure 1B and Figure 1C The dimensions corresponding to the height of the TSV structure are discussed.

[0038] exist Figure 1A In the illustrated embodiments, the continuous wells WA and WB comprise respective portions WAPn and WBPn, which are continuous with each other based on a corresponding single portion WAS or WBS extending in the Y direction and located within the respective border regions 100A or 100B. In various embodiments, one or both of the continuous wells WA or WB comprise respective portions WAPn or WBPn, which are continuous with each other based on multiple instances of the corresponding portions WAS or WBS extending in the Y direction and / or one or more instances of the corresponding portions WAS or WBS located in the IC structure 100 outside the respective border regions 100A or 100B.

[0039] With the above configuration, IC structure 100 includes consecutive wells WA and WB configured, for example, in an interdigitated, serpentine, or other configuration, such that each of the consecutive wells WA and WB is shared between more than two rows (e.g., rows R1-R5).

[0040] Each instance of the pick-up structures PA and PB (also referred to collectively as the connection structure in some embodiments) includes a heavy doping amount in a portion of the corresponding continuous well WA (one of the portions of WAPn) or a portion of the continuous well WB (one of the portions of WBPn), and has an n-type or p-type doping that matches the n-well or p-well type of the corresponding continuous well WA or WB.

[0041] Each instance of the pickup structure PA or PB also includes or contacts one or more conductive elements (not shown) configured to electrically connect the pickup structure to a corresponding power distribution structure (not shown). IC structure 100 is configured such that the n-type continuous well WA or WB and the corresponding instance of the pickup structure PA or PB are electrically connected to a power distribution structure configured to have a supply voltage, and that the p-type continuous well WA or WB and the corresponding instance of the pickup structure PA or PB are electrically connected to a power distribution structure configured to have a reference voltage (e.g., ground).

[0042] Each of the pickup structures PA and PB is thus configured to avoid latch-up events during operation by preventing the forward bias of a diode (which includes the respective continuous well WA or WB and the source / drain terminal of the transistor located in the respective continuous well WA or WB), for example, by biasing one of the continuous wells WA or WB that is an n-well using a supply voltage, thereby preventing latch-up events by preventing the forward bias of the diode (which includes the one of the continuous wells WA or WB and the p-type source / drain terminal of the PMOS transistor of the IC device 100C located in the one of the continuous wells WA or WB).

[0043] exist Figure 1A In the illustrated embodiment, instances of pickup structure PA are located in portions WAP2 and WAP3, instances of pickup structure PB are located in portions WBP1 and WBP2, a first instance of each of pickup structures PA and PB is located in row R2, a second instance of each of pickup structures PA and PB is located in row R4, and instances of pickup structures PA and PB are aligned in the Y direction and located within IC device 100C.

[0044] In various embodiments, instances of the pickup structures PA and / or PB are arranged in other ways. In some embodiments, instances of the pickup structures PA and / or PB are not aligned in the Y direction. In some embodiments, one or more instances of the pickup structures PA and / or PB are located in border regions 100A and / or border regions 100B, thereby being adjacent to one or both of the corresponding portions of the WAS or WBS.

[0045] exist Figure 1AIn the illustrated embodiment, the IC structure 100 includes a total of: two instances each of pickup structures PA and PB, three instances each of partial WAPn and WBPn, and five rows R1-R5, corresponding to the ratio of: three partial WAPn to two pickup structures PA, three partial WBPn to two pickup structures PB, and five rows R1-R5 to two instances each of pickup structures PA and PB.

[0046] In some embodiments, the IC structure 100 includes instances of pickup structures PA and / or PB, portions of WAPn and / or WBPn, and / or one or more of rows R1-R5. Figure 1A The quantities shown are different, and thus one or more corresponding ratios have the same characteristics as... Figure 1A The examples shown correspond to different values.

[0047] In some embodiments, one or both of the ratio of a portion of WAPn to instances of the picking structure PA or the ratio of a portion of WBPn to instances of the picking structure PB have a value from two to twenty. In some embodiments, one or both of the ratio of a portion of WAPn to instances of the picking structure PA or the ratio of a portion of WBPn to instances of the picking structure PB have a value from five to fifteen. In some embodiments, one or both of the ratio of a portion of WAPn to instances of the picking structure PA or the ratio of a portion of WBPn to instances of the picking structure PB have a value equal to ten (10).

[0048] In some embodiments, the ratio of rows (e.g., rows R1-R5) of IC device 100C to instances of pickup structures PA and / or PB has a value from three to forty. In some embodiments, the ratio of rows of IC device 100C to instances of pickup structures PA and / or PB has a value from ten to thirty. In some embodiments, the ratio of rows of IC device 100C to instances of pickup structures PA and / or PB has a value equal to twenty (20).

[0049] As the ratio of rows of WAPn and / or WBPn and / or instances of IC device 100C to instances of pickup structures PA and / or PB increases, for a given size of IC structure 100, the total number of instances of pickup structures PA and PB decreases, resulting in a decrease in the area occupied by pickup structures PA and PB relative to the total area of ​​IC structure 100, and an increase in the area that IC device 100C can occupy relative to the total area of ​​IC structure 100.

[0050] As mentioned above, the area where the given pickup structure PA or PB can avoid latch-up events is limited by several factors, such as characteristic geometry, doping level, and / or circuit application standards. Therefore, the ratios discussed above have an upper limit based on relevant design standards.

[0051] With the above configuration, the IC structure 100 includes each consecutive well WA and WB shared between more than two rows of IC devices 100C in such a way that each consecutive well WA and WB includes a portion WAS or WBS extending in the Y direction and a portion WAPn or WBPn extending into the multiple rows of IC devices 100C. The IC structure 100 can thus achieve latch-up protection by including one or more pickup structures PA or PB that can bias portions of WAPn or WBPn such that the number of pickup structures PA or PB is less than the number of portions of WAPn or WBPn. Compared to methods where each well corresponding to one or two rows of IC devices includes at least one pickup structure, the IC structure 100 including one or both of the consecutive wells WA or WB uses fewer pickup structures, thereby increasing the space utilization of the IC devices.

[0052] Figure 1B This is an illustration of an IC structure 100D according to some embodiments. In addition to the plan view of the IC structure 100D, Figure 1B The above describes Figure 1A The discussion focuses on the X and Y directions. IC structure 100D (in some embodiments, also referred to as IC die 100D) is an IC die, IC die portion, or other part or all of a semiconductor wafer, including the above-mentioned... Figure 1A The discussion includes one or more instances of the IC structure 100, and two or more instances of the TSV structure TSVS.

[0053] IC structure 100D is based on one or more IC layout diagrams (e.g., the following about Figures 6A-6C The discussion involves one or more IC layout diagrams (600A-600C) through the execution of the following... Figure 3 Non-limiting examples of IC dies or IC die portions manufactured using some or all of the methods discussed in 300.

[0054] A TSV structure (e.g., a TSV structure TSVS) is an IC die feature that includes one or more TSVs surrounded by one or more isolation structures (e.g., a TSV isolation structure TSVI) (which are configured to electrically isolate one or more TSVs from adjacent IC die features).

[0055] A TSV is a conductive segment extending from the front side of a semiconductor substrate (e.g., an IC die including IC structure 100D) to the back side of the substrate, and is therefore configured to electrically connect one or more structures located on the front side of the substrate to one or more structures located on the back side of the substrate. The TSV comprises one or more conductive materials, such as one or more of the following: polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other materials suitable for providing a low-resistance electrical connection between the front and back sides of the substrate.

[0056] exist Figure 1B In the illustrated embodiment, the IC structure 100D includes three instances of a TSV structure TSVS aligned in the X direction. A first instance of the IC structure 100 is located between a first instance and a second instance of the TSV structure TSVS, and a second and third instance of the IC structure 100 are located between the second and third instances of the TSV structure TSVS. The IC structure 100D thus includes instances of the IC structure 100 and the TSV structure TSVS aligned in the X direction.

[0057] Figure 1B The orientation and number of instances of IC structure 100 and TSV structure TSVS depicted are provided as non-limiting examples for illustrative purposes. In various embodiments, IC structure 100D includes IC structure 100 and / or TSV structure TSVS with Figure 1B The description in the text contrasts different numbers of instances, and / or has the same characteristics as... Figure 1B The depiction is different from the orientation (e.g., in the Y direction).

[0058] exist Figure 1B In the illustrated embodiment, the IC structure 100D includes each instance of the TSV structure TSVS, which includes a single TSV located within the TSV isolation structure TSVI. In some embodiments, the IC structure 100D includes one or more instances of the TSV structure TSVS, which includes more than one TSV located within the TSV isolation structure TSVI, or the IC structure 100D does not include TSVs located within the TSV isolation structure TSVI, for example, where the TSV isolation structure TSVI corresponds to a dummy region of the entire TSV structure TSVS. In some embodiments, in Figure 1B At one or more locations described as including instances of the TSV structure TSVS, IC structure 100D includes one or more structures other than an instance of the TSV structure TSVS, such as IC structure 100, IC circuit or device block, or one or more instances of other IC die features.

[0059] In various embodiments, IC structure 100D includes instances of IC structure 100, which are embodiments of IC structure 100 themselves or more than one embodiment of IC structure 100 (e.g., embodiments with different orientations, number of pick-up structures, and / or IC device 100C).

[0060] lie in Figure 1B The number of instances of IC structure 100 between adjacent instances of the depicted TSV structure TSVS is a non-limiting example. In various embodiments, IC structure 100D includes one or more instances of IC structure 100 located between adjacent instances of more than two TSV structures TSVS.

[0061] In some embodiments, with the configurations discussed above, IC structure 100D includes one or more instances of IC structure 100, wherein one or both of border regions 100A or 100B and one or both of continuous well portions WAS or WBS (each described above regarding...) Figure 1A (Discussed) Adjacent to an instance of the TSV isolation structure TSVI. In some embodiments, the border region 100A or 100B or the continuous well portion WAS or WBS adjacent to an instance of the TSV isolation structure TSVI is considered to be adjacent to the corresponding instance of the TSV structure TSVS and to the TSV within the adjacent instance of the TSV isolation structure TSVI.

[0062] With the configuration discussed above, IC structure 100D includes one or more instances of IC structure 100, and thereby enables the benefits discussed above regarding IC structure 100 to be realized.

[0063] Figure 1C An IC package 100P is depicted according to some embodiments. Besides the IC package 100P, Figure 1C The above describes Figure 1A The discussion focuses on the X direction and the Z direction, which is perpendicular to both the X and Y directions. Figure 1C Therefore, it corresponds to Figure 1A and Figure 1B A cross-sectional view of each plan view.

[0064] IC package 100P is one or more instances including IC structure 100D and is obtained by performing the following... Figure 3 Non-limiting examples of IC packages manufactured using some or all of the methods discussed in 300.

[0065] In addition to IC structure 100D, IC package 100P includes IC dies D1 and D2, which are electrically and mechanically connected to IC structure 100D via bump structure B, such that IC structure 100D and IC dies D1 and D2 are aligned in the Z direction.

[0066] Figure 1C The arrangement and number of IC dies D1 and D2 and IC structure 100D depicted are provided as non-limiting examples for illustrative purposes. In various embodiments, IC package 100P includes... Figure 1C Examples depicting different numbers of IC dies and / or IC structures 100D, and / or having the same... Figure 1C The depicted arrangement is different from other arrangements, such as more than one instance of IC structure 100D, and / or at least one IC die (not shown) other than IC die D1 or D2 is electrically and mechanically connected to IC structure 100D on the respective top or bottom surface of IC structure 100D.

[0067] In various embodiments, IC package 100P is a 2.5D IC package, a 3D IC package, an integrated fan-out (InFO) package, or other IC package type suitable for including instances of IC structure 100D with TSV structure TSVS.

[0068] Each IC die D1 and D2 is an IC die, IC die portion, or other portion or all of a semiconductor wafer. In some embodiments, one or both of IC dies D1 or D2 are substrates with a fan-out arrangement, such as interposers.

[0069] A bump structure (e.g., bump structure B) is a conductive structure that covers and contacts portions of IC structure 100D and / or die D1 and / or D2, thereby being configured to provide an electrical connection between IC structure 100D and die D1 and / or D2. In some embodiments, the bump structure includes lead. In some embodiments, the bump structure includes a lead-free material, such as tin, nickel, gold, silver, copper, or other materials suitable for providing electrical connections to external conductive elements. In some embodiments, the bump structure has a generally spherical shape. In some embodiments, the bump structure is a controlled-collapse chip connection (C4) bump, a ball grid array bump, a microbump, etc.

[0070] In some embodiments, the IC package 100P does not include a bump structure B between the IC structure 100D and one or both of the IC die D1 or D2, and the IC structure 100D is directly bonded and thereby electrically connected to the corresponding one or both of the IC die D1 or D2.

[0071] In some embodiments, some or all instances of the TSV structure TSVS on one or more instances of IC structure 100D, and one or more bump structures B (if present) are part of the power distribution structure of IC package 100P.

[0072] With the configuration discussed above, IC package 100P includes at least one instance of IC structure 100D, wherein one or more instances of IC structure 100 are adjacent to one or more instances of TSV structure TSVS, enabling IC package 100P to achieve the benefits discussed above regarding IC structure 100.

[0073] Figure 2 This is a flowchart of a method 200 for operating an IC device according to some embodiments. Method 200 can be used in IC structures including a common well (e.g., as mentioned above). Figures 1A-1C The IC structure discussed is 100).

[0074] exist Figure 2 The order of operations of method 200 described herein is for illustrative purposes only; the operations of method 200 can be performed in accordance with... Figure 2 The order shown may differ from the order of execution. In some embodiments, besides Figure 2 In addition to the operations described in the text, Figure 2 Other operations are performed before, between, during, and / or after the operations described in the text.

[0075] In some embodiments, some or all of the operations of method 200 are a subset of the following methods: operations include circuitry with a common well (e.g., those mentioned above). Figure 1A The methods for discussing IC device 100C and operating IC dies (e.g., the methods mentioned above) Figure 1B The methods and / or operations of the IC package discussed (e.g., the IC structure 100D) and IC packaging (e.g., the methods and operations discussed above) Figure 1C The method of IC packaging (100P) is discussed.

[0076] At operation 210, a power supply voltage is received at a first pickup structure, and a reference voltage is received at a second pickup structure. Receiving the power supply voltage includes receiving the power supply voltage from the first power distribution structure, and receiving the reference voltage includes receiving the reference voltage from a second power distribution structure separate from the first power distribution structure.

[0077] In some embodiments, receiving a power supply voltage at a first pickup structure includes receiving a power supply voltage at an instance of one of the pickup structures PA or PB, and receiving a reference voltage at a second pickup structure includes receiving a reference voltage at an instance of the other of the pickup structures PA or PB, as described above. Figure 1A The subject of discussion.

[0078] In some embodiments, the first pickup structure is one of a plurality of first pickup structures, and receiving a power supply voltage at the first pickup structure includes receiving a power supply voltage at each of the plurality of first pickup structures. In some embodiments, the second pickup structure is one of a plurality of second pickup structures, and receiving a reference voltage at the second pickup structure includes receiving a reference voltage at each of the plurality of second pickup structures.

[0079] At operation 220, a first pickup structure is used to bias an n-well shared among more than two rows of IC devices, and a second pickup structure is used to bias a p-well shared among more than two rows of IC devices. Biasing the shared n-well using the first pickup structure includes biasing the shared n-well with a power supply voltage, and biasing the shared p-well using the second pickup structure includes biasing the shared p-well with a reference voltage. Biasing the shared n-well with a power supply voltage includes preventing forward biasing of a diode (which includes an n-well and the S / D terminal of a PMOS transistor of the IC device), and biasing the shared p-well with a reference voltage includes preventing forward biasing of a diode (which includes a p-well and the S / D terminal of an NMOS transistor of the IC device).

[0080] In some embodiments, biasing a shared n-well using a first pickup structure includes: biasing a corresponding one of the continuous wells WA or WB using an instance of one of the pickup structures PA or PB; and biasing a shared p-well using a second pickup structure includes: biasing a corresponding other of the continuous wells WA or WB using an instance of the other of the pickup structures PA or PB, as described above regarding... Figure 1A The subject of discussion.

[0081] In some embodiments, using an instance of one of the pickup structures PA or PB to bias a corresponding one of the continuous wells WA or WB includes: using multiple instances of one of the pickup structures PA or PB to bias a corresponding one of the continuous wells WA or WB; and using an instance of the other of the pickup structures PA or PB to bias a corresponding other one of the continuous wells WA or WB includes: using multiple instances of the other of the pickup structures PA or PB to bias the corresponding other one of the continuous wells WA or WB, as described above regarding Figure 1A The subject of discussion.

[0082] In some embodiments, a shared n-well is one of a plurality of shared n-wells, each shared n-well including a corresponding first pickup structure among a plurality of first pickup structures, and biasing a shared n-well includes: biasing a corresponding shared n-well among the plurality of shared n-wells using each of the plurality of first pickup structures. In some embodiments, a power supply voltage is one of a plurality of power supply voltages, and biasing a corresponding shared n-well among the plurality of shared n-wells using each of the plurality of first pickup structures includes: biasing each subset of a plurality of subsets of the plurality of shared n-wells with the corresponding power supply voltage among the plurality of power supply voltages. In some embodiments, a shared p-well is one of a plurality of shared p-wells, each shared p-well including a corresponding second pickup structure among a plurality of second pickup structures, and biasing a shared p-well includes: biasing a corresponding shared p-well among the plurality of shared p-wells using each of the plurality of second pickup structures.

[0083] At operation 230, in some embodiments, the power supply voltage and reference voltage are used to operate the IC device. Operating the IC device includes operating a PMOS transistor located in a common n-well corresponding to more than two rows of IC devices, and operating an NMOS transistor located in a common p-well corresponding to more than two rows of IC devices.

[0084] In some embodiments, operating the IC device includes operating the above-mentioned... Figure 1A The IC device 100C under discussion. In some embodiments, operating the IC device includes operating a TSV structure (e.g., as mentioned above). Figure 1B and Figure 1C The discussion focuses on IC devices between TSV structures (TSVS). In some embodiments, the operating IC device includes an operating IC die (e.g., the one mentioned above). Figure 1B and Figure 1C The IC structure 100D discussed in this paper. In some embodiments, the operating IC device includes an operating IC package (e.g., the one mentioned above). Figure 1C The IC package under discussion is 100P.

[0085] By performing some or all of the operations of method 200, the power supply voltage and reference voltage are used to bias the n-well shared between more than two rows of IC devices and the p-well shared between more than two rows of IC devices, respectively, thereby obtaining the benefits discussed above regarding IC structure 100.

[0086] Figure 3 This is a flowchart of a method 300 for manufacturing an IC structure according to some embodiments. Method 300 is operable for forming the above-mentioned... Figure 1A and Figure 1B The IC structure discussed above is 100. Figure 1B and Figure 1C The IC structure 100D discussed, and / or the above regarding Figure 1C The IC package under discussion is 100P.

[0087] In some embodiments, the operation of method 300 is as follows: Figure 3 The sequence of operations described herein. In some embodiments, the operation of method 300 is in accordance with... Figure 3 The different sequences of operations depicted in the text are executed. In some embodiments, one or more other operations are performed before, during, and / or after the operation of method 300. In some embodiments, performing some or all of the operations of method 300 includes performing the following descriptions of the IC manufacturing system 900 and... Figure 9 One or more operations are being discussed.

[0088] At operation 310, each of the first well and the second well is configured to have a first portion extending in a first direction and a second portion and a third portion extending from the first portion in a second direction perpendicular to the first direction. Configuring the first well and the second well includes: configuring one of the first well or the second well as an n-well in the first IC die, and configuring the other of the first well or the second well as a p-well in the first IC die.

[0089] In some embodiments, configuring the first well to have a first portion extending in a first direction and a second and a third portion extending from the first portion in a second direction includes: configuring the continuous well WA to have two portions of a portion WAS extending in the Y direction and a portion WAPn extending in the X direction, and configuring the second well to have a first portion extending in the first direction and a second and a third portion extending from the first portion in the second direction includes: configuring the continuous well WB to have two portions of a portion WBS extending in the Y direction and a portion WBPn extending in the X direction, as described above regarding Figure 1A The subject of discussion.

[0090] In some embodiments, the first well is one of a plurality of first wells, the second well is one of a plurality of second wells, and configuring each of the first wells and the second wells includes: configuring each of the plurality of first wells and each of the plurality of second wells to have a first portion extending in a first direction and a second portion and a third portion extending from the first portion in a second direction perpendicular to the first direction.

[0091] In some embodiments, configuring a well (e.g., a first well and / or a second well) includes performing one or more implantation processes in a region of a semiconductor substrate corresponding to the well, thereby achieving a predetermined doping concentration for one or more given dopants, as described above regarding... Figure 1AAs discussed. In some embodiments, configuring a well includes configuring one of a first well or a second well by performing one or more implantation processes, whereby a region of the substrate outside the region of the first well or the second well is considered to be configured as the other of the first well or the second well, for example, configuring the first well as an n-well by performing P and / or As implantation, thereby configuring the region outside the first well as a p-well based on being part of a p-type substrate.

[0092] In some embodiments, configuring each of the first well and the second well includes: positioning one or both of the first well or the second well adjacent to the TSV structure, for example, positioning one or both of the consecutive wells WA and WB of the IC structure 100 adjacent to one or more instances of the TSV structure TSVS, as described above. Figure 1B Discussed.

[0093] In some embodiments, configuring each of the first well and the second well includes: based on the following... Figure 4 One or more units 400A-400C discussed and / or the following about Figures 6A-6C One or more IC layout diagrams 600A-600C are discussed to configure each of the first and second wells.

[0094] At operation 320, an IC device is formed, the IC device including a first pickup structure electrically connected to a first well and a second pickup structure electrically connected to a second well. Forming the IC device includes: forming at least one PMOS transistor in at least one of a second or third portion of a first well or a second well configured as an n-well, and forming at least one NMOS transistor in at least one of a second or third portion of a first well or a second well configured as a p-well.

[0095] Forming a pickup structure electrically connected to a first well and a second well includes performing one or more implantation processes, whereby the first pickup structure has the same doping type as the first well and a higher doping concentration than the first well, and the second pickup structure has the same doping type as the second well and a higher doping concentration than the second well.

[0096] Forming a pickup structure electrically connected to the first and second wells includes: forming an electrical connection from the first pickup structure to a first power distribution structure (which is configured to have either a power supply voltage or a reference voltage), and forming an electrical connection from the second pickup structure to a second power distribution structure (which is configured to have either a power supply voltage or a reference voltage).

[0097] In some embodiments, forming an IC device including a first pickup structure and a second pickup structure includes: forming the above-mentioned... Figure 1AThe discussion covers IC device 100C and one or more instances of each of the pickup structures PA and PB.

[0098] In some embodiments, the IC device is one of a plurality of IC device instances, the first well is one of a plurality of first wells, the second well is one of a plurality of second wells, and forming an IC device including a first pickup structure and a second pickup structure includes: forming each of the plurality of IC device instances including a first pickup structure and a second pickup structure corresponding to the first well in the plurality of first wells and the second well in the plurality of second wells.

[0099] Forming an IC device including a first pickup structure and a second pickup structure includes: constructing multiple IC devices (e.g., transistors, logic gates, memory cells, interconnect structures and / or other suitable devices) by performing multiple manufacturing operations (e.g., photolithography, diffusion, deposition, etching, planarization, or one or more other operations suitable for constructing multiple IC devices in a semiconductor wafer).

[0100] In some embodiments, forming an IC device including a first pickup structure and a second pickup structure includes: based on the following... Figure 4 One or more units 400A-400C discussed and / or the following about Figures 6A-6C One or more IC layouts 600A-600C are discussed to form an IC device including a first pickup structure and a second pickup structure.

[0101] At operation 330, in some embodiments, a TSV structure is constructed in a first IC die adjacent to a first well or a second well. Constructing the TSV structure includes: constructing a TSV that spans the front and back sides of the first IC die and is surrounded by a TSV isolation structure.

[0102] In some embodiments, constructing the TSV structure includes: constructing a TSV structure adjacent to each of the first well and the second well. In some embodiments, constructing the TSV structure includes: constructing the structure above regarding... Figure 1B and Figure 1C The TSV structure discussed includes at least one instance of TSVS.

[0103] In some embodiments, the first well is one of a plurality of first wells, the second well is one of a plurality of second wells, the TSV structure is one of a plurality of TSV structures, and constructing the TSV structure includes: constructing each of a plurality of TSV structures adjacent to a corresponding first well in the plurality of first wells and / or a corresponding second well in the plurality of second wells.

[0104] Constructing a TSV structure involves performing multiple manufacturing operations, including depositing and patterning one or more photoresist layers, performing one or more etching processes, and performing one or more deposition processes, thereby configuring one or more conductive materials to form a continuous low-resistance structure that spans the front and back sides of the IC die and is surrounded by one or more continuous dielectric layers, thereby electrically isolating the continuous low-resistance structure from adjacent features (e.g., a first well or a second well).

[0105] At operation 340, in some embodiments, the TSV structure is electrically connected to a second IC die of the IC package. In various embodiments, electrically connecting the TSV structure to the second IC die includes: directly connecting the TSV structure to the second IC die, or connecting the TSV structure to the second IC die via a bump structure. In some embodiments, electrically connecting the TSV structure to the second IC die of the IC package includes: electrically connecting the TSV structure to a second IC die of a 2.5D IC package, a 3D IC package, or an InFO package.

[0106] In some embodiments, electrically connecting the TSV structure to the second IC die of the IC package includes: electrically connecting at least one instance of the TSV structure (TSVS) to the above-mentioned... Figure 1C The IC package discussed is at least one of IC dies D1 or D2 in a 100P IC package.

[0107] Electrically connecting the TSV structure to the second IC die includes performing one or more IC package manufacturing operations, thereby connecting a portion or all of the IC die including the TSV structure to the second IC die of the IC package. In various embodiments, the one or more IC package manufacturing operations include one or more of the following: die separation process, molding or deposition, bonding process, metal deposition process, soldering process, annealing process, or another process suitable for manufacturing an IC package.

[0108] In some embodiments, operation 340 is repeated such that the TSV structure of a plurality of IC dies is electrically connected to a first IC die or a second IC die and / or one or more IC dies other than the first IC die and the second IC die.

[0109] By performing some or all of the operations of method 300, an IC structure is manufactured in which the first well and the second well are shared between more than two rows of IC devices, thereby obtaining the benefits discussed above regarding IC structures 100 and 100D and IC package 100P.

[0110] Figure 4 This is an illustration of the IC layout diagram of units 400A-400C according to some embodiments. Figure 4The plan view of each unit 400A-400C is depicted, along with the above information regarding... Figure 1A and Figure 1B The discussion focuses on the X and Y directions.

[0111] IC layout diagrams (e.g., IC layout diagrams including one or more cells 400A-400C) can be used in the manufacturing process (e.g., the above regarding...). Figure 3 Methods discussed 300 and / or related to the following: Figure 9 The IC manufacturing system 900 discussed (related to the IC manufacturing process) serves as a constraint on the IC structure (e.g., the one mentioned above). Figures 1A-3 A portion of one or more features of the IC structure 100 under discussion.

[0112] In various embodiments, the units (e.g., units 400A-400C) are independent units (e.g., stored in, for example, the following description). Figure 8 The discussion refers to standard cells in cell libraries such as 807, or larger IC layouts (e.g., those discussed below). Figures 6A-6C This discussion pertains to one or more IC layout diagrams (600A-600C).

[0113] In some embodiments, one or more units 400A-400C are executed by performing a method (e.g., the following regarding...). Figure 5 The method discussed (500) is generated by one or more operations.

[0114] Each of cells 400A-400C includes boundaries B1-B4, well regions WR1 and WR2, and in some embodiments, a pickup region PR1 located in well region WR1 and a pickup region PR2 located in well region WR2. Cell 400A has a cell height CH1, and each of cells 400B and 400C has a cell height CH2.

[0115] The orientation of each of units 400A-400C is a non-limiting example provided for illustrative purposes. Each of units 400A-400C is capable of rotation and / or inversion relative to one or both of the X or Y directions.

[0116] Well regions (e.g., well regions WR1 or WR2) are the following regions in the IC layout diagram that are included during the manufacturing process as part of the semiconductor substrate (e.g., the area above). Figures 1A-3 The IC structure discussed (100 or 100D) defines one or more n-well or p-well structures (e.g., those mentioned above). Figure 1A The discussion concerns a portion or all of the continuous wells (WA or WB).

[0117] Pickup areas (e.g., pickup areas PR1 or PR2) are the following areas in the IC layout diagram that are included during the manufacturing process as defining pickup structures (e.g., those mentioned above). Figures 1A-3 This is part of the picking structure (PA or PB) being discussed.

[0118] In some embodiments, one or more units 400A-400C are referred to as border units. In some embodiments where units 400A-400C include pickup areas PR1 and PR2, units 400A-400C are referred to as pickup units, strap units, or connecting units.

[0119] Each of the well regions WR1 and WR2 may serve as part of defining a portion of either the continuous well WA or WB, and each of the pick-up regions PR1 and PR2 may serve as part of defining an instance of the pick-up structure PA or PB corresponding to the continuous well WA or WB, as described above regarding Figures 1A-3 This has been discussed, and will be discussed further below.

[0120] Each of units 400A-400C has a border defined by boundaries B1-B4. Each of boundaries B1 and B3 extends in the X direction, and each of boundaries B2 and B4 extends in the Y direction. Each of units 400A-400C includes a well region WR1 that extends from boundary B1 to boundary B3 in the Y direction and from boundary B4 to boundary B2 in the X direction.

[0121] Unit 400A includes a well region WR1 that extends from boundary B1 to boundary B3 along the entire boundary B4 and along a portion of boundary B2 between boundary B1 and well region WR2. The well region WR1 also extends from boundary B4 to boundary B2 along the entire boundary B1 and along a portion of boundary B3 between boundary B4 and well region WR2.

[0122] Unit 400B includes a well region WR1 that extends from boundary B1 to boundary B3 along the entire boundary B4 and along a first portion of boundary B2 between boundary B1 and the well region WR2, and a second portion of boundary B2 between the well region WR2 and boundary B3. The well region WR1 extends from boundary B4 to boundary B2 along the entire boundary B1 and along the entire boundary B3.

[0123] Unit 400C includes a well region WR1 that extends from boundary B1 to boundary B3 along the entire boundary B4 and along a portion of boundary B2 between a first portion and a second portion of well region WR2. The well region WR1 extends from boundary B4 to boundary B2 along a portion of boundary B1 between boundary B4 and the first portion of well region WR2, and along a portion of boundary B3 between boundary B4 and the second portion of well region WR2.

[0124] exist Figure 4 In the illustrated embodiment, well region WR1 designates a portion of units 400A-400C extending along boundary B4, and well region WR2 designates one or two other portions of units 400A-400C as shaded areas. In some embodiments, well region WR2 corresponds to a portion of units 400A-400C extending along boundary B4, and well region WR1 corresponds to one or two other portions of units 400A-400C indicated by the shaded areas; well regions WR1 and WR2 are thus considered inverted.

[0125] Various embodiments of units 400A-400C can be combined to define portions of an n-well and / or p-well structure shared between more than two rows of IC devices, as discussed below and regarding Figures 5-7 Further discussion is needed.

[0126] exist Figure 4 In the illustrated embodiment, cell height CH1 is a single cell height corresponding to the height of a row of IC devices (which includes a single instance of PMOS transistors aligned in the Y direction with a single instance of NMOS transistors), and cell height CH2 is equal to twice cell height CH1 and corresponds to a double cell height for two rows of IC devices. In some embodiments, cells 400A-400C have a height corresponding to the height of a row of IC devices. Figure 4 The cell heights depicted are different, for example, one or both of cells 400B or 400C have a cell height CH1.

[0127] exist Figure 4 In each of the embodiments shown, cells 400A-400C include each of well regions WR1 and WR2, which have borders defined by boundaries extending in the X or Y direction. In some embodiments, one or more cells 400A-400C include well regions WR1 and WR2, which have borders defined by one or more boundaries oriented, for example, by extending diagonally relative to the X and Y directions. In some embodiments, cells 400A-400C do not include well region WR2, such that the boundary of well region WR1 matches cell boundaries B1-B4.

[0128] Based on the configuration discussed above, each IC layout corresponding to cells 400A-400C includes a well region WR1 extending from boundaries B1 and B4 to the corresponding boundaries B3 and B2, thereby defining a portion of the well structure shared between more than two rows of IC devices (as described below). Figures 5-7 (Further discussion) thereby gaining the benefits of the above discussion on IC structure 100.

[0129] Figure 5 It is a generated IC layout diagram based on some embodiments (e.g., the one mentioned above). Figure 4 The flowchart of method 500 (IC layout diagram of units 400A-400C discussed).

[0130] In some embodiments, generating an IC layout includes: generating an IC structure based on the generated IC layout (e.g., the one described above). Figures 1A-1C The IC layout diagram corresponding to the IC structure 100 discussed.

[0131] In some embodiments, some or all of the methods 500 are handled by a computer processor (e.g., as described below). Figure 8 The IC layout generation system 800 discussed is executed by processor 802.

[0132] Some or all of the operations of method 500 can be performed in the design room (e.g., below regarding...). Figure 9 The design process is carried out as part of the design process discussed in Design Room 920.

[0133] In some embodiments, the operation of method 500 is as follows: Figure 5 The operations of method 500 are executed sequentially as depicted. In some embodiments, the operations of method 500 are performed concurrently and / or in conjunction with... Figure 5 The different sequences of execution depicted herein. In some embodiments, one or more operations are performed before, between, during, and / or after one or more operations of method 500.

[0134] At operation 510, in some embodiments, an IC layout diagram of stored cells is obtained from a storage device, the stored cells including one or both of a first well region and a second well region. In some embodiments, the stored cells include each first well region extending from a first cell boundary to a second cell boundary but not from a third cell boundary to a fourth cell boundary.

[0135] In some embodiments, obtaining an IC layout diagram of the stored cells from a storage device includes: from the following... Figure 8 The IC layout generation system 800 discussed obtains the IC layout diagram of the stored cells from its cell library 807.

[0136] At operation 520, the first well region extends from a first cell boundary to a second cell boundary, the first cell boundary and the second cell boundary being relative boundaries of the cell in a first direction. In some embodiments, the first direction is perpendicular to the cell height, for example, as described above regarding... Figure 4 The unit height CH1 or CH2 is discussed in the X direction perpendicular to the height CH1 or CH2.

[0137] In some embodiments, extending the first well region from the first cell boundary to the second cell boundary includes extending the first well region along the entire third cell boundary and a portion of the fourth cell boundary. In some embodiments, extending the first well region from the first cell boundary to the second cell boundary includes extending the first well region along the entire third cell boundary and the entire fourth cell boundary. In some embodiments, extending the first well region from the first cell boundary to the second cell boundary includes extending the first well region along a portion of the third cell boundary and a portion of the fourth cell boundary.

[0138] In some embodiments, extending the first well region from the first cell boundary to the second cell boundary includes: extending the well region WR1 from boundary B4 of cells 400A-400C to boundary B2, as described above. Figure 4 The subject of discussion.

[0139] At operation 530, the first well region extends from the third cell boundary to the fourth cell boundary, the third cell boundary and the fourth cell boundary being the relative boundaries of the cell in a second direction perpendicular to the first direction. In some embodiments, the second direction is the direction of the cell height, for example, as mentioned above regarding... Figure 4 The Y direction of the unit height CH1 or CH2 is being discussed.

[0140] In some embodiments, extending the first well region from the third cell boundary to the fourth cell boundary includes extending the first well region along the entire first cell boundary. In some embodiments, extending the first well region from the third cell boundary to the fourth cell boundary includes extending the first well region along a portion of the second cell boundary.

[0141] In some embodiments, extending the first well region from the third cell boundary to the fourth cell boundary includes: extending the well region WR1 from boundary B1 of cells 400A-400C to boundary B3, as described above. Figure 4 The subject of discussion.

[0142] In some embodiments, extending the first well region from the third cell boundary to the fourth cell boundary includes: increasing the size of the first well region of the stored cell obtained in operation 510, and decreasing the size of the second well region of the stored cell obtained in operation 510.

[0143] At operation 540, in some embodiments, each of the first well region and the second well region overlaps with the pickup region. In some embodiments, overlapping each of the first well region and the second well region with the pickup region includes: overlapping well region WR1 with pickup region PR1, and overlapping well region WR2 with pickup region PR2, as described above regarding Figure 4 The subject of discussion.

[0144] At operation 550, in some embodiments, the IC layout diagram is stored in a storage device. In various embodiments, storing the IC layout diagram in a storage device includes: storing the IC layout diagram in a non-volatile computer-readable storage medium or a cell library (e.g., a database), and / or storing the IC layout diagram on a network. In some embodiments, storing the IC layout diagram in a storage device includes: storing the IC layout diagram in the following... Figure 8 The IC layout generation system 800 discussed is located in cell library 807 or on network 814.

[0145] At operation 560, in some embodiments, an IC layout pattern is placed in the IC layout pattern of the IC die. In various embodiments, placing the IC layout pattern in the IC layout pattern of the IC die includes: rotating the IC layout pattern about one or more axes, moving the IC layout pattern relative to one or more other IC layout patterns in one or more directions, and / or reversing the first well region and the second well region.

[0146] In some embodiments, placing the IC layout diagram in the IC die's IC layout diagram includes: placing the IC layout diagram in the following... Figures 6A-6C The discussion focuses on one of the IC layout diagrams 600A-600C.

[0147] In some embodiments, placing an IC layout diagram in the IC die's IC layout diagram includes: performing the following... Figure 7 The discussion covers one or more operations of method 700.

[0148] At operation 570, in some embodiments, at least one of one or more semiconductor masks or at least one component of a layer of a semiconductor IC is fabricated based on an IC layout diagram. The following is about... Figure 9 Discuss the fabrication of at least one component in a layer of one or more semiconductor masks or semiconductor ICs.

[0149] At operation 580, in some embodiments, one or more manufacturing operations are performed based on an IC layout diagram. In some embodiments, performing one or more manufacturing operations includes performing one or more photolithographic exposures based on the IC layout diagram. The following is about... Figure 9 The discussion focuses on performing one or more manufacturing operations (e.g., one or more photolithography exposures) based on IC layout diagrams.

[0150] By performing some or all of the operations of method 500, an IC layout diagram corresponding to an IC structure is generated, in which the first and second wells are shared between more than two rows of IC devices, thereby obtaining the benefits discussed above regarding IC structure 100.

[0151] Figures 6A-6C These are illustrations of various IC layouts 600A-600C according to some embodiments. Figures 6A-6C The plan view of each IC layout 600A-600C is depicted, as well as the above regarding... Figure 1A , Figure 1B and Figure 4 The X and Y directions are under discussion.

[0152] Each of the IC layout diagrams 600A-600C includes an IC device region (ICR), which includes the IC device region (ICR) mentioned above. Figure 1A The rows R1-R5 of the IC device 100C discussed correspond to rows R1-R5. The IC device region ICR is the following region in each of the IC layout diagrams 600A-600C, which includes multiple cells and / or other IC layout features, configured to be included in the manufacturing process as part of defining multiple IC devices (e.g., IC device 100C). Figures 6A-6C The depiction of the IC device region ICR in each of them is simplified for illustrative purposes, as shown above regarding Figure 1A The subject of discussion.

[0153] IC layout diagrams 600A-600C also include various border regions BR1A-BR1C corresponding to border region 100A and various border regions BR2A-BR2C corresponding to border region 100B, as mentioned above. Figure 1A The discussion focuses on the following: Each of the border regions BR1A and BR2A includes multiple instances of unit 400A, each of the border regions BR1B and BR2B includes multiple instances of unit 400B, and each of the border regions BR1C and BR2C includes multiple instances of unit 400C, as discussed above. Figure 4 The subject of discussion.

[0154] Figures 6A-6C The number of rows R1-R5 and examples of cells 400A-400C depicted are provided for illustrative purposes. In various embodiments, one or more IC layout diagrams 600A-600C include... Figures 6A-6C The number of rows or cells depicted varies.

[0155] As discussed below, each of the IC layout diagrams 600A-600C includes a corresponding instance of cells 400A-400C and an IC device region ICR having an arrangement of well regions WR1 and WR2 extending in both the X and Y directions. In some embodiments, well regions WR1 and WR2 correspond to the above-mentioned... Figure 1A The corresponding continuous wells WA and WB are discussed.

[0156] exist Figure 6A In the illustrated embodiment, each of the border regions BR1A and BR2A includes an instance of cell 400A in each of rows R1-R5. In border region BR1A, the instances of cell 400A in rows R1, R3, and R5 correspond to... Figure 4 The embodiments depicted, and instances of unit 400A in rows R2 and R4, correspond to rotations about the x-axis. Figure 4 The embodiment depicted. In the border region BR2A, instances of cell 400A in rows R2 and R4 correspond to well regions WR1 and WR2 that are rotated about the y-axis and include inversion. Figure 4 The embodiments depicted in the figure, and the instances of unit 400A in rows R1, R3 and R5 correspond to the instances in R2 and R4 that are further rotated about the x-axis.

[0157] exist Figure 6B In the illustrated embodiment, the border region BR1B includes instances of cell 400B in rows R1 and R2, instances of cell 400B in rows R3 and R4, and an instance of cell 400B having a portion of row R5, each instance of cell 400B corresponding to Figure 4 The embodiment depicted in the diagram. The border region BR2B includes instances of cell 400B having a portion of row R1, instances of cell 400B in rows R2 and R3, and instances of cell 400B in rows R4 and R5, each instance of cell 400B corresponding to well regions WR1 and WR2 rotated about the y-axis and having reversed orientation. Figure 4 The embodiments described herein.

[0158] exist Figure 6C In the illustrated embodiment, the border region BR1C includes instances of cell 400C having a portion of row R1, instances of cell 400C in rows R2 and R3, and instances of cell 400C in rows R4 and R5, each instance of cell 400C corresponding to Figure 4 The embodiment depicted in the diagram. The border region BR2C includes instances of cell 400C in rows R1 and R2, instances of cell 400C in rows R3 and R4, and an instance of cell 400C having a portion of row R5. Each instance of cell 400C corresponds to a well region WR1 and WR2 rotated about the y-axis and having an inverted shape. Figure 4The embodiments described herein.

[0159] exist Figures 6A-6C In the illustrated embodiments, each IC layout 600A-600C includes an instance of a single cell 400A-400C located in each corresponding border region BR1A-BR1C and BR2A-BR2C, whereby the corresponding well regions WR1 and WR2 of the cell 400A-400C and the IC device region ICR are aligned in the X direction. In various embodiments, one or more IC layouts 600A-600C include more than one instance of a cell 400A-400C located in one or both of the corresponding border regions BR1A-BR1C and BR2A-BR2C, whereby the corresponding well regions WR1 and WR2 of the cell 400A-400C and the IC device region ICR are aligned in the X direction.

[0160] Each IC layout 600A-600C includes one or more instances of pickup regions (not shown) in each well region WR1 and WR2, corresponding to one or more pickup structures in a well structure manufactured based on IC layout 600A-600C. The number of pickup regions is related to the following quantities: based on the pickup structures of IC structure 100 above and Figures 1A-3 The discussion focuses on the number of rows in the IC device region ICR, and the number of portions of the well regions WR1 and WR2 extending in the X direction.

[0161] In some embodiments, one or more pickup regions are included in the IC device region (ICR), for example, as one or more connection units, thereby corresponding to, for example, Figure 1A The pickup structures PA and PB are shown. In some embodiments, one or more pickup areas are pickup areas PR1 and PR2 included in one or more instances of units 400A-400C included in the corresponding IC layout diagrams 600A-600C.

[0162] Based on the configurations discussed above, each IC layout diagram 600A-600C, including each well region WR1 and WR2, is configured to define a portion of a well structure shared between more than two rows of IC devices (as described below). Figure 7 (As discussed further), thereby obtaining the benefits discussed above regarding IC structure 100. In embodiments including one or more pickup regions PR1 and PR2, the area available for the IC device, defined by the IC device region ICR, is further increased, thereby further improving layout efficiency and routing flexibility compared to methods where one or more pickup regions are located within the IC device region.

[0163] Figure 7 It is a generated IC layout diagram based on some embodiments (e.g., the one mentioned above). Figures 6A-6CA flowchart of method 700 (one of the IC layout diagrams 600A-600C discussed). In some embodiments, generating an IC layout diagram includes: generating and manufacturing based on the generated IC layout diagram. Figures 1A-1C The IC layout diagram corresponding to the IC structure 100 discussed.

[0164] In some embodiments, some or all of method 700 is executed by a computer's processor. In some embodiments, some or all of method 700 is executed by the following... Figure 8 The processor 802 of the IC layout generation system 800 discussed is executed.

[0165] Some or all of the operations of method 700 can be performed in the design room (e.g., as described below). Figure 9 The design process is carried out as part of the design process discussed in Design Room 920.

[0166] In some embodiments, the operation of method 700 is as follows: Figure 7 The operations of method 700 are executed sequentially as depicted. In some embodiments, the operations of method 700 are performed concurrently and / or in conjunction with... Figure 7 The different sequences of execution depicted herein. In some embodiments, one or more operations are performed before, between, during, and / or after one or more operations of method 700.

[0167] At operation 710, in some embodiments, a plurality of border units are received. Receiving the plurality of border units includes receiving each of the plurality of border units (which includes a first well region extending from a first boundary to a second boundary and from a third boundary to a fourth boundary).

[0168] In various embodiments, receiving a plurality of border units includes receiving some or all of the plurality of border units (which have the same or different orientations, and / or include designated first well regions and second well regions that have the same or reversed orientations).

[0169] In some embodiments, receiving a plurality of border units includes: receiving a plurality of units as described above. Figure 4 One or more units 400A-400C are discussed. In some embodiments, receiving multiple border units includes: performing the above-mentioned... Figure 5 The discussion covers one or more operations of method 500.

[0170] In some embodiments, receiving a plurality of border cells includes: from a cell library (e.g., as described below regarding...). Figure 8 The cell library 807 discussed receives multiple border cells.

[0171] At operation 720, a plurality of border units are arranged in a first border region and a second border region, thereby defining a first portion extending in a first direction for each of the first and second well regions. In some embodiments, defining the first portion includes aligning a third boundary and a fourth boundary of the plurality of border units in the first direction.

[0172] In some embodiments, arranging multiple border units includes: reorienting as described above. Figure 4 The discussion concerns one or more border units, and / or inverts them as described above. Figure 4 The first well region and the second well region of one or more border cells are discussed.

[0173] In some embodiments, arranging a plurality of border units in one or more border regions includes: arranging two or more units 400A-400C as described above. Figures 6A-6C The border regions BR1A-BR1C and BR2A-BR2C are under discussion.

[0174] At operation 730, the first border region and the second border region are aligned with the IC device region, thereby defining a plurality of well region portions of each of the first well region and the second well region extending in a second direction perpendicular to the first direction.

[0175] Aligning the first and second border regions with the IC device design region includes aligning the n-well and p-well regions of each border region with the n-well and p-well regions of the IC device design region.

[0176] In some embodiments, aligning the first border region and the second border region with the IC device region includes: aligning two or more units 400A-400C from the border regions BR1A-BR1C and BR2A-BR2C with the IC device design region ICR, as described above. Figures 6A-6C Discussed.

[0177] At operation 740, an IC layout diagram is generated, including multiple border cells and IC device design areas. The generation of the IC layout diagram is performed by the processor (e.g., as described below regarding...). Figure 8 The IC layout generation system 800 discussed is executed by processor 802. In some embodiments, generating an IC layout including multiple border cells and IC device design regions includes: executing one or more automatic placement and routing (APR) algorithms, whereby one or more functional cells are located in the IC device regions.

[0178] In some embodiments, generating an IC layout diagram includes: generating the above-mentioned... Figures 6A-6C One of the IC layouts 600A-600C is being discussed.

[0179] In some embodiments, the plurality of border cells are one of a plurality of border cells, the IC device design region is one of a plurality of IC device design regions, and generating the IC layout diagram includes generating an IC layout diagram having a plurality of border cells and a plurality of IC device design regions.

[0180] In some embodiments, generating an IC layout diagram including multiple border cells and IC device design regions includes: generating an IC layout diagram also including one or more TSV regions, which are configured to be included in the manufacturing process as defining one or more TSV structures (e.g., as mentioned above). Figure 1B and Figure 1C The TSV structure discussed is part of the TSV (TSVS) structure.

[0181] In some embodiments, at operation 750, the IC layout diagram is stored in a storage device. In various embodiments, storing the IC layout diagram in a storage device includes: storing the IC layout diagram in a non-transitory computer-readable storage medium or a cell library (e.g., a database), and / or storing the IC layout diagram on a network. In various embodiments, storing the IC layout diagram in a storage device includes: storing the IC layout diagram in the following... Figure 8 The IC layout generation system 800 discussed is located in a computer-readable storage medium 804 or on a network 814.

[0182] At operation 760, in some embodiments, at least one of one or more semiconductor masks or at least one component of a layer of a semiconductor IC is fabricated based on an IC layout diagram. The following concerns IC manufacturing system 900 and... Figure 9 Discuss the fabrication of at least one component in a layer of one or more semiconductor masks or semiconductor ICs.

[0183] At operation 770, in some embodiments, one or more manufacturing operations are performed based on an IC layout diagram. In some embodiments, performing one or more manufacturing operations includes performing one or more photolithographic exposures based on the IC layout diagram. The following is about... Figure 9 The discussion focuses on performing one or more manufacturing operations (e.g., one or more photolithography exposures) based on IC layout diagrams.

[0184] By performing some or all of the operations of method 700, an IC layout diagram corresponding to the IC structure is generated, in which the first well and the second well are shared between more than two rows of IC devices, thereby obtaining the benefits discussed above regarding IC structure 100 and IC layout diagrams 600A-600C.

[0185] Figure 8This is a block diagram of an IC layout generation system 800 according to some embodiments. According to one or more embodiments, the methods for designing IC layouts described herein can be implemented, for example, using the IC layout generation system 800 according to some embodiments.

[0186] In some embodiments, the IC layout generation system 800 is a general-purpose computing device including a hardware processor 802 and a non-transitory computer-readable storage medium 804. Among other things, the storage medium 804 is encoded with (i.e., stores) computer program code 806 (i.e., a set of executable instructions). The hardware processor 802 executes the instructions 806 (at least partially) representing an implementation method (e.g., regarding...). Figure 5 The method for generating IC layout diagrams described in 500 and / or about Figure 7 The method for generating IC layout diagrams described in 700 (hereinafter referred to as the referred process and / or method) is part or all of the EDA tools.

[0187] Processor 802 is electrically coupled to computer-readable storage medium 804 via bus 808. Processor 802 is also electrically coupled to I / O interface 810 via bus 808. Network interface 812 is also electrically coupled to processor 802 via bus 808. Network interface 812 is connected to network 814, enabling processor 802 and computer-readable storage medium 804 to be connected to external components via network 814. Processor 802 is configured to execute computer program code 806 encoded in computer-readable storage medium 804, such that IC layout generation system 800 can be used to perform some or all of the aforementioned processes and / or methods. In one or more embodiments, processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0188] In one or more embodiments, the computer-readable storage medium 804 is an electrical, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 804 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 804 includes optical disc read-only memory (CD-ROM), CD-R / W, and / or digital video optical disc (DVD).

[0189] In one or more embodiments, computer-readable storage medium 804 stores computer program code 806 configured to cause IC layout generation system 800 (where such execution (at least partially) represents an EDA tool) to perform part or all of the mentioned processes and / or methods. In one or more embodiments, computer-readable storage medium 804 also stores information that facilitates the execution of part or all of the mentioned processes and / or methods. In one or more embodiments, computer-readable storage medium 804 stores a cell library 807, including cells of the type disclosed herein, such as those described above. Figures 4-7 Units 400A-400C are discussed.

[0190] IC layout generation system 800 includes an I / O interface 810. The I / O interface 810 is coupled to external circuitry. In one or more embodiments, the I / O interface 810 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or cursor arrow keys for conveying information and commands to processor 802.

[0191] The IC layout generation system 800 also includes a network interface 812 coupled to the processor 802. The network interface 812 allows the system 800 to communicate with a network 814 to which one or more other computer systems are connected. The network interface 812 includes a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the aforementioned processes and / or methods are implemented in two or more IC layout generation systems 800.

[0192] The IC layout generation system 800 is configured to receive information via I / O interface 810. The information received via I / O interface 810 includes instructions, data, design rules, libraries of standard cells, and / or one or more other parameters for processing by processor 802. The information is transmitted to processor 802 via bus 808. The IC layout generation system 800 is also configured to receive UI-related information via I / O interface 810. This information is stored as a user interface (UI) 842 on computer-readable medium 804.

[0193] In some embodiments, some or all of the mentioned processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application part of an additional software application. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application part of an EDA tool. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application used by an IC layout generation system 800. In some embodiments, software applications such as those available from CADENCE DESIGN SYSTEMS are used. Tools such as those used in the layout generation tool or other suitable layout generation tools can be used to generate layouts that include standard cells.

[0194] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage devices or memory units, such as one or more of optical discs such as DVDs, magnetic disks such as hard disks, and semiconductor memories such as ROM, RAM, memory cards, etc.

[0195] Figure 9 This is a block diagram of an IC manufacturing system 900 and an associated IC manufacturing process according to some embodiments. In some embodiments, the manufacturing system 900 is used to manufacture at least one of (A) one or more semiconductor masks or (B) at least one component of a layer of a semiconductor integrated circuit, based on an IC layout diagram.

[0196] exist Figure 9 In this IC manufacturing system 900, entities such as design room 920, mask room 930, and IC manufacturer / fab 950 interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC devices 960. The entities in system 900 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design room 920, mask room 930, and IC fab 950 are owned by a single large company. In some embodiments, two or more of the design room 920, mask room 930, and IC fab 950 coexist in a shared facility and use shared resources.

[0197] The design studio (or design team) 920 generates the IC design layout 922. The IC design layout 922 includes various geometric patterns, such as those shown above. Figures 4-7 The discussed units 400A-400C and / or IC layout diagrams 600A-600C. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 960 to be manufactured. The various layers combine to form various IC functions. For example, a portion of the IC design layout diagram 922 includes various IC features to be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for pads. Design room 920 implements appropriate design processes to form the IC design layout diagram 922. The design processes include one or more of logic design, physical design, or layout and routing. The IC design layout diagram 922 is presented in one or more data files containing geometric pattern information. For example, the IC design layout diagram 922 can be expressed in GDSII or DFII file format.

[0198] Mask chamber 930 includes data preparation 932 and mask fabrication 944. Mask chamber 930 uses an IC design layout 922 to fabricate one or more masks 945 for fabricating various layers of an IC device 960 according to the IC design layout 922. Mask chamber 930 performs mask data preparation 932, in which the IC design layout 922 is converted into a representative data file (“RDF”). Mask data preparation 932 provides the RDF for use in mask fabrication 944. Mask fabrication 944 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 945 or a semiconductor wafer 953. The IC design layout 922 is processed by mask data preparation 932 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 950. Figure 9 In this embodiment, mask data preparation 932 and mask manufacturing 944 are shown as separate elements. In some embodiments, mask data preparation 932 and mask manufacturing 944 may be collectively referred to as mask data preparation.

[0199] In some embodiments, mask data preparation 932 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other processing effects, etc. OPC adjusts the IC design layout diagram 922. In some embodiments, mask data preparation 932 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0200] In some embodiments, mask data preparation 932 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout 922, which has already been processed in the OPC, including certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 922 to compensate for constraints during mask fabrication 944, and may undo a portion of the modifications performed by the OPC to satisfy the mask creation rules.

[0201] In some embodiments, mask data preparation 932 includes a lithography process check (LPC), which is simulated by an IC fab 950 to fabricate an IC device 960. The LPC simulates this process based on an IC design layout 922 to create a simulated fabricated device, such as IC device 960. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as projection contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, etc., or combinations thereof. In some embodiments, after the simulated fabricated device has been created via LPC, if the simulated device is not close enough in shape to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 922.

[0202] It should be understood that, for clarity, the above description of mask data preparation 932 has been simplified. In some embodiments, data preparation 932 includes additional features such as logic operations (LOPs) to modify the IC design layout 922 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 922 during data preparation 932 can be performed in various different sequences.

[0203] Following mask data preparation 932 and during mask fabrication 944, a mask 945 or mask set 945 is fabricated based on a modified IC design layout 922. In some embodiments, mask fabrication 944 includes performing one or more photolithographic exposures based on the IC design layout 922. In some embodiments, a mechanism using an electron beam (e-beam) or multiple electron beams is used to form a pattern on the mask (photomask or mask stencil) 945 based on the modified IC design layout 922. The mask 945 can be formed using various techniques. In some embodiments, a binary technique is used to form the mask 945. In some embodiments, the mask pattern includes opaque regions and transparent regions. Radiation beams (e.g., ultraviolet (UV) or EVU beams) used to expose an image-sensitive material layer (e.g., photoresist) already coated on the wafer are blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask version of the mask 945 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, a phase-shifting technique is used to form mask 945. In the phase-shifting mask (PSM) version of mask 945, various features in the pattern formed on the phase-shifting mask are configured to have appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase-shifting mask can be attenuated PSM or adjusted PSM. The mask(s) generated by mask fabrication 944 are used in various processes. For example, such masks(s) are used in ion implantation processes to form various doped regions in semiconductor wafer 953, in etching processes to form various etched regions in semiconductor wafer 953, and / or in other suitable processes.

[0204] IC Fab 950 is an IC manufacturing company that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC Fab 950 is a semiconductor foundry. For example, there may be one manufacturing plant for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, a second manufacturing plant for back-end manufacturing (back-end process (BEOL) manufacturing) of IC product interconnects and packaging, and a third manufacturing plant for additional services such as foundry operations.

[0205] IC fab 950 includes a wafer fabrication tool 952 configured to perform various fabrication operations on a semiconductor wafer 953 to fabricate an IC device 960 according to one or more masks (e.g., mask 945). In various embodiments, the fabrication tool 952 includes one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more of the fabrication processes discussed herein.

[0206] IC fab 950 uses one or more masks 945 manufactured by mask chamber 930 to fabricate IC device 960. Therefore, IC fab 950 uses IC design layout 922 at least indirectly to fabricate IC device 960. In some embodiments, IC fab 950 uses one or more masks 945 to fabricate semiconductor wafer 953 to form IC device 960. In some embodiments, IC fabrication includes performing one or more photolithographic exposures at least indirectly based on IC design layout 922. Semiconductor wafer 953 includes a silicon substrate or other suitable substrate on which material layers are formed. Semiconductor wafer 953 also includes one or more of various doped regions, dielectric features, multilayer interconnects, etc. (formed in subsequent fabrication steps).

[0207] Regarding IC manufacturing systems (e.g., Figure 9 Details of the system (900) and the associated IC manufacturing process can be found in the following documents: for example, U.S. Patent No. 9,256,709, granted February 9, 2016; U.S. Pre-Grant Publication No. 20150278429, published October 1, 2015; U.S. Pre-Grant Publication No. 20140040838, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007, which are incorporated herein by reference in their entirety.

[0208] In some embodiments, an IC structure includes: a first continuous well, which is one of an n-well or a p-well, the first continuous well including: a first well portion extending in a first direction; a second well portion extending from the first well portion in a second direction perpendicular to the first direction; and a third well portion extending from the first well portion in the second direction parallel to the second well portion. In some embodiments, the IC structure includes: a second continuous well, which is the other of an n-well or a p-well, the second continuous well including: a fourth well portion extending in the first direction; a fifth well portion extending upward from the fourth well portion in a third direction opposite to the second direction, and between the second well portion and the third well portion; and a sixth well portion extending upward in a third direction and parallel to the fifth well portion from the fourth well portion. In some embodiments, the second well portion and the fifth well portion correspond to a first row of IC devices, and the third well portion and the sixth well portion correspond to a second row of IC devices. In some embodiments, the IC structure includes: a third continuous well, comprising: a seventh well portion extending in a first direction; an eighth well portion extending from the seventh well portion in a second direction; and a ninth well portion extending from the seventh well portion in a second direction parallel to the eighth well portion; and a TSV structure located between the third continuous well and the first and second continuous wells. In some embodiments, the first and second continuous wells, the TSV structure, and the third continuous well are aligned along the second direction. In some embodiments, each of the fourth and seventh well portions is positioned along the border of the isolation structure of the TSV structure. In some embodiments, a first IC die includes an IC structure, an IC package includes a first IC die and a second IC die, and the TSV structure is electrically connected to the second IC die. In some embodiments, the first continuous well is an n-well and includes a single pickup structure electrically connected to a first power distribution structure configured to have a supply voltage, and the second continuous well is a p-well and includes a single pickup structure electrically connected to a second power distribution structure configured to have a reference voltage.

[0209] In some embodiments, an IC structure includes: a first TSV isolation structure and a second TSV isolation structure aligned along a first direction; a first continuous well, which is one of an n-well or a p-well, the first continuous well including: a first well portion adjacent to the first TSV isolation structure; and a plurality of second well portions extending from the first well portion in the first direction; and a second continuous well, which is the other of an n-well or a p-well, the second continuous well including: a third well portion adjacent to the second TSV isolation structure; and a plurality of fourth well portions extending from the third well portion in a second direction opposite to the first direction, wherein the plurality of second well portions alternate with the plurality of fourth well portions along a third direction perpendicular to the first and second directions. In some embodiments, the IC structure includes a plurality of connection structures, wherein each of the plurality of connection structures includes: a first pickup structure electrically connected to the first continuous well and a first power distribution structure; and a second pickup structure electrically connected to the second continuous well and a second power distribution structure separate from the first power distribution structure, and the number of connection structures in the plurality of connection structures is less than the number of well portions of each of the plurality of second well portions and the plurality of fourth well portions. In some embodiments, the ratio of the number of well portions of each of the plurality of second well portions and the plurality of fourth well portions to the number of connection structures of the plurality of connection structures has a value in the range of five to fifteen. In some embodiments, the connection structures of the plurality of connection structures are located adjacent to one of the first well portions or the third well portion. In some embodiments, a first continuous well and a second continuous well are included in a first die of a 3D IC package, a first TSV isolation structure surrounds a first TSV structure electrically connected to a second die of the 3D IC package, and a second TSV isolation structure surrounds a second TSV structure electrically connected to the second die. In some embodiments, the IC structure includes multiple rows of IC devices, wherein each row of IC devices includes: a first transistor located in a second well portion of the plurality of second well portions; and a second transistor located in a fourth well portion of the plurality of fourth well portions.

[0210] In some embodiments, a method of manufacturing an IC structure includes: configuring each of an n-well and a p-well in a first IC die to have the following portions: a first portion extending in a first direction; and second and third portions extending from the first portion in a second direction perpendicular to the first direction; and forming an IC device including a first pickup structure electrically connected to the n-well and a second pickup structure electrically connected to the p-well, wherein forming the IC device includes: forming a PMOS transistor in the second or third portion of the n-well and forming an NMOS transistor in the second or third portion of the p-well. In some embodiments, configuring each of the n-well and p-well to have a second and third portion extending from the first portion in the second direction includes: the second and third portions of the n-well and p-well having an interdigitated configuration. In some embodiments, configuring an n-well includes: performing an implantation process on a p-type substrate, and configuring a p-well includes: configuring a region outside the n-well as a p-well based on being part of the p-type substrate. In some embodiments, forming an IC device includes: forming a first electrical connection from a first pickup structure to a first power distribution structure configured to have a power supply voltage; and forming a second electrical connection from a second pickup structure to a second power distribution structure configured to have a reference voltage. In some embodiments, the method includes: constructing a TSV structure in a first die adjacent to a first portion of an n-well or a first portion of a p-well. In some embodiments, the method includes: electrically connecting the TSV structure to a second IC die of an IC package.

[0211] Those skilled in the art will readily recognize that the disclosed one or more embodiments achieve one or more of the advantages set forth above. Having read the foregoing specification, those skilled in the art will be able to appreciate the various variations, equivalents, and other embodiments widely disclosed herein. Therefore, the protection granted herein is limited only by the definitions contained in the appended claims and their equivalents.

[0212] Example

[0213] Example 1. An integrated circuit (IC) structure includes: a first continuous well, which is one of an n-well or a p-well, the first continuous well including: a first well portion extending in a first direction; a second well portion extending from the first well portion in a second direction perpendicular to the first direction; and a third well portion extending from the first well portion in the second direction parallel to the second well portion.

[0214] Example 2. The IC structure according to Example 1 further includes: a second continuous well, which is the other of the n-well or the p-well, the second continuous well including: a fourth well portion extending in the first direction; a fifth well portion extending upward from the fourth well portion in a third direction opposite to the second direction and between the second well portion and the third well portion; and a sixth well portion extending upward in the third direction and parallel to the fifth well portion from the fourth well portion.

[0215] Example 3. The IC structure according to Example 2, wherein the second well portion and the fifth well portion correspond to the first row of IC devices, and the third well portion and the sixth well portion correspond to the second row of IC devices.

[0216] Example 4. The IC structure according to Example 2 further includes: a third continuous well, comprising: a seventh well portion extending in the first direction; an eighth well portion extending from the seventh well portion in the second direction; and a ninth well portion extending from the seventh well portion in the second direction parallel to the eighth well portion; and a through-silicon via (TSV) structure located between the third continuous well and the first and second continuous wells.

[0217] Example 5. The IC structure according to Example 4, wherein the first continuous well and the second continuous well, the TSV structure, and the third continuous well are aligned along the second direction.

[0218] Example 6. The IC structure according to Example 5, wherein each of the fourth well portion and the seventh well portion is positioned along the border of the isolation structure of the TSV structure.

[0219] Example 7. The IC structure according to Example 4, wherein the first IC die includes the IC structure, the IC package includes the first IC die and the second IC die, and the TSV structure is electrically connected to the second IC die.

[0220] Example 8. The IC structure according to Example 1, wherein the first continuous well is the n-well and includes a single pickup structure electrically connected to a first power distribution structure configured to have a supply voltage, and the second continuous well is the p-well and includes a single pickup structure electrically connected to a second power distribution structure configured to have a reference voltage.

[0221] Example 9. An integrated circuit (IC) structure includes: a first through-silicon via (TSV) isolation structure and a second TSV isolation structure aligned along a first direction; a first continuous well, which is one of an n-well or a p-well, the first continuous well including: a first well portion adjacent to the first TSV isolation structure; and a plurality of second well portions extending from the first well portion in the first direction; and a second continuous well, which is the other of the n-well or the p-well, the second continuous well including: a third well portion adjacent to the second TSV isolation structure; and a plurality of fourth well portions extending from the third well portion in a second direction opposite to the first direction, wherein the plurality of second well portions alternate with the plurality of fourth well portions along a third direction perpendicular to the first direction and the second direction.

[0222] Example 10. The IC structure according to Example 9 further includes a plurality of connection structures, wherein each of the plurality of connection structures includes: a first pickup structure electrically connected to the first continuous well and the first power distribution structure; and a second pickup structure electrically connected to the second continuous well and a second power distribution structure separate from the first power distribution structure, and the number of connection structures of the plurality of connection structures is less than the number of well portions of each of the plurality of second well portions and the plurality of fourth well portions.

[0223] Example 11. The IC structure according to Example 10, wherein the ratio of the number of well portions of each of the plurality of second well portions and the plurality of fourth well portions to the number of connection structures of the plurality of connection structures has a value in the range of five to fifteen.

[0224] Example 12. The IC structure according to Example 10, wherein the connection structure of the plurality of connection structures is located adjacent to one of the first well portion or the third well portion.

[0225] Example 13. The IC structure according to Example 9, wherein the first continuous well and the second continuous well are included in a first die of a 3D IC package, the first TSV isolation structure surrounds a first TSV structure electrically connected to a second die of the 3D IC package, and the second TSV isolation structure surrounds a second TSV structure electrically connected to the second die.

[0226] Example 14. The IC structure according to Example 9 further includes multiple rows of IC devices, wherein each row of IC devices includes: a first transistor located in a second well portion of the plurality of second well portions; and a second transistor located in a fourth well portion of the plurality of fourth well portions.

[0227] Example 15. A method of manufacturing an integrated circuit (IC) structure, the method comprising: configuring each of an n-well and a p-well in a first IC die to have the following portions: a first portion extending in a first direction; and a second portion and a third portion extending from the first portion in a second direction perpendicular to the first direction; and forming an IC device including a first pickup structure electrically connected to the n-well and a second pickup structure electrically connected to the p-well, wherein forming the IC device comprises: forming a PMOS transistor in the second or third portion of the n-well and forming an NMOS transistor in the second or third portion of the p-well.

[0228] Example 16. The method according to Example 15, wherein configuring each of the n-well and the p-well to have a second portion and the third portion extending from the first portion in the second direction includes: the second portion and the third portion of the n-well and the p-well having an interdigitated configuration.

[0229] Example 17. The method according to Example 15, wherein configuring the n-well includes performing an implantation process on a p-type substrate, and configuring the p-well includes configuring a region outside the n-well as the p-well based on being part of the p-type substrate.

[0230] Example 18. The method according to Example 15, wherein forming the IC device includes: forming a first electrical connection from the first pickup structure to a first power distribution structure configured to have a power supply voltage; and forming a second electrical connection from the second pickup structure to a second power distribution structure configured to have a reference voltage.

[0231] Example 19. The method according to Example 15 further includes: constructing a through-silicon via (TSV) structure in the first die adjacent to a first portion of the n-well or a first portion of the p-well.

[0232] Example 20. The method according to Example 19 further includes: electrically connecting the TSV structure to a second IC die of the IC package.

Claims

1. An integrated circuit (IC) structure, comprising: The first continuous well is one of an n-well or a p-well, and the first continuous well includes: The first well portion extends in the first direction; The second well portion extends from the first well portion in a second direction perpendicular to the first direction; and The third well portion extends from the first well portion in the second direction parallel to the second well portion; The second continuous well is the other of the n-well or the p-well, and the second continuous well includes: The fourth well portion extends in the first direction; The fifth well portion extends upward from the fourth well portion in a third direction opposite to the second direction, and lies between the second well portion and the third well portion; and The sixth well portion extends upward from the fourth well portion and parallel to the fifth well portion on the third side; The third continuous well includes: The seventh well portion extends in the first direction; The eighth well portion extends from the seventh well portion in the second direction; and The ninth well portion extends from the seventh well portion in the second direction parallel to the eighth well portion; and A through-silicon via (TSV) structure is located between the third continuous well and the first and second continuous wells.

2. The integrated circuit (IC) structure according to claim 1, wherein, The second well portion and the fifth well portion correspond to the first row of integrated circuit (IC) devices, and The third well portion and the sixth well portion correspond to the second row of integrated circuit (IC) devices.

3. The integrated circuit (IC) structure according to claim 1, wherein, The first continuous well, the second continuous well, the through-silicon via (TSV) structure, and the third continuous well are aligned along the second direction.

4. The integrated circuit (IC) structure according to claim 3, wherein, Each of the fourth well portion and the seventh well portion is positioned along the border of the isolation structure of the through-silicon via (TSV) structure.

5. The integrated circuit (IC) structure according to claim 1, wherein, The first integrated circuit IC die includes the aforementioned integrated circuit IC structure. The integrated circuit (IC) package includes a first integrated circuit IC die and a second integrated circuit IC die, and The through-silicon via (TSV) structure is electrically connected to the second integrated circuit (IC) die.

6. The integrated circuit (IC) structure according to claim 1, wherein, The first continuous well is the n-well and includes a single pickup structure electrically connected to a first power distribution structure configured to have a supply voltage. The second continuous well is the p-well and includes a single pickup structure electrically connected to a second power distribution structure configured to have a reference voltage.

7. An integrated circuit (IC) structure, comprising: The first through-silicon via (TSV) isolation structure and the second through-silicon via (TSV) isolation structure are aligned along the first direction; The first continuous well is one of an n-well or a p-well, and the first continuous well includes: The first well portion is adjacent to the first through-silicon via (TSV) isolation structure; and Multiple second well portions extend from the first well portion in the first direction; and The second continuous well is the other of the n-well or the p-well, and the second continuous well includes: The third well portion is adjacent to the second through-silicon via (TSV) isolation structure; and Multiple fourth well sections extend from the third well section in a second direction opposite to the first direction. Wherein, the plurality of second well portions alternate with the plurality of fourth well portions along a third direction perpendicular to the first direction and the second direction; The third continuous well includes: The fifth well portion is adjacent to the second through-silicon via (TSV) isolation structure; and Multiple sixth well portions extend from the fifth well portion in the first direction. A through-silicon via (TSV) structure is located between the third continuous well and the first and second continuous wells.

8. The integrated circuit (IC) structure according to claim 7 further includes multiple connection structures, wherein, Each of the plurality of connection structures includes: A first pickup structure is electrically connected to the first continuous sink and the first power distribution structure; and The second pickup structure is electrically connected to the second continuous sink and a second power distribution structure separate from the first power distribution structure, and The number of connection structures in the plurality of connection structures is less than the number of well portions in each of the plurality of second well portions and the plurality of fourth well portions.

9. The integrated circuit (IC) structure according to claim 8, wherein, The ratio of the number of well portions of each of the plurality of second well portions and the plurality of fourth well portions to the number of connection structures of the plurality of connection structures has a value in the range of five to fifteen.

10. The integrated circuit (IC) structure according to claim 8, wherein, The connection structure in the plurality of connection structures is located adjacent to one of the first well portion or the third well portion.

11. The integrated circuit (IC) structure according to claim 7, wherein, The first and second consecutive wells are included in the first die of a 3D integrated circuit (IC) package. The first through-silicon via (TSV) isolation structure surrounds the first TSV structure electrically connected to the second die of the 3D integrated circuit IC package, and The second through-silicon via (TSV) isolation structure surrounds the second through-silicon via (TSV) structure electrically connected to the second die.

12. The integrated circuit (IC) structure according to claim 7 further includes multiple rows of integrated circuit (IC) devices, wherein, Each row of integrated circuit IC devices in the multi-row integrated circuit IC devices includes: A first transistor is located in the second well portion of the plurality of second well portions; and The second transistor is located in the fourth well portion of the plurality of fourth well portions.

13. A method for manufacturing an integrated circuit (IC) structure, the method comprising: A first continuous well, a second continuous well, and a third continuous well are formed in the substrate of the first integrated circuit IC die. Wherein, the first continuous well is one of an n-well or a p-well, and the first continuous well includes: The first well portion extends in the first direction; The second well portion extends from the first well portion in a second direction perpendicular to the first direction; and The third well portion extends from the first well portion in the second direction parallel to the second well portion; Wherein, the second continuous well is another of the n-well or the p-well, and the second continuous well includes: The fourth well portion extends in the first direction; The fifth well portion extends upward from the fourth well portion in a third direction opposite to the second direction, and lies between the second well portion and the third well portion; and The sixth well portion extends upward from the fourth well portion and parallel to the fifth well portion on the third side; The third continuous well includes: The seventh well portion extends in the first direction; The eighth well portion extends from the seventh well portion in the second direction; and The ninth well portion extends from the seventh well portion in the second direction parallel to the eighth well portion; A through-silicon via (TSV) structure is formed between the third continuous well and the first and second continuous wells; and An integrated circuit (IC) device is formed, the IC device including a first pickup structure electrically connected to the first continuous well and a second pickup structure electrically connected to the second continuous well. The formation of the integrated circuit (IC) device includes: forming a PMOS transistor in a second well portion or a third well portion of the first continuous well, and forming an NMOS transistor in a fifth well portion or a sixth well portion of the second continuous well.

14. The method according to claim 13, wherein, The second and third well portions of the first continuous well and the fifth and sixth well portions of the second continuous well have an interdigitated configuration.

15. The method according to claim 13, wherein, Configuring the first continuous well includes: performing an implantation process on the p-type substrate, and Configuring the second continuous well includes configuring a region outside the first continuous well as the second continuous well as part of the p-type substrate.

16. The method according to claim 13, wherein, The integrated circuit (IC) device comprises: Forming a first electrical connection from the first pickup structure to a first power distribution structure configured to have a power supply voltage; and A second electrical connection is formed from the second pickup structure to the second power distribution structure configured to have a reference voltage.

17. The method of claim 13, further comprising: A through-silicon via (TSV) structure is constructed in the first well portion of the first continuous well or the fourth well portion of the second continuous well in the first integrated circuit (IC) die.

18. The method of claim 17, further comprising: The through-silicon via (TSV) structure is electrically connected to the second integrated circuit IC die of the integrated circuit IC package.

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