Integrated circuit device and method of forming the same

Abstract

Embodiments of the present application disclose an integrated circuit (IC) device including a high voltage semiconductor device (HVSD) on a front side of a semiconductor body and further including an electrode on a back side of the semiconductor body, the back side being opposite the front side. The high voltage semiconductor device can be a transistor or other suitable type of semiconductor device, for example. The electrode has one or more voids directly underneath the HVSD. The one or more voids enhance the effect of the electrode in improving the breakdown voltage of the HVSD. According to other embodiments of the present application, methods of forming an integrated circuit device are also provided.

Description

Technical Field

[0001] Embodiments of this application relate to integrated circuit devices and methods of forming the same. Background Technology

[0002] Modern integrated circuits comprise millions or billions of semiconductor devices formed on a semiconductor substrate (e.g., silicon). Integrated circuit (IC) devices (chips) can use many different types of transistor devices, depending on the application of the IC. In recent years, the expanding market for cellular and RF (radio frequency) devices has led to a significant increase in the use of high-voltage transistor devices. For example, high-voltage transistor devices are frequently used in power amplifiers in RF transmission / reception chains due to their ability to handle high breakdown voltages (e.g., greater than about 50V) and high frequencies. Summary of the Invention

[0003] According to an embodiment of this application, an integrated circuit device is provided, comprising: a semiconductor body including a front side and a back side; a high voltage semiconductor device (HVSD) formed in the front side; and a conductive layer and an insulating layer on the back side, wherein the insulating layer is between the conductive layer and the semiconductor body; wherein the conductive layer is formed on an electrode directly below the high voltage semiconductor device; and the electrode has a gap directly below the high voltage semiconductor device.

[0004] According to another embodiment of this application, an integrated circuit device is provided, comprising: a semiconductor body; a plurality of high-voltage devices formed in the semiconductor body; an insulating layer beneath the semiconductor body; and one or more electrodes in a layer beneath the insulating layer; wherein each of the plurality of high-voltage devices has a berth beneath the semiconductor body; the one or more electrodes are formed in a repeating pattern within each berth; and the pattern has gaps within each berth.

[0005] According to another embodiment of this application, a method for forming an integrated circuit device is provided, comprising: forming a high voltage semiconductor device (HVSD) on the front side of a semiconductor body; forming an insulating layer and a conductive layer on the back side of the semiconductor body, wherein the insulating layer is between the conductive layer and the semiconductor body; and etching the conductive layer to define an electrode directly below the high voltage semiconductor device and an opening in the electrode; wherein the opening is directly below the high voltage semiconductor device.

[0006] Embodiments of this application relate to high-voltage devices with increased breakdown voltage. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0008] Figure 1A A cross-sectional side view of an integrated circuit (IC) device including a high-voltage semiconductor device is shown according to some aspects of this disclosure.

[0009] Figure 1B According to some embodiments of this disclosure Figure 1A A plan view of some surrounding structures within high-voltage semiconductor devices and IC devices.

[0010] Figure 1C This is a plan view of a back electrode with a gap according to some embodiments of the present disclosure.

[0011] Figure 1D Will Figure 1B and Figure 1C The components are combined in the representative Figure 1A The superimposed planar diagram of IC devices.

[0012] Figure 2 It is a display Figure 1A A plan view of another layout of high-voltage semiconductor devices for IC devices.

[0013] Figures 3-9 A cross-sectional side view of an integrated circuit (IC) device according to various aspects of this disclosure is shown.

[0014] Figures 10-22 A series of cross-sectional views illustrate the formation of, for example, according to this disclosure. Figure 1A IC device method

[0015] Figures 23-29 Some other aspects of this disclosure are illustrated in a series of cross-sectional views. Figures 10-22 Changes in methods.

[0016] Figures 30-34 Some other aspects of this disclosure are illustrated in a series of cross-sectional views. Figures 10-22 Changes in methods.

[0017] Figures 35-37 Flowcharts illustrating some processes according to this disclosure for forming IC devices according to this disclosure are provided. Detailed Implementation

[0018] This disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the individual embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0020] Integrated circuit (IC) devices can include high-voltage semiconductor devices (HVSDs), such as high-voltage transistors. HVSDs can have a breakdown voltage greater than about 20 volts (V), for example, a breakdown voltage in the range of about 50V to about 113V. Implementing HVSDs on a silicon-on-insulator (SOI) substrate can improve performance by reducing latch-up, increasing package density, and reducing leakage current. Further improvements can be achieved by implementing a reduced surface field (RESURF) concept using electrodes on the back side of the substrate, where an insulating layer separates the electrodes from the semiconductor body in which the HVSD is formed. The electrodes can be grounded or maintained with a suitable bias voltage, which can improve the breakdown voltage of the associated HVSD. Improvements can include increasing the absolute value of the breakdown voltage.

[0021] According to some aspects of this disclosure, the back electrode directly beneath the HVSD has one or more gaps directly beneath the HVSD. These gaps enhance the effectiveness of the back electrode in improving the breakdown voltage of the HVSD. The location and number of the most effective gaps in the back electrode can vary depending on the HVSD size and doping.

[0022] In some embodiments, one or more gaps are cutouts within the back electrode. Thus, in some embodiments, a first portion of the back electrode is on one side of the gap, and a second portion of the electrode is on the opposite side of the gap. In some embodiments, the first and second portions are combined. In some embodiments, the back electrode completely surrounds the gap. The gap may have a width less than half the width of the HVSD. In some embodiments, the solid portion of the back electrode covers most of the area directly beneath the HVSD.

[0023] HVSD can be any type of metal-oxide-semiconductor field-effect transistor (MOSFET), bipolar junction transistor (BJT), PN diode, other high-voltage semiconductor device, and combinations thereof. In some embodiments, the HVSD is completely surrounded by a deep trench isolation (DTI) structure. In some embodiments, the DTI structure extends from the front side to the back side of the semiconductor body in which the HVSD is formed. In some embodiments, the HVSD can be identified as a collection of semiconductor device structures surrounded by a single DTI structure.

[0024] In some embodiments, the gap has a shape corresponding to the shape of a structure such as the well region, source region, drain region, and gate electrode of an HVSD. The back electrode may be directly below the structure such as the well region, source region, drain region, and gate electrode, and its shape corresponds to the structure such as the well region, source region, drain region, and gate electrode. In some of these embodiments, the source region or drain region is annular and the gap is also annular. In some embodiments, the HVSD has source and drain regions that extend in a direction transverse to the source-to-drain direction. In some of these embodiments, one or more gaps also extend in the transverse direction. In some of these embodiments, one or more gaps have a transverse extent that is greater than the transverse extent of the source and drain regions. Note that the transverse extent may, for example, correspond to a dimension in the transverse direction. The back electrode may have a transverse extent that is greater than the transverse extent of the gap, thereby extending across one or both transverse ends of the gap. Gaps with these structural features can improve the electric field uniformity in an HVSD.

[0025] In some embodiments, the IC device has a plurality of HVSDs of comparable size and doping, and their corresponding back electrodes have a repeating pattern for each of the plurality of HVSDs. The patterning is such that each back electrode extends beyond some, but not all, of the occupancy of the corresponding HVSD. Incomplete coverage can be described based on one or more gaps in each of the back electrodes. In some embodiments, the gap is directly below the drain region of the HVSD. In some embodiments, the gap is directly below the PN junction including the drain region of the HVSD. In some embodiments, the gap is directly below the source region of the HVSD. In some embodiments, the gap is directly below the PN junction including the source region of the HVSD. In some embodiments, the gap is directly below the gate electrode of the HVSD on the front side of the substrate. In some embodiments, the gap is below the channel of the HVSD. In some embodiments, the gap is directly below the n-well of the HVSD. In some embodiments, the gap is directly below the p-well of the HVSD. In some of these embodiments, the HVSD is a transistor. For a particular type, size, and doping of the HVSD, the number and location of the gaps can be determined based on the HVSD structure.

[0026] In some embodiments, the HVSD is surrounded by a deep trench isolation (DTI) structure that extends through the entire thickness of the semiconductor body in which the HVSD is formed. In some embodiments, the back electrode of the HVSD extends beneath the DTI structure. In some embodiments, the back electrode is entirely within the outer periphery of the DTI structure. In some embodiments, a metal interconnect structure is disposed on the front side of the semiconductor body. In some embodiments, a through-substrate via (TSV) extends through the semiconductor body. In some embodiments, the TSV connects the back electrode to the metal interconnect structure. In some embodiments, the TSV passes through the DTI structure. In some embodiments, the back electrode is connected to a contact pad through which the back electrode can be grounded or held to a predetermined voltage. In some embodiments, the back electrode is connected to the contact pad such that the voltage on the back electrode varies continuously with the voltage on the contact pad.

[0027] In some embodiments, the logic devices are formed in the same semiconductor body as the HVSD. In some embodiments, the IC device includes multiple substrates. In some embodiments, a second substrate is connected to the front side. In some embodiments, a second substrate is connected to the back side. In some embodiments, an additional substrate is connected to both the front and back sides. In some embodiments, the IC device is a bipolar-CMOS-DMOS (BCD) device. In a BCD device, the HVSD and low-density logic devices may be formed on the first substrate, while other types of devices may be formed on different substrates connected to the first substrate.

[0028] Some aspects of this disclosure relate to methods of forming an IC device. According to these methods, an HVSD is formed on the front side of a semiconductor body. In some embodiments, an insulating layer and a conductive layer are formed on the back side of the semiconductor body. In some embodiments, the conductive layer is a metal layer. The conductive layer is patterned to form an electrode with an opening directly beneath the HVSD. The electrode may be connected to contact pads and used to improve the breakdown voltage of the HVSD. In some embodiments, the connection to the contact pads includes a TSV. In some embodiments, the electrode is patterned after the TSV is formed. In some embodiments, the electrode with the opening is formed by a damascene process.

[0029] Figure 1A A cross-sectional side view of an IC device 100A according to some aspects of this disclosure is shown. The IC device 100A includes a device layer 155, which includes a semiconductor body 159A having a front side 197 and a back side 195. A metal interconnect structure 137 is disposed on the front side 197. An insulating layer 163 and a conductive layer 165 are disposed on the back side 195, the insulating layer 163 separating the conductive layer 165 from the semiconductor body 159A. A high-voltage semiconductor device (HVSD) 115A is formed in the semiconductor body 159A adjacent to the front side 197. A back electrode 185A with a gap 191A is formed directly beneath the HVSD 115A in the conductive layer 165. The gap 191A is filled with a non-conductive material such as a dielectric 183. The back electrode 185A has a first sidewall 178 and a second sidewall 184 on both sides of each gap 191A. The first sidewall 178 and the second sidewall 184 are directly below the HVSD 115A and are separated by a dielectric 183.

[0030] Figure 1B A plan view of the HVSD 115A and some surrounding structures is shown. Figure 1C This is a plan view of the back electrode 185A. Figure 1D Combined Figure 1B and Figure 1C The view is shown to illustrate the geometric relationship between the location of the HVSD 115A and its component structure and the location of the back electrode 185A and its gap 191A. The gap 191A may be alternately described as an opening or space in the back electrode 185A.

[0031] In the illustrated example, the HVSD is a laterally diffused double-diffused metal-oxide-semiconductor (LDMOS) device using shallow trench isolation (STI). More specifically, the HVSDs in the examples are all high-voltage transistors. However, the HVSD can be any type of metal-oxide-semiconductor field-effect transistor (MOSFET), bipolar junction transistor (BJT), PN diode, other high-voltage semiconductor devices, and combinations thereof, and other types of isolation structures can be used.

[0032] The HVSD 115A includes a drain region 117, two source regions 129, and two gate electrodes 121. The drain region 117 is a heavily n-doped region of the semiconductor body 159A disposed between the two STI structures 123. The source regions 129 are heavily n-doped regions within p-wells 133. The p-wells 133 are separated from the drain region 117 by n-wells 127 and 119. The n-wells 127 and 119 are drift regions that improve breakdown voltage. The gate electrodes 121 are disposed on the front side 197 adjacent to the source regions 129. The gate electrodes 121 cover the PN junction 113 between the p-wells 133 and the n-wells 127, and may partially cover the STI structure 123. A region of the p-well 133 located directly below the gate electrodes 121 provides a channel 111. A gate dielectric 125 is disposed between the gate electrodes 121 and the channel 111. The semiconductor body 159A may be lightly p-doped. The voltage of the semiconductor body 159A can be adjusted by the heavily p-doped body contact region 131.

[0033] HVSD 115A has a footprint corresponding to a region surrounded by a deep trench isolation (DTI) structure 141 surrounding HVSD 115A. According to some embodiments, the DTI structure 141 extends from a front side 197 to a back side 195. A back electrode 185A, excluding gaps 191A, extends more than half or more of the footprint of HVSD 115A. In some embodiments, the back electrode 185A extends more than 75% of the footprint. In some embodiments, each gap 191A extends more than 25% or less of the footprint. In some embodiments, each gap 191A extends more than 15% or less of the footprint.

[0034] refer to Figure 1B The source region 129, drain region 117, and gate electrode 121 each extend in a direction Y transverse to the direction X, where direction X is the source-to-drain direction of the HVSD 115A. The gap 191A also extends in the Y direction. According to some embodiments, the length 145 of the gap 191A in the Y direction is greater than the length 142 of the source region 129 and drain region 117 in the Y direction. Furthermore, the length 145 of the gap 191A in the Y direction is greater than the length 147 of the gate electrode 121 in the Y direction. According to some embodiments, the gap 191A extends below the DTI structure 141, thus extending beyond the footprint of the HVSD 115A. Having the gap 191A at least this length can improve the electric field uniformity within the HVSD 115A.

[0035] refer to Figure 1CThe back electrode 185A has a lateral extent 146, which is greater than the length 145 of the gap 191A. The lateral extent is the length transverse to the source-to-drain direction (e.g., the X direction). The gap 191A is within the periphery 153 of the back electrode 185A. Therefore, a first portion 154 of the back electrode 185A is on one side 152 of the gap 191A, and a second portion 156 of the back electrode 185A is on the other side 151 of the gap 191A. The first portion 154 and the second portion 156 can be joined at the lateral end 148 of the gap 191A, thereby allowing the back electrode 185A to surround the gap 191A. Although the back electrode 185A can be divided into multiple portions by the gap 191A, joining the back electrode 185A into a single piece can improve the electric field uniformity.

[0036] In some embodiments, gap 191A is located directly below p-well 133, and heavily n-doped source region 129 is disposed within p-well 133. In some embodiments, gap 191A is completely below p-well 133. In some embodiments, gap 191A is directly below source region 129. These gap locations are distal relative to drain region 117, which is a high-voltage region. Simulations show that the breakdown voltage improvement is greatest when gap 191A is distal relative to the high-voltage region of a high-voltage device such as HVSD 115A.

[0037] refer to Figure 1C and Figure 1D In some embodiments, the back electrode 185A extends beneath the DTI structure 141, thus extending beyond the footprint of the HVSD 115A. Making the gap 191A at least this long can improve the electric field uniformity within the HVSD 115A. In some embodiments, the back electrode 185A is within the outer periphery 157 of the DTI structure 141. According to some embodiments, the region within the periphery 153 of the back electrode 185A, including the region of the back electrode 185A with the gap 191A, is larger than the footprint of the HVSD 115A. In some embodiments, the region within the periphery 153 is between 100% and 150% of the footprint of the HVSD 115A. In some embodiments, the region within the periphery 153 is between 100% and 120% of the footprint of the HVSD 115A. Making the region of the back electrode 185A larger than the footprint of the HVSD 115A can improve the electric field uniformity within the HVSD 115A. If the area of ​​the back electrode 185A is too large, it may occupy too much chip area. Furthermore, a through-substrate via (TSV) 139A can be provided within the DTI structure 141 surrounding the back electrode 185A. The size of the back electrode 185A can be limited to allow space for the TSV 139A to be positioned together with the DTI structure 141.

[0038] In some embodiments, the width 193 of the gap 191A is at least the width 143 of the source region 129 in the source-to-drain direction X (see...). Figure 1B Half of the width of the source region 129. In some embodiments, the width 193 of the gap 191A is at least equal to the width 143 of the source region 129. In some embodiments, the gap 191A does not exceed twice the width 143. In some embodiments, the gap 191A is smaller than the source-to-drain distance 144. The gap 191A can provide the maximum improvement in breakdown voltage within these limitations.

[0039] The width 193 of the gap 191A may vary relative to the thickness 187 of the insulating layer 163. In some embodiments, the thickness 187 of the insulating layer 163 is from about 0.1 μm to about 10 μm. In some embodiments, the thickness 187 is from about 0.5 μm to about 3 μm. In some embodiments, the thickness 187 is from about 1 μm to about 2 μm.

[0040] In some embodiments, the width 193 of gap 191A is 1 to 10 times the thickness 187. In some embodiments, the width 193 is 1 to 5 times the thickness 187. In some embodiments, the width 193 is about 0.1 μm to about 20 μm. In some embodiments, the width 193 is about 0.5 μm to about 5 μm. In some embodiments, the width 193 is about 1 μm to about 2 μm. Ensuring the width 193 of gap 191A within these limitations provides the greatest improvement in breakdown voltage.

[0041] refer to Figure 1A The back electrode 185A can be connected to the contact pad 175B, through which the back electrode 185A can be grounded or maintained to a predetermined voltage. In some embodiments, the contact pad 175B is on the back side 195. In some embodiments, the back electrode 185A is connected to the contact pad 175B via a metal interconnect structure 137. Optionally, the contact pad 175B can be on the front side 197, or the back electrode 185A can be directly connected to the contact pad 175B without using any connection to the metal interconnect structure 137 or any other structure on the front side 197.

[0042] In some embodiments, the back electrode 185A is connected to the metal interconnect structure 137 via one or more TSVs 139A. Alternatively, the back electrode 185A can be connected to the metal interconnect structure 137 via a multi-channel connection, which can be provided as a polysilicon ring along with the DTI structure 141 surrounding the HVSD 115A. Figure 1BAs shown, TSV 139A can be distributed around HVSD 115A and can be separated from HVSD 115A by deep trench isolation structure 141. TSV 139A can be connected to back electrode 185A via conductive lines 180 and vias 181 on back electrode 195. In some embodiments, back electrode 185A is a single structure. If back electrode 185A is divided into two or more blocks by gap 191A, conductive lines 180 and vias 181 can connect one or more TSV 139A to each block.

[0043] The metal interconnect structure 137 includes conductive lines 110 and vias 103 within an interlayer dielectric (ILD) 105. The ILD may include one or more layers of materials, such as low-k dielectrics (e.g., dielectric materials with a dielectric constant less than about 3.9), oxides (e.g., SiO2), nitrides (e.g., SiN), carbides (e.g., SiC), oxynitrides (e.g., SiON), carbon oxides (e.g., SiOC), undoped silicate glass (USG), doped silicon dioxide (e.g., carbon-doped silicon dioxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate-phosphosilicate glass (BPSG), fluorosilicate glass (FSG), spin-coated glass (SOG), etc.

[0044] All TSVs 139A associated with HVSD 115A and back electrode 185A can be interconnected with each other via metal interconnect structure 137 and connected to a single contact pad 175B. In particular, TSVs 139A can be connected to conductive line 109A, and further connected to TSV 139B via various conductive lines 110 and vias 103, TSV 139B being connected to contact pad 175B on the back side 195.

[0045] Two source regions 129 and two gate electrodes 121 can be connected together via a metal interconnect structure 137, enabling the HVSD 115A to operate as a single transistor. Specifically, the source regions 129 can be connected to conductive lines 110B via contact plugs 109B. Conductive lines 110B can be combined and further connected to TSV 139C via various conductive lines 110 and vias 103. TSV 139C is connected to contact pads 175A on the back surface 195. Gate electrodes 121 can be connected to conductive lines 110C via contact plugs 109C. Conductive lines 110C can be combined and further connected to TSV 139D via various conductive lines 110 and vias 103. TSV 139D is connected to contact pads 175C on the back surface 195. Drain region 117 can be connected to conductive line 110D via contact plug 109D. Conductive line 110D can be further connected to TSV139E via various conductive lines 110 and through-hole 103, and TSV139E is connected to contact pad 175D on the back side 195.

[0046] Figure 2 A plan view 200 is provided illustrating the HVSD 115B and its associated back electrode 185B. The HVSD 115B is similar to the HVSD 115A but has an alternative layout that can be used in the IC device 100A or any other instance of this disclosure. In the HVSD 115B, the gate electrode 121B, source region 129B, and body contact region 131B are annular. The gap 191B of the back electrode 185B is also annular. The source-to-drain distance 144 can be the same as that of the back electrode 185A. Similarly, the width 193 of the gap 191B can be the same as that of the gap 191A. The gap 191B can be completely surrounded by the DTI structure 141 without limiting the uniformity of the electric field.

[0047] Figure 3 A cross-sectional side view of an IC device 100C according to some other embodiments of the present disclosure is provided. The IC device 100C is similar to the IC device 100A, but has a back electrode 185C with a gap 191C. The gap 191C is directly below the gate electrode 121. In some embodiments, the gap 191C is as narrow as or narrower than the gate electrode 121. In some embodiments, the width 193C of the gap 191C is entirely within the occupancy of the gate electrode 121. In some embodiments, the width 193C is greater than the width 194 of the gate electrode 121. In some embodiments, the occupancy of the gate electrode 121 is entirely within the gap 191C. As used herein, a occupancy is a two-dimensional projection in a plane parallel to the upper surface of the semiconductor body.

[0048] Figure 4A cross-sectional side view of an IC device 100D according to some other embodiments of the present disclosure is provided. The IC device 100D is similar to the IC device 100A, but has a back electrode 185D with a gap 191D. The gap 191D is directly below the drain region 117. In some embodiments, the gap 191D is as narrow as or narrower than the drain region 117. In some embodiments, the width 193D of the gap 191D is entirely within the footprint of the drain region 117. In some embodiments, the width 193D is greater than the width 196 of the drain region 117. In some embodiments, the footprint of the drain region 117 is entirely within the gap 191D.

[0049] Figure 5 A cross-sectional side view of an IC device 100E according to some other embodiments of the present disclosure is provided. IC device 100E is similar to IC device 100A, but has a back electrode 185E with a gap 191E. The gap 191E is directly below a channel 111. In some embodiments, the gap 191E is as narrow as or narrower than the channel 111. In some embodiments, the channel 111 is entirely contained within the gap 191E. In some embodiments, a portion of the gap 191E is directly below a gate electrode 121, and a portion of the gap 191E is directly below a source region 129. In some embodiments, the gap 191E is directly below a PN junction 501. The PN junction 501 is the junction between the source region 129 and the channel 111. In some embodiments, the gap 191E extends from directly below the PN junction 501 to directly below the PN junction 113.

[0050] Figures 3-5 The embodiments provide various relationships between the structure in the HVSD 115A and the size, location, and number of gaps in the corresponding back electrode. Each of these relationships may be particularly well-suited to a specific implementation of the HVSD 115A, with the most suitable relationship being determined by the size of the HVSD 115A, the doping type and concentration in the HVSD 115A, the isolation structure used in the HVSD 115A, and the operating voltage of the HVSD 115A.

[0051] IC devices 100A, 100C, 100D, and 100E all include the HVSD 115A, which is an n-channel laterally diffused metal-oxide-semiconductor (n-LDMOS) transistor. Figures 6-9 An IC device 100F-100I with a corresponding structure but with opposite doping types is shown. Figure 6IC device 100F is shown, which is the same as IC device 100A, but has a lightly n-doped semiconductor body 159B and HVSD115B. HVSD 115B is the same as HVSD 115A, but has the opposite doping type to provide a p-channel laterally diffused metal-oxide-semiconductor (p-LDMOS) transistor.

[0052] Figure 6 IC device 100F is shown, which is related to Figure 1A It is the same as IC device 100A, but has semiconductor body 159B instead of semiconductor body 159A, and HVSD 115B instead of HVSD 115A. Figure 7 The IC device 100G is shown, which is related to Figure 3 It is the same as the IC device 100C, but has a semiconductor body 159B and HVSD 115B. Figure 8 IC device 100H is shown, which is related to Figure 4 It is the same as the IC device 100D, but has a semiconductor body 159B and HVSD 115B. Figure 9 IC device 100I is shown, which is related to Figure 5 It is the same as the IC device 100E, but has a semiconductor body 159B and HVSD 115B.

[0053] Figures 10 to 22 The cross-sectional view example illustrates a method according to the present disclosure for forming an IC device having HVSD and associated back electrodes having one or more gaps, according to the present disclosure. Although Figures 10 to 22 The various embodiments of the method are described with reference to the present invention, but it is understood that... Figures 10 to 22 The structure shown is not limited to this method, but can be used independently of it. Although Figures 10 to 22 It is described as a series of actions, but it is understood that the order of the actions may change in other embodiments. Although Figures 10 to 22 A specific set of behaviors has been shown and described, but in other embodiments, some of the shown and / or described behaviors may be omitted. Furthermore, other embodiments may include behaviors that are not shown and / or described. Although Figures 10 to 22 The method is to form Figure 1A The method described is for IC device 100A, but this method can be used to form other IC devices.

[0054] like Figure 10As shown in cross-sectional view 1000, the method can begin by forming a DTI structure 141 and an n-well 127 in a semiconductor body 159A. The semiconductor body 159A comprises a semiconductor, which may be, for example, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), some other semiconductor materials, combinations of the above materials, etc. In some embodiments, the semiconductor body 159A is p-doped to approximately 10-10. 14 To about 10 16 atoms / cm 3 The concentration is within the range of [specific range]. In some embodiments, the n-well 127 is n-doped to about 10 [specific values]. 15 To about 10 17 atoms / cm 3 The concentration range is specified. The DTI structure 141 can be formed by etching trenches in the semiconductor body 159A and filling the trenches with a dielectric. The trenches may have sloping or substantially vertical sidewalls. The dielectric may be or include, for example, oxides (e.g., SiO2), nitrides (e.g., SiN), oxynitrides (e.g., SiON), carbides (e.g., silicon carbide (SiC)), and combinations thereof. The n-well 127 may be doped before or after the formation of the DTI structure 141.

[0055] like Figure 11 As shown in cross-sectional view 1100, this method can continue to form STI structure 123. STI structure 123 can be formed by etching trenches in semiconductor body 159A and filling the trenches with a dielectric. The trenches may have sloping or substantially vertical sidewalls. The dielectric can be or include, for example, oxides (e.g., SiO2), nitrides (e.g., SiN), oxynitrides (e.g., SiON), carbides (e.g., silicon carbide (SiC)), and combinations thereof. Some STI structures 123 can be formed directly over DTI structure 141.

[0056] like Figure 12 As shown in the cross-sectional view 1200, additional doping can be performed to form the n-well 119 and p-well 133. The STI structure 123 and a photoresist mask can be used to align these dopants. In some embodiments, the n-well 119 is more heavily doped than the n-well 127. In some embodiments, the n-well 119 is n-doped to approximately 10-10. 17 To about 10 18 atoms / cm 3 The concentration range. In some embodiments, p-well 133 is p-doped to about 10. 17 To about 10 18 atoms / cm 3 Concentration within the range.

[0057] like Figure 13As shown in cross-sectional view 1300, the method can continue to form a gate dielectric 125, a gate electrode 121, a drain region 117, a source region 129, and a body contact region 131 to complete the formation of the HVSD 115A. The process may include forming and patterning a gate stack including a gate dielectric layer and a gate electrode layer. In some embodiments, the gate electrode layer is or includes polysilicon, etc. In such embodiments, the gate dielectric layer may be or includes, for example, an oxide (e.g., silicon dioxide (SiO2)). In some other embodiments, the gate electrode layer may be or includes a metal, such as aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), cobalt (Co), etc. In such embodiments, the gate dielectric layer may be or includes a high-k dielectric material, such as hafnium oxide (HfO), tantalum oxide (TaO), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), aluminum oxide (AlO), zirconium oxide (ZrO), etc.

[0058] Gate electrode 121, any associated sidewall spacers (not shown), STI structure 123, and one or more photoresists (not shown) may provide a mask for doping drain region 117, source region 129, and body contact region 131. Source region 129 and drain region 117 may be n-doped to approximately 10n. 20 atoms / cm 3 Or even higher concentrations. The main contact region 131 can be p-doped to approximately 10-10. 20 atoms / cm 3 Or even higher concentrations. All of the above actions may be part of the front-end process (FEOL) treatment.

[0059] like Figure 14 As shown in cross-sectional view 1400, the method can proceed to back-to-office (BEOL) processing and the formation of metal interconnect structure 137. Forming the metal interconnect structure 137 can include a series of damascene or dual-damascene processes. This process includes forming contact plugs 109B, 109C, and 109D, conductive lines 110, and vias 103. Contact plugs 109B, 109C, and 109D can be or include, for example, tungsten (W), copper (Cu), aluminum (Al), etc. Contact plug 109B can be connected to both the body contact region 131 and the source region 129. Conductive lines 110 and vias 103 can be or include, for example, copper (Cu), aluminum (Al), gold (Au), silver (Ag), platinum (Pt), etc.

[0060] like Figure 15As shown in cross-sectional view 1500, at this stage of the process, the workpiece including the semiconductor body 159A can be flipped, and the method can continue to thin the semiconductor body 159A down to the device layer 155. After thinning the semiconductor body 159A, the DTI structure 141 extends to the back side 195, which is now on top. The thinning process can be, or includes, for example, chemical mechanical polishing (CMP), mechanical grinding, etching, a combination of the foregoing, etc. Before thinning, the semiconductor body 159A may have a thickness of, for example, about 750 μm. In some embodiments, after thinning, the semiconductor body 159A has a thickness in the range of about 2 μm to about 15 μm.

[0061] like Figure 16 As shown in cross-sectional view 1600, this method can further form an insulating layer 163, a conductive layer 165, and an ILD layer 167 on the back side 195. The insulating layer 163 and the ILD layer 167 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, any other suitable process, or combinations thereof. The conductive layer 165 can be formed by CVD, PVD, electroplating, electroless plating, some other deposition processes, or combinations thereof.

[0062] The insulating layer 163 may be or include low-k dielectrics (e.g., dielectric materials with a dielectric constant less than about 3.9), high-k dielectric materials (e.g., dielectric materials with a dielectric constant greater than about 3.9, such as hafnium oxide (HfO), tantalum oxide (TaO), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), aluminum oxide (AlO), zirconium oxide (ZrO), etc.), oxides (e.g., silicon dioxide (SiO2)), nitrides (e.g., silicon nitride (SiN)), oxynitrides (e.g., silicon oxynitride (SiON)), undoped silicate glass (USG), doped silicon dioxide (e.g., carbon-doped silicon dioxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), fluorosilicate glass (FSG), spin-coated glass (SOG), some other dielectric materials, combinations thereof, etc.

[0063] The conductive layer 165 can be any conductive material, such as a metal, a heavily doped semiconductor such as heavily doped polycrystalline silicon, or a conductive carbon-based material such as graphene. In some embodiments, the conductive layer 165 comprises a metal. The metal can be copper (Cu), aluminum (Al), tungsten (W), gold (Au), silver (Ag), platinum (Pt), or combinations thereof. In some embodiments, the conductive layer 165 is copper (Cu), aluminum (Al), a copper-aluminum alloy (CuAl), etc. In some embodiments, the conductive layer 165 has a thickness of about 1 μm to about 5 μm.

[0064] like Figure 17As shown in cross-sectional view 1700, a mask 1703 can be formed and used to pattern the conductive layer 165. The mask 1703 can be formed by photolithography. Patterning can include wet etching, dry etching, reactive ion etching (RIE), some other etching processes, combinations thereof, etc. Etching can be stopped in or on the insulating layer 163. Patterning can form a back electrode 185A from the conductive layer 165. Patterning can also form a gap 191A and an opening 1701 in the back electrode 185A, through which the TSV will pass through the conductive layer 165. The opening 1701 can be aligned with the DTI structure 141. After etching, the mask 1703 can be peeled off.

[0065] like Figure 18 As shown in cross-sectional view 1800, the method can continue to fill gap 191A and opening 1701 with dielectrics 183 and 179, respectively. Dielectrics 183 and 179 can be the same dielectric. Dielectrics 183 and 179 can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, any other suitable process, or combinations thereof. Excess dielectric can be removed by planarization processes such as chemical mechanical polishing (CMP). Dielectrics 183 and 179 can extend through both conductive layer 165 and ILD layer 167. Dielectric 179 can be horizontally aligned with DTI structure 141.

[0066] like Figure 19 As shown in the cross-sectional view 1900, a mask 1903 can be formed and used to etch TSV openings 1901. TSV openings 1901 can extend through dielectric 179, through insulating layer 163, through DTI structure 141 through semiconductor body 159A, and extend to metal interconnect structure 137 on front side 197. Etching processes can include wet etching, dry etching, reactive ion etching (RIE), some other etching processes, combinations thereof, etc. After etching, mask 1903 can be peeled off.

[0067] like Figure 20 As shown in cross-sectional view 2000, the method can proceed to form a mask 2003 and use it to etch via openings 2001 in the ILD layer 167. The back electrode 185A is exposed through the via openings 2001. Etching can include wet etching, dry etching, reactive ion etching (RIE), some other etching processes, combinations thereof, etc. It should be understood that the via openings 2001 can be formed before, after, or simultaneously with the TSV openings 1901. After etching, the mask 2003 can be peeled off.

[0068] like Figure 21As shown in cross-sectional view 2100, conductive material can be deposited to fill via openings 2001 and TSV openings 1901, forming a conductive layer 2101 on the back surface 195. The conductive material can be a metal, polysilicon, some other conductive materials, or combinations thereof. In some embodiments, the conductive material is a metal. Suitable metals can be, for example, copper (Cu), aluminum (Al), gold (Au), silver (Ag), or platinum (Pt), or combinations thereof. The conductive material can be deposited by CVD, PVD, electroplating, electroless plating, some other deposition processes, or combinations thereof. The conductive material forms TSVs 139A-139E and vias 181.

[0069] like Figure 22 As shown in the cross-sectional view 2200, a mask 2201 can be formed and used to pattern the conductive layer 2101 to form conductive lines 180. Some conductive lines 180 can couple vias 181 to TSV139A. Other conductive lines 180 can couple TSV139B-139E to contact pads or other structures on the back side 195. Etching can include wet etching, dry etching, reactive ion etching (RIE), some other etching processes, combinations thereof, etc. Additional processing forms ILD layers 169 and 171 and contact pads 175A-175D to provide, for example, Figure 1A The structure of IC device 100A. After etching, mask 2291 can be peeled off.

[0070] Figures 23-29 It is shown Figures 10-22 A series of cross-sectional views of the process variation. In this variation, gap 191A is formed after TSV 139A-139E. Forming gap 191A after TSV 139A-139E avoids contamination.

[0071] The change begins with the formation of an opening 1701 in the conductive layer 165. For example... Figure 23 As shown in the cross-sectional view 2300, an opening 1701 is formed and the back electrode 185A is patterned, while a gap 191A is formed simultaneously, as shown. Figure 17 The cross-sectional view is shown in Figure 1700.

[0072] like Figure 24 As shown in the cross-sectional view 2400, the change continues by filling the opening 1701 with dielectric 179, followed by etching the TSV opening 1901 and the via opening 2001, as... Figure 25 The cross-sectional view is shown in Figure 2500. Figure 26 As shown in the cross-sectional view 2600, conductive material is deposited to fill the via opening 2001 to form via 181, to fill the TSV opening 1901 to form TSV 139A-139E, and to form a conductive layer 2101. Figure 27As shown in the cross-sectional view 2700, the conductive layer 2101 can then be patterned to form conductive lines 180.

[0073] like Figure 28 As shown in the cross-sectional view 2800, a mask 2801 can then be formed and used to etch the gap 191A in the back electrode 185A. After etching, the mask 2801 can be peeled off. Figure 29 As shown in cross-sectional view 2900, gap 191A can then be filled with dielectric 183. Dielectric 183 can be the same as or different from dielectric 179. Excess dielectric 183 can be removed by a planarization process, such as CMP, stopping on conductive lines 180. When using this variation, ILD layer 169 can have the same composition as the dielectric 183 filling gap 191A.

[0074] Figures 30-34 It is shown Figures 10-22 A series of cross-sectional views of another variation in the process. In this variation, the back electrode 185A is formed by an inlay process, thereby avoiding the etching of the conductive layer 165.

[0075] like Figure 30 As shown in cross-sectional view 3000, an etch stop layer 3003 and a dielectric layer 3001 may be deposited over the insulating layer 163. The etch stop layer 3003 is optional. In some embodiments, the etch stop layer 3003 is a nitride (e.g., SiN), a carbide (e.g., SiC), an oxide oxynitride (e.g., SiON), an oxide carbon (e.g., SiOC), or combinations thereof. The dielectric layer 3001 is a material that fills the gap 191A of the dielectric 183.

[0076] like Figure 31 As shown in the cross-sectional view 3100, a mask 3101 can be formed and used to pattern the dielectric layer 3001 to form openings 3103 to provide a mold for the back electrode 185A, and additional openings 3105 can be formed at other locations where the conductive layer 165 is required. Forming openings 3103 and 3105 may include etching, with an etch stop layer 3003 providing endpoints for them.

[0077] like Figure 32 As shown in cross-sectional view 3200, mask 3101 can be peeled off and conductive material deposited to fill openings 3103 and 3105. Any excess conductive material can be removed by a planarization process such as CMP. The conductive material filling opening 3103 forms the back electrode 185A, and the conductive material filling opening 3105 forms the remainder of conductive layer 165.

[0078] like Figure 33As shown in the cross-sectional view 3300, an ILD layer 167 can then be formed and patterned with through-hole openings 2001. (See figure 3300) Figure 34 The cross-sectional view is shown in Figure 3400, and then the TSV opening 1901 can be etched. As shown... Figures 26 to 29 As shown in cross-sectional views 2600-2900, further processing can proceed. In the resulting IC device, an etch stop layer 3003 can be disposed between the back electrode 185A and the insulating layer 163.

[0079] Figure 35 A flowchart of process 3500, which can be used to form an IC device according to this disclosure, is presented. Although... Figure 35 The process 3500 is shown and described herein as a series of actions or events; however, it should be understood that the order in which these actions or events are shown should not be construed as limiting. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all of the shown actions may be required to implement one or more aspects or embodiments described herein, and one or more of the actions depicted herein may be performed in one or more separate actions and / or phases.

[0080] Process 3500 can begin with action 3501, which forms the DTI structure, and action 3503, which forms the lightly doped trap. Figure 10 Cross-sectional view 1000 provides an example of the resulting structure. The process continues to action 3505, forming the STI structure. Figure 11 Cross-sectional Figure 1100 provides an example of the resulting structure. Action 3507 is the formation of a moderately doped well. Figure 12 Cross-sectional view 1200 provides an example of the resulting structure.

[0081] Action 3509 forms the gate on the front side. Action 3511 forms a heavily doped contact region. These processes are performed by... Figure 13 The cross-sectional view 1300 is shown. Action 3513 is to form a metal interconnect structure on the front side. Figure 14 Cross-sectional Figure 1400 provides an example of the resulting structure. Action 3515 thins the substrate down to the device layer. Figure 15 Cross-sectional view 1500 provides an example of the resulting structure.

[0082] Action 3517 is to form an isolation layer on the back side. Action 3519 is to form a conductive layer on the isolation layer. Action 3521 is to form an ILD layer on the conductive layer. Figure 16 Cross-sectional view 1600 provides an example of the resulting structure.

[0083] Action 3523 is to pattern the back conductive layer. This patterning defines a back electrode from the back conductive layer. In some embodiments, this patterning also forms openings in the back electrode. This patterning may also provide openings in the back conductive layer to allow channels of the TSV to pass through the back conductive layer without contacting it. Figure 17 Cross-sectional view 1700 provides an example of the resulting structure.

[0084] Action 3525 is to fill the opening in the back conductive layer with dielectric. Figure 18 Cross-sectional view 1800 provides an example of the resulting structure. Action 3527 is the formation of the TSV opening. Figure 19 Cross-sectional view 1900 provides an example of the resulting structure. Action 3529 is the formation of an opening for connecting to a through-hole on the back electrode. Figure 20 Cross-sectional view 2000 provides an example of the resulting structure. Action 3531 is the deposition of metal to form the TSV, back electrode via, and back metal layer. Figure 21 Cross-sectional view 2100 provides an example of the resulting structure.

[0085] Action 3533 is patterned back metal. Patterned metal forms connections between the back electrode vias and some TSVs, can form connections between other TSVs and other structures on the back, and can further interconnect structures on the back. Figure 22 Cross-sectional view 2200 provides an example of the resulting structure. Action 3535 is the formation of the back contact and related structure. Figure 1A An example of the resulting structure is provided.

[0086] Figure 36 The flowchart of process 3600 is presented. Process 3600 is... Figure 35 A variation of process 3500 can be used to form similar IC devices. In this variation, the opening in the back electrode is formed after the TSV.

[0087] Process 3600 includes many of the same actions as process 3500. The change begins with action 3601, which patterns the back conductive layer. Action 3601 is similar to action 3523, except that action 3601 does not include etching openings in the back electrode. Figure 23 Cross-sectional view 2300 provides an example of the resulting structure.

[0088] The next change occurs in action 3603, which is to pattern the openings in the back electrode. In process 3600, action 3603 follows action 3533, where the back metal is patterned. Figure 28 Cross-sectional view 2800 provides an example of the resulting structure.

[0089] Process 3600 continues with operation 3605, filling the opening in the back electrode with dielectric, and operation 3607, CMP to remove excess dielectric. Figure 29 Cross-sectional view 2900 provides an example of the resulting structure. The back contact can then be formed as in process 3500.

[0090] Figure 37 The flowchart of process 3700 is presented. Process 3700 is... Figure 35 Another variation of process 3500, which can also be used to form similar IC devices, involves forming the back electrode and its opening using a mosaic process.

[0091] Process 3700 includes many of the same operations as process 3500. A variation can begin with operation 3701, which forms an etch stop layer on the isolation layer. This operation is optional if an etch stop layer is not required. Operation 3703 is the formation of a dielectric fill layer, which is a dielectric filling the openings in the back electrode. Figure 30 Cross-sectional view 3000 provides an example of the resulting structure. Action 3705: Patterning the dielectric fill layer. Figure 31 Cross-sectional view 3100 provides an example of the resulting structure.

[0092] Action 3707 is the deposition of conductive material for the back electrode. Action 3709 is chemical mechanical polishing, which removes any conductive material deposited outside the openings in the dielectric fill layer. Figure 32 Cross-sectional view 3200 provides an example of the resulting structure.

[0093] This process can continue as in process 3500. Optionally, in action 3529, etching the electrode contact holes precedes action 3527, etching the holes for the TSV. This process sequence is as follows: Figure 33 and Figure 34 Cross-sectional views 3300 and 3400 are shown.

[0094] Some aspects of this disclosure relate to an IC device including a semiconductor body having a front side and a back side. A high-voltage variable disk (HVSD) is disposed on the front side. A conductive layer and an insulating layer are disposed on the back side. The insulating layer is located between the conductive layer and the semiconductor body. An electrode is formed directly beneath the HVSD. The electrode has a gap directly beneath the HVSD. In some embodiments, a first portion of the electrode is on a first side of the gap, and a second portion of the electrode is on a second side of the gap, the second side of the gap being opposite to the first side of the gap. In some embodiments, the first and second portions are combined. In some embodiments, the gap is longer than the HVSD.

[0095] In some embodiments, the region of the electrode directly beneath the HVSD is larger than the region of the gap directly beneath the HVSD. In some embodiments, the gap has a shape corresponding to the shape of the source region, drain region, gate electrode, or a channel that is part of the HVSD and is on the front side. In some embodiments, the HVSD has source and drain regions that extend in a lateral direction relative to the source-to-drain direction, and the gap also extends in a lateral direction. In some embodiments, the gap has a width that is 1 to 10 times the thickness of the insulating layer. In some embodiments, the gap is one of a plurality of gaps in the electrode directly beneath the HVSD. In some embodiments, the HVSD is a transistor. In some embodiments, the gap is directly beneath the source region, drain region, or gate electrode of the transistor. In some embodiments, the gap is directly beneath the PN junction of the transistor.

[0096] Some aspects of this disclosure relate to an IC device including a semiconductor body. A plurality of high-voltage devices are formed within the semiconductor body and have berths beneath the semiconductor body. An insulating layer is present beneath the semiconductor body, and one or more electrodes are present beneath the insulating layer. The one or more electrodes extend beyond a portion of each berth, but not entirely, and have a repeating pattern within each berth. In some embodiments, the pattern includes a gap surrounded by one of the one or more electrodes. In some embodiments, each of the one or more electrodes is entirely within the periphery of a deep trench isolation structure surrounding one of the plurality of high-voltage devices. In some embodiments, each of the one or more electrodes has a pair of sidewalls separated by a dielectric and directly beneath one of the plurality of high-voltage devices. In some embodiments, the electrodes are longer than the high-voltage devices.

[0097] Some aspects of this disclosure relate to a method comprising forming a high-voltage semiconductor device (HVSD) on a front side of a semiconductor body and forming an insulating layer and a conductive layer on a back side of the semiconductor body. The insulating layer is located between the conductive layer and the semiconductor body. The conductive layer is etched to define an electrode directly beneath the HVSD and an opening in the electrode. The opening is directly beneath the HVSD. In some embodiments, the method further comprises forming a metal interconnect structure on the front side of the semiconductor body, forming through-substrate vias, and connecting the electrode to the metal interconnect structure through the through-substrate vias. In some embodiments, the method further comprises biasing electrodes to increase the breakdown voltage of the HVSD.

[0098] According to one embodiment of this application, an integrated circuit device is provided, comprising: a semiconductor body including a front side and a back side; a high voltage semiconductor device (HVSD) formed in the front side; and a conductive layer and an insulating layer on the back side, wherein the insulating layer is between the conductive layer and the semiconductor body; wherein the conductive layer is formed on an electrode directly beneath the high voltage semiconductor device; and the electrode having a gap directly beneath the high voltage semiconductor device. In some embodiments, a first portion of the electrode is on a first side of the gap; and a second portion of the electrode is on a second side of the gap, the second side of the gap being opposite to the first side of the gap. In some embodiments, the first portion and the second portion are combined. In some embodiments, the gap is longer than the high voltage semiconductor device. In some embodiments, the region of the electrode directly beneath the high voltage semiconductor device is larger than the region of the gap directly beneath the high voltage semiconductor device. In some embodiments, the shape of the gap corresponds to the shape of a source region, a drain region, a gate electrode, or a channel that is part of the high voltage semiconductor device and is on the front side. In some embodiments, the high voltage semiconductor device has a source region and a drain region that extend in a lateral direction relative to the source-to-drain direction; and the gap extends in the lateral direction. In some embodiments, the width of the gap is 1 to 10 times the thickness of the insulating layer. In some embodiments, the gap is one of a plurality of gaps in the electrode directly beneath the high-voltage semiconductor device. In some embodiments, the high-voltage semiconductor device is a transistor. In some embodiments, the gap is directly beneath the source region, drain region, or gate electrode of the transistor. In some embodiments, the gap is directly beneath the PN junction of the transistor.

[0099] According to another embodiment of this application, an integrated circuit device is provided, comprising: a semiconductor body; a plurality of high-voltage devices formed in the semiconductor body; an insulating layer beneath the semiconductor body; and one or more electrodes in a layer beneath the insulating layer; wherein each of the plurality of high-voltage devices has a berth beneath the semiconductor body; the one or more electrodes are formed in a repeating pattern within each berth; and the pattern has gaps within each berth. In some embodiments, each gap is surrounded by one of the one or more electrodes. In some embodiments, each of the plurality of high-voltage devices is surrounded by a identifiable deep trench isolation structure; and each of the one or more electrodes is entirely within the outer periphery of one of the deep trench isolation structures. In some embodiments, each of the one or more electrodes has a pair of sidewalls separated by a dielectric and within one of the berths. In some embodiments, the electrodes are longer than the high-voltage devices.

[0100] According to another embodiment of this application, a method for forming an integrated circuit device is provided, comprising: forming a high-voltage semiconductor device (HVSD) on the front side of a semiconductor body; forming an insulating layer and a conductive layer on the back side of the semiconductor body, wherein the insulating layer is between the conductive layer and the semiconductor body; and etching the conductive layer to define an electrode directly beneath the high-voltage semiconductor device and an opening in the electrode; wherein the opening is directly beneath the high-voltage semiconductor device. In some embodiments, the method for forming the integrated circuit device further comprises: forming a metal interconnect structure on the front side of the semiconductor body; forming a through-substrate via; and connecting the electrode to the metal interconnect structure through the through-substrate via. In some embodiments, the method for forming the integrated circuit device further comprises biasing the electrode to increase the breakdown voltage of the high-voltage semiconductor device.

[0101] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a base to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit device, comprising: The semiconductor body includes the front and back sides; A high-voltage semiconductor device (HVSD) is formed in the front side; as well as A conductive layer and an insulating layer are provided on the back side, wherein the insulating layer is located between the conductive layer and the semiconductor body. The conductive layer is formed as a continuous electrode directly beneath the high-voltage semiconductor device; and The continuous electrode has a gap directly below the high-voltage semiconductor device.

2. The integrated circuit device according to claim 1, wherein... The first portion of the continuous electrode is on the first side of the gap; and The second portion of the continuous electrode is on the second side of the gap, which is opposite to the first side of the gap.

3. The integrated circuit device according to claim 2, wherein, The first part and the second part are combined.

4. The integrated circuit device according to claim 1, wherein, The gap is longer than the high-voltage semiconductor device.

5. The integrated circuit device according to claim 1, wherein, The region of the continuous electrode directly beneath the high-voltage semiconductor device is larger than the region of the gap directly beneath the high-voltage semiconductor device.

6. The integrated circuit device according to claim 1, wherein, The shape of the gap corresponds to the source region, drain region, gate electrode, or the shape of a channel that is part of the high-voltage semiconductor device and is on the front side.

7. The integrated circuit device according to claim 1, wherein: The high-voltage semiconductor device has a source region and a drain region, which extend in a lateral direction relative to the source-to-drain direction; and The gap extends in the lateral direction.

8. The integrated circuit device according to claim 1, wherein, The width of the gap is 1 to 10 times the thickness of the insulating layer.

9. The integrated circuit device according to claim 1, wherein, The gap is one of a plurality of gaps in the continuous electrodes located directly below the high-voltage semiconductor device.

10. The integrated circuit device according to claim 1, wherein, The high-voltage semiconductor device is a transistor.

11. The integrated circuit device according to claim 10, wherein, The gap is directly below the source region, drain region, or gate electrode of the transistor.

12. The integrated circuit device according to claim 10, wherein, The gap is directly below the PN junction of the transistor.

13. An integrated circuit device, comprising: Semiconductor body; Multiple high-voltage devices are formed within the semiconductor body; An insulating layer is located beneath the semiconductor body. as well as One or more electrodes in the layer beneath the insulating layer; Each of the plurality of high-voltage devices has a space below the semiconductor body; The one or more electrodes are formed as a continuous electrode beneath each of the high-voltage devices, the continuous electrode forming a repeating pattern within the corresponding occupancy; and The pattern of the continuous electrode has a gap located directly below the corresponding high-voltage device within each occupancy.

14. The integrated circuit device of claim 13, wherein each of the gaps is surrounded by one of the one or more electrodes.

15. The integrated circuit device according to claim 13, wherein: Each of the plurality of high-voltage devices is surrounded by a identifiable deep trench isolation structure; and Each of the one or more electrodes is completely within the outer periphery of one of the deep trench isolation structures.

16. The integrated circuit device according to claim 13, wherein, Each of the one or more electrodes has a pair of sidewalls separated by a dielectric and located within one of the berths of the berth.

17. The integrated circuit device of claim 13, wherein the electrode is longer than the high-voltage device.

18. A method for forming an integrated circuit device, comprising: High voltage semiconductor device (HVSD) is formed on the front side of the semiconductor body. as well as An insulating layer and a conductive layer are formed on the back side of the semiconductor body, wherein the insulating layer is between the conductive layer and the semiconductor body; and The conductive layer is etched to define a continuous electrode directly beneath the high-voltage semiconductor device and an opening in the continuous electrode. The opening is located directly below the high-voltage semiconductor device.

19. The method of claim 18, further comprising: A metal interconnect structure is formed on the front side of the semiconductor body; Forming through-substrate vias; as well as The electrode is connected to the metal interconnect structure through the through-substrate via.

20. The method of claim 18, further comprising biasing the electrode to increase the breakdown voltage of the high-voltage semiconductor device.

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