Method of erase operation for three-dimensional memory

Abstract

The application provides a method for erasing a three-dimensional memory, which increases the erasing speed of electrons in a charge capturing layer of different side channel structures through a double-side erasing mode, and avoids the problem of a decrease in on-current by doping N-type ions in a channel connecting layer connecting the two side channel structures.

Description

[0001] This invention is a divisional application of Chinese patent application filed on January 21, 2021, with application number 202110081844.3 and title "Erase Operation Method for Three-Dimensional Memory". Technical Field

[0002] This invention relates to the field of semiconductors, and in particular to an erasure operation method for a three-dimensional memory. Background Technology

[0003] With the development of semiconductor technology, the feature size of semiconductor devices is shrinking and the integration density is increasing. Since the manufacturing process of two-dimensional memory has approached its physical limits and it is difficult to further increase its storage cell density, three-dimensional memory flash memory has emerged. It stacks storage cells in a three-dimensional manner, which not only solves the problems of high cost and low reliability of two-dimensional memory, but also brings greater storage capacity to memory.

[0004] However, as the number of stacked layers in a 3D memory increases, in addition to the high aspect ratio of the channel structure affecting the functionality of the 3D memory, solving the high aspect ratio problem of the channel structure may also affect the erasure operation of the 3D memory, such as incomplete data erasure or slower erasure speed, especially when the number of stacked layers increases. Therefore, it is necessary to provide an erasure operation method for 3D memory to solve the problems existing in the prior art.

[0005] Public content

[0006] The purpose of this invention is to provide an erasure operation method for a three-dimensional memory to solve the problems of the prior art.

[0007] To achieve the above objectives, a first aspect of the present invention provides an erasure operation method for a three-dimensional memory, the three-dimensional memory comprising:

[0008] Substrate, including doped regions implanted with ions;

[0009] The first stacked layer includes a plurality of first insulating layers and a plurality of first gate electrodes that are stacked alternately on the substrate along a first direction perpendicular to the substrate;

[0010] A first channel structure extends through the first stacked layer to the doped region along the first direction and has a first channel layer;

[0011] A connecting insulating layer is disposed on the first stacked layer and contains a channel connecting layer;

[0012] The second stacked layer includes a plurality of second insulating layers and a plurality of second gate electrodes that are alternately stacked on the connection insulating layer along the first direction; and

[0013] The second channel structure extends through the second stacked layer to the channel connection layer along the first direction, and has a second channel layer and a drain electrode located at the top of the second channel structure. The second channel layer is connected to the first channel layer through the channel connection layer.

[0014] The erasure operation method includes the following steps:

[0015] Provide a gate erase voltage to the plurality of first gate electrodes and the plurality of second gate electrodes; and

[0016] Simultaneously, a storage erase voltage is provided to the doped region and the drain electrode.

[0017] Furthermore, the width of the channel connection layer along a second direction parallel to the substrate is a first width, the width of the top surface of the first channel structure along the second direction is a second width, and the first width is not less than the second width.

[0018] Furthermore, the ion is a P-type ion, and the doped region is a P-well.

[0019] Furthermore, the channel connection layer is implanted with N-type ions.

[0020] Furthermore, the doping concentration of the N-type ions is no higher than 10. 20 (cm -3 ).

[0021] Furthermore, the first channel structure includes an epitaxial layer located at the bottom of the first channel structure, and a first functional layer and a first channel layer sequentially disposed on the epitaxial layer and along the sidewall of the first channel structure toward the center of the first channel structure. The second channel structure includes a second functional layer and a second channel layer sequentially disposed on the channel connection layer and along the sidewall of the second channel structure toward the center of the second channel structure. The drain electrode is connected to the second functional layer and the second channel layer.

[0022] Further, the first stacked layer includes a first sub-stacked layer, a second sub-stacked layer, and a sub-connection insulating layer disposed between the first sub-stacked layer and the second sub-stacked layer. The first channel structure includes a first sub-channel structure and a second sub-channel structure. The first sub-channel structure penetrates the first sub-stacked layer along the first direction to the doped region. The second sub-channel structure penetrates the second sub-stacked layer along the first direction to the first sub-channel structure. The first sub-stacked layer is connected to the second sub-stacked layer at the sub-connection insulating layer.

[0023] Furthermore, the first sub-channel structure includes the epitaxial layer located at the bottom of the first sub-channel structure, and a first sub-functional layer and a first sub-channel layer sequentially disposed on the epitaxial layer and along the sidewall of the first sub-channel structure toward the center of the first sub-channel structure. The second sub-channel structure includes a second sub-functional layer and a second sub-channel layer sequentially disposed along the sidewall of the second sub-channel structure toward the center of the second sub-channel structure. The first sub-functional layer is connected to the second functional layer through the sub-connection insulation layer, and the first sub-channel layer is connected to the second channel layer through the sub-connection insulation layer.

[0024] Further, the plurality of second gate electrodes includes a top selection transistor gate electrode located at the topmost layer of the plurality of second gate electrodes, and the erase operation method includes the following steps:

[0025] Set the gate electrode of the top selection transistor to a floating state.

[0026] Furthermore, before performing the erase operation, the potential of the gate electrode of the top selection transistor is 0 volts.

[0027] Furthermore, the three-dimensional memory also includes a plurality of dummy gate electrodes located among the plurality of first gate electrodes and the plurality of second gate electrodes, and the erase operation method includes the following steps:

[0028] A ground voltage is provided to the plurality of dummy gate electrodes.

[0029] Furthermore, the gate erase voltage is the ground voltage.

[0030] This invention increases the speed of electron erasure in the first and second charge-capturing layers by employing a bilateral erasure method. Simultaneously, it allows for the doping of N-type ions in the channel interconnect layer, preventing a decrease in the conduction current of the second semiconductor channel. Therefore, this invention demonstrates high industrial applicability and significant inventiveness. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a three-dimensional memory according to a first embodiment of the present invention.

[0032] Figure 2 for Figure 1 A magnified view of a portion of the medium-thick dashed box E.

[0033] Figure 3 This is a schematic diagram of a three-dimensional memory according to a second embodiment of the present invention.

[0034] Figure 4 for Figure 3 A magnified view of a portion of the medium-thick dashed box R.

[0035] Figure 5 This is a schematic diagram of the erasure operation method of the three-dimensional memory according to the present invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention, and the term "embodiment" as used in this specification is intended to be an example, illustration, or illustration, and is not intended to limit the invention.

[0037] The present invention provides an erasure operation method, comprising: providing a ground voltage to a plurality of first gate electrodes and a plurality of second gate electrodes; simultaneously providing a storage erasure voltage to a doped region and a drain electrode; setting the gate electrode of a top selection transistor to a floating state; and providing a ground voltage to a plurality of dummy gate electrodes, and the method is particularly applicable to a three-dimensional memory with the structure described below.

[0038] Please refer to Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of a three-dimensional memory according to a first embodiment of the present invention. Figure 2 for Figure 1 A partially enlarged schematic diagram of the thick dashed box E. The three-dimensional memory includes a substrate 10, a first stacked layer 20, a first channel structure 50, a connecting insulating layer 30, a second stacked layer 40, and a second channel structure 60.

[0039] Furthermore, the substrate 10 may be a substrate made of semiconductor materials such as single-crystal silicon (Si), silicon germanium (SiGe), gallium arsenide (GaAs), silicon-on-insulator (SOI).

[0040] Furthermore, the substrate 10 includes a doped region 101 implanted with ions. The doped region 101 extends from the top surface of the substrate 10 into the substrate 10, i.e., the top surface of the doped region 101 is aligned with the top surface of the substrate 10. When the three-dimensional memory is being erased, a storage erase voltage (described later) is applied to the doped region 101.

[0041] Further, the first stacked layer 20 is provided with a plurality of first insulating layers 21 and a plurality of first gate electrodes 22 staggeredly stacked on the substrate 10 along a first direction Y perpendicular to the substrate 10; the first channel structure 50 extends through the first stacked layer 20 to the doped region 101 along the first direction Y. Specifically, an initial stacked layer (not shown) is first formed on the substrate 10, the initial stacked layer having a plurality of pairs of the plurality of first insulating layers 21 and a plurality of sacrificial layers (not shown) staggeredly stacked along the first direction Y. The plurality of first insulating layers 21 includes a gate oxide layer (not shown) formed at the bottom layer and a protective oxide layer (not shown) formed at the top layer. The plurality of first insulating layers 21 and the plurality of sacrificial layers are staggered in the first direction Y, that is, each first insulating layer 21 is between two sacrificial layers, and each sacrificial layer is between two first insulating layers 21. The number of the plurality of first insulating layers 21 and the plurality of sacrificial layers can be stacked as needed to form the number of pairs of memory cells in the three-dimensional memory. The materials of the plurality of first insulating layers 21 include, but are not limited to, silicon oxide (SiOx), and the materials of the plurality of sacrificial layers include, but are not limited to, silicon nitride (SiNx). The plurality of first insulating layers 21 and the plurality of sacrificial layers can be formed by one or more thin film deposition processes, including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0042] Furthermore, after the initial stacked layer is formed on the substrate 10, a first channel structure 50 extending through the initial stacked layer to the doped region 101 is formed by semiconductor processes such as development and etching. The first channel structure 50 includes an epitaxial layer 501 located at the bottom of the first channel structure 50, and a first functional layer 502 and a first channel layer 503 sequentially disposed on the epitaxial layer 501 and along the sidewalls of the first channel structure 50 towards the center of the first channel structure 50. The first functional layer 502 sequentially comprises a first barrier layer 5021, a first charge trapping layer 5022, and a first tunnel layer 5023 along the sidewalls of the first channel structure 50 towards the center of the first channel structure 50. The first channel layer 503 sequentially comprises a first semiconductor channel 5031 and a first dielectric layer 5032 along the sidewalls of the first tunnel layer 5023 towards the center of the first channel structure 50. In this embodiment, the epitaxial layer 501 can be made of silicon semiconductor material (e.g., monocrystalline silicon or polycrystalline silicon), the first barrier layer 5021 can be made of silicon oxide, silicon oxynitride, high-k dielectric constant material, or any combination thereof, the first charge trapping layer 5022 can be made of silicon nitride, silicon oxide, silicon, or any combination thereof, the first tunnel layer 5023 can be made of silicon oxide, silicon nitride, or any combination thereof, the first semiconductor channel 5031 is filled with silicon semiconductor material (e.g., monocrystalline silicon or polycrystalline silicon), and the first dielectric layer 5032 can be made of silicon oxide. In another embodiment, the first barrier layer 5021, the first charge trapping layer 5022, and the first tunnel layer 5023 can form a composite film of silicon oxide / silicon oxynitride / silicon oxide (ONO). Next, the plurality of sacrificial layers are removed by using a gate gap (not shown) combined with dry etching and / or wet etching to form the gate filling region, and then the material of the plurality of first gate electrodes 22 (e.g., tungsten metal) is deposited to form the first stacked layer 20. Specifically, the surface silicon oxide formed on the plurality of sacrificial layers can be removed first using an aqueous hydrofluoric acid solution, and then the plurality of sacrificial layers made of silicon nitride can be removed using hot phosphoric acid to form the gate filling region. It is understood that the accompanying drawings of this invention use a few logarithmic representations of the plurality of first insulating layers 21 / the plurality of first gate electrodes 22 for illustrative purposes only and should not be construed as limiting the invention.

[0043] Furthermore, to increase the storage capacity of 3D memory, the stacked layers are typically thickened. However, when the stacked layer is too thick, the aspect ratio of the channel structure becomes extremely high, thus affecting the storage function of the 3D memory. To avoid this technical problem, the present invention forms a second stacked layer 40 by providing a connection insulating layer 30 containing a channel connection layer 31 on the first stacked layer 40, and by alternately stacking multiple second insulating layers 41 and multiple second gate electrodes 42 on the connection insulating layer 30 along the first direction Y. At the same time, a second channel structure 60 is formed along the first direction Y, penetrating the second stacked layer 40 to the channel connection layer 31. By using such a multiple deck, both the first channel structure 50 and the second channel structure 60 can maintain a considerable aspect ratio. It should be noted that during the formation of the second channel structure 60, the alignment mark on the wafer used to fabricate the three-dimensional memory may receive a poor alignment signal due to the relatively thick thickness of the first stacked layer 20, reducing the accuracy of the direct connection between the first semiconductor channel 5031 and the second semiconductor channel 6021 (in the absence of the channel connection layer 31). Therefore, to increase the connection accuracy between the first semiconductor channel 5031 and the second semiconductor channel 6021, this invention uses the channel connection layer 31 to connect the first semiconductor channel 5031 and the second semiconductor channel 6021. The width of the channel connection layer 31 along the second direction X parallel to the substrate 10 is a first width W1, and the width of the top surface of the first channel structure 50 along the second direction X is a second width W2. The first width W1 is not less than the second width W2. In this way, the second semiconductor channel 6021 has a larger buffer to connect with the first semiconductor channel 5031, reducing the risk of misalignment. The material of the channel connection layer 31 is polycrystalline silicon. The plurality of second gate electrodes 42 includes a top selection transistor gate electrode 421 located at the topmost layer of the plurality of second gate electrodes 42.

[0044] Further, the second channel structure 60 includes a second functional layer 601 and a second channel layer 602 sequentially disposed on the channel connection layer 31 and along the sidewall of the second channel structure 60 toward the center of the second channel structure 60, and a drain electrode 603 located at the top of the second channel structure 60, wherein the drain electrode 603 is connected to the second channel layer 602. The side of the channel connection layer 31 facing the substrate 10 is connected to the first functional layer 502 and the first channel layer 503, and the other side is connected to the second functional layer 601 and the second channel layer 602. The steps for forming the second channel structure 60 can be referred to the above description of forming the first channel structure 50, and will not be repeated here.

[0045] Furthermore, the second functional layer 602 is provided with a second barrier layer 6011, a second charge trapping layer 6012, and a second tunnel layer 6013 sequentially disposed along the sidewall of the second channel structure 60 towards the center of the second channel structure 60. The second channel layer 602 is provided with a second semiconductor channel 6021 and a second dielectric layer 6022 sequentially disposed along the sidewall of the second tunnel layer 6013 towards the center of the second channel structure 60. The material of the second barrier layer 6011 may include silicon oxide, silicon oxynitride, high dielectric constant (high-k) material, or any combination thereof. The material of the second charge trapping layer 6012 may include silicon nitride, silicon oxide, silicon, or any combination thereof. The material of the second tunnel layer 6013 may include silicon oxide, silicon nitride, or any combination thereof. The second semiconductor channel 6021 is filled with silicon semiconductor material (e.g., monocrystalline silicon or polycrystalline silicon). The material of the second dielectric layer 6022 may include silicon oxide. In another embodiment, the second barrier layer 6011, the second charge trapping layer 6012, and the second tunnel layer 6013 may form a composite film of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0046] In one embodiment, the three-dimensional memory further includes a plurality of dummy gate electrodes (not shown) located among the plurality of first gate electrodes 22 and the plurality of second gate electrodes 42.

[0047] Please refer to Figure 3 and Figure 4 , Figure 3 This is a schematic diagram of a three-dimensional memory according to a second embodiment of the present invention. Figure 4 for Figure 3A partially enlarged schematic diagram of the medium-thick dashed box R. The second embodiment of the present invention preferably proposes a three-dimensional memory with a first channel structure 50 having a lower aspect ratio compared to the first embodiment. The difference between the second embodiment and the first embodiment is that the first stacked layer 20 includes a first sub-stacked layer 201, a second sub-stacked layer 202, and a sub-connection insulating layer 203 disposed between the first sub-stacked layer 201 and the second sub-stacked layer 202; the first channel structure 50 includes a first sub-channel structure 51 and a second sub-channel structure 52. The first sub-channel structure 50 extends through the first sub-stacked layer 201 to the doped region 101 along the first direction Y, and includes the epitaxial layer 501 located at the bottom of the first sub-channel structure 51, and a first sub-functional layer 511 and a first sub-channel layer 512 sequentially disposed on the epitaxial layer 501 and along the sidewall of the first sub-channel structure 51 toward the center of the first sub-channel structure 51; the second sub-channel structure 52 extends through the second sub-stacked layer 202 to the first sub-channel structure 51 along the first direction Y, and includes a second sub-functional layer 521 and a second sub-channel layer 522 sequentially disposed along the sidewall of the second sub-channel structure 52 toward the center of the second sub-channel structure 52. The first sub-functional layer 511 has a first sub-barrier layer 5111, a first sub-charge trapping layer 5112, and a first sub-tunneling layer 5113 sequentially disposed along the sidewall of the first sub-channel structure 51 towards the center of the first sub-channel structure 51. The second sub-functional layer 521 has a second sub-barrier layer 5211, a second sub-charge trapping layer 5212, and a second sub-tunneling layer 5213 sequentially disposed along the sidewall of the second sub-channel structure 52 towards the center of the second sub-channel structure 52. The first sub-channel layer 512 has a first sub-semiconductor channel 5121 and a first sub-dielectric layer 5122 sequentially disposed along the sidewall of the first sub-tunneling layer 5113 towards the center of the first sub-channel structure 51. The second sub-channel layer 522 has a second sub-tunneling layer 5213 sequentially disposed along the sidewall of the first sub-tunneling layer 5113 towards the center of the first sub-channel structure 51. A second sub-semiconductor channel 5221 and a second sub-dielectric layer 5222 are sequentially disposed on the sidewall of 13 toward the center of the second sub-channel structure 52. That is, the first barrier layer 5021 includes the first sub-barrier layer 5111 and the second sub-barrier layer 5211, the first charge trapping layer 5022 includes the first sub-charge trapping layer 5112 and the second sub-charge trapping layer 5212, the first tunnel layer 5023 includes the first sub-tunnel layer 5113 and the second sub-tunnel layer 5213, the first semiconductor channel 5031 includes the first sub-semiconductor channel 5121 and the second sub-semiconductor channel 5221, and the first dielectric layer 5032 includes the first sub-dielectric layer 5112 and the second sub-dielectric layer 5222.The first sub-functional layer 511 is connected to the sub-connection insulating layer 203 and the second sub-functional layer 521. The first sub-channel structure 512 is connected to the sub-connection insulating layer 203 and the second sub-channel structure 522. That is, the first sub-barrier layer 5111 is connected to the sub-connection insulating layer 203 and the second sub-barrier layer 5211. The first sub-charge trapping layer 5112 is connected to the sub-connection insulating layer 203 and the second sub-charge trapping layer 5212. The first sub-tunnel layer 5113 is connected to the sub-connection insulating layer 203 and the second sub-tunnel layer 5213. The first sub-semiconductor channel 5121 is connected to the sub-connection insulating layer 203 and the second sub-semiconductor channel 5221. The first sub-dielectric layer 5122 is connected to the sub-connection insulating layer 203 and the second sub-dielectric layer 5222. The second sub-barrier layer 5211, the second sub-charge trapping layer 5212, the second sub-tunnel layer 5213, the second sub-semiconductor channel 5221, and the second sub-dielectric layer 5222 are connected to the channel connection layer 31. The steps for forming the first sub-channel structure 51 and the second sub-channel structure 52 can be referred to the description of forming the first channel structure 50 above, and will not be repeated here.

[0048] Furthermore, the materials of the first sub-barrier layer 5111 and the second sub-barrier layer 5211 may include silicon oxide, silicon oxynitride, high-k dielectric constant (high-k) materials, or any combination thereof; the materials of the first sub-charge trapping layer 5112 and the second sub-charge trapping layer 5212 may include silicon nitride, silicon oxide, silicon, or any combination thereof; the materials of the first sub-tunnel layer 5113 and the second sub-tunnel layer 5213 may include silicon oxide, silicon nitride, or any combination thereof; the first sub-semiconductor channel 5121 and the second sub-semiconductor channel 5221 are filled with silicon semiconductor materials (e.g., single-crystal silicon or polycrystalline silicon); and the materials of the first sub-dielectric layer 5112 and the second sub-dielectric layer 5222 may include silicon oxide. In another embodiment, the first sub-barrier layer 5111, the first sub-charge trapping layer 5112, and the first sub-tunneling layer 5113 can form a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite film, and the second sub-barrier layer 521, the second sub-charge trapping layer 5212, and the second sub-tunneling layer 5213 can form a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite film. This invention forms the first sub-channel structure 51 and the second sub-channel structure 52 in the form of multiple decks, ensuring that both the first sub-channel structure 51 and the second sub-channel structure 52 maintain a considerable aspect ratio, thus guaranteeing the storage function of the three-dimensional memory.

[0049] In this invention, when the erasure method according to the embodiment of the invention is applied to the various types of three-dimensional memory described above, electrons used for storing data in the first charge trapping layer 5022 are released or recombine, and electrons in the second charge trapping layer 6012 are released or recombine. Specifically, when a storage erase voltage is applied to the doped region 101, the first gate electrode 22 and the second gate electrode 42 are grounded or connected to a zero-volt operating voltage, and the drain electrode 603 is in a floating state, holes in the doped region 101 can enter the first semiconductor channel 5031 from the doped region 101 and enter the second semiconductor channel 6021 through the channel connection layer 31, so that the first semiconductor channel 5031 and the second semiconductor channel 6021 have a higher potential than the first gate electrode 22 and the second gate electrode 42. This potential can cause the electrons used for storing data in the first charge trapping layer 5022 and the second charge trapping layer 6012 to produce a tunneling effect. The electrons in the doped region 101 can also be injected into the first semiconductor channel 5031 and the second semiconductor channel 6021 by gaining sufficient energy based on the storage erase voltage, and generate a tunneling effect that allows the holes to enter the first charge trapping layer 5022 and the second charge trapping layer 6012 and recombine with the electrons used to store data therein, thereby realizing the erasure operation of the three-dimensional memory. It should be noted that the three-dimensional memory also includes a bit line (not shown) connected to the drain electrode 603. Applying a bias voltage (e.g., the memory erase voltage) to the drain electrode 603 means applying a bias voltage to the bit line. If the doped region 101 is a high-voltage P-type well (HVPW), that is, the ions are P-type ions (e.g., boron ions), then since the majority carriers of the high-voltage P-type well are holes, it is advantageous to perform the erase operation on the three-dimensional memory (e.g., reduce the value of the memory erase voltage).

[0050] Combination Figure 5The diagram shows a potential schematic of the erase operation method for a three-dimensional memory according to the present invention. The inventors discovered that the channel connection layer 31 causes a decrease in the conduction current of the second semiconductor channel 6021. Therefore, the present invention preferably implants a second ion, which is an N-type ion (e.g., a phosphorus ion), into the channel connection layer 31, and the doping concentration can be no higher than 10. 20 (cm -3 The doping concentration is preferably 10. 20 (cm -3The channel interconnect layer 31, implanted with N-type ions, provides sufficient electrons to the second semiconductor channel 6021 to prevent a decrease in its conduction current. However, the N-type ion implantation in the channel interconnect layer 31 affects the erasure operation of the second semiconductor channel 6021 on the second charge trapping layer 6012. This is because the majority carriers of the N-type ion implanted channel interconnect layer 31 are electrons, which are different from the holes required for the erasure operation. As a result, the number of holes implanted in the second semiconductor channel 6021 is reduced, thereby lowering the potential of the second semiconductor channel 6021 during the erasure operation and slowing down the erasure operation on the second charge trapping layer 6012. Therefore, the inventors further propose a method for performing an erase operation in the three-dimensional memory, comprising the following steps: providing a gate erase voltage to the plurality of first gate electrodes 22 and the plurality of second gate electrodes 42 (preferably, the gate erase voltage is a ground voltage); providing a storage erase voltage Vers to the doped region 101 and the drain electrode 603; setting the top select transistor gate electrode 421 to a floating state; and providing a ground voltage to the plurality of dummy gate electrodes.Specifically, the first charge trapping layer 5022 can erase electrons in the first charge trapping layer 5022 by applying the storage erase voltage Vers to the doped region 101 and connecting a zero-volt operating voltage (or ground) to the first gate electrode 22 (and / or at least a portion of the plurality of dummy gate electrodes). (Hole in the doped region 101 can enter the first semiconductor channel 5031 from the doped region 101, giving the first semiconductor channel 5031 a higher potential relative to the first gate electrode 22. This potential can cause the electrons in the first charge trapping layer 5022 used for storing data to undergo a tunneling effect, crossing the quantum barrier of the first tunnel layer 5023 and directly tunneling through the first tunnel layer 5023 to the first semiconductor channel 5031, thereby releasing the electrons in the first charge trapping layer 5022 used for storing data.) Meanwhile, the second charge trapping layer 601... 2. The electron erasure operation in the second charge trapping layer 6012 can be performed by applying the storage erase voltage Vers to the drain electrode 603, setting the top select transistor gate electrode 421 to a floating state, and connecting a zero-volt operating voltage (or ground) to the second gate electrode 42 (and / or at least a portion of the plurality of dummy gate electrodes). (Hole in the drain electrode 603 can enter the second semiconductor channel 6021 from the drain electrode 603, giving the second semiconductor channel 6021 a higher potential relative to the second gate electrode 42. This potential can cause the electrons used to store data in the second charge trapping layer 6012 to tunnel across the quantum barrier of the second tunnel layer 6013 and directly tunnel through the second tunnel layer 6013 to the second semiconductor channel 6021, thereby releasing the electrons used to store data in the second charge trapping layer 6012.) It should be noted that during the erase operation, the top select transistor gate electrode 421 is set to a floating state, so that the potential of the top select transistor gate electrode 421 increases (or decreases) as the potential of the second semiconductor channel 6021 increases (or decreases), thus suppressing the release of electrons from the second charge trapping layer 6012 for erasure. Furthermore, before performing the erase operation, the top select transistor gate electrode 421 is set to 0 volts. At this time, a potential difference is formed between the potential of the top select transistor gate electrode 421 and the potential of the second semiconductor channel 6021, causing the release of electrons from the second charge trapping layer 6012 for erasure.

[0051] Based on the above, the present invention increases the speed of the electron erasure operation in the first charge trapping layer 5022 and the second charge trapping layer 6012 by means of bilateral erasure, and can also dope the channel connection layer 31 with N-type ions to avoid the problem of the decrease in the conduction current of the second semiconductor channel 6021.

[0052] Although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A method for erasing a three-dimensional memory, characterized in that, The three-dimensional memory includes: Semiconductor layer containing doped regions; A first stacked layer, located on the semiconductor layer, includes a plurality of first gate electrodes spaced apart along a first direction perpendicular to the semiconductor layer; A first channel structure extends through the first stacked layer and is electrically connected to the doped region; The second stacked layer is located on the first stacked layer and includes a plurality of second gate electrodes spaced apart along the first direction; The second channel structure extends through the second stacked layer; The drain electrode is electrically connected to the second channel structure; The top selection transistor gate electrode is located above the plurality of second gate electrodes; An insulating layer is provided between the first stacked layer and the second stacked layer; The erasure operation method includes the following steps: Provide a gate erase voltage to the plurality of first gate electrodes and the plurality of second gate electrodes; and Provide a storage erase voltage to the doped region; Provide a storage erase voltage to the drain electrode; Set the gate electrode of the top selection transistor to a floating state.

2. The method according to claim 1, characterized in that: The doped region is a P-well.

3. The method according to claim 1, characterized in that: The three-dimensional memory includes a channel connection layer located within the connection insulating layer, the channel connection layer being implanted with N-type ions.

4. The method according to claim 3, characterized in that: The doping concentration of the N-type ions is no higher than 10. 20 cm -3 .

5. The method according to claim 1, characterized in that: The first stacked layer includes a first sub-stacked layer, a second sub-stacked layer, and a sub-connection insulating layer disposed between the first sub-stacked layer and the second sub-stacked layer; The first channel structure includes a first sub-channel structure and a second sub-channel structure. The first sub-channel structure penetrates the first sub-stack layer and is electrically connected to the doped region. The second sub-channel structure penetrates the second sub-stack layer and is electrically connected to the first sub-channel structure.

6. The method according to claim 1, characterized in that: During the erase operation, the voltage application phase on the gate electrode of the top-select transistor includes a first phase and a second phase following the first phase; the erase operation method includes the following steps: In the first stage, the voltage of the gate electrode of the top selection transistor is ground voltage; In the second stage, the gate electrode of the top selection transistor is made to float, and the voltage on the gate electrode of the top selection transistor is a first voltage, which is greater than the ground voltage.

7. The method according to claim 6, characterized in that: The pulse of the storage erase voltage of the drain electrode begins to rise in the first phase, and the pulse of the first voltage begins to rise in the second phase.

8. The method according to claim 1, characterized in that: The gate erase voltage is the ground voltage.

9. The method according to claim 1, characterized in that: The three-dimensional memory also includes a bit line connected to the drain electrode; Providing a storage erase voltage to the drain electrode includes: The bit line is used to provide a storage erase voltage to the drain electrode.

10. A three-dimensional memory, characterized in that, The three-dimensional memory includes: a memory cell array and peripheral circuitry coupled to the memory cell array; wherein, The storage cell array includes: Semiconductor layer containing doped regions; A first stacked layer, located on the semiconductor layer, includes a plurality of first gate electrodes spaced apart along a first direction perpendicular to the semiconductor layer; A first channel structure extends through the first stacked layer and into the doped region; The second stacked layer is located on the first stacked layer and includes a plurality of second gate electrodes spaced apart along the first direction; The second channel structure extends through the second stacked layer; The drain electrode is located at the top of the second channel structure; The top selection transistor gate electrode is located above the plurality of second gate electrodes; An insulating layer is provided between the first stacked layer and the second stacked layer; The peripheral circuit is configured as follows: During the erase operation, a gate erase voltage is provided to the plurality of first gate electrodes and the plurality of second gate electrodes; and Provide a storage erase voltage to the doped region; Provide a storage erase voltage to the drain electrode; Set the gate electrode of the top selection transistor to a floating state.

11. The three-dimensional memory according to claim 10, characterized in that: During the erase operation, the voltage application phase on the gate electrode of the top select transistor includes a first phase and a second phase; The peripheral circuit is configured as follows: In the first stage, the voltage of the gate electrode of the top selection transistor is ground voltage; In the second stage, the gate electrode of the top selection transistor is made to float, and the voltage on the gate electrode of the top selection transistor is a first voltage, which is greater than the ground voltage.

12. The three-dimensional memory according to claim 11, characterized in that: The pulse of the first voltage rises after the pulse of the storage erase voltage of the drain electrode rises.

13. The three-dimensional memory according to claim 10, characterized in that: The gate erase voltage is the ground voltage.

14. The three-dimensional memory according to claim 10, characterized in that: The three-dimensional memory also includes a bit line connected to the drain electrode; The peripheral circuitry is configured to provide a storage erase voltage to the drain electrode using the bit line.

15. The three-dimensional memory according to claim 10, characterized in that: The doped region is a P-well.

16. The three-dimensional memory according to claim 10, characterized in that: The three-dimensional memory includes a channel interconnect layer located within the interconnect insulating layer, and the channel interconnect layer is N-type doped.

17. The three-dimensional memory according to claim 16, characterized in that: The doping concentration of the channel interconnect layer is no higher than 10. 20 cm -3 .

18. The three-dimensional memory according to claim 10, characterized in that: The first stacked layer includes a first sub-stacked layer, a second sub-stacked layer, and a sub-connection insulating layer disposed between the first sub-stacked layer and the second sub-stacked layer; The first channel structure includes a first sub-channel structure and a second sub-channel structure; the first sub-channel structure penetrates the first sub-stacked layer and is electrically connected to the doped region; the second sub-channel structure penetrates the second sub-stacked layer and is electrically connected to the first sub-channel structure.

19. An erasing operation method for a three-dimensional memory, characterized in that, The three-dimensional memory includes: Semiconductor layer containing doped regions; A stacked layer, located on the semiconductor layer, includes a plurality of gate electrodes spaced apart along a first direction perpendicular to the semiconductor layer; A channel structure that penetrates the stacked layers and is electrically connected to the doped region; The top-selected transistor gate electrode is located above multiple gate electrodes; The erasure operation method includes: Provide a gate erase voltage to the plurality of gate electrodes; and Provide a storage erase voltage to the doped region; A voltage is provided to the gate electrode of the top selection transistor, the voltage on the gate electrode of the top selection transistor including a first-stage voltage and a second-stage voltage; In the first stage, the voltage of the gate electrode of the top selection transistor is ground voltage; In the second stage, the gate electrode of the top select transistor is made to float, and the voltage on the gate electrode of the top select transistor is a first voltage, which is less than the storage erase voltage.

20. The method according to claim 19, characterized in that: The three-dimensional memory also includes a drain electrode located above the channel structure; during an erase operation, a storage erase voltage is provided to the drain electrode.

21. The method according to claim 20, characterized in that: It also includes a bit line connected to the drain electrode; The bit line is used to provide a storage erase voltage to the drain electrode.

22. The method according to claim 21, characterized in that: The pulse of the storage erase voltage of the drain electrode begins to rise in the first phase, and the pulse of the first voltage begins to rise in the second phase.

23. The method according to claim 19, characterized in that: The stacked layer includes: A first stacked layer, located on the semiconductor layer, includes a plurality of first gate electrodes spaced apart along a first direction perpendicular to the semiconductor layer; A first channel structure extends through the first stacked layer and is electrically connected to the doped region; The second stacked layer is located on the first stacked layer and includes a plurality of second gate electrodes spaced apart along the first direction; The second channel structure extends through the second stacked layer; The three-dimensional memory further includes a connection insulating layer disposed between the first stacked layer and the second stacked layer.

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