Electronic devices including blocks of different memory cells and related methods and systems

Abstract

This application relates to an electronic device comprising blocks having different memory cells in a first and a second block, and related methods and systems. The memory cells in the first and second blocks include memory pillars extending through the stack. Each memory pillar includes a charge-blocking material laterally adjacent to the stack, a storage nitride material laterally adjacent to the charge-blocking material, a tunneling dielectric material laterally adjacent to the storage nitride material, a channel material laterally adjacent to the tunneling dielectric material, and a filling material between opposite sides of the channel material. One or more of the storage nitride material and the tunneling dielectric material in the first block differ in thickness or material composition from one or more of the storage nitride material and the tunneling dielectric material in the second block. Additional electronic devices are disclosed, as well as methods and related systems for forming such electronic devices.

Description

[0001] Priority Claim

[0002] This application claims the benefit of U.S. Patent Application No. 17 / 301,915, filed April 19, 2021, entitled "Electronic Devices Comprising Blocks With Different Memory Cells, and Related Methods and Systems," the entire disclosure of which is hereby incorporated herein by reference. Technical Field

[0003] The embodiments disclosed herein relate to electronic devices and the manufacture of electronic devices. More specifically, embodiments of this disclosure relate to electronic devices including blocks having memory cells configured to exhibit different electrical properties on a single die, as well as related methods and systems. Background Technology

[0004] Designers of electronic devices (e.g., semiconductor devices, memory devices) typically aim to increase the integration or density of features (e.g., components) within electronic devices by reducing the size of individual features and the spacing between adjacent features. Electronic device designers also aim to design architectures that are not only compact but also offer performance advantages and simplified designs. Reducing feature size and spacing places increasingly higher demands on the methods used to form electronic devices. One solution is to form three-dimensional (3D) electronic devices, such as 3D NAND devices, where memory cells are vertically stacked on a substrate.

[0005] A 3D NAND device may contain single-level cell (SLC) blocks that store one bit of data and multi-level cell (MLC) blocks that store multiple bits per cell. MLC blocks may contain three-level cell (TLC) blocks or four-level cell (QLC) blocks. A single 3D NAND device contains SLC and MLC blocks on a single die, with both SLC and MLC blocks residing in the same memory array. SLC blocks are used for short-term data storage, while MLC blocks are used for long-term data storage. Data is written to SLC blocks, accumulated, and programmed into MLC blocks. Because all data passes through SLC blocks, the number of programming and erasing (e.g., cycling) operations on SLC blocks is several orders of magnitude greater than that on MLC blocks. Therefore, SLC blocks have more stringent requirements for durability and data retention properties than MLC blocks, requiring higher cycle life and endurance. SLC and MLC blocks also have different reliability requirements because the electronic data in MLC blocks is more densely packed than in SLC blocks, and the electronic system can use SLC and MLC blocks at different frequencies. However, achieving the desired property balance between SLC blocks and MLC blocks is difficult because improving one property often adversely affects the other. Summary of the Invention

[0006] An electronic device is disclosed. The electronic device includes a first block and a second block comprising an array of memory cells. The memory cells in the first block and the second block include memory pillars extending through a stack of alternating dielectric and conductive materials. Each memory pillar includes a charge-blocking material laterally adjacent to the stack, a storage nitride material laterally adjacent to the charge-blocking material, a tunneling dielectric material laterally adjacent to the storage nitride material, a channel material laterally adjacent to the tunneling dielectric material, and a filling material between opposite sides of the channel material. One or more of the storage nitride material and the tunneling dielectric material in the first block differ in thickness or material composition from one or more of the storage nitride material and the tunneling dielectric material in the second block.

[0007] Another electronic device is disclosed, comprising a memory array of a single die, the memory array including a first block and a second block laterally adjacent to the first block. The memory cells of the first block are configured to exhibit different electrical properties relative to the memory cells of the second block. The first block includes pillar regions comprising memory pillars extending through a stack of layers. Each of the memory pillars includes a charge-blocking material between the layers and a storage nitride material, the storage nitride material between the charge-blocking material and a tunneling dielectric material, and a tunneling dielectric material between the storage nitride material and a channel material. One or more of the storage nitride material and the tunneling dielectric material of the second block exhibit a greater thickness than one or more of the storage nitride material or the tunneling dielectric material of the first block.

[0008] A method for forming an electronic device is disclosed. The method includes forming pillar openings in a stack comprising a first block and a second block laterally adjacent to the first block. A charge blocking material and a storage nitride material are formed in the pillar openings of the first and second blocks. A mask material is formed over the second block, and a portion of the storage nitride material of the first block is removed. The mask material is removed from the second block. A tunneling dielectric material is formed adjacent to the storage nitride material of the first and second blocks. A channel material is formed adjacent to the tunneling dielectric material of the first and second blocks, and a filler material is formed between opposing portions of the channel material.

[0009] Another method for forming an electronic device is disclosed. The method includes forming pillar openings in a stack comprising a first block and a second block. A charge-blocking material, a storage nitride material, and a tunneling dielectric material are formed in the pillar openings of the first and second blocks. A portion of the tunneling dielectric material is oxidized to form an oxidized portion of the tunneling dielectric material. A mask material is formed over the second block. A portion of the oxidized portion of the tunneling dielectric material is removed from the first block. A channel material is formed adjacent to the tunneling dielectric material of the first and second blocks. A filler material is formed between opposing portions of the channel material.

[0010] A system is also disclosed. The system includes: a processor operatively coupled to input and output devices; and one or more electronic devices operatively coupled to the processor. The one or more electronic devices include memory cells in a first and a second block of a single die. The memory cells include memory pillars containing cell material. One or more of the storage nitride material or tunneling dielectric material of the cell material in the first block differs in thickness from the storage nitride material or the tunneling dielectric material of the second block. Attached Figure Description

[0011] Figure 1 This is a cross-sectional view of an electronic device comprising different memory cells in different blocks of a single die, according to embodiments of the present disclosure;

[0012] Figure 2 An electronic device comprising different memory units in different blocks of a single die, according to embodiments of the present disclosure;

[0013] Figure 3-9 This describes the formation according to embodiments of the present disclosure. Figure 1 A cross-sectional view of an electronic device;

[0014] Figure 10-14 This describes the formation according to embodiments of the present disclosure. Figure 2 A cross-sectional view of an electronic device;

[0015] Figure 15 These are partial, cross-sectional, perspective, and schematic diagrams of a device comprising one or more electronic devices according to embodiments of the present disclosure;

[0016] Figure 16 This is a functional block diagram of a memory array including one or more electronic devices according to embodiments of the present disclosure; and

[0017] Figure 17 This is a simplified block diagram of a system comprising one or more electronic devices according to embodiments of the present disclosure. Detailed Implementation

[0018] Disclosed are electronic devices (e.g., apparatuses, semiconductor devices, memory devices) that contain different memory cells in different (e.g., separate) blocks of a single die. The die (e.g., an integrated circuit) contains different memory cells in first and second blocks. The memory cells in the different blocks differ in the thickness of a particular cell material, in the composition of a particular cell material, or in both the thickness and composition of a particular cell material. The cell material that differs between blocks of a single die may be one or more of charge-blocking materials, storage nitride materials, or tunneling dielectric materials. The differences in the properties (e.g., thickness, composition) of the cell materials in the first and second blocks of the electronic device allow the memory cells in the first and second blocks to exhibit different electrical properties during use and operation of the electronic device. For example, one or more of the charge-blocking material, storage nitride material, or tunneling dielectric material of the memory cells may differ in thickness between the first and second blocks of the electronic device. Alternatively, the memory cells may differ in the thickness and material composition of a particular cell material (e.g., one or more of charge-blocking materials, storage nitride materials, or tunneling dielectric materials) in the first and second blocks of the electronic device. Individual dies containing different memory cells in the first and second blocks of an electronic device can exhibit different electrical properties of the memory cells in the first and second blocks. The first and second blocks of the electronic device can be configured to exhibit different electrical properties to achieve the desired overall electrical properties of the dies of the electronic device containing different memory cells.

[0019] A method for forming an electronic device is also disclosed. This involves forming a first block and a second block of the electronic device that contain different memory cells, the memory cells in the first block and the second block exhibiting different electrical properties, such as cycling or reliability properties. The first block and the second block are exposed to different process conditions to form different memory cells in the first block and the second block on a single die. The method for forming an electronic device according to embodiments of this disclosure produces different memory cells without adding complex process steps to the overall formation of the electronic device. The method for forming an electronic device is also compatible with conventional process steps, thereby enabling cost-effective manufacturing of the electronic device.

[0020] The following description provides specific details, such as material type, material thickness, and process conditions, to provide a thorough description of the embodiments described herein. However, those skilled in the art will understand that the embodiments disclosed herein can be practiced without these specific details. In fact, the embodiments can be practiced in conjunction with conventional manufacturing techniques used in the semiconductor industry. Furthermore, the description provided herein does not constitute a complete description of an electronic device or a complete process flow for manufacturing an electronic device, and the structures described below do not constitute a complete electronic device. Only those process actions and structures necessary for understanding the embodiments described herein are described in detail below. Additional actions to form a complete electronic device can be performed using conventional techniques.

[0021] Unless otherwise indicated, the materials described herein can be formed using conventional techniques, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD) (including sputtering, evaporation, ionization PVD, and / or plasma-enhanced CVD), or epitaxial growth. Alternatively, the materials can be grown in situ. Depending on the specific material to be formed, those skilled in the art can choose the techniques used for depositing or growing the materials. Removal of the material can be accomplished using any suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor phase etching), ion milling, planarization (e.g., chemical mechanical planarization (CMP)), or other known methods, unless the context otherwise indicates.

[0022] The accompanying drawings presented herein are for illustrative purposes only and do not represent actual views of any particular material, component, structure, electronic device, or electronic system. Variations in the shapes depicted in the drawings are expected due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or areas illustrated, but rather include shape deviations, for example, due to manufacturing processes. For instance, an area illustrated or described as box-shaped may have rough and / or non-linear characteristics, and an area illustrated or described as circular may contain some rough and / or linear characteristics. Furthermore, illustrated acute angles may be rounded, and vice versa. Therefore, the areas illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the areas and do not limit the scope of the claims. The drawings are not necessarily drawn to scale. Additionally, elements common to each figure may retain the same numerical names.

[0023] As used herein, the singular forms “a,” “one,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0024] As used in this document, “and / or” includes any and all combinations of one or more of the associated listed items.

[0025] As used herein, “about” or “approximate” with respect to a particular parameter includes the value and the degree of deviation from the value within acceptable tolerances for the particular parameter, as would be understood by one of ordinary skill in the art. For example, “about” or “approximate” with respect to a value may include an additional value within the range of 90.0% to 110.0% of the value, such as within the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0026] As used herein, for ease of description, spatially related terms such as “below,” “under,” “bottom,” “top,” “above,” “upper,” “front,” “back,” “left,” “right,” etc., may be used to describe the relationship of one element or feature to another element(s), as illustrated in the figures. Unless otherwise specified, spatially related terms are intended to cover different orientations of material in addition to the orientation depicted in the figures. For example, if the material in the figures were inverted, an element described as “below other elements or features,” “below other elements or features,” “under other elements or features,” or “on the bottom of other elements or features” would be oriented as “above other elements or features” or “on the top of other elements or features.” Thus, the term “below” can cover both orientations of “above” and “below”, depending on the context in which the term is used, which will be obvious to those skilled in the art. The material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped) and the spatially related descriptive terms used herein shall be interpreted accordingly.

[0027] As used herein, the term "block" refers to and includes a number of memory columns in an electronic device that are configured to be programmable and erasable at specific times. The electronic device comprises an array of memory columns in repeating blocks. The memory columns in each block of the electronic device are programmable at different times during the use and operation of the electronic device. The number of memory columns in each block can be on the order of thousands or more and is not limited to any particular number.

[0028] As used herein, the term "unit material" refers to and includes charge-blocking materials, storage nitride materials, or tunneling dielectric materials for pillar regions (e.g., memory pillar regions) of electronic devices. Pillar regions also include channel materials and filler materials.

[0029] As used herein, the term "conductive material" means and includes electrically conductive materials. Conductive materials may include, but are not limited to, one or more of doped polycrystalline silicon, undoped polycrystalline silicon, metals, alloys, conductive metal oxides, conductive metal nitrides, conductive metal silicides, and conductive doped semiconductor materials. For example only, conductive materials may be tungsten (W) or tungsten nitride (WN). y Nickel (Ni), Tantalum (Ta), Tantalum nitride (TaN) y ), Tantalum silicide (TaSi) x Platinum (Pt), Copper (Cu), Silver (Ag), Gold (Au), Aluminum (Al), Molybdenum (Mo), Titanium (Ti), Titanium Nitride (TiN) y Titanium silicide (TiSi) x ), titanium silicon nitride (TiSi) x N y ), titanium aluminum nitride (TiAl) x N y ), molybdenum nitride (MoN) x ), Iridium (Ir), Iridium oxide (IrO2), Ruthenium (Ru), Ruthenium oxide (RuO2) z One or more of the following: n-doped polycrystalline silicon, p-doped polycrystalline silicon, undoped polycrystalline silicon, and conductive doped silicon.

[0030] As used herein, the term “configured” means that the size, shape, material composition, and arrangement of one or more of at least one structure and at least one device facilitate the operation of one or more of the structure and device in a predetermined manner.

[0031] As used herein, the phrase “coupled to” refers to structures that are operatively connected to each other, such as by direct ohmic connection or by indirect connection (e.g., via another structure) and electrically connected.

[0032] As used herein, the term "dielectric material" means and includes electrically insulating materials. Dielectric materials may include, but are not limited to, one or more of insulating oxide materials or insulating nitride materials. Dielectric oxides may be oxide materials, metal oxide materials, or combinations thereof. Dielectric oxides may include, but are not limited to, silicon oxide (SiO₂). x Silica (SiO2) and doped SiO x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, tetraethyl orthosilicate (TEOS), alumina (AlO) x ), gadolinium oxide (GdO) x ), Hafnium oxide (HfO) x ), magnesium oxide (MgO) x ), niobium oxide (NbO) x ), tantalum oxide (TaO) x Titanium oxide (TiO)x Zirconium oxide (ZrO) x Hafnium silicate, dielectric oxynitride materials (e.g., SiO2), x N y ), dielectric carbonitride materials (e.g., SiO2) x C z N y ( ), or combinations thereof, or combinations of one or more of the listed materials with silicon oxide. Dielectric nitride materials may include, but are not limited to, silicon nitride.

[0033] As used herein, the term “different unit material” means and includes differences in thickness, composition, or thickness and composition between a particular unit material in one block and a unit material of the same type in another block.

[0034] As used herein, the term "different memory cell" refers to and includes memory cells in a separate block of an electronic device that differ in the thickness of the cell material, the composition of the cell material, or both. Different memory cells of an electronic device reside on a single die, a single integrated circuit, or a single memory array.

[0035] As used herein, the term "electronic device" includes, but is not limited to, memory devices and semiconductor devices that may or may not incorporate memory, such as logic devices, processor devices, or radio frequency (RF) devices. Furthermore, among other functions, electronic devices may incorporate memory, such as a so-called "system-on-a-chip" (SoC) that includes both a processor and memory, or an electronic device that includes both logic and memory. For example, an electronic device may be a 3D electronic device, such as a 3D NAND flash memory device.

[0036] As used herein, referring to an element as "on another element" or "above another element" means and includes that the element is directly on top of, adjacent to (e.g., laterally adjacent to, vertically adjacent to) another element, below another element, or in direct contact with another element. It also includes that the element is indirectly on top of, adjacent to (e.g., laterally adjacent to, vertically adjacent to) another element, below another element, or near another element, while other elements are present therein. In contrast, when an element is referred to as "directly on another element" or "directly adjacent to another element," there is no intervening element.

[0037] As used herein, the term "stack" means and includes the feature of having one or more materials that are vertically adjacent to each other. A stack may comprise alternating dielectric and conductive materials, such as alternating oxide and metallic materials or alternating oxide and polycrystalline silicon materials. Depending on the manufacturing stage of the electronic structure containing the stack, the stack may alternatively comprise alternating dielectric and nitride materials, such as alternating oxide and silicon nitride materials.

[0038] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes the degree to which a given parameter, property, or condition is satisfied with a certain degree of deviation, such as within acceptable manufacturing tolerances, as would be understood by one of ordinary skill in the art. For example, depending on the specific parameter, property, or condition that is substantially satisfied, it may be satisfied with at least 90.0%, at least 95.0%, at least 99.0%, or even at least 99.9%.

[0039] As used herein, the term "substrate" means and includes a material (e.g., a base material) or structure on which additional material is formed. A substrate can be an electronic substrate, a semiconductor substrate, a base semiconductor layer on a support structure, an electrode, an electronic substrate having one or more materials, layers, structures, or regions formed thereon, or a semiconductor substrate having one or more materials, layers, structures, or regions formed thereon. Materials on an electronic or semiconductor substrate may include, but are not limited to, semiconductive, insulating, and conductive materials. A substrate can be a conventional silicon substrate or other bulk substrate including layers of semiconductor material. As used herein, the term "bulk substrate" means not only including silicon wafers, but also silicon-on-insulator ("SOI") substrates, such as silicon-on-sapphire ("SOS") and silicon-on-glass ("SOG") substrates, silicon epitaxial layers on a base semiconductor substrate, and other semiconductor or optoelectronic materials, such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. Substrates can be doped or undoped.

[0040] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” refer to the principal plane of the structure and are not necessarily defined by the Earth’s gravitational field. A “horizontal” or “lateral” direction is substantially parallel to the principal plane of the structure, while a “vertical” or “longitudinal” direction is substantially perpendicular to the principal plane of the structure. The principal plane of the structure is defined by the surface of the structure that has a relatively large area compared to the other surfaces of the structure.

[0041] like Figure 1 and 2As shown, electronic devices 100, 100' according to embodiments of the present disclosure include memory cells 105, 105' configured to exhibit different electrical properties in a first block 110 and a second block 115 of the electronic devices 100, 100'. The difference in the properties of the cell materials in the first block 110 and the second block 115 enables the electronic devices 100, 100' to exhibit different durability and reliability properties in the first block 110 and the second block 115. The different electrical properties may be due to the cell film materials ( ) of the memory cells 105, 105' in the first block 110 and the second block 115. Figure 1 The different thicknesses of one or more of them or due to the unit film materials of memory cells 105, 105' in the first block 110 and the second block 115 Figure 2 The first block 110 and the second block 115 may be configured as single-level cell (SLC) blocks or multi-level cell (MLC) blocks (e.g., three-level cell (TLC), four-level cell (QLC)). In some embodiments, the first block 110 is configured as a TLC block and the second block 115 is configured as an SLC block. In other embodiments, the first block 110 is configured as a QLC block and the second block 115 is configured as an SLC block. Although Figure 1 and 2 The electronic devices 100 and 100' are described as having two blocks, but depending on the desired electrical properties of the electronic devices 100 and 100', there may be more than two blocks. The electronic devices 100 and 100' may also include combinations of SLC blocks, TLC blocks and QLC blocks.

[0042] For example, the thicknesses of the charge blocking material 160, the storage nitride material 120, or the tunneling dielectric material 125 may differ in the first block 110 and the second block 115 of the electronic device 100. The electronic device 100 may, for example, include a specific unit material in the first block 110 that is thinner (e.g., less thick) than that in the second block 115. For example, and as... Figure 1As shown herein, the storage nitride materials 120, 120′ of the unit material may differ in thickness (indicated by W1 and W2) between the first block 110 and the second block 115. Alternatively or additionally, the charge blocking material 160 or tunneling dielectric material 125 of the memory cell 105′ may differ in thickness between the first block 110 and the second block 115. Although the embodiments described and illustrated herein show that the first block 110 contains a particular unit material that is thinner than that in the second block 115, the electronic device 100 may, for example, contain a particular unit material that is thicker (e.g., more substantial) in the first block 110 than in the second block 115. The different relative thicknesses of the particular unit material in the first block 110 and the second block 115 refer to the average thickness of that unit material, because minute thickness variations may occur during the formation of the unit material due to process limitations in forming the particular unit material.

[0043] Different electrical properties may also be due to differences in material composition and the varying thicknesses of one or more of the unit materials in the first block 110 and the second block 115. For example, the material composition and thickness of the charge blocking material 160, the storage nitride material 120, or the tunneling dielectric material 125 may differ between the first block 110 and the second block 115. This is merely an example. Figure 2 As shown herein, the first block 110 and the second block 115 of the memory cell 105 may contain tunnel dielectric materials 125′, 125′a with different material compositions and thicknesses. Alternatively or additionally, the material composition and thickness of the charge blocking material 160 or the storage nitride material 120 of the memory cell 105 may differ between the first block 110 and the second block 115. Although the embodiments described and illustrated herein show the first block 110 containing cell materials exhibiting different material compositions and thicknesses, the electronic device 100′ may, for example, contain cell materials exhibiting different material compositions and thicknesses in the second block 115.

[0044] Alternating stacks 135 of dielectric material 145 and conductive material 140 define cell regions of electronic devices 100, 100', and the cell materials define pillar regions of electronic devices 100, 100'. The cell materials may include charge-blocking materials, storage nitride materials, tunneling dielectric materials, channel materials 165, and filler materials 170 of the pillar regions (e.g., memory pillar regions) of electronic devices 100, 100'. A pillar region of a first block 110 is adjacent (e.g., laterally adjacent) to a cell region of the first block 110, and a pillar region of a second block 115 is adjacent (e.g., laterally adjacent) to a cell region of the second block 115. Specific pillar regions are positioned between two cell regions, and specific cell regions are positioned between two pillar regions. The pillar regions include pillars 155, 155' of the cell material.

[0045] The charge blocking material 160 (also referred to as a blocking oxide material) may comprise, but is not limited to, silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, or combinations thereof. In some embodiments, the charge blocking material 160 is silicon dioxide. The storage nitride material 120 may comprise, but is not limited to, silicon nitride, silicon oxynitride, or combinations thereof. In some embodiments, the storage nitride material 120 is silicon nitride. The tunneling dielectric material 125 may comprise, but is not limited to, silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or combinations thereof. By way of example only, the tunneling dielectric material 125 may be a so-called "oxide-nitride-oxide" (ONO) structure (e.g., an interlayer silicon-based dielectric structure). In some embodiments, the tunneling dielectric material 125 is silicon nitride or silicon oxynitride. In other embodiments, the tunneling dielectric material 125 is silicon nitride and includes a silicon-rich portion. In still other embodiments, the tunneling dielectric material 125 is silicon oxynitride and includes a silicon-rich portion.

[0046] The first block 110 and the second block 115 of electronic devices 100 and 100' comprise a stack 135 of alternating conductive materials 140 and dielectric materials 145. The stack 135 comprises layers 150, each layer 150 comprising a single conductive material 140 and a single dielectric material 145. The stack 135 may comprise multiple layers of alternating layers of dielectric materials 145 and conductive materials 140, for example, greater than or equal to 50 layers 150, greater than or equal to 100 layers 150, greater than or equal to 200 layers 150, or greater than or equal to 500 layers 150. The pillars 155 (e.g., memory pillars) of memory cells 105 and 105' comprise a charge-blocking material 160, storage nitride materials 120 and 120', tunneling dielectric materials 125' and 125'a, a channel material 165, and a fill material 170. To simplify the accompanying drawings, only a few posts 155 in each of the first and second blocks 110 and 115 are shown, where the break line between the first 110 and the second block 115 indicates the possible presence of additional posts 155. Figure 1 As shown, charge blocking material 160 may be adjacent (e.g., laterally adjacent) to alternating conductive material 140 and dielectric material 145, storage nitride materials 120, 120' may be adjacent (e.g., laterally adjacent) to charge blocking material 160, and tunnel dielectric material 125 may be adjacent (e.g., laterally adjacent) to storage nitride materials 120, 120'. Figure 2 As shown, charge blocking material 160 may be adjacent to (e.g., laterally adjacent to) alternating conductive material 140 and dielectric material 145, storage nitride material 120 may be adjacent to (e.g., laterally adjacent to) charge blocking material 160, and tunnel dielectric materials 125′, 125′a may be adjacent to (e.g., laterally adjacent to) storage nitride materials 120, 120′.

[0047] exist Figure 1 and 2 In both cases, channel material 165 may be adjacent to (e.g., laterally adjacent to) tunnel dielectric material 125, and filler material 170 may be adjacent to (e.g., laterally adjacent to) channel material 165. Channel material 165 may comprise, but is not limited to, doped polysilicon, undoped polysilicon, or other channel materials. In some embodiments, the channel material is polysilicon. Charge blocking material, storage nitride material, and tunnel dielectric material extend together with the height of stack 135. Channel material 165 extends together with the height of stack 135. Filler material 170 may be a dielectric material, including, but not limited to, silicon dioxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, titanium dioxide, hafnium oxide, zirconium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, or combinations thereof. Filler material 170 may be recessed in stack 135, and conductive material 175 (e.g., plug material) may be adjacent to (e.g., vertically adjacent to) filler material 170. The cap material 180 may be adjacent to (e.g., vertically adjacent to) the stack 135 and the post 155. Although in Figure 1 and 2 The description states that, during subsequent process operations, the cap material 180 is removed to achieve the desired electrical connection between the post 155 and the overlying contact (not shown).

[0048] To form the electronic device 100, a stack 135' comprising alternating layers of dielectric material 145, layers of nitride material 305, and pillar openings 315 is formed, such as Figure 3 As shown in the diagram. The layered dielectric material 145 and the layered nitride material 305 are collectively referred to as layered dielectric material 310 and are formed using conventional techniques. The region of stack 135' corresponds to the first block 110 (e.g., an MLC block), and the region of stack 135' corresponds to the second block 115 (e.g., an SLC block). Pillar openings 315 are formed in the first block 110 and the second block 115 using conventional techniques, passing through the layered dielectric material 145 and the layered nitride material 305. The pillar openings 315 may be high aspect ratio openings extending through the layered dielectric material 310. Although in Figure 3 The text describes three column openings 315 in the first block 110 and two column openings 315 in the second block 115, but additional column openings 315 can be formed in the first block 110 and the second block 115.

[0049] A charge-blocking material 160 of the unit material is formed in the pillar opening 315. The charge-blocking material 160 can be formed on the sidewalls of the layered dielectric material 310 and the layered nitride material 305. The charge-blocking material 160 can be formed using conventional techniques, such as conformal deposition. In some embodiments, the charge-blocking material 160 is formed by ALD. The charge-blocking material 160 can be formed to a desired thickness such that a portion of the pillar opening 315 remains unfilled (e.g., open). In other words, only a portion of the pillar opening 315 is occupied by the charge-blocking material 160. The charge-blocking materials 160 of the first block 110 and the second block 115 can be formed to the same thickness. By way of example only, the charge-blocking material 160 can be formed to a thickness from about 5 nm to about 15 nm, such as from about 5 nm to about 10 nm, from about 7 nm to about 12 nm, or from about 6 nm to about 10 nm.

[0050] like Figure 4 As shown, a storage nitride material 120 is formed in the pillar opening 315 adjacent to (e.g., laterally adjacent to) the charge blocking material 160 and the upper surface of the stack 135. The storage nitride material 120 can be formed conformally on the sidewalls of the charge blocking material 160 and the upper surface of the stack 135. The storage nitride material 120 can be formed using conventional techniques. In some embodiments, the storage nitride material 120 is formed by an ALD (Alternating Discharge Damping). The storage nitride material 120 can be formed to a desired thickness indicated as W1. The thickness of the formed storage nitride material 120 can be substantially the same in the first block 110 and the second block 115. By way of example only, the formed storage nitride material 120 can be formed from a thickness of about 5 nm to about 15 nm, for example from about 7 nm to about 15 nm, from about 7 nm to about 12 nm, from about 8 nm to about 12 nm, or from about 6 nm to about 9 nm. Depending on the desired thickness of the storage nitride material 120, 120' in the first and second blocks 110, 115 of the electronic device 100, it may be optionally added before performing additional processing operations. Figure 4 The process stage shown removes (e.g., trims) a portion of the already formed storage nitride material 120 from the first and second blocks 110, 115. Optional portions of the already formed storage nitride material 120 can be removed using conventional techniques.

[0051] Next, a portion of the storage nitride material 120 in the first block 110 is removed, such as... Figure 5 and 6As shown, the storage nitride material 120′ of the first block 110 has a thickness W2 that is different from the thickness W1 of the storage nitride material 120 of the second block 115. The storage nitride material 120 of the second block 115 may, for example, be thicker than the storage nitride material 120′ of the first block 110. A mask 405 is formed over the second block 115 to protect the storage nitride material 120 of the second block 115, as shown. Figure 5 As shown in the diagram. Mask 405 can be used, for example, as a masking material, mask area, cap material, or cap area. Mask 405 can be formed from resist material or carbon material using conventional techniques. Mask 405 protects the unit material of the second block 115, while the storage nitride material 120 within the pillar opening 315 of the first block 110 is exposed to etch conditions for removing the desired portion of the storage nitride material 120', such as... Figure 6 As shown in the diagram. For example, the storage nitride material 120 of the first block 110 can be exposed to a wet etching process. The storage nitride material 120 of the first block 110 can be removed using conventional techniques, such as by exposing the storage nitride material 120 to a diluted HF solution or by using a vapor phase etching process. By adjusting one or more of the etching conditions—etcher concentration, temperature, flow rate, time, pressure, and dispersion method (immersion, spraying, etc.)—about 1 nm to about 4 nm of the storage nitride material 120 of the first block 110 can be removed. For example, about 1 nm to about 3 nm or about 2 nm to about 4 nm of the storage nitride material 120 can be removed to form storage nitride material 120′. Therefore, the storage nitride material 120′ of the first block 110 is thinner than the storage nitride material 120 of the second block 115. In other words, the thickness W2 of the storage nitride material 120′ is less than the thickness W1 of the storage nitride material 120. The thickness difference between the storage nitride material 120′ of the first block 110 and the storage nitride material 120 of the second block 115 can be, for example, between about 1 nm and about 3 nm. The thickness difference between the storage nitride material 120′ of the first block 110 and the storage nitride material 120 of the second block 115 can be easily adjusted by adjusting the process conditions of the wet etching process.

[0052] If in Figure 4 The process stage shown removes optional portions of the already formed storage nitride material 120. This removal can be performed using different etching chemicals than those used to form the storage nitride material 120'. For example, the optional removal of the storage nitride material 120 can be performed using a relatively fast and inexpensive wet etching process, while a slower, more controlled wet etching process can be used to form the storage nitride material 120'. For instance, a more controlled wet etching process can control the surface roughness of the storage nitride material 120'.

[0053] The remaining material of the removable mask 405 and the unit material that can be formed in the pillar opening 315, such as Figure 7 As shown in the diagram. Mask 405 can be removed using conventional techniques. A tunnel dielectric material 125 is formed in and adjacent to (e.g., laterally adjacent to) the stored nitride material 120 in the pillar opening 315, a channel material 165 is formed adjacent to (e.g., laterally adjacent to) the tunnel dielectric material 125, and a filler material 170' is formed adjacent to (e.g., laterally adjacent to) the channel material 165. The tunnel dielectric material 125 and the channel material 165 can be sequentially formed in and adjacent to the upper surface of the stack 135 (e.g., above the upper surface of the stack 135). The tunnel dielectric material 125 can be conformally formed on the sidewalls of the stored nitride material 120, and the channel material 165 can be conformally formed on the sidewalls of the tunnel dielectric material 125. The tunnel dielectric material 125 and the channel material 165 can be formed at a desired thickness. For example only, each of the tunneling dielectric material 125 and the channel material 165 can be formed with a thickness from about 5 nm to about 15 nm, such as from about 7 nm to about 15 nm, from about 7 nm to about 12 nm, from about 8 nm to about 12 nm, or from about 6 nm to about 9 nm. A filler material 170' is formed in the remaining portion of the pillar opening 315 and adjacent to the upper surface of the stack 135 (e.g., above the upper surface of the stack 135). The tunneling dielectric material 125, the channel material 165, and the filler material 170' can be formed using conventional techniques.

[0054] Remove a portion of the filler material 170', thereby causing the filler material 170 to be recessed in the column opening 315, as shown. Figure 8 As shown in the diagram. The filler material 170′ can be removed using conventional techniques, such as wet or vapor phase etching processes. The conductive material 175′ is formed in the pillar opening 315 and adjacent to the upper surface of the stack 135 (e.g., above the upper surface of the stack 135). The conductive material 175′ can be formed adjacent to (e.g., above the filler material 170) and on the sidewalls of the channel material 165. The conductive material 175′ can be, for example, polysilicon. For example, a portion of the conductive material 175′ and the unit material (e.g., tunnel dielectric material 125, channel material, storage nitride materials 120, 120′) can be removed from the upper surface of the stack 135 by a planarization process, such as... Figure 9 As shown in the diagram. Conductive material 175 can be used as a conductive plug above filler material 170. For example... Figure 6-9 As shown, the storage nitride materials 120 and 120′ exhibit different thicknesses in the first block 110 and the second block 115.

[0055] The layered nitride material 305 of the stack 135 can be removed and replaced with a layered conductive material 140 to form an electronic device 100 containing storage nitride materials 120, 120' of different thicknesses in the first block 110 and the second block 115, such as Figure 1 As shown in the diagram. The layer nitride material 305 is removed and replaced with a layer conductive material 140 by a so-called "replacement gate" process. A slit (not shown) is formed through the stack 135 and a wet etching process is performed to remove the layer nitride material 305 through the slit. The layer nitride material 305 can be removed by exposing the layer nitride material 305 to a wet etching process, such as a so-called "wet nitride stripping" process. The layer conductive material 140 is formed in the opening (not shown) formed by removing the layer nitride material 305. Optionally, a pad (not shown) can be formed in the opening before forming the layer conductive material 140. Thus, the alternating dielectric material 145 and the layer nitride material 305 are transformed into alternating dielectric material 145 and layer conductive material 140 of the electronic device 100. Therefore, the electronic device 100 ( Figure 1 The memory cells 105 and 105' with different thicknesses are contained in the first block 110 and the second block 115.

[0056] Because the first block 110 (e.g., an MLC block) contains a thinner storage nitride material 120' and the second block 115 (e.g., an SLC block) contains a thicker storage nitride material 120, the improved cycling and retention properties of the SLC block's memory cells 105 can be achieved relative to the MLC block's memory cells 105'. Therefore, memory cells 105, 105' can be tuned in the first block 110 and the second block 115 to achieve more stringent cycling and retention properties in the SLC block's memory cells 105 than in the MLC block's memory cells 105'. Different memory cells 105, 105' according to embodiments of the present disclosure are formed in the first block 110 and the second block 115 of a single die by exposing the first block 110 and the second block 115 to different process conditions. In contrast, conventional methods of forming memory cells expose memory cells in different blocks to the same process conditions.

[0057] Although the above process describes the formation of a thinner storage nitride material 120' in the first block 110 than the storage nitride material 120 in the second block 115, the relative thicknesses of the storage nitride materials 120 and 120' can be reversed, wherein the storage nitride material 120' in the first block 110 is thicker than the storage nitride material 120 in the second block 115. Additionally, more than one mask forming and mask removal operation can be performed to form additional storage nitride material 120 of different thicknesses in the blocks, for example, in the first and second blocks 110 and 115. For example, two or more mask forming and mask removal operations can be performed to form storage nitride material 120 of three or more thicknesses in different blocks of the electronic devices 100 and 100'. For example, if electronic devices 100, 100' comprise three different blocks, such as a first block 110, a second block 115, and a third block (not shown), then the thickness of the storage nitride material 120 in each of the blocks can be different by performing two or more mask forming and mask removal operations.

[0058] Alternatively, the different electrical properties may be due to differences in the material composition and thickness of one or more of the unit materials in the first block 110 and the second block 115. For example, the material composition and thickness of the charge blocking material 160, the storage nitride material 120, or the tunneling dielectric material 125 may differ in the electronic device 100'. Figure 2The first block 110 and the second block 115 may differ. The material composition may differ in the relative amounts (e.g., concentrations) of one or more of the elements (e.g., chemical elements) in the unit membrane material. For example only, the storage nitride material 120' of the first block 110 may contain a stoichiometric compound of said material, while the storage nitride material 120 of the second block 115 may similarly contain a stoichiometric compound of said material or a smaller stoichiometric compound of said material. For example only, if the tunneling dielectric materials 125' and 125'a are formed of silicon nitride or silicon oxynitride, then the tunneling dielectric materials 125' and 125'a may differ in silicon content. Alternatively, the material composition may differ, wherein different chemical elements may be present in the tunneling dielectric materials 125' and 125'a. For example only, the tunneling dielectric material 125' may contain silicon nitride and the tunneling dielectric material 125'a may contain silicon oxynitride. Alternatively, tunneling dielectric material 125′ may be a substantially homogeneous silicon nitride material or a substantially homogeneous silicon oxynitride material, while tunneling dielectric material 125′a may be a heterogeneous silicon nitride material or a heterogeneous silicon oxynitride material. The heterogeneous silicon nitride or heterogeneous silicon oxynitride of tunneling dielectric material 125′a may contain a portion that differs from tunneling dielectric material 125′ in the relative amount (e.g., concentration) of one or more of the elements (e.g., chemical elements). By way of example only, tunneling dielectric material 125′a may contain a thickness across one or more of the elements that comprises a gradient of one or more of the elements, or may contain a portion of one or more of the elements that has a different relative amount (e.g., concentration). In some embodiments, tunneling dielectric materials 125′, 125′a are silicon nitride or silicon oxynitride. In other embodiments, tunneling dielectric materials 125′, 125′a are silicon nitride or silicon oxynitride and further comprise an oxidized portion of silicon nitride or silicon oxynitride.

[0059] To form the electronic device 100', charge blocking material 160 and storage nitride material 120 of the first block 110 and the second block 115 are formed on the stack 135, as described above. Figure 3 and 4 As described. A tunnel dielectric material 125 may be formed adjacent to (e.g., laterally adjacent to) the storage nitride material 120, such as... Figure 10 As shown in the illustration. For example, a tunneling dielectric material 125 can be conformally formed above the sidewalls and upper surface of the stored nitride material 120. Figure 10In the process stages shown, each of the charge blocking material 160, storage nitride material 120, and tunneling dielectric material 125 exhibits substantially the same material composition in both the first block 110 and the second block 115, and each of the charge blocking material 160, storage nitride material 120, and tunneling dielectric material 125 exhibits substantially the same thickness in both the first block 110 and the second block 115. The materials used and the thickness of each of the charge blocking material 160, storage nitride material 120, and tunneling dielectric material 125 can be as described above for... Figure 3-7 As described.

[0060] An oxidation process is performed, during which the tunneling dielectric material 125 is exposed to an oxidized portion of the tunneling dielectric material 125, forming conditions such as... Figure 11A and 11B As shown in the diagram. The oxidation process may include, but is not limited to, free radical oxidation, steam oxidation, or water vapor oxidation. The oxidation process oxidizes the upper portions of the tunnel dielectric material 125 of the first and second blocks 110, 115 to a desired depth, thereby producing tunnel dielectric material 125'. For example, if the tunnel dielectric material 125 is formed of silicon oxynitride, then a portion of the tunnel dielectric material 125 is converted to silicon oxide by the oxidation process, thereby forming tunnel dielectric material 125' containing an upper portion of silicon oxide. Similarly, if the tunnel dielectric material 125 is formed of silicon nitride, then a portion of the tunnel dielectric material 125 is converted to silicon oxide by the oxidation process, thereby forming tunnel dielectric material 125' containing an upper portion of silicon oxide.

[0061] Following the oxidation process, the tunnel dielectric materials 125' of the first block 110 and the second block 115 exhibit the same material composition and the same thickness. By adjusting the oxidation conditions, the thickness of the oxidized portion of the tunnel dielectric material 125' can vary from about 1 nm to about 4 nm, for example, from about 1 nm to about 3 nm or from about 2 nm to about 4 nm. During the oxidation process, only a portion of the tunnel dielectric material 125' is oxidized, thereby controlling the thickness of the oxidized portion. Therefore, the tunnel dielectric material 125' can exhibit a heterogeneous composition over its entire thickness, wherein the oxidized portion contains a higher concentration of oxygen atoms than the underlying tunnel dielectric material 125 of the first block 110 and the tunnel dielectric material 125 of the second block 115. The oxidized portion (e.g., the oxygen-rich portion) exhibits a greater oxygen content (e.g., amount) relative to the oxygen content of the already formed tunnel dielectric material 125. By way of example only, the tunnel dielectric materials 125' of the first block 110 and the second block 115 may contain stoichiometric compounds of the material on which the oxidized portion of the tunnel dielectric material 125 is formed. For example, if the already formed tunnel dielectric material 125 is a silicon oxynitride material, then the ratio of silicon:oxygen:nitrogen atoms in the oxidized portion may differ from that of the already formed tunnel dielectric material 125′.

[0062] Optionally, a removal process can be performed to remove some or all of the oxidized portion of the tunnel dielectric material 125′. The removal process can be performed using conventional techniques. Then, and as... Figure 11A As shown, a mask 405 is formed adjacent to the second piece 115 (e.g., above the second piece 115), as described above for... Figure 5 As described, the charge blocking material 160, the storage nitride material 120, and the tunneling dielectric material 125' of the second block 115 are protected during subsequent process operations. The mask 405 can be formed from a resist material or a carbon material using conventional techniques. The mask 405 protects the unit material of the second block 115, while the tunneling dielectric material 125' within the pillar opening 315 of the first block 110 remains exposed. A removal process is performed to remove a portion of the tunneling dielectric material 125' of the first block 110, thereby creating tunneling dielectric material 125'a in the first block 110. For example, a portion of the oxide portion of the tunneling dielectric material 125' of the first block 110 can be removed. Therefore, the tunneling dielectric material 125'a of the first block 110 and the tunneling dielectric material 125' of the second block 115 differ in the thickness of the oxide portion 125b retained on the tunneling dielectric material 125'a. Figure 11B yes Figure 11A An enlarged view of the framed area, showing the tunneling dielectric material 125′a containing the oxide portion 125b on the tunneling dielectric material 125′. For simplicity, the figures are shown below. Figure 11BOnly the oxidized portion 125b of the tunnel dielectric material 125′a in the first block 110 is shown. The oxidized portion 125b of the tunnel dielectric material 125′a in the first block 110 has a thickness that is reduced relative to the thickness of the oxidized portion of the tunnel dielectric material 125′ in the second block 115. As a process stage, the tunnel dielectric materials 125′a in the first block 110 and 125′ in the second block 115 differ in relative thickness, wherein the thickness of the tunnel dielectric material 125′ is greater than that of the tunnel dielectric material 125′a. The tunnel dielectric materials 125′ and 125′a in the first and second blocks 110 and 115 can exhibit substantially the same material composition and differ only in thickness at this process stage, with the oxidized portion 125b being the main difference between the first and second blocks.

[0063] Optionally, one or more oxidation processes can then be performed to produce tunnel dielectric materials 125' and 125'a that differ in both thickness and material composition. Additional oxidation processes may produce tunnel dielectric materials 125' and 125'a with different material compositions. Therefore, the first and second blocks 110, 115 may comprise tunnel dielectric materials 125' and 125'a that differ in both thickness and material composition. Depending on the desired thickness and material composition of the tunnel dielectric materials 125' and 125'a, the mask 405 may be removed before or after the optional oxidation processes. The mask 405 can be removed using conventional techniques. Therefore, the first and second blocks 110, 115 may comprise tunnel dielectric materials 125' and 125'a that differ in thickness, material composition, or both thickness and material composition. Due to the different oxidation and removal processes in the first block 110 and the second block 115, the oxidized portion 125b of the tunnel dielectric material 125′a may contain a higher quality material (e.g., exhibiting fewer defects) than the oxidized portion of the tunnel dielectric material 125′. The tunnel dielectric materials 125′a and 125′ may exhibit heterogeneous composition across their entire thickness, with the oxidized portion exhibiting a higher oxygen atom concentration than the underlying portion. For example, if the formed tunnel dielectric material 125 is silicon oxynitride, the oxidized portion may differ from the formed portion in the silicon:oxygen:nitrogen atom ratio.

[0064] Channel material 165, filler material 170', and conductive material 175' can be formed in the remaining volume of the column opening 315, such as... Figure 12 and 13 As shown in the diagram. The channel material 165 and the filler material 170′ can be substantially as described for... Figure 7 Formed as described above. Remove a portion of the filler material at 170°, as described above. Figure 8As described, a conductive material 175' is subsequently formed adjacent to the filler material 170 (e.g., above the filler material 170). Figure 14 As shown, a portion of the conductive material 175' is removed, thereby forming the conductive material 175 over the filler material 170. The desired portion of the conductive material 175' is as described above for... Figure 9 The gate is removed as described above. The gate replacement process can be performed as described above, thereby forming an electronic device 100' containing memory cell 105. Figure 2 The memory cells 105 in the first block 110 and the second block 115 have different material compositions and thicknesses.

[0065] Since the first block 110 contains tunneling dielectric material 125′a and the second block 115 contains tunneling dielectric material 125′, the memory cells 105′, 105 of the first and second blocks 110, 115 are different and configured to exhibit different electrical properties during use and operation of the electronic device 100′ containing memory cells 105′, 105. For example only, the memory cell 105′ of the first block 110 may exhibit a different (e.g., improved) programming speed relative to the memory cell 105 of the second block 115, while the memory cell 105 of the second block 115 may have improved cycle endurance relative to the memory cell 105′ of the first block 110.

[0066] Electronic devices 100, 100' include a stack 135 of alternating conductive materials 140 and dielectric materials 145, wherein the conductive materials 140 serve as word lines (e.g., control gates). The conductive materials 140 of the stack 135 may be conductive materials, including but not limited to n-doped polysilicon, p-doped polysilicon, undoped polysilicon, or metals. In some embodiments, the conductive material 140 is tungsten. In other embodiments, the conductive material 140 is n-doped polysilicon. The dielectric material 145 of the stack 135 may be silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials. In some embodiments, the dielectric material 145 is silicon oxide. During use and operation of electronic devices 100, 100', a charge blocking material 160 may be used as a barrier material between layer 150 and storage nitride materials 120, 120'. During use and operation of electronic devices 100, 100', storage nitride materials 120, 120' may be used as charge trapping materials. During the use and operation of electronic devices 100, 100′, tunnel dielectric materials 125, 125′, 125′a can be used as barrier materials to store the potential between nitride materials 120, 120′ and channel material 165.

[0067] Therefore, an electronic device is disclosed. The electronic device includes a first block and a second block comprising an array of memory cells. The memory cells in the first block and the second block include memory pillars extending through a stack of alternating dielectric and conductive materials. Each memory pillar includes a charge-blocking material laterally adjacent to the stack, a storage nitride material laterally adjacent to the charge-blocking material, a tunneling dielectric material laterally adjacent to the storage nitride material, a channel material laterally adjacent to the tunneling dielectric material, and a filling material between opposite sides of the channel material. One or more of the storage nitride material and the tunneling dielectric material in the first block differ in thickness or material composition from one or more of the storage nitride material and the tunneling dielectric material in the second block.

[0068] Therefore, another electronic device is disclosed, comprising a memory array of a single die, the memory array including a first block and a second block laterally adjacent to the first block. The memory cells of the first block are configured to exhibit different electrical properties relative to the memory cells of the second block. The first block includes pillar regions comprising memory pillars extending through a stack of layers. Each of the memory pillars includes a charge-blocking material between the layers and a storage nitride material, the storage nitride material between the charge-blocking material and a tunneling dielectric material, and a tunneling dielectric material between the storage nitride material and a channel material. One or more of the storage nitride material and the tunneling dielectric material of the second block exhibit a greater thickness than one or more of the storage nitride material or the tunneling dielectric material of the first block.

[0069] Therefore, a method for forming an electronic device is disclosed. The method includes forming pillar openings in a stack comprising a first block and a second block laterally adjacent to the first block. A charge blocking material and a storage nitride material are formed in the pillar openings of the first and second blocks. A mask material is formed over the second block, and a portion of the storage nitride material of the first block is removed. The mask material is removed from the second block. A tunneling dielectric material is formed adjacent to the storage nitride material of the first and second blocks. A channel material is formed adjacent to the tunneling dielectric material of the first and second blocks, and a filler material is formed between opposing portions of the channel material.

[0070] Therefore, a method for forming an electronic device is disclosed. The method includes forming pillar openings in a stack comprising a first block and a second block. A charge blocking material, a storage nitride material, and a tunneling dielectric material are formed in the pillar openings of the first block and the second block. A portion of the tunneling dielectric material is oxidized to form an oxidized portion of the tunneling dielectric material. A mask material is formed over the second block. A portion of the oxidized portion of the tunneling dielectric material is removed from the first block. A channel material is formed adjacent to the tunneling dielectric material of the first block and the second block. A filler material is formed between opposing portions of the channel material.

[0071] One or more of the electronic devices 100, 100' according to embodiments of the present disclosure may be present in a device (e.g., a memory device), which may be a 3D electronic device, such as a 3D NAND flash memory device (e.g., a multilayer 3D NAND flash memory device). Figure 15 This is a partial cross-section, perspective, and schematic diagram of a device 1500 that includes one or more electronic devices 1501 (corresponding to electronic devices 100, 100' according to embodiments of this disclosure). The electronic devices 1501 may be related to embodiments of the electronic devices 100, 100' described above (e.g., ...). Figure 1 and 2 The electronic devices 100, 100' are substantially similar and can be formed by the methods described above. Device 1500 may include a stepped structure 1520 defining contact areas for connecting word lines 1506 to conductive material 1505 of a layer. Device 1500 may include vertical strings 1507 connected in series with each other. The vertical strings 1507 may extend vertically (e.g., in the Z direction) and orthogonally to bit lines 1502 (e.g., data lines). Device 1500 also includes a first select gate drain 1508 (e.g., upper select gate, first select gate, select gate drain (SGD)), a select line 1509, and a second select gate 1510 (e.g., lower select gate, source select gate (SGS)). Vertical conductive contacts 1511 can electrically couple components to each other, as illustrated. Bit lines 1502 can be electrically coupled to vertical strings 1507 via conductive contact structures (not shown).

[0072] Device 1500 may also include a control unit 1512 positioned below the stepped structure 1520. Control unit 1512 may include at least one of a string driver circuitry, a transmission gate, a circuitry for selecting a gate, a circuitry for selecting bit line 1502 and word line 1506, a circuitry for amplifying a signal, and a circuitry for sensing a signal. For example, control unit 1512 may be electrically coupled to bit line 1505, word line 1506, source level 1504, first select gate drain 1508, and second select gate 1510. In some embodiments, control unit 1512 includes a CMOS (Complementary Metal-Oxide-Semiconductor) circuitry. In such embodiments, control unit 1512 may be characterized to have an "array-under CMOS" ("CuA") configuration.

[0073] Electronic devices 100 and 100' may reside in memory array 1600, such as Figure 16 The diagram illustrates the concept. Memory array 1600 includes an array of memory cells 1602 and control logic components 1604. Memory array 1600 includes different memory cells 105, 105' in first and second blocks 110, 115. The array of memory cells 1602 includes different memory cells 105, 105' in the first and second blocks 110, 115 of electronic devices 100, 100' according to embodiments of the present disclosure. By way of example only, memory array 1600 may include MLC blocks (TLC blocks, QLC blocks, or TLC and QLC blocks) in so-called "MLC regions" and memory cells 105, 105' in so-called "SLC regions". One or more MLC regions and one or more SLC regions may exist in memory array 1600. The number of SLC blocks may represent a relatively small portion of the total number of blocks in memory array 1600, while MLC blocks (TLC blocks and / or QLC blocks) represent the remaining portion of the blocks. For example, SLC blocks can account for less than or equal to about 10% of the total blocks, such as about 1% to about 5% of the total blocks or about 5% to about 10% of the total blocks.

[0074] Control logic component 1604 can be configured to operatively interact with the memory array of memory cells 105, 105' to read, write, or refresh any or all memory cells within the memory array of memory cells 1602. Memory cells 105, 105' of memory array 1600 are coupled to access lines, and the access lines are coupled to the control gates of memory cells 105, 105'. The memory cells of memory array 1600 are serially coupled between source lines and data lines (e.g., bit lines). Memory cells 105, 105' are positioned between access lines and data lines. Access lines may be electrically contacted with conductive material 140, such as stack 135, and data lines may be electrically contacted with electrodes (e.g., top electrodes) of stack 135. Data lines may directly overlay rows or columns of memory cells 105, 105' and contact their top electrodes. Each of the access lines may extend in a first direction and may connect to rows of memory cells 105, 105'. Each of the data lines may extend in a second direction at least substantially perpendicular to the first direction and may connect to a column of memory cells 105, 105'. The voltage applied to the access lines and data lines is controllable, allowing an electric field to be selectively applied at the intersection of at least one access line and at least one bit line, thereby enabling selective operation of the memory cells 105, 105'. Additional process operations for forming the memory array 1600 including electronic devices 100, 100' are performed using conventional techniques.

[0075] The device 1500, which includes the electronic device 100, can be used in embodiments of the electronic systems disclosed herein. For example... Figure 17 The system 1700 shown in the disclosure also includes one or more of electronic devices 100, 100' according to embodiments of the present disclosure. Figure 17 This is a simplified block diagram of system 1700 according to one or more embodiments described herein. System 1700 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer, for example... or Tablet computers, e-books, navigation devices, etc. System 1700 includes at least one memory device 1702, which includes electronic devices 100, 100' as previously described. System 1700 may further include at least one processor 1704, such as a microprocessor, to control system functions and request processing in system 1700. Processor device 1704 and other sub-components of system 1700 may include memory cells.

[0076] Depending on the functions performed by system 1700, various other devices may be coupled to processor device 1704. For example, input device 1706 may be coupled to processor device 1704 for inputting information into system 1700 by a user, such as, for example, a mouse or other pointing device, button, switch, keyboard, touchpad, light pen, digitizer and stylus, touchscreen, voice recognition system, microphone, control panel, or a combination thereof. Output device 1708 for outputting information (e.g., visual or audio output) to the user may also be coupled to processor device 1704. Output device 1708 may include an LCD display, SED display, CRT display, DLP display, plasma display, OLED display, LED display, 3D projector, audio display, or a combination thereof. Output device 1708 may also include a printer, audio output jack, speaker, etc. In some embodiments, input device 1706 and output device 1708 may include a single touchscreen device that can be used to both input information into system 1700 and output visual information to the user. One or more input devices 1706 and output devices 1708 may be in electrical communication with at least one of the memory device 1702 and the processor device 1704. At least one memory device 1702 and processor device 1704 may also be used in a system-on-a-chip (SoC).

[0077] Therefore, a system is disclosed. The system includes: a processor operatively coupled to input and output devices; and one or more electronic devices operatively coupled to the processor. The one or more electronic devices include memory cells in a first and a second block of a single die. The memory cells include memory pillars containing cell material. One or more of the storage nitride material or tunneling dielectric material of the cell material in the first block differs in thickness from the storage nitride material or the tunneling dielectric material of the second block.

[0078] Non-limiting examples of embodiments disclosed herein include: Embodiment 1. An electronic device comprising: a first block and a second block comprising an array of memory cells, wherein the memory cells in the first block and the second block comprise: memory pillars extending through an alternating stack of dielectric and conductive materials, the memory pillars comprising a charge blocking material laterally adjacent to the stack, a storage nitride material laterally adjacent to the charge blocking material, a tunneling dielectric material laterally adjacent to the storage nitride material, a channel material laterally adjacent to the tunneling dielectric material, and a filling material between opposite sides of the channel material, wherein one or more of the storage nitride material and the tunneling dielectric material in the first block differ in thickness or material composition from one or more of the storage nitride material and the tunneling dielectric material in the second block.

[0079] Example 2. The electronic device according to Example 1, wherein the memory cell in the first block is configured as a multilevel memory cell.

[0080] Example 3. The electronic device according to Example 1, wherein the memory cell in the second block is configured as a single-level memory cell.

[0081] Example 4. An electronic device according to Examples 1 to 3, wherein the thickness of the storage nitride material in the memory cell of the first block is different from the thickness of the storage nitride material in the memory cell of the second block.

[0082] Example 5. The electronic device according to Examples 1 to 4, wherein the thickness of the storage nitride material in the memory cell of the first block is less than the thickness of the storage nitride material in the memory cell of the second block.

[0083] Example 6. The electronic device according to Examples 1 to 5, wherein the difference between the thickness of the storage nitride material in the memory cell of the first block and the thickness of the storage nitride material in the memory cell of the second block is between about 1 nm and about 4 nm.

[0084] Example 7. The electronic device according to Examples 1 to 6, wherein the storage nitride material in the memory cell of the first block and the memory cell of the second block comprises silicon nitride.

[0085] Example 8. The electronic device according to Examples 1 to 6, wherein the storage nitride material in the memory cell of the first block and the memory cell of the second block comprises silicon oxynitride.

[0086] Example 9. An electronic device according to Examples 1 to 8, wherein the material composition of the tunneling dielectric material in the memory cell of the first block is different from the material composition of the tunneling dielectric material in the memory cell of the second block.

[0087] Example 10. An electronic device according to Examples 1 to 9, wherein the material composition of the tunnel dielectric material in the memory cell of the second block includes silicon oxynitride or silicon nitride, and the material composition of the tunnel dielectric material in the memory cell of the first block includes an oxide portion.

[0088] Example 11. An electronic device according to Examples 1 to 10, wherein the memory cells of the first block and the memory cells of the second block exist on a single die.

[0089] Example 12. An electronic device comprising: a memory array of a single die, the memory array including a first block and a second block laterally adjacent to the first block, memory cells of the first block being configured to exhibit different electrical properties relative to memory cells of the second block, the first block including pillar regions, the pillar regions including memory pillars extending through a stack of layers, each of the memory pillars including a charge-blocking material between the layers and a storage nitride material, the storage nitride material between the charge-blocking material and a tunneling dielectric material, and a tunneling dielectric material between the storage nitride material and a channel material. The second block includes a pillar region comprising memory pillars extending through the stack of layers, each of the memory pillars including a charge-blocking material between the layer and the storage nitride material, a storage nitride material between the charge-blocking material and the tunneling dielectric material, and a tunneling dielectric material between the storage nitride material and the channel material, wherein one or more of the storage nitride material and the tunneling dielectric material of the second block exhibit a greater thickness than one or more of the storage nitride material or the tunneling dielectric material of the first block.

[0090] Example 13: The electronic device according to Example 12, wherein the tunneling dielectric material of the second block exhibits a different material composition than the tunneling dielectric material of the first block.

[0091] Example 14: The electronic device according to Examples 12 and 13, wherein the charge blocking material, the storage nitride material, and the tunneling dielectric material extend together with the height of the stacked layers.

[0092] Example 15. An electronic device according to Examples 12 to 14, wherein the channel material extends in conjunction with the height of the layer stack.

[0093] Example 16: An electronic device according to Examples 12 to 15, wherein one or more of the storage nitride material or the tunneling dielectric material of the second block exhibits a material composition different from that of the storage nitride material or the tunneling dielectric material of the second block.

[0094] Example 17. A method of forming an electronic device, comprising: forming pillar openings in a stack including a first block and a second block laterally adjacent to the first block; forming a charge blocking material and a storage nitride material in the pillar openings of the first block and the second block; forming a mask material over the second block; removing a portion of the storage nitride material of the first block; removing the mask material from the second block; forming a tunnel dielectric material adjacent to the storage nitride material of the first block and the second block; forming a channel material adjacent to the tunnel dielectric material of the first block and the second block; and forming a filler material between opposing portions of the channel material.

[0095] Example 18. The method according to Example 17, wherein forming a charge blocking material and a storage nitride material in the column opening includes conformally forming the charge blocking material on the sidewalls of the stack and conformally forming the storage nitride material on the sidewalls of the charge blocking material.

[0096] Example 19. The method according to Example 17 or Example 18, wherein forming the mask material over the second block includes forming the mask material over the second block without forming the mask material over the first block.

[0097] Example 20. The method according to Examples 17 to 19, wherein removing a portion of the storage nitride material of the first block includes reducing the thickness of the storage nitride material of the first block without reducing the thickness of the storage nitride material of the second block.

[0098] Example 21. The method according to Examples 17 to 20, wherein removing a portion of the storage nitride material from the first block includes removing about 1 nm to about 4 nm of the storage nitride material from the first block.

[0099] Example 22. A method of forming an electronic device, comprising: forming pillar openings in a stack including a first block and a second block laterally adjacent to the first block; forming a charge blocking material, a storage nitride material, and a tunneling dielectric material in the pillar openings of the first block and the second block; oxidizing a portion of the tunneling dielectric material to form an oxidized portion of the tunneling dielectric material in the first block and the second block; forming a mask material over the second block; removing a portion of the oxidized portion of the tunneling dielectric material from the first block; forming a channel material adjacent to the tunneling dielectric material of the first block and the second block; and forming a filler material between opposing portions of the channel material.

[0100] Example 23. The method according to Example 22 further includes removing a portion of the tunnel dielectric material before forming the mask material over the second block.

[0101] Example 24. The method according to Examples 22 and 23, wherein removing a portion of the oxidized portion of the tunneling dielectric material from the first block includes forming a tunneling dielectric material in the first block exhibiting a different thickness than the tunneling dielectric material in the second block.

[0102] Example 25. The method according to Examples 22 to 24, further comprising oxidizing an additional portion of the tunneling dielectric material to form the tunneling dielectric material of the first block exhibiting a composition different from that of the tunneling dielectric material of the second block.

[0103] Example 26. A system comprising: a processor operatively coupled to an input device and an output device; and one or more electronic devices operatively coupled to the processor, the one or more electronic devices comprising memory cells in a first block and a second block of a single die, the memory cells comprising: memory pillars comprising cell material, wherein one or more of a storage nitride material or a tunneling dielectric material of the cell material of the first block are different in thickness from the storage nitride material or the tunneling dielectric material of the second block, respectively.

[0104] While certain illustrative embodiments have been described with reference to the figures, those skilled in the art will recognize and understand that the embodiments covered by this disclosure are not limited to those explicitly shown and described herein. Rather, many additions, deletions, and modifications can be made to the embodiments described herein without departing from the scope of the embodiments covered by this disclosure, such as those claimed below (including legal equivalents). Furthermore, features from one disclosed embodiment may be combined with features from another disclosed embodiment while still being covered within the scope of this disclosure.

Claims

1. An electronic device comprising: The first block and the second block comprise an array of memory cells, wherein the memory cells in the first block and the second block include: A memory pillar extending through an alternating stack of dielectric and conductive materials, the memory pillar comprising a charge-blocking material laterally adjacent to the stack, a storage nitride material laterally adjacent to the charge-blocking material, a tunneling dielectric material laterally adjacent to the storage nitride material, a channel material laterally adjacent to the tunneling dielectric material, and a filling material between opposite sides of the channel material, wherein the tunneling dielectric material in the first block differs in material composition from the tunneling dielectric material in the second block.

2. The electronic device of claim 1, wherein the memory cell in the first block is configured as a multilevel memory cell.

3. The electronic device of claim 1, wherein the memory cell in the second block is configured as a single-level memory cell.

4. The electronic device according to any one of claims 1 to 3, wherein the thickness of the storage nitride material in the memory cell of the first block is different from the thickness of the storage nitride material in the memory cell of the second block.

5. The electronic device of claim 4, wherein the thickness of the storage nitride material in the memory cell of the first block is less than the thickness of the storage nitride material in the memory cell of the second block.

6. The electronic device of claim 4, wherein the difference between the thickness of the storage nitride material in the memory cell of the first block and the thickness of the storage nitride material in the memory cell of the second block is between 1 nm and 4 nm.

7. The electronic device of claim 4, wherein the storage nitride material in the memory cell of the first block and the memory cell of the second block comprises silicon nitride.

8. The electronic device of claim 4, wherein the storage nitride material in the memory cell of the first block and the memory cell of the second block comprises silicon oxynitride.

9. The electronic device of claim 1, wherein the material composition of the tunnel dielectric material in the memory cell of the second block comprises silicon oxynitride or silicon nitride, and the material composition of the tunnel dielectric material in the memory cell of the first block comprises an oxide portion.

10. The electronic device according to any one of claims 1 to 3, wherein the memory cells of the first block and the memory cells of the second block are located on a single die.

11. An electronic device comprising: A memory array consisting of a single die, the memory array comprising a first block and a second block laterally adjacent to the first block, wherein the memory cells of the first block are configured to exhibit different electrical properties relative to the memory cells of the second block. The first block includes a pillar region, the pillar region including memory pillars extending through the stack of layers, each of the memory pillars including a charge-blocking material between the layer and the storage nitride material, the storage nitride material between the charge-blocking material and the tunneling dielectric material, and the tunneling dielectric material between the storage nitride material and the channel material; and The second block includes pillar regions, each of which includes memory pillars extending through the stack of layers, each of which includes a charge-blocking material between the layer and the storage nitride material, a storage nitride material between the charge-blocking material and the tunneling dielectric material, and a tunneling dielectric material between the storage nitride material and the channel material. The storage nitride material of the second block exhibits a greater average thickness than the storage nitride material of the first block.

12. The electronic device of claim 11, wherein the tunneling dielectric material of the second block exhibits a different material composition than the tunneling dielectric material of the first block.

13. The electronic device of claim 11, wherein the charge blocking material, the storage nitride material, and the tunneling dielectric material extend together with the height of the stacked layers.

14. The electronic device of claim 11, wherein the channel material extends in conjunction with the height of the layer stack.

15. The electronic device according to any one of claims 11, 13 and 14, wherein one or more of the storage nitride material or the tunneling dielectric material of the second block exhibits a material composition different from that of the storage nitride material or the tunneling dielectric material of the first block.

16. A method of forming an electronic device, comprising: A column opening is formed in the stack including the first block and a second block laterally adjacent to the first block; Charge-blocking material and nitride storage material are formed in the column openings of the first and second blocks; A mask material is formed above the second block; Remove a portion of the storage nitride material from the first block; Remove the mask material from the second block; The storage nitride material adjacent to the first and second blocks forms a tunnel dielectric material; The tunnel dielectric material adjacent to the first and second blocks forms the channel material; and A filler material is formed between the opposite portions of the channel material.

17. The method of claim 16, wherein forming the charge blocking material and the storage nitride material in the column opening comprises conformally forming the charge blocking material on the sidewalls of the stack and conformally forming the storage nitride material on the sidewalls of the charge blocking material.

18. The method of claim 16, wherein forming the mask material over the second block comprises forming the mask material over the second block without forming the mask material over the first block.

19. The method of claim 16, wherein removing a portion of the storage nitride material of the first block comprises reducing the thickness of the storage nitride material of the first block without reducing the thickness of the storage nitride material of the second block.

20. The method according to any one of claims 16 to 19, wherein removing a portion of the storage nitride material from the first block comprises removing 1 nm to 4 nm of the storage nitride material from the first block.

21. A method of forming an electronic device, comprising: A column opening is formed in the stack including the first block and a second block laterally adjacent to the first block; Charge blocking material, storage nitride material, and tunneling dielectric material are formed in the column openings of the first and second blocks; Oxidize a portion of the tunneling dielectric material to form an oxidized portion of the tunneling dielectric material in the first and second blocks; A mask material is formed above the second block; Remove a portion of the oxidized portion of the tunnel dielectric material from the first block; The tunnel dielectric material adjacent to the first and second blocks forms the channel material; and A filler material is formed between the opposite portions of the channel material.

22. The method of claim 21, further comprising removing a portion of the tunnel dielectric material before forming the mask material over the second block.

23. The method of claim 21, wherein removing a portion of the oxidized portion of the tunneling dielectric material from the first block comprises forming a tunneling dielectric material in the first block exhibiting a different thickness than the tunneling dielectric material in the second block.

24. The method according to any one of claims 21 to 23, further comprising oxidizing an additional portion of the tunneling dielectric material to form the tunneling dielectric material of the first block exhibiting a composition different from that of the tunneling dielectric material of the second block.

25. An electronic system comprising: A processor operatively coupled to input and output devices; and One or more electronic devices operatively coupled to the processor, the one or more electronic devices including memory cells in a first and a second block of a single die, the memory cells comprising: A memory column comprising cell material, wherein one or more of the storage nitride material or tunneling dielectric material of the cell material in the first block are different in average thickness from the average thickness of the storage nitride material or the tunneling dielectric material of the second block, and the material composition of the tunneling dielectric material in the first block is different from the material composition of the tunneling dielectric material in the second block.

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