Display panel and its manufacturing method, display device

Abstract

This application provides a display panel and its manufacturing method and display device. The display panel includes a thin-film transistor layer disposed on a substrate. The thin-film transistor layer includes an active layer, a gate insulating layer and a gate disposed above the substrate. The active layer is made of metal oxide and includes a channel region and a doped region connected to the channel region. The orthogonal projection of the gate on the substrate covers the orthogonal projection of the channel region on the substrate. The doped region includes a plurality of oxygen vacancies and nitrogen ions that at least partially fill the oxygen vacancies. This application reduces the oxygen vacancies in the active layer and improves the carrier transport rate by providing that the channel region includes nitrogen ions that at least partially fill the oxygen vacancies.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0002] Currently, please refer to Figure 1 This is a schematic diagram of the structure of an existing display panel. The existing display panel includes a substrate 10, and a thin-film transistor layer 20, a passivation layer 30, a bridging portion 40, a planarization layer 50, a light-emitting device layer 60, a pixel definition layer 70, and an encapsulation layer 80 stacked on the substrate 10. The substrate 10 includes a substrate 11, a light-shielding layer 12, and a buffer layer 13 stacked on the substrate 10. The thin-film transistor layer 20 includes an active layer 21, a gate insulating layer 22, a gate 23A, an interlayer insulating layer 24, a source 25A, and a drain 25B stacked sequentially on the substrate 10. The active layer 21 includes a first doped region 211B, a second doped region 212B, and a channel region 21A located between the first doped region 211B and the second doped region 212B. The source 25A is connected to the first doped region 211B of the active layer 21, and the drain 25B is connected to the second doped region 212B of the active layer 21.

[0003] It is understood that in the prior art, the thin-film transistor layer 20 includes a plurality of thin-film transistors 20A arranged in a matrix. Transistors (TFTs), particularly oxide thin-film transistors (TFTs), are considered one of the most promising next-generation TFTs due to their advantages such as low processing temperature, high mobility, transparency to visible light, ability to fabricate large-area high-quality thin films at room temperature, compatibility with existing production line equipment, and ability to be fabricated on flexible substrates 11. During the fabrication of oxide TFTs 20A, when the metal (i.e., source 25A and drain 25B) and the active layer 21 come into contact, a potential barrier is formed at the interface. The presence of this barrier leads to a large interface resistance, resulting in insufficient on-state current of the TFT 20A, which in turn affects the display quality of the screen. To ensure good contact between the source 25A and drain 25B and the active layer 21 in the TFT 20A, it is necessary to reduce the overlap impedance between the metal and the active layer 21. This is typically achieved by conductiveing ​​the contact points of the active layer 21 with the source 25A and drain 25B, thereby reducing the overlap impedance and improving the performance of the TFT 20A. However, in the prior art, when dry etching-conducting treatment is used for the active layer, plasma gas is often used to conduct the positions in the active layer that are in contact with the source and drain. However, the plasma gas diffuses from the overlap region 21B1 along the doped region to the channel region, resulting in poor uniformity of the actual channel length of the thin film transistor on the substrate, and even causing it to lose its semiconductor performance, thereby affecting the display effect of the display panel. Summary of the Invention

[0004] This application provides a display panel, a method for manufacturing the same, and a display device to alleviate the shortcomings of related technologies.

[0005] To achieve the above functions, the technical solutions provided in this application are as follows:

[0006] This application provides a display panel, including:

[0007] Base;

[0008] A thin-film transistor layer is disposed on the substrate. The thin-film transistor layer includes an active layer, a gate insulating layer, and a gate disposed above the substrate. The active layer is made of metal oxide and includes a channel region and a doped region connected to the channel region. The orthogonal projection of the gate on the substrate covers the orthogonal projection of the channel region on the substrate.

[0009] The doped region includes a plurality of oxygen vacancies and nitrogen ions that fill at least a portion of the oxygen vacancies.

[0010] In the display panel provided in this application embodiment, the concentration of nitrogen ions is less than the concentration of oxygen vacancies.

[0011] In the display panel provided in the embodiments of this application, the display panel further includes a first metal layer stacked with the active layer, and the doped region includes an overlap region connected to the first metal layer and a doped sub-region located between the overlap region and the channel region, wherein the concentration of nitrogen ions in the doped sub-region is less than the concentration of nitrogen ions in the overlap region.

[0012] In the display panel provided in this application embodiment, the first metal layer includes a source and a drain, the overlap area includes a first overlap area in contact with the source and a second overlap area in contact with the drain, and the channel area is located between the first overlap area and the second overlap area;

[0013] Wherein, along the direction from the first overlap area to the second overlap area, the width of the channel area is less than and equal to 3 micrometers.

[0014] In the display panel provided in the embodiments of this application, the doped sub-region includes a first doped sub-region and a second doped sub-region, the first doped sub-region being located between the first overlap region and the channel region, and the second doped sub-region being located between the second overlap region and the channel region;

[0015] Wherein, the concentration of nitrogen ions in the first doped sub-region is less than the concentration of nitrogen ions in the first overlapping region, and the concentration of nitrogen ions in the second doped sub-region is less than the concentration of nitrogen ions in the second overlapping region.

[0016] In the display panel provided in the embodiments of this application, the thin-film transistor layer further includes a second metal layer, and the second metal layer includes the gate;

[0017] The second metal layer includes a first sub-metal layer and a second sub-metal layer stacked on the substrate, wherein the material of the second sub-metal layer includes an inert metal material, and the conductivity of the first sub-metal layer is greater than that of the second sub-metal layer.

[0018] In the display panel provided in this application embodiment, the material of the second sub-metal layer includes at least one of molybdenum, titanium, and molybdenum-titanium alloy, and the material of the first sub-metal layer includes at least one of copper, aluminum, and silver.

[0019] In the display panel provided in the embodiments of this application, the second metal layer further includes a third sub-metal layer located between the first sub-metal layer and the gate insulating layer, and the material of the third sub-metal layer includes at least one of molybdenum, titanium, and molybdenum-titanium alloy.

[0020] This application provides a method for manufacturing a display panel, the steps of which include:

[0021] A substrate is provided on which an active layer, a gate insulating layer and a gate are sequentially formed.

[0022] The active layer is conductiveized to form a channel region and a doped region connected to the channel region, wherein the orthogonal projection of the gate on the substrate covers the orthogonal projection of the channel region on the substrate, and the doped region includes a plurality of oxygen vacancies;

[0023] The doped region is subjected to plasma doping treatment to make the doped region include nitrogen atoms, wherein the nitrogen atoms at least partially fill the oxygen vacancies.

[0024] A display device comprising any of the display panels described above.

[0025] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide a display panel and a method for manufacturing the same, as well as a display device. The display panel includes a thin-film transistor layer stacked on a substrate. The thin-film transistor layer includes an active layer, a gate insulating layer, and a gate disposed above the substrate. The active layer is made of metal oxide and includes a channel region and a doped region connected to the channel region. The orthogonal projection of the gate on the substrate covers the orthogonal projection of the channel region on the substrate. The doped region includes a plurality of oxygen vacancies and nitrogen ions that at least partially fill the oxygen vacancies. By providing that the channel region includes nitrogen ions that at least partially fill the oxygen vacancies, the number of oxygen vacancies in the active layer is reduced, thereby improving the carrier transport rate. Attached Figure Description

[0026] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0027] Figure 1 This is a schematic diagram of the structure of an existing display panel;

[0028] Figure 2 This is a schematic diagram of a first structure of the display panel provided in an embodiment of this application;

[0029] Figure 3 This is a schematic diagram of a second structure of the display panel provided in an embodiment of this application.

[0030] Figure 4 A flowchart illustrating the method for manufacturing the display panel provided in the embodiments of this application;

[0031] Figures 5A to 5G for Figure 4 A flowchart illustrating the structural process of manufacturing the central display panel. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0033] This application provides a display panel, a method for manufacturing the same, and a display device. These will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0034] Please see Figures 2 to 5G This application provides a display panel, a method for manufacturing the same, and a display device. The display panel includes:

[0035] Base 10;

[0036] A thin-film transistor layer 20 is disposed on the substrate 10. The thin-film transistor layer 20 includes an active layer 21, a gate insulating layer 22, and a gate 23A disposed above the substrate 10. The active layer 21 is made of metal oxide and includes a channel region 21A and a doped region 21B connected to the channel region 21A. The orthogonal projection of the gate 23A on the substrate 10 covers the orthogonal projection of the channel region 21A on the substrate 10.

[0037] The doped region 21B includes a plurality of oxygen vacancies and nitrogen ions that fill at least a portion of the oxygen vacancies.

[0038] It is understood that, in this embodiment of the application, by setting the doped region 21B to include nitrogen ions that at least partially fill the oxygen vacancies, the oxygen vacancies in the active layer 21 are reduced, thereby improving the carrier transport rate.

[0039] The technical solution of this application will now be described in conjunction with specific embodiments.

[0040] In one embodiment, please refer to Figure 2 This is a schematic diagram of a first structure of a display panel provided in an embodiment of this application.

[0041] This embodiment provides a display panel, which includes, but is not limited to, one of light-emitting diode (LED) and organic light-emitting diode (OLED) display panels. This embodiment does not impose specific limitations on either one. It should be noted that this embodiment uses an organic light-emitting diode display panel as an example to describe the technical solution of this application.

[0042] In this embodiment, the display panel includes a substrate 10 and a thin-film transistor layer 20 located on the substrate 10; wherein, the substrate 10 includes a substrate 11 and a buffer layer 13 disposed on the substrate 11, the substrate 11 may include a rigid substrate or a flexible substrate, and the material of the buffer layer 13 includes, but is not limited to, monolayer silicon nitride (Si3N4), monolayer silicon dioxide (SiO2), and monolayer silicon oxynitride (SiON). x It can be a double-layer structure of the above membrane layers, but this embodiment does not impose specific limitations on it.

[0043] The thin-film transistor layer 20 includes a plurality of thin-film transistors 20A arranged in a matrix. The thin-film transistor 20A includes an active layer 21, a gate insulating layer 22, and a gate 23A disposed above the substrate 10. The active layer 21 is made of metal oxide, including but not limited to indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), or indium gallium zinc titanium oxide (IGZTO). Preferably, this embodiment uses indium gallium zinc oxide as an example to illustrate the technical solution of this application.

[0044] In this embodiment, the display panel further includes a first metal layer 25 stacked with the active layer 21. The active layer 21 includes a channel region 21A and a doped region 21B connected to the channel region 21A. The orthogonal projection of the gate 23A on the substrate 10 covers the orthogonal projection of the channel region 21A on the substrate 10. The first metal layer 25 is connected to the doped region 21B. The doped region 21B includes a plurality of oxygen vacancies and nitrogen ions that at least partially fill the oxygen vacancies.

[0045] Furthermore, in this embodiment, the first metal layer 25 includes the source 25A and drain 25B of the thin film transistor 20A, and the display panel further includes an interlayer insulating layer 24 located between the gate 23A and the first metal layer 25. The interlayer insulating layer 24 has a via that exposes a portion of the doped region 21B, and the first metal layer 25 is connected to the doped region 21B through the first via.

[0046] It should be noted that, in this embodiment, the active layer 21, the gate insulating layer 22, the gate 23A and the first metal layer 25 are sequentially stacked on the substrate 10 as an example to illustrate the technical solution of this application. This embodiment does not impose specific limitations on the film layer structure of the thin film transistor 20A.

[0047] Further, in this embodiment, the doped region 21B includes a first doped region 211B connected to the source 25A and a second doped region 212B connected to the drain 25B, and the channel region 21A is located between the first doped region 211B and the second doped region 212B; the first doped region 211B includes a plurality of oxygen vacancies and a nitrogen ion that fills at least a portion of the oxygen vacancies; the second doped region 212B includes a plurality of oxygen vacancies and a nitrogen ion that fills at least a portion of the oxygen vacancies.

[0048] Understandably, in combination Figure 1 To ensure good contact between the source 25A and drain 25B in the thin-film transistor 20A and the active layer 21, it is necessary to reduce the overlap impedance between the first metal layer 25 and the active layer 21. In the prior art, a common method is to perform a conductive treatment on the positions in the active layer 21 that are in contact with the source 25A and drain 25B to reduce the overlap impedance of the source 25A and drain 25B, thereby improving the performance of the thin-film transistor 20A. However, when dry etching-conductivity treatment is used on the active layer 21, plasma gas is often used to conduct the conductive treatment on the positions in the active layer 21 that are in contact with the source 25A and drain 25B. However, the plasma gas diffuses from the doped region 21B to the channel region 21A, resulting in poor uniformity of the actual channel length of the thin-film transistor 20A on the substrate, and even causing it to lose its semiconductor performance, thereby affecting the display effect of the display panel.

[0049] It is understood that, in this embodiment of the application, the doped region 21B is configured to include a first doped region 211B connected to the source 25A and a second doped region 212B connected to the drain 25B. The first doped region 211B includes nitrogen ions that fill at least a portion of the oxygen vacancies, and the second doped region 212B includes nitrogen ions that fill at least a portion of the oxygen vacancies, thereby reducing oxygen vacancies in the active layer 21 and improving the carrier transport rate.

[0050] It should be noted that in this embodiment, the concentration of nitrogen ions is less than the concentration of oxygen vacancies, thereby maintaining the conductor properties of the doped region 21B and avoiding damage to the high electron mobility of the oxide semiconductor thin film transistor 20A.

[0051] In this embodiment, the interlayer insulating layer 24 has a first via (not marked in the figure) that exposes a portion of the first doped region 211B and a second via (not marked in the figure) that exposes a portion of the second doped region 212B. The source electrode 25A is connected to the first doped region 211B through the first via, and the drain electrode 25B is connected to the second doped region 212B through the second via.

[0052] In this embodiment, the thin-film transistor layer 20 further includes a second metal layer 23, which includes the gate 23A of the thin-film transistor 20A; wherein the second metal layer 23 includes a first sub-metal layer 231A and a second sub-metal layer 231B stacked on the substrate 10, wherein the material of the second sub-metal layer 231B includes an inert metal material, and the conductivity of the first sub-metal layer 231A is greater than the conductivity of the second sub-metal layer 231B.

[0053] Specifically, in this embodiment, the oxidation resistance of the second sub-metal layer 231B is greater than that of the first sub-metal layer 231A. The material of the second sub-metal layer 231B includes, but is not limited to, at least one of molybdenum (Mo), titanium (Ti), and molybdenum-titanium alloy (MoTi). The material of the first sub-metal layer 231A includes, but is not limited to, at least one of copper (Cu), aluminum (Al), and silver (Ag).

[0054] It is understood that in existing display panels, copper (Cu) is typically used as the material. However, in this embodiment, when plasma is used to dope nitrogen ions into the doped region 21B, if the plasma includes oxygen ions, such as nitrous oxide (N2O), the gate 23A is at risk of oxidation. Therefore, this embodiment provides the second metal layer 23 with a first sub-metal layer 231A and a second sub-metal layer 231B stacked on the substrate 10. The material of the second sub-metal layer 231B is an inert metal material, and the conductivity of the first sub-metal layer 231A is greater than that of the second sub-metal layer 231B. This provides protection for the first sub-metal layer 231A, preventing its oxidation and ensuring the stable operation of the thin-film transistor 20A.

[0055] Furthermore, in this embodiment, the second metal layer 23 further includes a third sub-metal layer 231C located between the first sub-metal layer 231A and the gate insulating layer 22, wherein the bonding force between the third sub-metal layer 231C and the gate insulating layer 22 is greater than the bonding force between the first sub-metal layer 231A and the gate insulating layer 22.

[0056] Specifically, the material of the third sub-metal layer 231C is the same as that of the second sub-metal layer 231B. The material of the third sub-metal layer 231C includes an inert metal material, including but not limited to at least one of molybdenum (Mo), titanium (Ti), and molybdenum-titanium alloy (MoTi). It can be understood that, in this embodiment, by setting the second metal layer 23 to also include a third sub-metal layer 231C located between the first sub-metal layer 231A and the gate insulating layer 22, the bonding force between the third sub-metal layer 231C and the gate insulating layer 22 is greater than the bonding force between the first sub-metal layer 231A and the gate insulating layer 22, thereby increasing the adhesion between the gate 23A and the gate insulating layer 22 and avoiding the peeling problem of the gate 23A during the fabrication process of the thin film transistor 20A.

[0057] It should be noted that the above-described method of using nitrous oxide (N2O) to perform plasma doping treatment on the doped region 21B is only for illustrative purposes, and this embodiment does not impose specific limitations on the type of plasma.

[0058] Furthermore, in this embodiment, the display panel also includes a passivation layer 30, a bridging portion 40, a planarization layer 50, a light-emitting device layer 60, and an encapsulation layer 80 located on the side of the thin-film transistor layer 20 away from the substrate 10. It should be noted that other functional film layers may also be provided between the substrate 10 and the encapsulation layer 80, and this embodiment does not impose specific limitations on this.

[0059] In this embodiment, the light-emitting device layer 60 includes an anode 61, a light-emitting layer 62, and a cathode 63 stacked on the planarization layer 50. The passivation layer 30 has a third via (not marked in the figure) exposing a portion of the source electrode 25A or the drain electrode 25B. The bridging portion 40 is connected to the source electrode 25A or the drain electrode 25B through the third via. The planarization layer 50 has a fourth via (not marked in the figure) exposing a portion of the bridging portion 40. The anode 61 is connected to the bridging portion 40 through the fourth via. That is, the anode 61 is connected to the source electrode 25A or the drain electrode 25B through the bridging portion 40. Preferably, in this embodiment, the passivation layer 30 has the third via exposing a portion of the drain electrode 25B. The bridging portion 40 is connected to the drain electrode 25B through the third via, and the anode 61 is connected to the drain electrode 25B through the bridging portion 40.

[0060] It should be noted that, in this embodiment, the display panel further includes a pixel definition layer 70 located on the side of the anode 61 away from the planarization layer 50. An opening (not marked in the figure) is formed on the pixel definition layer 70 to expose the anode 61. The light-emitting layer 62 is located in the opening. The light-emitting layer 62 is connected to the anode 61 through the opening. The cathode 63 is connected to the light-emitting layer 62 through the opening.

[0061] The substrate 10 further includes a light-shielding layer 12 disposed between the substrate 11 and the buffer layer 13. The orthographic projection of the light-shielding layer 12 on the substrate 10 covers the orthographic projection of the active layer 21 on the substrate 10. The light-shielding layer 12 can block light incident on the active layer 21, thereby reducing the increase in leakage current caused by photogenerated carriers generated by light irradiating the active layer 21, and thus maintaining the stability of the display panel during operation.

[0062] In another embodiment, please refer to Figure 3 This is a schematic diagram of a second structure of the display panel provided in an embodiment of this application.

[0063] In this embodiment, the structure of the display panel is similar to that of the display panel provided in the above embodiments. Please refer to the description of the display panel in the above embodiments for details, which will not be repeated here. The only difference between the two is:

[0064] In this embodiment, the doped region 21B includes an overlap region 21B1 connected to the first metal layer 25 and a doped sub-region 21B2 located between the overlap region 21B1 and the channel region 21A, wherein the concentration of nitrogen ions in the doped sub-region 21B2 is less than the concentration of nitrogen ions in the overlap region 21B1.

[0065] Specifically, the overlap region 21B1 includes a first overlap region 211B1 contacting the source electrode 25A and a second overlap region 212B1 contacting the drain electrode 25B. The channel region 21A is located between the first overlap region 211B1 and the second overlap region 212B1. The doped sub-region 21B2 includes a first doped sub-region 211B2 located between the first overlap region 211B1 and the channel region 21A, and a second doped sub-region 212B2 located between the second overlap region 212B1 and the channel region 21A. The width of the channel region 21A is less than or equal to 3 micrometers along the direction from the first overlap region 211B1 to the second overlap region 212B1. The concentration of nitrogen ions in the first doped sub-region 211B2 is less than the concentration of nitrogen ions in the first overlap region 211B1, and the concentration of nitrogen ions in the second doped sub-region 212B2 is less than the concentration of nitrogen ions in the second overlap region 212B1.

[0066] It is understood that in this embodiment, the doped region 21B includes an overlap region 21B1 connected to the first metal layer 25 and a doped sub-region 21B2 located between the overlap region 21B1 and the channel region 21A. The concentration of nitrogen ions in the doped sub-region 21B2 is less than the concentration of nitrogen ions in the overlap region 21B1. By reserving a distance for the diffusion region of plasma gas, the plasma gas in the overlap region 21B1 is prevented from diffusing toward the channel region 21A during the conductive process of the active layer 21. This avoids the channel region 21A from losing its semiconductor properties during the conductive process of the active layer 21, thereby ensuring the effective channel length and facilitating the short-channel fabrication of the thin-film transistor 20A.

[0067] Please combine Figure 2 , Figure 4 , Figures 5A to 5E ;in, Figure 4 A flowchart illustrating the method for manufacturing the display panel provided in the embodiments of this application; Figures 5A to 5G for Figure 4 A flowchart illustrating the structural process of manufacturing the central display panel.

[0068] This embodiment provides a method for manufacturing a display panel, the steps of which include:

[0069] Step S100: Provide a substrate 10, on which an active layer 21, a gate insulating layer 22 and a gate 23A are sequentially formed.

[0070] Specifically, in this embodiment, step S100 includes the following steps:

[0071] Step S101: Providing the substrate 10 includes providing a substrate 11, and a light-shielding layer 12 and a buffer layer 13 sequentially formed on the substrate 11; as shown Figure 5A As shown;

[0072] When the substrate is a rigid substrate, the material can be metal or glass; when the substrate 11 is a flexible substrate, the material can include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane-based resin, cellulose resin, siloxane resin, polyimide-based resin, and polyamide-based resin.

[0073] The thickness of the light-shielding layer 12 ranges from 1000 angstroms to 8000 angstroms, and the material of the light-shielding layer 12 includes, but is not limited to, metallic materials, including, but not limited to, one or more alloys of molybdenum (Mo), titanium (Ti), and nickel (Ni); the thickness of the buffer layer 13 ranges from 1000 angstroms to 5000 angstroms, and the material of the buffer layer 13 includes, but is not limited to, single-layer silicon nitride (Si3N4), single-layer silicon dioxide (SiO2), single-layer silicon oxynitride (SiONx), or a bilayer structure of the above films.

[0074] Step S102: Deposit a metal oxide thin film on the buffer layer 13, and pattern the metal oxide thin film to form the active layer 21, such as... Figure 5B As shown.

[0075] Specifically, the materials of the oxide thin film include, but are not limited to, indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), or indium gallium zinc titanium oxide (IGZTO). Preferably, this embodiment uses the materials of the oxide thin film, including but not limited to indium gallium zinc oxide, as an example to illustrate the technical solution of this application.

[0076] In this embodiment, a metal oxide semiconductor layer is deposited on the buffer layer 13 using physical vapor deposition (PVD), and the oxide semiconductor layer is patterned using photolithography to form the active layer 21. The thickness of the active layer 21 ranges from 400 angstroms to 1000 angstroms. The orthographic projection of the light-shielding layer 12 on the substrate covers the orthographic projection of the active layer 21 on the substrate.

[0077] Step S103: A gate insulating layer 22 and a gate 23A are sequentially formed on the active layer 21, wherein the orthographic projection of the gate 23A on the substrate 10 overlaps with the orthographic projection of the gate insulating layer 22 on the substrate 10, and the orthographic projection of the gate insulating layer 22 on the substrate 10 is located within the orthographic projection range of the active layer 21 on the substrate 10.

[0078] Specifically, step S103 includes the following steps:

[0079] Step S1031: A gate insulating material layer is formed on the active layer 21. The material of the gate insulating material layer includes, but is not limited to, silicon oxide (SiO2). X The thickness of the gate insulating material layer ranges from 1000 angstroms to 3000 angstroms.

[0080] Step S1032: A second metal layer 23 is formed on the side of the gate insulating material layer away from the active layer 21. The thickness of the second metal layer 23 is in the range of 2000 angstroms to 8000 angstroms. The second metal layer 23 includes a third sub-metal layer 231C, a first sub-metal layer 231A, and a second sub-metal layer 231B stacked on the gate insulating material layer. The materials of the third sub-metal layer 231C and the second sub-metal layer 231B include, but are not limited to, at least one of molybdenum (Mo), titanium (Ti), and molybdenum-titanium alloy (MoTi). The materials of the first sub-metal layer 231A include, but are not limited to, at least one of copper (Cu), aluminum (Al), and silver (Ag).

[0081] Preferably, this embodiment uses the material of the third sub-metal layer 231C as a molybdenum-titanium alloy (MoTi), the material of the first sub-metal layer 231A as copper (Cu), and the material of the second sub-metal layer 231B as a molybdenum-titanium alloy (MoTi) as an example to illustrate the technical solution of this application.

[0082] It is understood that in this embodiment, the third sub-metal layer 231C, the first sub-metal layer 231A, and the second sub-metal layer 231B can be fabricated simultaneously through a single photomask process, without adding an additional photomask process, making the process simpler.

[0083] Step S1033: Pattern the second metal layer 23, form a gate 23A on the gate insulating material layer, use the gate 23A to self-align the gate insulating material layer, etch the gate insulating material layer to form the gate insulating layer 22, as shown. Figure 5C As shown.

[0084] Step S200: Conduct the active layer 21 to form a channel region 21A and a doped region 21B connected to the channel region 21A, wherein the orthogonal projection of the gate 23A on the substrate 10 covers the orthogonal projection of the channel region 21A on the substrate 10, and the doped region 21B includes a plurality of oxygen vacancies.

[0085] Further, in this embodiment, the doped region 21B includes a first doped region 211B and a second doped region 212B, and the channel region 21A is located between the first doped region 211B and the second doped region 212B, as shown below. Figure 5D As shown.

[0086] Specifically, step S200 includes: performing plasma doping on the active layer 21 to form the channel region 21A and the doped region 21B connected to the channel region 21A. The plasma is one or more of helium, argon, hydrogen and oxygen, and this embodiment does not impose specific limitations on this. It should be noted that the plasma doping on the active layer 21 is only for illustrative purposes, and this embodiment does not impose specific limitations on the method of making the active layer 21 conductive.

[0087] It is understood that this embodiment reduces the contact impedance between the active layer 21 and the source 25A and drain 25B formed in subsequent fabrication processes by performing plasma doping on the active layer 21, thereby improving the performance of the thin film transistor 20A. However, when using plasma gas to conductionize the positions in the active layer 21 that are in contact with the source 25A and drain 25B, the plasma gas will diffuse from the doped region 21B to the channel region 21A. Therefore, in the prior art, when plasma is used to dope the active layer 21, the channel region 21A may lose its semiconductor performance.

[0088] Step S300: Perform plasma doping treatment on the doped region 21B to make the doped region 21B include nitrogen atoms, wherein the nitrogen atoms at least partially fill the oxygen vacancies, such as... Figure 5E As shown.

[0089] Specifically, in step S300, plasma doping is performed on the doped region 21B, and the plasma includes one or more of nitrogen and nitrous oxide. Preferably, in this embodiment, nitrous oxide is used as an example to illustrate the technical solution of this application.

[0090] It is understood that this embodiment reduces oxygen vacancies in the active layer 21 and improves the carrier transport rate by setting the doped region 21B to include nitrogen ions that at least partially fill the oxygen vacancies. At the same time, when the active layer 21 is conductiveized using plasma gas, it can effectively prevent the plasma gas from diffusing into the channel region 21A, avoiding the loss of semiconductor properties of the channel region 21A during the conductiveization process of the active layer 21, thereby maintaining the working stability of the display panel device. Furthermore, nitrogen ion doping does not affect the internal lattice structure of the active layer 21 material, and the doping dosage is controllable and the process is simple.

[0091] In this embodiment, the method for manufacturing the display panel further includes the following steps:

[0092] Step S400: An interlayer insulating layer 24 and a first metal layer 25 are sequentially formed on the gate 23A;

[0093] Specifically, step S400 includes the following steps:

[0094] Step S401: An interlayer insulating layer 24 is formed on the side of the gate 23A away from the gate insulating layer 22 using a physical vapor deposition process. The thickness of the interlayer insulating layer 24 ranges from 2000 angstroms to 10000 angstroms. The interlayer insulating layer 24 has strong water and oxygen barrier capabilities and insulating capabilities. Its material includes, but is not limited to, silicon oxide (SiO2). X ), silicon nitride (SiN) X ), silicon oxynitride (SiNO), or their stacks.

[0095] Step S402: The interlayer insulating layer 24 is patterned to form vias that expose a portion of the doped region 21B; specifically, the interlayer insulating layer 24 is provided with a first via exposing a portion of the first doped region 211B and a second via exposing a portion of the second doped region 212B.

[0096] Step S403: The first metal layer 25 is formed on the interlayer insulating layer 24 using physical vapor deposition. The thickness of the first metal layer 25 is in the range of 2000 angstroms to 8000 angstroms. The material of the first metal layer 25 includes, but is not limited to, conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), and may include a single layer or multiple layers of the above materials.

[0097] Step S404: The first metal layer 25 is patterned to form a source electrode 25A and a drain electrode 25B spaced apart. The source electrode 25A is in contact with the first doped region 211B through the first via, and the drain electrode 25B is in contact with the second doped region 212B through the second via. Figure 5F As shown; wherein, preferably, the first metal layer 25 is patterned by photolithography and wet etching.

[0098] Step S500: A passivation layer 30 is formed on the side of the first metal layer 25 away from the interlayer insulating layer 24, wherein the thickness of the passivation layer 30 is in the range of 1000 angstroms to 5000 angstroms, and the material of the passivation layer 30 includes, but is not limited to, silicon oxide (SiO2). X ), silicon nitride (SiN) X The passivation layer 30 can be fabricated by methods including, but not limited to, vapor deposition.

[0099] Step S600: A bridging portion 40 is formed on the side of the passivation layer 30 away from the first metal layer 25, such as... Figure 5G As shown; the bridging part 40 is made of a metallic material, which includes, but is not limited to, at least one of the following metals: molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), and tungsten (W).

[0100] Specifically, step S500 includes patterning the passivation layer 30 to form a third via that exposes a portion of the drain electrode 25B, and the bridging portion 40 is connected to the drain electrode 25B through the third via.

[0101] Step S700: A planarization layer 50 is formed on the side of the bridging portion 40 away from the first metal layer 25. The planarization layer 50 is patterned to form a fourth via that exposes a portion of the bridging portion 40. Preferably, the thickness of the planarization layer 50 is in the range of 10,000 angstroms to 30,000 angstroms. The planarization layer 50 can be fabricated by chemical vapor deposition (CVD).

[0102] Step S800: A pixel definition layer 70, a light-emitting device layer 60, and an encapsulation layer 80 are sequentially formed on the side of the planarization layer 50 away from the bridging portion 40, such as... Figure 2As shown; the light-emitting device layer 60 includes an anode 61, a light-emitting layer 62, and a cathode 63 stacked on the planarization layer 50, wherein the anode 61 is a stacked structure of indium tin oxide / silver / indium tin oxide; wherein the pixel definition layer 70, the light-emitting layer 62, the cathode 63, and the encapsulation layer 80 are conventional film layers widely used in the prior art, and will not be described in detail in this embodiment.

[0103] This embodiment provides a display device, which includes the display panel described in any of the above embodiments.

[0104] It is understood that the display panel has been described in detail in the above embodiments, and will not be repeated here.

[0105] In specific applications, the display device can be the display screen of devices such as smartphones, tablets, laptops, smart bracelets, smartwatches, smart glasses, smart helmets, desktop computers, smart TVs, or digital cameras, and can even be applied to electronic devices with flexible displays.

[0106] This application provides a display panel and its manufacturing method and display device. The display panel includes a thin-film transistor layer stacked on a substrate. The thin-film transistor layer includes an active layer, a gate insulating layer, and a gate disposed above the substrate. The active layer is made of metal oxide and includes a channel region and a doped region connected to the channel region. The orthogonal projection of the gate on the substrate covers the orthogonal projection of the channel region on the substrate. The doped region includes a plurality of oxygen vacancies and nitrogen ions that at least partially fill the oxygen vacancies. By providing that the channel region includes nitrogen ions that at least partially fill the oxygen vacancies, the number of oxygen vacancies in the active layer is reduced, thereby improving the carrier transport rate.

[0107] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0108] The foregoing has provided a detailed description of a display panel, its manufacturing method, and the display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate; a thin film transistor layer disposed on the substrate, the thin film transistor layer comprising an active layer, a gate insulating layer and a second metal layer disposed above the substrate, the second metal layer comprising a gate electrode, the active layer being made of metal oxide, the active layer comprising a channel region and a doped region connected to the channel region, a normal projection of the gate electrode on the substrate covering a normal projection of the channel region on the substrate; wherein the doped region comprises a plurality of oxygen vacancies and nitrogen ions filling at least part of the oxygen vacancies; the second metal layer comprises a first sub-metal layer and a second sub-metal layer stacked on the substrate, the second sub-metal layer having a greater oxidation resistance than the first sub-metal layer, and the first sub-metal layer having a greater electrical conductivity than the second sub-metal layer.

2. The display panel of claim 1, wherein, The concentration of the nitrogen ions is less than the concentration of the oxygen vacancies.

3. The display panel of claim 1, wherein, The display panel further comprises a first metal layer stacked with the active layer, the doped region comprising an overlap region connected to the first metal layer and a sub-doped region between the overlap region and the channel region, wherein the concentration of the nitrogen ions in the sub-doped region is less than the concentration of the nitrogen ions in the overlap region.

4. The display panel of claim 3, wherein, The first metal layer comprises a source electrode and a drain electrode, the overlap region comprises a first overlap region in contact with the source electrode and a second overlap region in contact with the drain electrode, and the channel region is between the first overlap region and the second overlap region; wherein the width of the channel region is less than or equal to 3 microns in a direction from the first overlap region to the second overlap region.

5. The display panel of claim 4, wherein, The sub-doped region comprises a first sub-doped region between the first overlap region and the channel region and a second sub-doped region between the second overlap region and the channel region; wherein the concentration of the nitrogen ions in the first sub-doped region is less than the concentration of the nitrogen ions in the first overlap region, and the concentration of the nitrogen ions in the second sub-doped region is less than the concentration of the nitrogen ions in the second overlap region.

6. The display panel of claim 1, wherein, The material of the second sub-metal layer comprises an inert metal material.

7. The display panel of claim 6, wherein, The material of the second sub-metal layer comprises at least one of molybdenum, titanium and a molybdenum-titanium alloy, and the material of the first sub-metal layer comprises at least one of copper, aluminum and silver.

8. The display panel of claim 7, wherein, The second metal layer further comprises a third sub-metal layer between the first sub-metal layer and the gate insulating layer, the material of the third sub-metal layer comprising at least one of molybdenum, titanium and a molybdenum-titanium alloy.

9. A manufacturing method of a display panel, comprising: The manufacturing method comprises the steps of: providing a substrate, and sequentially forming an active layer, a gate insulating layer and a second metal layer on the substrate, the second metal layer comprising a gate electrode, wherein the second metal layer comprises a first sub-metal layer and a second sub-metal layer stacked on the substrate, the second sub-metal layer having a greater oxidation resistance than the first sub-metal layer, and the first sub-metal layer having a greater electrical conductivity than the second sub-metal layer; The active layer is conductorized to form a channel region and a doped region connected to the channel region, wherein a normal projection of the gate on the substrate covers a normal projection of the channel region on the substrate, and the doped region comprises a plurality of oxygen vacancies; The doped region is subjected to a plasma doping treatment so that the doped region comprises nitrogen atoms which at least fill part of the oxygen vacancies.

10. A display device, characterized by comprising: The display device comprises the display panel as claimed in any one of claims 1-8.

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