Super junction LDMOS device

Abstract

The application provides a super junction LDMOS device. The super junction LDMOS device is arranged on a semiconductor substrate, and comprises: an epitaxial layer arranged on the semiconductor substrate, the epitaxial layer having source regions and drain regions arranged at intervals, and the epitaxial layer having a first side away from the semiconductor substrate; a drift region located at the first side, and the drift region having a first surface away from the epitaxial layer; and a plurality of doped regions, the plurality of doped regions comprising a plurality of columns distributed along a first direction, and adjacent two columns of the plurality of doped regions being arranged alternately. The on-resistance and output capacitance of the device are further reduced, and the alternating arrangement of the plurality of doped regions can also make the doped regions more evenly distributed in the drift region, so as to achieve more flattened electric field modulation and effectively balance the electric field of the drift region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more specifically, to a superjunction LDMOS device. Background Technology

[0002] Laterally diffused metal-oxide-semiconductor field-effect transistors (LDMOS), as one of the power devices, have been widely used due to their superior frequency characteristics and have now become the core semiconductor device in the field of radio frequency applications.

[0003] To further improve the switching characteristics of LDMOS, SiC material can be used for device fabrication. However, the on-resistance and output capacitance of SiC LDMOS have a significant impact on high-frequency characteristics and need to be further reduced. Summary of the Invention

[0004] The main objective of this invention is to provide a superjunction LDMOS device to solve the problems of large on-resistance and output capacitance in the prior art.

[0005] To achieve the above objectives, according to one aspect of the present invention, a superjunction LDMOS device is provided. The superjunction LDMOS device includes: an epitaxial layer disposed on a semiconductor substrate, having a source region and a drain region spaced apart therein, the epitaxial layer having a first surface away from the semiconductor substrate; a drift region located in the epitaxial layer and disposed near or in contact with the first surface; and a plurality of doped regions located in the drift region, the plurality of doped regions comprising multiple columns distributed along a first direction, the doped regions in adjacent columns being staggered, the first direction being the direction from the source region to the drain region.

[0006] Furthermore, the epitaxial layer has a second surface opposite to the first surface, and the doped region extends from the first surface to the second surface.

[0007] Furthermore, the doping concentrations of the multiple doped regions are equal.

[0008] Furthermore, the projected areas of the multiple doped regions on the epitaxial layer are equal.

[0009] Furthermore, doped regions located in the same column constitute doped region units, and adjacent doped region units are arranged at equal intervals.

[0010] Furthermore, the spacing between adjacent doped regions in different columns is equal.

[0011] Furthermore, the doped regions located in the same column are spaced apart along a second direction, which is parallel to the epitaxial layer and perpendicular to the first direction.

[0012] Furthermore, the direction from the drain region to the source region is the third direction, and the multiple doped regions include a first part near the source region and a second part near the drain region. Both the first part and the second part include multiple rows of doped regions. The doping concentration of the multiple rows of doped regions in the first part increases along the third direction, and the doping concentration of the multiple rows of doped regions in the second part increases along the first direction.

[0013] Furthermore, the direction from the drain region to the source region is the third direction, and the multiple doped regions include a first part near the source region and a second part near the drain region. Both the first part and the second part include multiple rows of doped regions. The projected area of ​​the multiple rows of doped regions in the first part on the first surface increases along the third direction, and the projected area of ​​the multiple rows of doped regions in the second part on the first surface increases along the first direction.

[0014] Furthermore, the direction from the drain region to the source region is the third direction. The multiple doped regions include a first part near the source region and a second part near the drain region. Both the first and second parts include multiple columns of doped regions. The doped regions in the same column constitute a doped region unit. The spacing between adjacent doped region units in the first part decreases along the third direction, and the spacing between adjacent doped region units in the second part decreases along the first direction.

[0015] According to the technical solution of the present invention, a superjunction LDMOS device is provided. The device includes: a superjunction LDMOS device disposed on a semiconductor substrate, the superjunction LDMOS device including: an epitaxial layer disposed on the semiconductor substrate, the epitaxial layer having source and drain regions spaced apart, the epitaxial layer having a first side away from the semiconductor substrate; a drift region located on the first side, the drift region having a first surface away from the epitaxial layer; and multiple doped regions including multiple columns distributed along a first direction, with multiple doped regions in adjacent columns being staggered, the first direction being the direction from the source region to the drain region. By arranging the multiple doped regions in an alternating pattern in adjacent columns within the drift region, with a certain positional offset between the multiple doped regions in adjacent columns, the distance between each doped region and the drift region can be balanced. This superjunction structure can compensate for the charge deficiency caused by the substrate-assisted depletion effect, assist in depleting excess carriers in the doped regions, effectively widen the depletion region width, thereby adjusting the electric field distribution in the drift region. This reduces the electric field peak value near the bulk region, effectively improving the device breakdown voltage, further reducing the lateral drift region width and increasing the drift region doping concentration. Consequently, the on-resistance and output capacitance of the device are further reduced. Furthermore, the alternating arrangement of multiple doped regions allows for a more uniform distribution of the doped regions in the drift region, achieving a more flattened electric field modulation and effectively balancing the electric field in the drift region. Attached Figure Description

[0016] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0017] Figure 1 A cross-sectional structural schematic diagram of a superjunction LDMOS device according to an embodiment of the present invention is shown;

[0018] Figure 2 A cross-sectional structural schematic diagram of another superjunction LDMOS device according to an embodiment of the present invention is shown;

[0019] Figure 3 It shows Figure 1 or Figure 2 The diagram shows a cross-sectional view of a superjunction LDMOS device along the DD' direction.

[0020] The above figures include the following reference numerals:

[0021] 10. Semiconductor substrate; 20. Buffer layer; 30. Epitaxial layer; 40. Body region; 50. Drift region; 60. Drain region; 70. Body region contact region; 80. Drain region buffer layer; 90. First metal layer; 100. First connection portion; 110. Second connection portion; 120. Third connection portion; 130. Gate; 131. Gate oxide layer; 140. Source region; 150. Doped region; 160. Doped region cell. Detailed Implementation

[0022] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0023] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] As mentioned in the background section, superjunction LDMOS devices, as a type of power device, are widely used due to their superior frequency characteristics. However, the on-resistance and output capacitance of superjunction LDMOS devices have a significant impact on their high-frequency characteristics. Therefore, in order to improve the characteristics of superjunction LDMOS devices, it is necessary to further reduce their on-resistance and output capacitance.

[0026] To address the aforementioned technical problems, the inventors of this application propose a superjunction LDMOS device. This superjunction LDMOS device is disposed on a semiconductor substrate, which has a source region and a drain region. The superjunction LDMOS device includes: an epitaxial layer disposed on the semiconductor substrate, the epitaxial layer having a first surface away from the semiconductor substrate; a drift region located in the epitaxial layer and disposed near or in contact with the first surface; and multiple doped regions located in the drift region, the multiple doped regions comprising multiple columns distributed along a first direction, with adjacent columns of doped regions alternately arranged. The first direction is the direction from the source region to the drain region.

[0027] For the aforementioned superjunction LDMOS device, the direction from the source region to the drain region on the semiconductor substrate is defined as the first direction. By distributing multiple columns of doped regions along the first direction and staggering the multiple doped regions in adjacent columns, a certain positional offset is achieved between the multiple doped regions in adjacent columns. This allows the multiple doped regions to be more evenly distributed in the drift region, thereby enabling more flattened electric field control and effectively balancing the electric field in the drift region. Furthermore, by adding multiple doped regions, each doped region forms a superjunction structure with the drift region. This superjunction structure can shorten the lateral drift region width of the device, further reducing the on-resistance and output capacitance of the device.

[0028] For example, such as Figure 1As shown, the superjunction LDMOS device is disposed on a semiconductor substrate 10, and the semiconductor substrate 10 has a source region 140 and a drain region 60 spaced apart. In some optional embodiments, the superjunction LDMOS device further includes: a buffer layer 20, an epitaxial layer 30, a body region 40, a drift region 50, a drain region 60, a body region contact region 70, a drain region buffer layer 80, a first metal layer 90, a first connection portion 100, a second connection portion 110, a third connection portion 120, a gate 130, a gate oxide layer 131, and a source region 140.

[0029] In the above example, the buffer layer 20 is located on one side of the semiconductor substrate 10, and the semiconductor substrate 10 is of the first doping type. The doping type of the buffer layer 20 is opposite to that of the semiconductor substrate 10. The epitaxial layer 30 is disposed on the side of the buffer layer 20 away from the semiconductor substrate 10. The epitaxial layer 30 has a first surface away from the semiconductor substrate 10, and the doping type of the epitaxial layer 30 is the same as that of the buffer layer 20. On the side of the epitaxial layer 30 away from the buffer layer 20, a body region 40, a drift region 50, and a drain region 60 are sequentially disposed. The doping type of the drift region 50 is opposite to that of the epitaxial layer 30, the doping type of the body region 40 is opposite to that of the drift region 50, and the doping type of the drain region 60 is the same as that of the drift region 50. On the side of the body region 40 away from the drift region 50, a body region contact region 70 and a source region 140 are sequentially disposed. The drain region 60 is disposed... On the side of the drain buffer layer 80 away from the drift region 50, and on the side of the body region 40, body contact region 70, drift region 50, drain buffer layer 80 and drain region 60 away from the epitaxial layer 30, the gate 130 partially covers part of the surface of the body region 40 located in the first surface, and another part of the gate 130 covers part of the surface of the drift region 50 located in the first surface. The gate oxide layer 131 is located on the side of the epitaxial layer 30 near the gate 130. The device also includes a first metal layer 90, which is located on the side away from the body region 40, drift region 50 and drain region 60. A first connection portion 100 connects the first metal layer 90 and the source region 140, a second connection portion 110 connects the first metal layer 90 and the drain region 60, and a third connection portion 120 connects the first metal layer 90 and the semiconductor substrate 10.

[0030] like Figure 1 As shown, in some optional embodiments, the superjunction LDMOS device is further provided with a plurality of doped regions 150. When the direction from the source region 140 to the drain region 60 is taken as the first direction A, any one of the plurality of doped regions 150 extends along the first direction A and does not overlap with the adjacent doped region 150. That is, the plurality of doped regions 150 are divided into multiple columns arranged along the first direction A, and the doped regions 150 in adjacent columns are staggered.

[0031] from Figure 1 As can be seen, the doped regions 150 in adjacent columns are staggered along the first direction A. Since the doping type of each doped region 150 is opposite to that of the drift region 50, each doped region 150 and the drift region 50 form a superjunction structure. Each superjunction structure can cancel the excess charge around it, improve the hot carrier injection effect, and thus modulate the charge imbalance problem in the drift region 50 of the superjunction LDMOS device, so that the doped region 150 can be fully depleted, thereby improving the breakdown voltage of the device. Furthermore, since the drift region 50 has a doped region 150 with a doping type opposite to that of the drift region 50, an accumulation region can be introduced into the channel of the device, thereby shortening the effective gate length and improving the carrier mobility in the channel. Moreover, the superjunction structure formed by the multiple doped regions and the drift region can help deplete the excess carriers in the doped region, thereby reducing the lateral drift region width of the device and effectively reducing the on-resistance and output capacitance of the device. Since the doped region 150 is located in the drift region 50, it can increase the doping concentration in the drift region 50, thereby further reducing the on-resistance of the device. In addition, since the multiple doped regions 150 are independent regions arranged at intervals, the robustness of the device is further improved.

[0032] It should be noted that the cross-sectional shape of the doped region 150 along the DD' direction can be circular, rectangular, or any other arbitrary shape, and the present invention does not impose any specific limitations.

[0033] To facilitate faster removal of holes from the device body from the injected drift region 50, in some alternative embodiments, the epitaxial layer 30 has a second surface opposite to the first surface, and the doped region 150 extends from the first surface to the second surface, such as... Figure 2 As shown. Optionally, the doped region 150 may further extend from the first surface to the side of the epitaxial layer 30 away from the drift region 50. The arrangement of the doped region 150 in this embodiment effectively accelerates the hole extraction speed in the device drift region 50, further improving the hot carrier injection effect within the device, thereby enhancing the switching performance of the superjunction LDMOS device.

[0034] In some optional embodiments, the doping concentration of the plurality of doped regions 150 is equal. In the above embodiments, for the plurality of superjunction structures formed by the plurality of doped regions 150 and the drift region 50, since the doping concentration of each doped region 150 is equal, the modulation capability of each superjunction structure formed by the doped region 150 and the drift region 50 is the same throughout the entire drift region 50. Therefore, the plurality of superjunction structures can achieve modulation of the electric field in the entire drift region 50 to achieve the purpose of balancing the bulk electric field in the device. Furthermore, since the doped region 150 is located in the drift region 50, it can increase the doping concentration in the drift region 50, thereby further reducing the on-resistance of the device.

[0035] In some optional embodiments, the projected areas of the multiple doped regions 150 on the epitaxial layer 30 are equal. The projected area can be understood as the area of ​​the projected region after orthographic projection of the doped regions 150 onto the epitaxial layer 30. The projected region of the doped regions 150 on the epitaxial layer 30 can be circular; in other optional embodiments, the projected region of the doped regions 150 on the epitaxial layer 30 can also be rectangular, such as... Figure 3 As shown.

[0036] In the above embodiments, by setting the projected areas of the multiple doped regions 150 on the epitaxial layer to be equal, the superjunction structure formed by each doped region 150 and the drift region 50 in the entire drift region 50 has the same ability to modulate the electric field. Therefore, the multiple superjunction structures can achieve electric field modulation in the entire drift region 50 to achieve the purpose of balancing the bulk electric field in the device.

[0037] In some optional embodiments, doped regions 150 located in the same column constitute a doped region unit 160, and adjacent doped region units 160 are equally spaced. In the superjunction LDMOS device, the drift region 50 contains multiple doped regions 150. In the above embodiment, the multiple doped regions 150 in the drift region 50 are divided into multiple columns, and these multiple columns of doped regions 150 are arranged sequentially along a first direction A. Each column of doped regions 150 constitutes a doped region unit 160, and adjacent doped region units 160 are equally spaced, with multiple doped regions 150 in adjacent units being staggered. Further optionally, each doped region unit 160 includes multiple doped regions 150, and the number of doped regions 150 in each doped region unit 160 can be the same or different.

[0038] In the above embodiments, the adjacent doped region units 160 are arranged at equal intervals, so that the superjunction structure in the first direction A is uniformly distributed along the first direction A, and the bulk electric field in the drift region 50 is uniformly modulated in the first direction A, thereby maintaining the overall breakdown voltage of the device. Furthermore, since the multiple doped region units 160 are independent regions arranged at intervals, the robustness of the device is further improved.

[0039] In some optional embodiments, the spacing between adjacent doped regions 150 in different columns is equal. In the above embodiments, the number of doped regions 150 in adjacent columns can be the same or different. Since the multiple doped regions 150 in adjacent columns are distributed in the drift region 50 in an alternating manner, there is a certain positional offset between the doped regions 150 in two adjacent columns. That is, in the above embodiments, taking one doped region 150 in any column as a reference, the distance between the two doped regions 150 in an adjacent column and the doped region 150 used as a reference is equal, and so on. In the first direction A, the spacing between adjacent doped regions 150 in different columns is equal.

[0040] In the above embodiments, by using adjacent doped regions 150 located in different columns with equal spacing, the superjunction structure in the first direction A is further uniformly distributed along the first direction A, so that the superjunction structure formed by each doped region 150 and the drift region 50 has the same electric field modulation capability in the drift region 50, thereby maintaining the overall breakdown voltage of the device and achieving electric field modulation in the entire drift region 50, thus achieving the purpose of balancing the bulk electric field in the device.

[0041] In some alternative embodiments, doped regions 150 located in the same column are spaced apart along a second direction B, which is parallel to the epitaxial layer and perpendicular to the first direction A, such as... Figure 3 As shown. The first direction A is the direction from the source region 140 to the drain region 60. Each column includes multiple doped regions 150, and adjacent doped regions 150 in each column are spaced apart along the second direction B. Further optionally, the spacing between adjacent doped regions 150 in each column is equal.

[0042] In the above embodiments, by arranging the doped regions 150 located in the same column at intervals along the second direction B, each doped region 150 is independently disposed in the drift region 50, and the electric field in the drift region 50 is modulated more evenly, thereby improving the robustness of the device.

[0043] In some alternative embodiments, the plurality of doped regions 150 include multiple columns distributed along a first direction A, with the doped regions 150 in adjacent columns being staggered. The direction from the drain region 60 to the source region 140 is a third direction C. The plurality of doped regions 150 include a first portion near the source region 140 and a second portion near the drain region 60. Both the first portion and the second portion include multiple columns of doped regions 150. The doping concentration of the multiple columns of doped regions 150 in the first portion increases along the third direction C, and the doping concentration of the multiple columns of doped regions 150 in the second portion increases along the first direction A.

[0044] The above-described implementation improves the ability of each superjunction structure in the drift region 50 to enhance the hot carrier injection effect. The superjunction structure increases uniformly from the center of the drift region 50 along the first direction AA and the third direction CC, and the doped regions 150 between adjacent columns are staggered. This reduces the electric field peaks near the source region 140 and near the drain region 60 in the drift region 50, while making the electric field in the drift region 50 flatter, thereby balancing the electric field in the drift region 50. Furthermore, due to the presence of superjunction structures in the drift region 50, the auxiliary depletion effect of the superjunctions can shorten the effective gate length, reduce the lateral drift region width of the device, thereby increasing the saturation current and reducing the output capacitance and on-resistance of the device.

[0045] In some alternative embodiments, the plurality of doped regions 150 include multiple columns distributed along a first direction A, with the doped regions 150 in adjacent columns being staggered. The direction from the drain region 60 to the source region 140 is a third direction C. The plurality of doped regions 150 include a first portion near the source region 140 and a second portion near the drain region 60. Both the first portion and the second portion include multiple columns of doped regions 150. The projected area of ​​the multiple columns of doped regions 150 in the first portion on the first surface increases along the third direction C, and the projected area of ​​the multiple columns of doped regions 150 in the second portion on the first surface increases along the first direction A.

[0046] In the above embodiment, since the projected area of ​​the multi-column doped region 150 in the first part increases along the third direction C on the first surface, and the projected area of ​​the multi-column doped region 150 in the second part increases along the first direction A on the first surface, and the doped regions 150 in adjacent columns are staggered, the electric field peaks on the side near the source region 140 and the side near the drain region 60 during the above drift are reduced. While reducing the electric field peaks on both sides of the drift region 50, the electric field in the drift region 50 is made flatter, thereby achieving the purpose of balancing the electric field in the drift region 50.

[0047] In some optional embodiments, the plurality of doped regions 150 include multiple columns distributed along a first direction A, with the doped regions 150 in adjacent columns being staggered. The direction from the drain region 60 to the source region 140 is a third direction C. The plurality of doped regions 150 include a first portion near the source region 140 and a second portion near the drain region 60. Both the first portion and the second portion include multiple columns of doped regions 150. The doped regions 150 in the same column constitute a doped region unit 160. The spacing between adjacent doped region units 160 in the first portion decreases along the third direction C, and the spacing between adjacent doped region units 160 in the second portion decreases along the first direction A.

[0048] In the above embodiment, by decreasing the spacing of adjacent doped region units 160 in the first part along the third direction C, decreasing the spacing of adjacent doped region units 160 in the second part along the first direction A, and staggering the doped regions 150 between adjacent columns, the doped regions 150 near the source region 140 and near the drain region 60 are made more dense, and the electric field peaks near the source region 140 and near the drain region 60 in the drift region 50 are reduced. While reducing the electric field peaks on both sides of the drift region 50, the electric field in the drift region 50 is made flatter, thereby achieving the purpose of balancing the electric field in the drift region.

[0049] As can be seen from the above description, the embodiments of the present invention achieve the following technical effects:

[0050] 1. The structure of this invention can compensate for the charge deficiency caused by the substrate-assisted depletion effect, assist the drift region in depleting excess carriers in the doped region, effectively widen the width of the depletion region, thereby adjusting the electric field distribution in the drift region, reducing the electric field peak on the side near the bulk region, achieving the purpose of balancing the electric field in the drift region, thereby effectively improving the device breakdown voltage, further reducing the lateral drift region width of the device and increasing the drift region doping concentration, thereby further reducing the on-resistance and output capacitance of the device;

[0051] 2. By arranging the multiple doped regions in an alternating pattern of adjacent columns within the drift region, with a certain positional offset between adjacent columns, the doped regions are more evenly distributed within the drift region, achieving a more flattened electric field control and effectively balancing the electric field in the drift region. Furthermore, since the multiple doped regions are set as independent regions with intervals, the robustness of the device can be effectively improved.

[0052] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A superjunction LDMOS device, characterized in that, The superjunction LDMOS device is disposed on a semiconductor substrate, and the superjunction LDMOS device includes: An epitaxial layer is disposed on the semiconductor substrate, the epitaxial layer having source and drain regions spaced apart, and the epitaxial layer having a first surface remote from the semiconductor substrate; A drift region is located in the epitaxial layer and is disposed near or in contact with the first surface; Multiple doped regions are located in the drift region, and the multiple doped regions include multiple columns distributed along a first direction, with the doped regions in adjacent columns being staggered. The first direction is the direction from the source region to the drain region. The epitaxial layer has a second surface opposite to the first surface, and the doped region extends from the first surface to the second surface; The direction from the drain region to the source region is a third direction. The plurality of doped regions include a first portion near the source region and a second portion near the drain region. Both the first portion and the second portion include multiple columns of the doped regions. The doping concentration of the multiple columns of doped regions in the first portion increases along the third direction, and the doping concentration of the multiple columns of doped regions in the second portion increases along the first direction.

2. The superjunction LDMOS device according to claim 1, characterized in that, The doping concentrations of the multiple doped regions are equal.

3. The superjunction LDMOS device according to claim 1, characterized in that, The projected areas of the multiple doped regions on the epitaxial layer are equal.

4. The superjunction LDMOS device according to claim 1, characterized in that, The doped regions located in the same column constitute a doped region unit, and adjacent doped region units are arranged at equal intervals.

5. The superjunction LDMOS device according to claim 4, characterized in that, The spacing between adjacent doped regions located in different columns is equal.

6. The superjunction LDMOS device according to any one of claims 1 to 5, characterized in that, The doped regions located in the same column are spaced apart along a second direction, which is parallel to the epitaxial layer and perpendicular to the first direction.

7. The superjunction LDMOS device according to claim 1, characterized in that, The direction from the drain region to the source region is a third direction. The plurality of doped regions include a first portion near the source region and a second portion near the drain region. Both the first portion and the second portion include multiple columns of the doped regions. The projected area of ​​the multiple columns of doped regions in the first portion on the first surface increases along the third direction, and the projected area of ​​the multiple columns of doped regions in the second portion on the first surface increases along the first direction.

8. The superjunction LDMOS device according to claim 1, characterized in that, The direction from the drain region to the source region is a third direction. The plurality of doped regions include a first part near the source region and a second part near the drain region. Both the first part and the second part include multiple columns of doped regions. The doped regions in the same column constitute a doped region unit. The spacing between adjacent doped region units in the first part decreases along the third direction, and the spacing between adjacent doped region units in the second part decreases along the first direction.

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