Three-dimensional memory structure

Abstract

This invention provides a three-dimensional memory structure, comprising a semiconductor substrate, a stacked structure on the semiconductor substrate, the stacked structure including alternating gate layers and insulating dielectric layers, a channel via and an array common-source structure passing through the stacked structure in a direction perpendicular to the semiconductor substrate, with a spacing between the channel via and the array common-source structure, and a source region located within the semiconductor substrate. The array common-source structure includes an inner core and an outer layer surrounding the inner core, the inner core including a polysilicon filling layer, and the outer layer including a metal layer, the outer layer being electrically connected to the source region. The array common-source structure of this invention, including the outer layer and the inner core, can improve the overall stress, resistance, and leakage current of the device through the filling of the inner core, thereby increasing device speed and optimizing device performance.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor design and manufacturing, and in particular relates to a three-dimensional memory structure. Background Technology

[0002] With the development of planar flash memory, semiconductor manufacturing processes have made tremendous progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, limitations of existing development technologies, and limits of storage electron density. Against this backdrop, in order to solve the difficulties encountered by planar flash memory and to pursue lower production costs per unit of memory cell, three-dimensional memory structures have emerged. Three-dimensional memory structures allow each memory die in a memory device to have a greater number of memory cells.

[0003] In non-volatile memories, such as NAND flash memory, one way to increase memory density is by using vertical memory arrays, i.e., 3D NAND flash memory. The existing 3D NAND flash memory fabrication process mainly includes: first, forming a stacked structure of alternating sacrificial layers and inter-gate dielectric layers, and then removing the sacrificial layers and filling them to form gate layers to obtain 3D NAND flash memory. With the development of the process, in order to achieve higher storage density, the number of stacked layers in 3D NAND flash memory also needs to be significantly increased, such as from 32 layers to 64 layers, and then to 96 layers or even 128 layers. However, with the increase in the number of stacked layers in 3D NAND flash memory, the filling of gate trenches makes it difficult to effectively improve the stress and resistance of the device structure, and the leakage current increases. At the same time, the process difficulty increases, such as the etching difficulty becomes more and more difficult. In order to reduce the challenge of etching holes in the stacked structure, efforts have been made to compress the height of each sacrificial layer to thin the height of the entire stacked structure. However, this will cause the resistance (RS) of the gate word line layer (WL) to increase sharply, affecting device performance.

[0004] Therefore, it is necessary to provide a three-dimensional memory structure and fabrication method to solve the above-mentioned problems in the prior art. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a three-dimensional memory structure to solve the problems of difficulty in effectively improving device structure stress, resistance and leakage current caused by gate trench filling, and increased gate word line resistance caused by compressing the height of the sacrificial layer in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a method for fabricating a three-dimensional memory structure, the method comprising the following steps:

[0007] Provide semiconductor substrates;

[0008] A stacked structure is formed on the semiconductor substrate, and a channel hole and a gate spacer with a spacing between them are formed in the stacked structure. Both the channel hole and the gate spacer penetrate the stacked structure in a direction perpendicular to the semiconductor substrate.

[0009] A source region is formed in the semiconductor substrate corresponding to the bottom of the gate trench; and

[0010] An inner core and an outer layer surrounding the inner core are formed within the gate trench to form an array common source structure, wherein the inner core and the outer layer are made of different materials, and the outer layer is electrically connected to the source region.

[0011] Optionally, the laminated structure includes alternating stacked sacrificial layers and insulating dielectric layers, and the fabrication method includes the following steps:

[0012] The sacrificial layer is removed based on the gate trench to form a sacrificial gap; and

[0013] A gate layer is formed within the sacrificial gap.

[0014] Optionally, the gate spacer includes N sub-gate spacers that are connected vertically, where N is an integer greater than or equal to 2.

[0015] Optionally, the channel hole includes N sub-channel holes that are connected vertically, each sub-channel hole corresponds to each sub-gate spacer, and at least the first to the (N-1)th sub-channel holes are fabricated using the same process as the first to the (N-1)th sub-gate spacers.

[0016] Optionally, the first sub-channel via to the (N-1)th sub-channel via are fabricated using the same process as the first sub-gate spacer to the (N-1)th sub-gate spacer. After forming the (N-1)th sub-channel via and the (N-1)th sub-gate spacer, the process includes forming the Nth sub-channel via and fabricating the channel via, and filling the channel via with a functional material layer. After filling the functional material layer, the process further includes forming the Nth sub-gate spacer to fabricate the gate spacer.

[0017] Optionally, the stacked structure includes N sub-stacked structures stacked sequentially in a direction perpendicular to the surface of the semiconductor substrate, each sub-stacked structure corresponding one-to-one with each sub-gate trench, wherein the method for forming the gate trench and the stacked structure includes:

[0018] A bottom sub-layer structure is formed on the semiconductor substrate;

[0019] A bottom sacrificial column is formed in the bottom sub-layer structure, penetrating the bottom sub-layer structure;

[0020] A top sub-layer structure is formed on the bottom sub-layer structure and the bottom sacrificial pillar;

[0021] A top-level sub-gate spacer is formed within the top-level sub-stack structure to expose the lower-level sacrificial pillar;

[0022] The sacrificial pillar below is removed through the top-layer sub-gate slot.

[0023] Optionally, after forming the gate spacer, the method further includes the step of forming an isolation layer on the sidewall of the gate spacer, and the outer layer is formed on the isolation layer.

[0024] Optionally, after forming the isolation layer, the method further includes the step of: preparing a transition layer on the surface of the isolation layer, wherein the outer layer is formed on the surface of the transition layer.

[0025] Optionally, after forming the channel hole, the method further includes the steps of: forming a high dielectric constant dielectric layer on the inner wall of the channel hole, forming a functional sidewall layer on the surface of the high dielectric constant dielectric layer, and forming a channel layer on the surface of the functional sidewall layer.

[0026] Optionally, the fabrication method further includes the step of fabricating a bottom stacked structure on the semiconductor substrate, wherein the stacked structure is formed on the bottom stacked structure, and the method further includes the step of fabricating a bottom epitaxial layer at the bottom of the channel hole, wherein the bottom epitaxial layer is in contact with the bottom stacked structure, and a sidewall protective layer is formed on the outer wall of a portion of the epitaxial layer based on the bottom stacked structure.

[0027] Optionally, the process of forming the outer layer further includes the step of forming a gate spacer cavity in the gate spacer based on the outer layer, the gate spacer cavity constituting the inner core, wherein the outer layer surrounds the gate spacer cavity.

[0028] Optionally, after forming the outer layer, the step further includes: forming a conductive plug extending into the top of the gate spacer.

[0029] Optionally, the inner core includes a polycrystalline silicon filling layer; the outer layer includes a metal layer.

[0030] Optionally, the metal layer includes a fluorine-free tungsten layer.

[0031] The present invention also provides a three-dimensional memory structure, which is preferably prepared using the three-dimensional memory preparation method provided by the present invention, and the three-dimensional memory structure includes:

[0032] Semiconductor substrate;

[0033] A stacked structure located on the semiconductor substrate, the stacked structure comprising alternating gate layers and insulating dielectric layers;

[0034] A channel hole and an array common source structure pass through the stacked structure in a direction perpendicular to the semiconductor substrate, wherein there is a gap between the channel hole and the array common source structure;

[0035] The source region is located within the semiconductor substrate;

[0036] The array common source structure includes: an inner core and an outer layer surrounding the inner core, wherein the inner core and the outer layer are made of different materials, and the outer layer is electrically connected to the source electrode.

[0037] Optionally, the gate spacer includes N sub-gate spacers that are connected vertically, where N is an integer greater than or equal to 2.

[0038] Optionally, the channel hole includes N sub-channel holes that are connected vertically, and each sub-channel hole corresponds to each sub-gate spacer; the stacking structure includes N sub-stacked structures that are stacked sequentially in a direction perpendicular to the surface of the semiconductor substrate, and each sub-stacked structure corresponds to each sub-gate spacer.

[0039] Optionally, the array common source structure further includes an isolation layer surrounding the outer layer.

[0040] Optionally, the array common source structure further includes a transition layer located between the isolation layer and the outer layer.

[0041] Optionally, the three-dimensional memory structure further includes a high dielectric constant dielectric layer, a functional sidewall layer, and a channel layer stacked sequentially, wherein the high dielectric constant dielectric layer is formed on the inner wall of the channel hole.

[0042] Optionally, the three-dimensional memory structure further includes a gate spacer cavity formed in the gate spacer, the gate spacer cavity constituting the inner core, and the outer layer surrounding the gate spacer cavity.

[0043] Optionally, the three-dimensional memory structure further includes a conductive plug extending into the top of the gate slot.

[0044] Optionally, the inner core includes a polycrystalline silicon filling layer; the outer layer includes a metal layer.

[0045] Optionally, the metal layer includes a fluorine-free tungsten layer.

[0046] As described above, the three-dimensional memory structure and fabrication method of the present invention fill the gate spacer with a structure that includes at least an inner core and an outer layer surrounding the inner core. Based on the conductivity of the outer layer, the filling of the inner core can improve the overall stress, resistance, and leakage current of the device. Furthermore, fabricating a gate spacer cavity within the gate spacer can alleviate the stress caused by the material layer, reduce the stress on the entire device structure, decrease device resistance, and improve device performance. Simultaneously, fabricating the gate spacer of the three-dimensional memory with at least two sub-gate spacers connected vertically allows for easier control of the fabrication of individual sub-gate spacers, thereby reducing their critical dimension (CD). This increases the distance between the channel via and the gate spacer, increasing the length of the subsequent gate layer, reducing the resistance of the gate layer, improving device speed, and optimizing device performance. Attached Figure Description

[0047] Figure 1 The diagram shows the process flow for fabricating the three-dimensional memory structure of this invention.

[0048] Figure 2 The illustration shows a semiconductor substrate provided in the fabrication of the three-dimensional memory structure of the present invention.

[0049] Figure 3 The diagram illustrates the formation of a stacked structure during the fabrication of the three-dimensional memory structure of this invention.

[0050] Figure 4 The illustration shows the fabrication of a three-dimensional memory structure, including the formation of gate trenches and channel holes, as an example of the present invention.

[0051] Figure 5 The illustration shows the fabrication of a three-dimensional memory structure to form the first sub-gate spacer in an example of the present invention.

[0052] Figure 6 The illustration shows the fabrication of a three-dimensional memory structure to form the first sacrificial pillar, as shown in an example of the present invention.

[0053] Figure 7 The illustration shows a three-dimensional memory structure fabrication process forming a second sub-layer structure, as shown in an example of the present invention.

[0054] Figure 8 The illustration shows the fabrication of a second sub-gate spacer in a three-dimensional memory structure according to an example of the present invention.

[0055] Figure 9 The illustration shows the fabrication of a three-dimensional memory structure, including the formation of gate trenches and channel holes, as an example of the present invention.

[0056] Figure 10(a) shows a top view of the formation of a gate trench during the fabrication of an example three-dimensional memory structure according to the present invention.

[0057] Figure 10(b) shows a top view illustration of the formation of a gate trench during the fabrication of an example three-dimensional memory structure according to the present invention.

[0058] Figure 11(a) shows an illustration of the fabrication of a three-dimensional memory structure to form a second sacrificial pillar in an example of the present invention.

[0059] Figure 11(b) shows an illustration of the fabrication of a three-dimensional memory structure to form a second sub-channel hole in an example of the present invention.

[0060] Figure 12 The diagram shows the formation of a high dielectric constant dielectric layer, a functional sidewall layer, and a channel layer in the channel hole during the fabrication of the three-dimensional memory structure of this invention.

[0061] Figure 13 The diagram shows the formation of the sacrificial epitaxial layer during the fabrication of the three-dimensional memory structure of this invention.

[0062] Figure 14 The diagram shows the formation of an insulating layer during the fabrication of the three-dimensional memory structure of this invention.

[0063] Figure 15 The illustration shows the removal of the sacrificial epitaxial layer during the fabrication of the three-dimensional memory structure of this invention.

[0064] Figure 16 The illustration shows the removal of the bottom sacrificial layer during the fabrication of the three-dimensional memory structure of this invention.

[0065] Figure 17 The diagram shows the formation of the sidewall protective layer during the fabrication of the three-dimensional memory structure of this invention.

[0066] Figure 18 The diagram illustrates the formation of sacrificial gaps during the fabrication of the three-dimensional memory structure of this invention.

[0067] Figure 19(a) shows a diagram illustrating the formation of a gate layer during the fabrication of an example three-dimensional memory structure according to the present invention.

[0068] Figure 19(b) shows a diagram illustrating the formation of a gate layer during the fabrication of an example three-dimensional memory structure according to the present invention.

[0069] Figure 20(a) shows an example of the formation of the outer layer and inner core in the fabrication of the three-dimensional memory structure of the present invention.

[0070] Figure 20(b) shows another example of the formation of the outer layer and inner core in the fabrication of the three-dimensional memory structure of the present invention.

[0071] Figure 21 The diagram shows the formation of conductive plugs during the fabrication of the three-dimensional memory structure of this invention.

[0072] Figure 22 The diagram illustrates the formation of the top cover layer during the fabrication of the three-dimensional memory structure of this invention.

[0073] Figure 23 This is shown as an example of the arrangement of channel holes and gate slots in the three-dimensional memory structure of the present invention.

[0074] Figure 24 The graph shows the relationship between resistance and gate height.

[0075] Component designation explanation

[0076] 101 semiconductor substrate

[0077] 102 stacked structure

[0078] 102a sub-stacked structure

[0079] 103 Insulating Dielectric Layer

[0080] 104 Sacrificial Layer

[0081] 105 bottom stacked structure

[0082] 105a bottom dielectric layer

[0083] 105b bottom sacrificial layer

[0084] 106 channel holes

[0085] 106a sub-channel hole

[0086] 107 gate spacer

[0087] 107a Subgate Spacing

[0088] 108 Sacrificial Pillars

[0089] 109 high dielectric constant dielectric layer

[0090] 110 Functional Sidewall Layer

[0091] 111 channel layer

[0092] 112 Filler Insulation Layer

[0093] 113 Insulation Gap

[0094] 114 Sacrificial Epitaxial Layer

[0095] 115 insulation layer

[0096] 116 Sidewall Protective Layer

[0097] 117 gate layer

[0098] 118 stacked structure

[0099] 118a sub-stacked structure

[0100] 119 isolation layer

[0101] 120 outer layer

[0102] 121 Source Region

[0103] 122 conductive plug

[0104] 123 inner core

[0105] 124a First Cover Layer

[0106] 124b Second Cover Layer

[0107] 125 connecting block

[0108] 126 Top Cover Layer

[0109] 127 Bottom Epitaxial Layer

[0110] Steps S1 to S2 Detailed Implementation

[0111] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. For ease of explanation, when detailing the embodiments of the present invention, the cross-sectional views showing the device structure are partially enlarged, not according to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0112] For ease of description, spatial relation terms such as "below," "below," "lower than," "below," "above," and "upper" may be used herein to describe the relationship between an element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for the device in use or operation. Furthermore, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more layers in between. In the context of this application, the described structure of a first feature "above" a second feature may include embodiments where the first and second features are formed in direct contact, or embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact. It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the invention; therefore, the illustrations only show components relevant to the invention and are not drawn according to the actual number, shape, and size of components in implementation. In actual implementation, the shape, quantity, and proportion of each component may be arbitrarily changed, and the component layout may be more complex.

[0113] Example 1:

[0114] like Figure 1 As shown, the present invention provides a method for fabricating a three-dimensional memory structure, comprising the following steps:

[0115] Provide semiconductor substrates;

[0116] A stacked structure is formed on the semiconductor substrate, and a channel hole and a gate spacer with a spacing between them are formed in the stacked structure. Both the channel hole and the gate spacer penetrate the stacked structure in a direction perpendicular to the semiconductor substrate.

[0117] A source region is formed in the semiconductor substrate corresponding to the bottom of the gate trench; and

[0118] An inner core and an outer layer surrounding the inner core are formed within the gate trench to form an array common source structure, wherein the inner core and the outer layer are made of different materials, and the outer layer is electrically connected to the source region.

[0119] The fabrication process of the three-dimensional memory structure in this invention will be described in detail below with reference to the accompanying drawings.

[0120] like Figure 1 S1 and Figure 2 As shown, a semiconductor substrate is provided.

[0121] Specifically, the semiconductor substrate 101 can be selected according to the actual needs of the device. The semiconductor substrate 101 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, or a GOI (Germanium-on-Insulator) substrate, etc. In other embodiments, the semiconductor substrate 101 may also be a substrate containing other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide. The semiconductor substrate 101 may also be a multilayer structure, such as a silicon / germanium-silicon multilayer. In this embodiment, the semiconductor substrate 101 includes a single-crystal silicon substrate. Furthermore, the semiconductor substrate 101 can be an ion-doped substrate, which may be P-type doped or N-type doped. Multiple peripheral devices, such as field-effect transistors, capacitors, inductors, and / or pn junction diodes, may also be formed in the semiconductor substrate 101. The semiconductor substrate 101 may also have peripheral circuitry.

[0122] like Figure 1 S2 and Figure 3-12 As shown, a stacked structure 102 is formed on the semiconductor substrate 101, and a channel hole 106 and a gate spacer 107 with a spacing between them are formed in the stacked structure 102. The channel hole 106 and the gate spacer 107 both penetrate the stacked structure 102 in a direction perpendicular to the semiconductor substrate 101.

[0123] As an example, the gate spacer 107 includes N vertically connected sub-gate spacers 107a, where N is greater than or equal to 2. See [link to documentation]. Figure 4 and 9 As shown. In other embodiments, the channel hole 106 also includes N sub-channel hole structures that are connected vertically.

[0124] As an example, the stacked structure 102 includes alternating stacked sacrificial layers 104 and insulating dielectric layers 103.

[0125] Specifically, the stacked structure 102 includes alternating layers of insulating dielectric layers 103 and sacrificial layers 104. The insulating dielectric layers 103 of the stacked structure 102 include, but are not limited to, silicon dioxide layers, and the sacrificial layers 104 include, but are not limited to, silicon nitride layers. The insulating dielectric layers 103 and the sacrificial layers have a certain selectivity ratio in the same etching / etching process to ensure that the insulating dielectric layers 103 are hardly removed when the sacrificial layers are removed. The stacked structure can be formed using processes such as Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD). In one example, the stacked structure may include the insulating dielectric layers 103 and the sacrificial layers alternately stacked from bottom to top. The bottom and top layers of the stacked structure are both insulating dielectric layers 103, and the upper surface of the top insulating dielectric layer 103 is the upper surface of the stacked structure. The number of insulating dielectric layer 103 and sacrificial layer in the stacked structure may include 32 layers, 64 layers, 96 layers or 128 layers, etc. Specifically, the number of insulating dielectric layer 103 and sacrificial layer 104 in the stacked structure can be set according to actual needs, and is not limited here.

[0126] In this invention, a gate spacer 107 is fabricated in the stacked structure, and a structure comprising at least two sub-gate spacers 107a is further fabricated. Three or more sub-gate spacers 107a can be vertically connected. The arrangement of multiple sub-gate spacers 107a makes the fabrication of a single sub-gate spacer 107a easier to control, thereby reducing its critical dimension (CD), which includes the width of the gate spacer. Currently, with the increase in the number of layers in 3D memory processes, efforts are being made to control the thinning of the sacrificial layer to reduce the challenges to vias (such as gate spacers, CH), such as etching difficulty. This results in a thinner overall stacked structure, ultimately leading to a linear increase in the resistance of the filled gate layer (GL). See [link to relevant documentation]. Figure 24 As shown, this affects device performance. The solution of this invention, as shown in Figures 10(a) and 10(b), involves fabricating a gate spacer 107 comprising at least two sub-gate spacers 107a. This reduces the feature size of the gate spacer 107, decreases the width of w in the figures, and thereby increases the distance between the channel via 106 and the gate spacer 107, i.e., increases the length d. This increases the length of the subsequent gate layer, reduces the resistance of the gate layer, improves device speed, and optimizes device performance. Figure 9The cross-sectional view of the related structure can be a cross-section along the AA direction of the top view shown in Figure 10(a). Additionally, Figure 10(b) shows another schematic diagram of the positional relationship between the gate spacer and the channel via. It should be noted that, using the process of this invention, the critical dimension of the gate spacer can be reduced from 180nm to 120nm, a reduction of 50%, and the dimension d can be increased from 130nm to 160nm, resulting in a 20% reduction in resistivity after filling.

[0127] Of course, in other embodiments, the gate trench 107 can be a through hole formed by directly penetrating the stacked structure 102, such as the gap formed by directly penetrating all the stacked layer structures 102 after the channel hole 106 is formed. In this case, the cross-sectional shape of the gate trench 107 includes an inverted trapezoid.

[0128] As an example, such as Figure 5 As shown, the stacked structure 102 includes N sub-stacked structures 102a stacked sequentially in a direction perpendicular to the surface of the semiconductor substrate 101. Each sub-stacked structure 102a corresponds one-to-one with each sub-gate spacer 107a. The method for forming the gate spacer 107a and the stacked structure 102 includes:

[0129] A bottom sub-layer structure is formed on the semiconductor substrate 101;

[0130] A bottom sacrificial column is formed in the bottom sub-layer structure, penetrating the bottom sub-layer structure;

[0131] A top sub-layer structure is formed on the bottom sub-layer structure and the bottom sacrificial pillar;

[0132] A top-level sub-gate spacer is formed within the top-level sub-stack structure to expose the lower-level sacrificial pillar;

[0133] The sacrificial pillar below is removed through the top-layer sub-gate slot.

[0134] Specifically, further, in one example, a more specific method for forming the gate spacer 107 and the stacked structure 102 is provided, the specific steps of which include:

[0135] A first sub-stacked structure is formed on the semiconductor substrate 101;

[0136] A first sub-gate spacer is formed in the first sub-stacked structure, penetrating the first sub-stacked structure;

[0137] The first sacrificial pillar is filled into the first sub-gate spacer.

[0138] A second sub-stack structure is formed on the first sub-stack structure on which the first sacrificial pillar is formed, and a second sub-gate trench is formed in the second sub-stack structure that penetrates the second sub-stack structure.

[0139] A second sacrificial pillar is formed in the second sub-gate spacer;

[0140] The subsequent sub-stack structure 102a, sub-gate trench 107a and sacrificial pillar 108 are formed on the semiconductor substrate 101 until the Nth sub-stack structure, the Nth sub-gate trench and the (N-1)th sacrificial pillar are formed, such that the top sub-gate trench exposes the sacrificial pillar in the lower sub-gate trench. When the gate trench includes two sub-gate trenches, the second gate trench is not filled.

[0141] By removing each sacrificial pillar 108 from the top sub-gate spacer, the gate spacer 107 and the stacked structure 102 are obtained.

[0142] Specifically, an example of fabrication of the gate spacer 107 and the stacked structure 102 of the present invention is provided. In the figure, two sub-gate spacers 107a are used as an example for illustration. Of course, in other examples, there can be three or more. In addition, it should be noted that the multiple sub-gate spacers 107a can be sequentially referred to as the first sub-gate spacer, the second sub-gate spacer, the third sub-gate spacer, and so on up to the Nth sub-gate spacer from the semiconductor substrate 101 upwards. Similarly, the names of each sub-stacked structure 102a and each sacrificial pillar 108 are similar, and the Nth sub-gate spacer, the Nth sub-stacked structure, and the Nth sacrificial pillar correspond one-to-one. The correspondence between the sub-gate spacer 107a and the sub-stacked structure 102a refers to the part of the material layer of the stacked structure formed on the periphery of the sub-gate spacer 107a and in contact with the sub-gate spacer 107a. The correspondence between the sub-gate spacer 107a and the sacrificial pillar 108 refers to the sacrificial pillar filled in the sub-gate spacer corresponding one-to-one with the sub-gate spacer.

[0143] In one example, such as Figure 5-11(b) As shown in the figure, the example given is one containing two sub-gate spacers 107a. Figure 5 As shown, firstly, the sub-stacked structure 102a, i.e., the first sub-stacked structure, is formed on the semiconductor substrate 101. The formation method of the sub-stacked structure is consistent with the formation method of the stacked structure described above, including the sacrificial layer and the insulating dielectric layer 103 stacked alternately. The number of each material layer is set according to the actual situation. Preferably, the bottom material layer and the top material layer of the sub-stacked structure 102a are both set as the insulating dielectric layer 103. Next, the sub-gate trench 107a, i.e., the first sub-gate trench, is formed in the formed sub-stacked structure 102a, which can be completed by etching process; then, as Figure 6 As shown, the sacrificial pillars, i.e., the first sacrificial pillars, are filled in the formed sub-gate trench 107a. This can be achieved by depositing a via-filling sacrificial material layer onto the structure surface using a deposition process, followed by chemical mechanical polishing to grind the top of the material until it is flush with the upper surface of the first sub-layer structure, thus obtaining the first sacrificial pillars. The material of each sacrificial pillar can be polycrystalline silicon. These sacrificial pillars are removed in subsequent processes. Then, as... Figure 7 As shown, the sacrificial layer and the insulating dielectric layer 103 are then alternately deposited on the structure where the first sacrificial pillar has been formed to form another sub-stack structure 102a, namely the second sub-stack structure; continuing, as... Figure 8 As shown, a second sub-gate spacer is formed in the subsequently formed second sub-stack structure, such that the second sub-gate spacer corresponds one-to-one with the previously formed first sub-gate spacer, and the upper sub-gate spacer 107a exposes the sacrificial pillar 108 filled in the corresponding lower sub-gate spacer 107a; finally, as Figure 9 As shown, the first sacrificial pillar of the lower layer is removed based on the second sub-gate trench formed on the upper layer, thereby obtaining the first sub-gate trench and the second sub-gate trench that are connected vertically, and finally obtaining the desired gate trench. The sacrificial pillars can be removed by wet etching. It should also be noted that, in an optional example, when the gate trench 107 includes three or more connected sub-gate trenches 107a, during the fabrication process, the sub-gate trenches 107a formed from the first to the penultimate layer are filled with the sacrificial pillars 108, while the last layer, i.e., the uppermost sub-gate trench 107a, is not etched; only the uppermost sub-channel via is etched, and the sacrificial layer in the other sub-channel vias is removed, forming a vertically connected via structure. Subsequently, a memory structure is formed in the via, and then the uppermost sub-gate trench is etched again, and the sacrificial layer in the other sub-gate trenches is removed, forming a vertically connected gate trench.

[0144] As an example, as shown in FIG11(a), the step of continuing to form subsequent sub-stack structures 102a, sub-gate trenches 107a and sacrificial pillars 108 on the semiconductor substrate 101 further includes: filling the Nth sub-gate trench to form the Nth sacrificial pillar.

[0145] Specifically, this example also includes the step of filling the sacrificial pillar in the topmost sub-gate trench 107a. That is, when the gate trench 107 includes N sub-gate trenches 107a, the Nth sacrificial pillar is filled in the Nth sub-gate trench. This facilitates the formation of an auxiliary material layer, such as a photoresist layer, on the gate trench, thereby facilitating other processes. For example, the gate trench can be shielded, allowing the process to be performed in the channel hole 106 in the stacked structure, thus avoiding the impact of the process in the channel hole on the gate trench 107.

[0146] As an example, the channel hole 106 includes N sub-channel holes 106 arranged vertically and vertically, each sub-channel hole 106 corresponding to each sub-gate spacer 107a, wherein at least the first sub-channel hole to the (N-1)th sub-channel hole corresponds to the first sub-gate spacer to the (N-1)th sub-gate spacer and is fabricated using the same process.

[0147] Specifically, in one example, the channel hole 106 includes N sub-channel holes 106 arranged vertically and vertically, which are sequentially arranged from the semiconductor substrate 101 upwards as the first sub-channel hole, the second sub-channel hole to the Nth sub-channel hole. In an optional example, each sub-channel hole 106a corresponds one-to-one with each sub-gate spacer 107a, that is, the Nth sub-channel hole 106a corresponds one-to-one with the Nth sub-gate spacer 107a, and the two are formed in the same sub-stack structure 102a. In an optional example, the corresponding sub-channel hole 106a and the sub-gate spacer 107a are prepared based on the same process. For example, after the first sub-stack structure 102a is formed, the first sub-gate spacer 107a and the first sub-channel hole 106 are formed in the first sub-stack structure 102a based on the same process.

[0148] As an example, the first sub-channel hole to the (N-1)th sub-channel hole correspond to the first sub-gate spacer to the (N-1)th sub-gate spacer, which are fabricated using the same process. After forming the (N-1)th sub-channel hole and the (N-1)th sub-gate spacer, the process includes forming the Nth sub-channel hole and fabricating the channel hole 106, as well as filling the channel hole 106 with a functional material layer. After filling the functional material layer, the process further includes forming the Nth sub-gate spacer to fabricate the gate spacer 107.

[0149] Specifically, in one example, referring to Figure 11(b), a fabrication process for the channel via 106 and the gate spacer 107 in a three-dimensional memory structure is provided. In this example, the (N-1)th sub-channel via and the sub-channel vias preceding it are fabricated using the same process as the (N-1)th sub-gate spacer and the sub-gate spacer preceding it. That is, a first sub-stack structure is formed on the semiconductor substrate, a first sub-gate spacer and a first sub-channel via are formed in the first sub-stack structure, and a first sacrificial pillar is filled in the first sub-gate spacer and the first sub-channel via. The above steps are repeated until the (N-1)th sub-stack structure, the (N-1)th sub-channel via, the (N-1)th sub-gate spacer are formed, and the (N-1)th sub-channel via and the (N-1)th sub-gate spacer are filled with the Nth sacrificial pillar. -1 Sacrificial pillar. After the above steps are formed, an Nth sub-stack structure is formed on the obtained structure, and an Nth sub-channel via is formed. In this example, an Nth sub-gate spacer is not formed in this step. At this time, each sacrificial pillar in each sub-channel via is removed based on the Nth sub-channel via to obtain each sub-channel via, forming the channel via 106. Then, a functional material layer is filled in the channel via. In one example, the functional material layer can be a stack composed of the high dielectric constant dielectric layer, the functional sidewall, and the channel layer mentioned above. Next, in this example, after the functional material layer is filled, an Nth sub-gate spacer is formed in the Nth sub-stack structure, thereby removing each sacrificial pillar in each sub-gate spacer based on the Nth sub-gate spacer to obtain each sub-gate spacer, forming the gate spacer.

[0150] As an example, after forming the channel hole 106, the method further includes the steps of: forming a high dielectric constant dielectric layer 109 on the inner wall of the channel hole 106, forming a functional sidewall layer 110 on the surface of the high dielectric constant dielectric layer 109, and forming a channel layer 111 on the surface of the functional sidewall layer 110.

[0151] Specifically, in one example, such as Figure 12 As shown, the method also includes the steps of forming the high dielectric constant dielectric layer 109, the functional sidewall layer 110, and the channel layer 111 in the channel hole 106. In an optional example, each sacrificial pillar is filled in the gate trench 107, and the uppermost sub-gate trench 107a is filled with the sacrificial pillar. At this time, a mask layer is formed on the obtained structure. The mask layer covers the gate trench 107 and exposes the channel hole 106 that needs to be processed. The channel hole 106 is processed based on the mask layer. For example, the sacrificial material layer in the channel hole 106 may be removed, and then a deposition process is performed in the channel hole 106, thereby protecting the gate trench 107.

[0152] Specifically, a high-dielectric-constant dielectric layer 109 is formed on the inner wall of the channel via 106, that is, a high-dielectric-constant dielectric layer 109 (high-K dielectric layer) is formed on the sidewall and bottom surface of the channel via 106. The gate layer formed subsequently is in contact with the high-dielectric-constant dielectric layer 109. Its material can be alumina or the like, and it can be formed by atomic layer deposition. The functional sidewall layer 110 is formed on the surface of the high-dielectric-constant dielectric layer 109. In an optional example, the functional sidewall layer 110 includes a barrier layer, a storage layer, and a tunneling layer (not shown in the figure) in sequence from the sidewall of the channel via 106 to the center.

[0153] The barrier layer can be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). Preferably, in this embodiment, the barrier layer is formed on the sidewall surface of the channel via 106 using ALD. The storage layer can be formed using PVD, CVD, or ALD. Preferably, in this embodiment, the storage layer is formed using ALD. The tunneling layer can be formed using PVD, CVD, or ALD. Preferably, in this embodiment, the tunneling layer is formed using ALD. In one example, the barrier layer may include, but is not limited to, a silicon oxide layer; the storage layer may include, but is not limited to, a silicon nitride layer; and the tunneling layer may include, but is not limited to, a silicon oxide layer. In one example, the barrier layer includes a silicon oxide layer, the storage layer includes a silicon nitride layer, and the tunneling layer includes a silicon oxide layer, thereby forming a functional sidewall layer of an ONO structure.

[0154] Specifically, a channel layer 111 is formed on the surface of the functional sidewall layer 110. The channel layer 111 can be formed on the surface of the functional sidewall using physical vapor deposition, chemical vapor deposition, or atomic layer deposition. Preferably, in this embodiment, the channel layer 111 is formed on the surface of the functional sidewall using atomic layer deposition. In one example, the material of the channel layer 111 may include polysilicon. Of course, in other examples, the material of the channel layer 111 may be other semiconductor materials.

[0155] Specifically, in one example, the sum of the thicknesses of the high dielectric constant dielectric layer 109, the functional sidewall, and the channel layer 111 can be less than half the width of the channel hole 106. In this case, after forming the channel layer 111, a reserved space for filling the insulating layer is still retained in the channel hole 106. When retaining the reserved space, the process also includes forming a filling insulating layer 112 within the channel hole 106. This filling insulating layer 112 can be formed using physical vapor deposition, chemical vapor deposition, or atomic layer deposition. Preferably, in this embodiment, atomic layer deposition is used to form the filling insulating layer 112 within the channel hole 106. The material of the filling insulating layer 112 can include an oxide dielectric layer, such as silicon oxide, etc., and the filling insulating layer can completely fill the channel hole 106. Additionally, in one example, the insulating gap 113 can also be formed in the filling insulating layer 112 by controlling the deposition process parameters of the filling insulating layer 112.

[0156] As an example, the fabrication of the three-dimensional memory structure further includes the step of forming a bottom epitaxial layer 127 corresponding to the bottom of the channel hole 106, wherein the bottom epitaxial layer 127 extends into the semiconductor substrate 101, and at least the channel layer 111 is in contact with the bottom epitaxial layer 127.

[0157] As an example, the method for fabricating the three-dimensional memory structure further includes the step of fabricating a bottom stacked structure 105 on the semiconductor substrate 101, wherein the stacked structure 102 is formed on the bottom stacked structure 105. In one example, a bottom epitaxial layer 127 is included, the upper surface of which is lower than the upper surface of the bottom stacked structure 105. The method for fabricating the three-dimensional memory structure further includes the step of forming a sidewall protection layer 116 on the outer wall of the bottom epitaxial layer 127 based on the bottom stacked structure 105. In an optional example, the bottom stacked structure 105 may include a bottom dielectric layer 105a and a bottom sacrificial layer 105b located between adjacent bottom dielectric layers, wherein the upper surface of the bottom epitaxial layer 127 is higher than the upper surface of the bottom sacrificial layer 105b. Optionally, the bottom dielectric layer may include, but is not limited to, a silicon oxide layer, and the bottom sacrificial layer may include, but is not limited to, a silicon nitride layer.

[0158] As an example, after forming the gate spacer 107, the following steps are also included:

[0159] like Figure 13As shown, a sacrificial epitaxial layer 114 is formed at the bottom of the gate trench 107. In one example, the thickness of the sacrificial epitaxial layer 114 is greater than the distance from the upper surface of the bottom sacrificial layer to the bottom surface of the gate trench 107. Specifically, the sacrificial epitaxial layer 114 can be formed using, but is not limited to, a selective epitaxial process (SEG).

[0160] Furthermore, such as Figure 14 As shown, an insulating isolation layer 115 is formed on the sidewall of the gate trench 107; specifically, the insulating isolation layer 115 is first formed on the bottom and sidewall of the gate trench 107, and then the insulating isolation layer 115 located at the bottom of the gate trench 107 is removed. The insulating isolation layer 115 may include, but is not limited to, a silicon oxide layer.

[0161] Next, as Figure 15 As shown, the sacrificial epitaxial layer 114 can be removed by, but is not limited to, wet etching.

[0162] Next, as Figure 16 As shown, the bottom sacrificial layer is removed based on the gate trench 107 to form a bottom sacrificial gap. The bottom sacrificial gap can be removed by, but is not limited to, wet etching process. Further, in an optional example, the sidewall protection layer 116 is formed on the sidewall of the bottom epitaxial layer 127. The sidewall protection layer 116 can be formed by, but is not limited to, thermal oxidation process.

[0163] Finally, as Figure 17 As shown, the insulating isolation layer 115 can be removed by, but is not limited to, wet etching process.

[0164] like Figure 18 As shown, the stacked structure 102 includes alternating stacked sacrificial layers and insulating dielectric layers. The method for fabricating the three-dimensional memory structure further includes the step of removing the sacrificial layers based on the gate trench 107 to form a sacrificial gap.

[0165] Specifically, the sacrificial layer 104 can be removed by a wet etching process. A wet etching solution with a high etching removal rate on the sacrificial layer and almost no removal on the insulating dielectric layer 103 can be used to remove the sacrificial layer. Specifically, the wet etching solution is placed in the gate trench 107, and the wet etching solution laterally etches the sacrificial layer to completely remove it.

[0166] In other embodiments, the sacrificial epitaxial layer 114 and the insulating isolation layer 115 may not be formed. Instead, after the gate trench 107 is formed, the sacrificial layer and the bottom sacrificial layer in the stacked structure 103 can be removed directly through the gate trench. Figure 18 The structure shown.

[0167] As shown in Figures 19(a) and 19(b), the fabrication method further includes the step of forming a gate layer 117 within the sacrificial gap.

[0168] Figure 19(a) shows a schematic diagram of the structure of the gate layer 117 when the bottom stack structure 105 is present. In other embodiments, the bottom stack structure 105 may not be present, and when removing the sacrificial layer by the gate trench, only the sacrificial layer in the stack structure 102 needs to be removed. Figure 19(b) shows a schematic diagram of the structure of the gate layer 117 when the bottom stack structure 105 is absent.

[0169] Specifically, the gate layer 117 can be formed within the sacrificial gap using physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The material of the gate layer 117 can include metal (e.g., tungsten or cobalt) or silicon. Preferably, in this embodiment, the material of the gate layer 117 can include tungsten. In one example, the gate layer 117 is formed within the sacrificial gap, and a gate layer is also formed within the bottom sacrificial gap, resulting in a bottom stacked structure 105 including the bottom dielectric layer and the gate layer located between the bottom dielectric layers. Alternatively, in one example, the gate layer material is also deposited in the gate spacer 107. In this case, a step of removing the gate layer material from the gate spacer 107 is also included.

[0170] like Figure 1 S3 and Figure 12 As shown, a source region 121 is formed in the semiconductor substrate 101 corresponding to the bottom of the gate trench 107;

[0171] like Figure 1 S4 and Figures 20(a)-21 As shown, an inner core 123 and an outer layer 120 surrounding the inner core 123 are formed in the gate trench 107 to form an array common source structure, wherein the inner core 123 and the outer layer 120 are made of different materials, and the outer layer 120 is electrically connected to the source region 121.

[0172] As an example, the inner core 123 includes a polycrystalline silicon filling layer.

[0173] As an example, the outer layer 120 includes a metal layer.

[0174] As an example, the metal layer includes a tungsten structure layer; as an example, the metal layer includes a fluorine-free tungsten layer.

[0175] Specifically, in this step, the outer layer 120 and the inner core 123 are formed within the gate spacer. The filler in the gate spacer 107 can achieve its conductive function based on the outer layer. In one example, the outer layer 120 includes a tungsten structure layer. In a further optional example, the tungsten structure layer includes a fluorine-free tungsten layer. The design of the fluorine-free tungsten layer can avoid the preparation of the barrier layer, thereby facilitating the reduction of the gate spacer size and the increase of the distance between the channel via and the gate spacer. This can increase the length of the subsequent gate layer, reduce the resistance of the gate layer, improve device speed, and optimize device performance. The metal layer can be prepared using a low-fluorine process, which can improve the purity of the metal and reduce resistance. For example, fluorine-free tungsten metal can be prepared using tungsten chloride and hydrogen. Furthermore, by designing the filling of the gate spacer 107 to be the same as that of the outer layer 120 and the inner core 123, the performance of the entire gate spacer filling can be improved based on the material of the inner core 123, while still achieving the function of the gate spacer in the device. In one example, the material of the inner core 123 can be a material with a resistance lower than that of the tungsten structure layer, thereby improving the overall resistance of the filling and thus improving device performance. In an optional example, the inner core 123 includes a polysilicon filling layer, as shown in Figure 20(a). Of course, in other examples, the inner core 123 can also be an air cavity formed without additional filling of material layers, such as the gate spacer cavity described later, as shown in Figure 20(b). In addition, the tungsten structure layer can be a single layer of tungsten material, or it can be a stacked structure composed of a tungsten material layer and other material layers, such as a stack composed of other metals, as the outer layer.

[0176] As an example, as shown in FIG20(b), the process of forming the outer layer 120 further includes forming a gate spacer cavity in the gate spacer 107 based on the outer layer 120, the gate spacer cavity constituting the inner core 123, and the outer layer 120 surrounding the gate spacer cavity.

[0177] Specifically, in one example, the outer layer 120 can be formed using atomic layer deposition (ALD) to facilitate its formation on the surface of the isolation layer, thereby facilitating the formation of the gate cavity. For example, it can be a tungsten layer formed by ALD.

[0178] As an example, such as Figure 21 As shown, after forming the outer layer 120, the method further includes: preparing a conductive plug 122 in at least the gate spacer 107, the conductive plug extending into the top of the gate spacer, so that the conductive plug and the outer layer 120 form the gate spacer cavity 123.

[0179] As an example, the conductive plug is prepared using a physical vapor deposition process, which has a low pore filling rate.

[0180] Specifically, such as Figure 21 As shown, the method also includes the step of forming a conductive plug 122 in the gate spacer 107. The conductive plug 122 is formed at the top of the gate spacer 107 and contacts the outer layer 120 to achieve electrical connection. The conductive plug 122 and the outer layer 120 together form the gate spacer cavity. The gate spacer cavity can alleviate stress generated by the surrounding material layer, reduce resistance, ground, alleviate stress on the entire device structure, and reduce leakage current. Furthermore, the conductive plug 122 is formed within the gate spacer 107 and extends onto the material layer surrounding the gate spacer 107. For example, see... Figure 21 As shown, it may extend into the first cover layer 124a and the second cover layer 124b formed on the stacked structure.

[0181] In one example, as shown in Figures 20(a) and 20(b), after forming the gate trench 107, the steps include forming an isolation layer 119 on the sidewall of the gate trench 107 and forming an outer layer 120 on the surface of the isolation layer 119. In one example, the above steps are performed after the gate layer 117 is formed in the sacrificial gap.

[0182] Specifically, an isolation layer is formed on the sidewall of the gate trench 107. The isolation layer can be formed first on the sidewall and bottom of the gate trench 107, and then the isolation layer at the bottom of the gate trench 107 can be removed. Then, the outer layer 120 is formed on the surface of the isolation layer. The isolation layer can be formed on the sidewall of the gate trench 107 using physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The isolation layer is used to electrically isolate the outer layer 120 from the gate layer 117. The material of the isolation layer can include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or hafnium oxide, etc.

[0183] As an example, after forming the isolation layer, the method further includes the step of preparing a transition layer on the surface of the isolation layer, and the outer layer is formed on the surface of the transition layer. In other embodiments, a transition layer may be omitted, and a metal layer may be formed directly on the surface of the isolation layer. Specifically, in one example, the outer layer 120 is formed on the surface of the transition layer, wherein the transition layer may be a titanium layer, a titanium nitride layer, or a stacked structure composed of both.

[0184] As an example, before forming the outer layer 120, the method further includes the step of forming a source region 121 in the semiconductor substrate 101 corresponding to the bottom of the gate trench 107, wherein the outer layer 120 is in contact with the source region 121.

[0185] Specifically, in one example, an ion implantation process can be used to implant ions into the semiconductor substrate 101 at the bottom of the gate spacer 107 to form the source region 121. In an optional example, when ion implanting the semiconductor substrate 101 at the bottom of the gate spacer 107, the bottom isolation oxide layer located at the bottom of the gate spacer 107 is not removed. That is, the source region is formed after the isolation layer is formed. The presence of the bottom oxide layer can protect the semiconductor substrate 101 during the ion implantation process to avoid lattice damage to the semiconductor substrate 101 caused by ion implantation. Of course, in other examples, the source region can also be formed before the isolation layer is formed, see [reference needed]. Figure 12 As shown. In one example, after forming the source region within the semiconductor substrate 101 at the bottom of the gate trench 107, a step of removing the bottom oxide layer is included. Specifically, a dry etching process or a wet etching process can be used to remove the bottom oxide layer. The isolation layer can be formed first on the sidewalls and bottom of the gate trench 107. To ensure electrical contact between the outer layer 120 formed within the gate trench 107 and the source region, after the isolation layer is formed, a step of removing the isolation layer located at the bottom of the gate trench 107 is included.

[0186] Specifically, in one example, see Figure 21 As shown, the method also includes the step of preparing a connecting block 125 after the material layer in the channel hole 106 is prepared. In one example, after the channel hole 106 is filled, a first capping layer 124a is prepared on the surface of the obtained semiconductor structure and patterned to show the channel hole 106. Conductive material is deposited on the top of the corresponding channel hole 106 to form the connecting block 125. The connecting block is located on the top of the channel hole 106 and is in contact with the functional sidewall and the channel layer 111 to achieve electrical connection. After the connecting block 125 is formed, a second capping layer 124b is prepared on the obtained structure. The materials of the first capping layer 124a and the second capping layer 124b include, but are not limited to, silicon oxide. In one example, when the conductive plug is formed, the conductive plug extends into the first capping layer 124a and the second capping layer 124b. Optionally, the upper surface of the conductive plug is higher than the upper surface of the first capping layer 124a and the upper surface of the conductive plug is lower than the upper surface of the second capping layer 124b.

[0187] Specifically, in one example, after forming the conductive plug, a top capping layer 126 is also fabricated on the resulting semiconductor structure, the top capping layer being in contact with the conductive plug. In one example, when the first capping layer and the second capping layer are formed, the top capping layer further extends into the second capping layer, where it contacts the conductive plug.

[0188] It should also be noted that, in one example, the transition layer includes a titanium layer and a titanium nitride layer formed sequentially. The titanium layer is prepared using HP (high-density deposition) technology, and the titanium nitride layer is prepared using atomic layer deposition technology. The outer layer includes a tungsten layer prepared using atomic layer deposition technology. The inner core includes the gate spacer cavity, and the conductive plug includes a tungsten conductive plug obtained by physical vapor deposition and chemical mechanical polishing. Compared with the process of polysilicon filling, polysilicon etch-back, and chemical vapor deposition of tungsten metal to prepare conductive materials, this method can save 50% of the cost.

[0189] Example 2:

[0190] like Figure 22 and Figure 23 As shown, for reference Figure 1-21 The present invention also provides a three-dimensional memory structure, which is preferably prepared using the preparation method of the present invention. The three-dimensional memory structure includes:

[0191] Semiconductor substrate 101;

[0192] A stacked structure 118 located on the semiconductor substrate, the stacked structure 118 including alternating gate layers 117 and insulating dielectric layers 103;

[0193] A channel hole 106 and an array common source structure pass through the stacked structure 118 in a direction perpendicular to the semiconductor substrate 101, and there is a gap between the channel hole 106 and the array common source structure;

[0194] The source region 121 is located within the semiconductor substrate;

[0195] The array common source structure includes an inner core 123 and an outer layer 120 surrounding the inner core 123. The inner core 123 and the outer layer 120 are made of different materials, and the outer layer 120 is electrically connected to the source region 121.

[0196] As an example, the gate spacer 107 includes N sub-gate spacers 107a that are connected vertically, where N is an integer greater than or equal to 2.

[0197] Specifically, the semiconductor substrate 101 can be selected according to the actual needs of the device. The semiconductor substrate 101 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, or a GOI (Germanium-on-Insulator) substrate, etc. In other embodiments, the semiconductor substrate 101 may also be a substrate containing other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide. The semiconductor substrate 101 may also be a multilayer structure, such as a silicon / germanium-silicon multilayer. In this embodiment, the semiconductor substrate 101 includes a single-crystal silicon substrate. Furthermore, the semiconductor substrate 101 can be an ion-doped substrate, which may be P-type doped or N-type doped. Multiple peripheral devices, such as field-effect transistors, capacitors, inductors, and / or pn junction diodes, may also be formed in the semiconductor substrate 101. The semiconductor substrate 101 may also have peripheral circuitry.

[0198] Specifically, the stacked structure includes alternating layers of insulating dielectric layers 103 and sacrificial layers 104. The insulating dielectric layers 103 include, but are not limited to, silicon dioxide layers, and the sacrificial layers include, but are not limited to, silicon nitride layers. The insulating dielectric layers 103 and the sacrificial layers have a certain selectivity ratio in the same etching / etching process to ensure that the insulating dielectric layers 103 are hardly removed when the sacrificial layers are removed. In one example, the stacked structure may include the insulating dielectric layers 103 and the sacrificial layers alternately stacked from bottom to top. The bottom and top layers of the stacked structure are both insulating dielectric layers 103, and the upper surface of the top insulating dielectric layer 103 is the upper surface of the stacked structure. The number of insulating dielectric layers 103 and the sacrificial layers in the stacked structure may include 32, 64, 96, or 128 layers, etc. Specifically, the number of insulating dielectric layers 103 and the sacrificial layers in the stacked structure can be set according to actual needs and is not limited here.

[0199] The present invention forms an array common-source structure in the stacked structure, wherein the array common-source structure is based on a gate spacer 107 and its internal filling material, the internal filling material including at least the inner core and the outer layer. A gate spacer 107 is fabricated in the stacked structure, and a structure including at least two sub-gate spacers 107a is further fabricated. Three or more sub-gate spacers 107a can be vertically connected. The arrangement of multiple sub-gate spacers 107a makes the fabrication of a single sub-gate spacer 107a easier to control, thereby reducing its critical dimension (CD), the critical dimension including the width of the gate spacer. Currently, with the increase in the number of layers in 3D memory processes, in order to reduce the challenges to vias (such as gate spacers 107, CH), such as etching difficulty, efforts are made to control the thinning of the sacrificial layer, resulting in a thinner overall stacked structure. This ultimately leads to a linear increase in the resistance of the filled gate layer (GL), see [reference needed]. Figure 24 As shown, this affects device performance. The solution of this invention, as illustrated in Figures 10(a) and 10(b), reduces the feature size of the gate spacer 107, decreases the width of w in the figures, and thus increases the distance between the channel via 106 and the gate spacer 107, i.e., increases the length d. This increases the length of the subsequent gate layer, reduces the resistance of the gate layer, improves device speed, and optimizes device performance. It should be noted that the critical dimension of the gate spacer using this invention can be reduced from 180nm to 120nm, a 50% reduction, and the dimension d can be increased from 130nm to 160nm, resulting in a 20% reduction in resistivity after filling.

[0200] As an example, the stacked structure 118 includes N sub-stacked structures 118 stacked sequentially in a direction perpendicular to the surface of the semiconductor substrate 101, and each sub-stacked structure 118 corresponds one-to-one with each sub-gate spacer 107a.

[0201] As an example, the channel hole 106 includes N sub-channel holes 106 arranged vertically and vertically, and each sub-channel hole 106 corresponds one-to-one with each sub-gate spacer 107a.

[0202] Specifically, the multiple sub-gate trenches 107a can be sequentially referred to as the first sub-gate trench 107a, the second sub-gate trench 107a, the third sub-gate trench 107a, and so on, up to the Nth sub-gate trench 107a, from the semiconductor substrate 101 upwards. Similarly, the names of the various sub-stack structures 102a are similar, and the Nth sub-gate trench 107a and the Nth sub-stack structure 102a correspond one-to-one. The correspondence between the sub-gate trench 107a and the sub-stack structure 102a refers to the portion of the material layer of the stack structure formed around and in contact with the sub-gate trench 107a. In one example, the channel hole 106 includes N sub-channel holes 106 arranged vertically and interconnectedly, which are sequentially arranged from the semiconductor substrate 101 upwards as a first sub-channel hole 106, a second sub-channel hole 106 to an Nth sub-channel hole 106. In an optional example, each sub-channel hole 106 corresponds one-to-one with each sub-gate spacer 107a, that is, the Nth sub-channel hole 106 corresponds one-to-one with the Nth sub-gate spacer 107a, and the two are formed in the same sub-stack structure 102a. In an optional example, the corresponding sub-channel holes 106 and sub-gate spacers 107a are fabricated based on the same process. For example, after the first sub-stack structure 102a is formed, the first sub-gate spacer 107a and the first sub-channel hole 106 are formed in the first sub-stack structure 102a based on the same process.

[0203] As an example, the three-dimensional memory structure further includes a high dielectric constant dielectric layer 109, a functional sidewall layer 110, and a channel layer 111 stacked sequentially, wherein the high dielectric constant dielectric layer 109 is formed on the inner wall of the channel hole 106.

[0204] Specifically, a high-dielectric-constant dielectric layer 109 is formed on the inner wall of the channel via 106, that is, a high-dielectric-constant dielectric layer 109 (high-K dielectric layer) is formed on the sidewall and bottom surface of the channel via 106. The gate layer formed subsequently is in contact with the high-dielectric-constant dielectric layer 109, and its material can be alumina or the like. The functional sidewall layer 110 is formed on the surface of the high-dielectric-constant dielectric layer 109. In an optional example, the functional sidewall layer 110 sequentially includes a barrier layer, a storage layer, and a tunneling layer (not shown in the figure) from the sidewall of the channel via 106 to the center. In one example, the barrier layer may include, but is not limited to, a silicon oxide layer; the storage layer may include, but is not limited to, a silicon nitride layer; and the tunneling layer may include, but is not limited to, a silicon oxide layer. In one example, the barrier layer includes a silicon oxide layer, the storage layer includes a silicon nitride layer, and the tunneling layer includes a silicon oxide layer, thereby forming the functional sidewall layer 110 of an ONO structure. Specifically, a channel layer 111 is formed on the surface of the functional sidewall layer 110. In one example, the material of the channel layer 111 may include polysilicon. Of course, in other examples, the material of the channel layer 111 may also be other semiconductor materials.

[0205] Specifically, in one example, the sum of the thicknesses of the high dielectric constant dielectric layer 109, the functional sidewall, and the channel layer 111 can be less than half the width of the channel hole 106. In this case, after forming the channel layer 111, a reserved space for a filling insulating layer is still retained in the channel hole 106. When retaining the reserved space, the process also includes forming a filling insulating layer within the channel hole 106. The material of the filling insulating layer can include an oxide dielectric layer, such as silicon oxide, etc., and the filling insulating layer can completely fill the channel hole 106. Alternatively, in one example, the insulating gap 113 can be formed in the filling insulating layer by controlling the deposition process parameters of the filling insulating layer.

[0206] As an example, the three-dimensional memory structure also includes a bottom epitaxial layer 127 formed at the bottom of the channel hole 106, wherein the bottom epitaxial layer 127 extends into the semiconductor substrate 101, and at least the channel layer 111 is in contact with the bottom epitaxial layer 127.

[0207] As an example, a bottom stack structure 105 is also formed on the semiconductor substrate 101. The bottom stack structure 105 is located between the semiconductor substrate 101 and the stack structure. The bottom stack structure 105 may include a bottom dielectric layer and a bottom sacrificial layer located between adjacent bottom dielectric layers. Optionally, the bottom dielectric layer may include, but is not limited to, a silicon oxide layer, and the bottom sacrificial layer may be made of the same material as the gate layer. FIG19(a) shows a schematic diagram of the structure of the gate layer 117 when the bottom stack structure 105 is present. In other embodiments, the bottom stack structure 105 may not be present, and when removing the sacrificial layer by the gate trench, only the sacrificial layer in the stack structure 102 needs to be removed. FIG19(b) shows a schematic diagram of the structure of the gate layer 117 when the bottom stack structure 105 is absent.

[0208] As an example, a sidewall protection layer 116 is also formed on a portion of the outer wall of the bottom epitaxial layer 127. The sidewall protection layer 116 is located around the bottom epitaxial layer 127, and in one example, it is located in the gap corresponding to the bottom sacrificial layer in the bottom stacked structure 105.

[0209] Specifically, the three-dimensional memory structure further includes a source region 121, which is formed in the semiconductor substrate 101 corresponding to the bottom of the gate trench 107, and the outer layer 120 is in contact with the source region.

[0210] Specifically, an ion implantation process can be used to implant ions into the semiconductor substrate 101 at the bottom of the gate trench 107 to form an ion implantation region, thereby obtaining the source region.

[0211] As an example, the inner core 123 includes a polycrystalline silicon filling layer.

[0212] As an example, the outer layer 120 includes a metal layer.

[0213] As an example, the metal layer includes a tungsten structure layer; as an example, the metal layer includes a fluorine-free tungsten layer.

[0214] Specifically, the outer layer 120 and the inner core 123 are formed within the gate spacer. The filler in the gate spacer 107 can achieve its conductive function based on the outer layer. In one example, the outer layer 120 includes a tungsten structure layer. In a further optional example, the tungsten structure layer includes a fluorine-free tungsten layer. The design of the fluorine-free tungsten layer can avoid the preparation of the barrier layer, thereby facilitating the reduction of the gate spacer size and the increase of the distance between the channel via and the gate spacer. This can increase the length of the subsequent gate layer, reduce the resistance of the gate layer, improve device speed, and optimize device performance. The metal layer can be prepared using a low-fluorine process, which can improve the purity of the metal and reduce resistance. For example, fluorine-free tungsten metal can be prepared using tungsten chloride and hydrogen. Furthermore, by designing the filling of the gate spacer 107 to be the same as that of the outer layer 120 and the inner core 123, the performance of the entire gate spacer filling can be improved based on the material of the inner core 123, while still achieving the function of the gate spacer in the device. In one example, the material of the inner core 123 can be a material with a resistance lower than that of the tungsten structure layer, thereby improving the overall resistance of the filling and thus improving device performance. In an optional example, the inner core 123 includes a polysilicon filling layer, as shown in Figure 20(a). Of course, in other examples, the inner core 123 can also be an air cavity formed without additional filling of material layers, such as the gate spacer cavity, as shown in Figure 20(b). In addition, the tungsten structure layer can be a single layer of tungsten material, or it can be a stacked structure composed of a tungsten material layer and other material layers, such as a stack composed of other metals, as the outer layer.

[0215] As an example, the three-dimensional memory structure further includes an isolation layer 119 formed on the sidewall of the gate trench 107, and an outer layer 120 formed on the surface of the isolation layer, that is, the array common source structure further includes an isolation layer 119 surrounding the outer layer 120.

[0216] As an example, the three-dimensional memory structure further includes a transition layer formed on the surface of the isolation layer 119, and the outer layer 120 formed on the surface of the transition layer. That is, the array common source structure further includes a transition layer located between the isolation layer 119 and the outer layer 120.

[0217] Specifically, the material of the isolation layer may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or hafnium oxide, etc. In one example, the outer layer 120 is formed on the surface of the transition layer, wherein the transition layer may be a titanium layer, a titanium nitride layer, or a stacked structure composed of both.

[0218] As an example, the three-dimensional memory structure further includes a gate partition cavity formed in the gate partition 107, the outer layer 120 surrounding the gate partition cavity, and the gate partition cavity constituting the core.

[0219] As an example, the three-dimensional memory structure further includes a conductive plug 122, which is formed at least in the gate spacer 107, extends into the top of the gate spacer 107, and the conductive plug 122 and the outer layer 120 form the gate spacer cavity.

[0220] Specifically, the conductive plug 122 is formed at the top of the gate spacer 107 and contacts the outer layer 120 to achieve electrical connection. The conductive plug 122 and the outer layer 120 together form the gate spacer cavity. This cavity can alleviate stress generated by the surrounding material layer, reduce resistance, ground, relieve stress on the entire device structure, and reduce leakage current. Furthermore, the conductive plug 122 is formed within the gate spacer 107 and extends onto the material layer surrounding the gate spacer 107. For example, see... Figure 21 As shown, it can extend into the first and second cover layers formed on the stacked structure.

[0221] Specifically, in one example, the three-dimensional memory structure further includes a connecting block located at the top of the channel hole 106 and in contact with the functional sidewall and the channel layer 111 to achieve electrical connection. The connecting block may be located in a first cover layer, which is located on the surface of the stacked structure. In addition, a second cover layer is included covering the surface of the first cover layer. When the conductive plug is formed, the conductive plug extends into the first cover layer and the second cover layer. Optionally, the upper surface of the conductive plug is higher than the upper surface of the first cover layer and lower than the upper surface of the second cover layer.

[0222] Specifically, in one example, after forming the conductive plug, a top capping layer is also fabricated on the resulting semiconductor structure, the top capping layer being in contact with the conductive plug. In one example, when the first capping layer and the second capping layer are formed, the top capping layer further extends into the second capping layer, where it contacts the conductive plug.

[0223] In summary, the present invention provides a three-dimensional memory structure and its fabrication method. The fabrication method includes the following steps: providing a semiconductor substrate; forming a stacked structure on the semiconductor substrate, and forming a channel hole and a gate spacer with a spacing between them in the stacked structure, wherein the channel hole and the gate spacer both penetrate the stacked structure in a direction perpendicular to the semiconductor substrate; forming a source region in the semiconductor substrate corresponding to the bottom of the gate spacer; forming an inner core and an outer layer surrounding the inner core in the gate spacer to form an array common source structure, wherein the inner core and the outer layer are made of different materials, and the outer layer is electrically connected to the source region. Through the above-described scheme, this invention fills the gate spacer with a structure comprising at least an inner core and an outer layer surrounding the inner core. Based on the conductivity of the outer layer, the filling of the inner core can improve the overall stress, resistance, and leakage current of the device. Furthermore, the formation of a gate spacer cavity within the gate spacer alleviates stress from the material layer, reduces stress on the entire device structure, decreases device resistance, and improves device performance. Simultaneously, the gate spacer of the three-dimensional memory is fabricated as a structure comprising at least two interconnected sub-gate spacers. The arrangement of multiple sub-gate spacers makes the fabrication of each individual sub-gate spacer easier to control, thereby reducing its critical dimension (CD). This increases the distance between the channel via and the gate spacer, increasing the length of the subsequent gate layer, reducing the resistance of the gate layer, improving device speed, and optimizing device performance. This invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0224] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A three-dimensional memory structure comprising: The three-dimensional memory structure includes: Semiconductor substrate; A bottom stacked structure is disposed on the semiconductor substrate, the bottom stacked structure including a bottom dielectric layer and a first gate layer located between adjacent bottom dielectric layers; A stacked structure located on the bottom stacked structure, the stacked structure including alternately arranged second gate layers and insulating dielectric layers, the insulating dielectric layers being in contact with the bottom dielectric layer; The channel hole and the array common source structure pass through the bottom stacked structure, the stacked structure and the array common source structure in a direction perpendicular to the semiconductor substrate, and there is a gap between the channel hole and the array common source structure; A bottom epitaxial layer is formed at the bottom of the channel hole and is in contact with the bottom stacked structure. A sidewall protective layer is formed on the outer wall of the bottom epitaxial layer and is in contact with the bottom dielectric layer of the bottom stacked structure. The source region is located within the semiconductor substrate; The array common source structure includes: an inner core and an outer layer surrounding the inner core, the inner core including a polysilicon filling layer; the outer layer including a metal layer, the outer layer being electrically connected to the source region.

2. The three-dimensional memory structure of claim 1, wherein, The array common source structure also includes an isolation layer surrounding the outer layer.

3. The three-dimensional memory structure according to claim 2, characterized in that, The array common source structure also includes a transition layer located between the isolation layer and the outer layer.

4. The three-dimensional memory structure according to claim 1, characterized in that, The three-dimensional memory structure further includes a high dielectric constant dielectric layer, a functional sidewall layer, and a channel layer stacked sequentially, wherein the high dielectric constant dielectric layer is formed on the inner wall of the channel hole.

5. The three-dimensional memory structure according to claim 1, characterized in that, The metal layer includes a fluorine-free tungsten layer.

6. A three-dimensional memory structure, characterized in that, The three-dimensional memory structure includes: Semiconductor substrate; A bottom stacked structure is disposed on the semiconductor substrate, the bottom stacked structure including a bottom dielectric layer and a first gate layer located between adjacent bottom dielectric layers; a stacked structure is disposed on the bottom stacked structure, the stacked structure including alternately disposed second gate layers and insulating dielectric layers, the insulating dielectric layers being in contact with the bottom dielectric layers; The channel hole and the array common source structure pass through the bottom stacked structure, the stacked structure and the array common source structure in a direction perpendicular to the semiconductor substrate, and there is a gap between the channel hole and the array common source structure; A bottom epitaxial layer is formed at the bottom of the channel hole and is in contact with the bottom stacked structure. A sidewall protective layer is formed on the outer wall of the bottom epitaxial layer and is in contact with the bottom dielectric layer of the bottom stacked structure. The source region is located within the semiconductor substrate; The array common source structure includes: an inner core and an outer layer surrounding the inner core, the inner core including a polysilicon filling layer; the outer layer including a metal layer, the outer layer being electrically connected to the source region; A conductive plug is located on the upper part of the inner core, and at least a portion of the conductive plug is in contact with the outer layer.

7. The three-dimensional memory structure according to claim 6, characterized in that, The array common source structure also includes an isolation layer surrounding the outer layer.

8. The three-dimensional memory structure according to claim 7, characterized in that, The array common source structure also includes a transition layer located between the isolation layer and the outer layer.

9. The three-dimensional memory structure according to claim 6, characterized in that, The three-dimensional memory structure further includes a high dielectric constant dielectric layer, a functional sidewall layer, and a channel layer stacked sequentially, wherein the high dielectric constant dielectric layer is formed on the inner wall of the channel hole.

10. The three-dimensional memory structure according to claim 6, characterized in that, The metal layer includes a fluorine-free tungsten layer.

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