Dielectric materials, capacitors, and memory arrays

Abstract

Embodiments of the present disclosure relate to dielectric materials, capacitors, and memory arrays. Some embodiments include a dielectric material having a first region containing HfO and having a second region containing ZrO, where the chemical formulas indicate the primary constituents rather than a specific stoichiometry. The first region is substantially free of Zr, and the second region is substantially free of Hf. Some embodiments include a capacitor having a first electrode, a second electrode, and a dielectric material between the first electrode and the second electrode. The dielectric material includes one or more first regions and one or more second regions. The first regions contain Hf and are substantially free of Zr. The second regions contain Zr and are substantially free of Hf. Some embodiments include a memory array.

Description

Technical Field

[0001] Dielectric materials. Capacitors. Memory arrays. Integrated assemblies. Background Technology

[0002] Dielectric materials have many applications in integrated circuit systems. For example, dielectric materials can be provided between a pair of electrodes to form a capacitor. Capacitors can be used in memory, such as dynamic random access memory (DRAM).

[0003] An example DRAM cell (memory cell) may contain a combination of transistors and capacitors. Transistors can be used to selectively access capacitors and can be called access devices. Capacitors can electrostatically store energy as an electric field within the capacitor dielectric. The electrical state of the capacitor can be used to represent the memory state.

[0004] A DRAM array (memory array) can contain a large number of memory cells. Memory cells can be written to or read from using digital lines (also called bit lines, data lines, read lines, or data / read lines) and access lines (also called word lines). Digital lines extend along the columns of the array, and access lines extend along the rows. Each memory cell can be uniquely addressed via a combination of digital lines and access lines.

[0005] There is a need to develop improved dielectric materials, and there is a need to develop improved devices (e.g., memory cells) using these improved dielectric materials. Summary of the Invention

[0006] According to one embodiment of this disclosure, a dielectric material is provided. The dielectric material includes a first region containing HfO and a second region containing ZrO. The chemical formula indicates the major components rather than a specific stoichiometry. The first region is substantially free of Zr, and the second region is substantially free of Hf.

[0007] According to another embodiment of this disclosure, a capacitor is provided. The capacitor includes a first electrode, a second electrode, and a dielectric material between the first electrode and the second electrode. The dielectric material includes one or more insulating first regions and one or more insulating second regions. The one or more insulating first regions include Hf and substantially exclude Zr, and the one or more insulating second regions include Zr and substantially exclude Hf.

[0008] According to another embodiment of this disclosure, a memory array including memory cells is provided. Each of the memory cells includes an access means coupled to a capacitor. Each of the capacitors includes a dielectric material between a pair of electrodes, wherein the dielectric material comprises a stack of insulating layers. Some of the insulating layers within the stack are Hf-containing layers that are substantially free of Zr, and some of the insulating layers within the stack are Zr-containing layers that are substantially free of Hf. Attached Figure Description

[0009] Figures 1A to 1G This is a schematic cross-sectional side view of the example region of the example capacitor.

[0010] Figures 2A to 2C This is a schematic view of the instance region of an instance memory cell, including instance capacitors.

[0011] Figure 3 This is a schematic diagram of the instance region of an instance memory array. Detailed Implementation

[0012] Some embodiments include a dielectric material having HfO x (where x is a number) and does not contain one or more regions of detectable Zr, and contains ZrO y (Where y is a number) and does not contain one or more regions where Hf can be detected. The dielectric material can be used in the capacitor, and the capacitor can be used in the memory array. Example embodiments are described with reference to Figures 1 to 3.

[0013] refer to Figure 1A The image shows a portion of an example capacitor 10. The capacitor includes a first electrode 12, a second electrode 14, and a dielectric material 16 between the first and second electrodes.

[0014] The first electrode 12 and the second electrode 14 may comprise any suitable conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). The first electrode and the second electrode may comprise the same composition as each other, or may comprise compositions that are different from each other.

[0015] The dielectric material 16 comprises an insulating first region (bulk, layer, film, etc.) 18 including HfO, and an insulating second region (bulk, layer, film, etc.) 20 including ZrO. The chemical formulas HfO and ZrO are used to indicate the main components rather than specific stoichiometry (where Hf, Zr, and O correspond to hafnium, zirconium, and oxygen, respectively). The HfO material may be HfO2, or more generally, HfO. xWhere x is a number. The material ZrO can be ZrO2, or more generally ZrO. y , where y is a number.

[0016] The first region 18 may be referred to as the Hf-containing region, and the second region 20 may be referred to as the Zr-containing region. The Hf-containing region 18 may substantially exclude Zr (or, in some embodiments, absolutely exclude Zr), and the Zr-containing region 20 may substantially exclude Hf (or, in some embodiments, absolutely exclude Hf). A region may be considered substantially excluding an element if the effective atomic percentage of the specified element within reasonable tolerances for manufacturing and measurement (detection) is 0. In some embodiments, the hafnium-containing region 18 may be considered to include HfO, consist substantially of HfO, or consist of HfO, and the zirconium-containing region 20 may be considered to include ZrO, consist substantially of ZrO, or consist of ZrO. Unless otherwise specified, the chemical formulas HfO and ZrO used herein should be understood to refer to major components rather than specific stoichiometry.

[0017] Figure 1A The dielectric material 16 described includes two of the first regions 18 and two of the second regions 20. Generally, the dielectric material will include at least one of the first regions 18 and at least one of the second regions 20. In some embodiments, regions 18 and 20 may be considered as primary regions of the dielectric material 16. The dielectric material may include such primary regions in a total number ranging from about 2 to about 10, from about 2 to about 8, from about 2 to about 5, etc.

[0018] Figure 1A One of the regions 20 is designated 20a, and one of the regions 18 is designated 18a. Regions 20a and 18a are directly adjacent to each other along interface 21. In some embodiments, this interface may correspond to an abrupt boundary such that there is effectively no intermingling of hafnium from layer 18a and zirconium from layer 20a across the boundary. In the event of any apparent mixing along the interface, this may be caused solely (or at least substantially entirely) by the roughness of the edges of regions 18a and 20a along this interface. In other embodiments, interface 21 may comprise a boundary region between the zirconium-containing material of block 20a and the hafnium-containing material of block 18a. This boundary region may comprise both hafnium and zirconium (i.e., may include intermingled hafnium and zirconium). Generally, if present, the boundary region will be extremely thin (e.g., less than or equal to approximately Thickness, less than or equal to approximately Thick, etc.).

[0019] The dielectric material 16 is shown to include additional regions (blocks, layers, films, etc.) 22a to c in addition to regions 18 and 20. Regions 22a to c may be referred to as insulating third regions and may include one or more insulating compositions (e.g., insulating oxides). In some embodiments, the third region may include oxygen in combination with one or more of Al (aluminum), Y (yttrium), La (lanthanum), Si (silicon), Ge (germanium), Zr (zirconium), Hf (hafnium), Sr (strontium), Mg (magnesium), Ca (calcium), Ce (cerium), Pr (praseodymium), Nb (niobium), and Ti (titanium). In some embodiments, the third region may include oxygen in combination with one or more lanthanide elements (i.e., elements 57 to 71 of the periodic table). Regions 22a to c may include compositions identical to each other, or at least one of the regions may include a composition different from at least one other region.

[0020] Regions 22a and 22b are labeled “interface” regions to indicate that such regions are interfaces along electrodes 12 and 14, respectively. The interface regions can serve as barriers to mitigate or prevent unwanted oxidation of the conductive material of electrodes 12 and 14, which may additionally occur if one of regions 18 and 20 directly abuts the conductive material of such electrodes. Alternatively or additionally, regions 22a and 22b can improve the crystallization of the dielectric material 16 along the surfaces of electrodes 12 and 14 relative to crystallization that would occur if regions 18 and 20 directly abut the surfaces of such electrodes, and / or can improve the adhesion of the dielectric material 16 to electrodes 12 and 14 compared to embodiments in which regions 18 and 20 directly abut the surfaces of such electrodes.

[0021] Region 22c is labeled "dopant" and may be provided to allow the properties of dielectric material 16 to be tailored for a specific application. Such properties may include, for example, leakage properties, capacitance-voltage hysteresis properties, etc. In some embodiments, in addition to or instead of utilizing the dopant region 22c, a suitable dopant may be dispersed in one or more of regions 18 and 20. It should be noted that the oxides suitable for use in dopant region 22c described above comprise zirconium oxide and hafnium oxide. This may be advantageous in providing the dopant using a single region 22c, as it allows the dielectric material 16 to contain a dopant region 22c containing a mixture of hafnium oxide and zirconium oxide, while the dielectric material 16 has other regions corresponding to the hafnium-containing region 18 lacking Zr and the zirconium-containing region 20 lacking Hf.

[0022] Regions 22a to c are optional, and in some embodiments one or more of these regions may be omitted. Furthermore, although... Figure 1A Only one dopant region 22c is described in this embodiment, but in other embodiments, two or more such dopant regions may exist.

[0023] The dielectric material 16 may have any suitable thickness T. In some embodiments, this thickness may be approximately... To date Within the scope, in approximately To date Within the scope, in approximately To date Within the scope, in approximately To date Within the range, etc.

[0024] Blocks 18 and 20 may have any suitable thicknesses T1 and T2, and in some embodiments, this thickness may be approximately To date Within the scope, in approximately To date Within the scope, in approximately To date Within the range, etc. Block 18 may all have approximately the same thickness as each other, or may have a thickness that is different from each other. Similarly, blocks 20 may all have approximately the same thickness as each other, or may have a thickness that is different from each other. Furthermore, one or more of blocks 20 may have approximately the same thickness as one or more of blocks 18, or may have a thickness that is different from one or more of blocks 18.

[0025] In some embodiments, the thickness T may be considered as the total thickness of the dielectric material 16 between the first electrode 12 and the second electrode 14. The first region 18 (hafnium-containing region) may comprise, by volume, about 15% to about 55% of this total thickness; or, by volume, about 15% to about 25% of this total thickness; etc. The second region 20 (zirconium-containing region) may comprise, by volume, about 40% to about 90% of this total thickness; or, by volume, about 40% to about 80% of this total thickness; etc. In some embodiments, the zirconium-containing region 20 comprises a larger percentage of the total thickness T of the dielectric material 16 by volume compared to the hafnium-containing region 18.

[0026] Interface regions 22a and 22b may include any suitable thickness, wherein an instance thickness T4 is displayed relative to layer 22a. Interface regions 22a and 22b may include the same thickness as each other or may include different thicknesses relative to each other. In some embodiments, the thickness T4 may be less than or equal to approximately Layers 22a and 22b may be continuous, and therefore may have a minimum thickness corresponding to a single layer. Alternatively, at least one of layers 22a and 22b may be discontinuous.

[0027] The dopant layer 22c may include any suitable thickness T3, and in some embodiments may include less than or equal to approximately The thickness of layer 22c. Layer 22c can be continuous, and therefore can have the minimum thickness corresponding to a single layer. Alternatively, layer 22c can be discontinuous.

[0028] Forming the dielectric material 16 into discrete blocks comprising HfO-containing regions 18 and ZrO-containing regions 20 offers numerous advantages. For example, properties (e.g., leakage properties, capacitance voltage hysteresis properties, etc.) can be customized by modifying the size and number of blocks 18 and 20 within the dielectric material 16. Furthermore, in some embodiments, the dielectric material 16 can be configured (i.e., engineered) to achieve selected criteria, such as equivalent oxide thickness (EOT). EOT quantifies the electrical properties of the dielectric material 16 in terms of representative physical thickness. For example, EOT can be defined as the theoretical thickness of the silicon dioxide layer required to achieve the same capacitance density as a given dielectric 16, neglecting leakage current and reliability considerations. In some embodiments, the size and number of blocks 18 and 20 within the dielectric material 16 can be customized to achieve the desired EOT. In some embodiments, the EOT achieved using discrete HfO-containing blocks 18 and ZrO-containing blocks 20 of the embodiments described herein may be superior to the EOT achieved using conventional dielectric materials. This means that the dielectric material 16 may be formed as thinner than conventional dielectric materials (e.g., dielectric materials containing a mixture of HfO and ZrO in the material) while still achieving the same or better EOT.

[0029] Blocks 18 and 20 may be formed from Hf and Zr, respectively, deposited under suitable conditions (e.g., atomic layer deposition), and subsequently oxidized using one or more suitable oxidants (e.g., ozone). It has been found that the Hf and Zr of blocks 18 and 20 can be completely oxidized and crystallized at temperatures lower than those of blocks comprising a mixture of HfO and ZrO. Therefore, in some embodiments, the capacitors described herein (e.g., Figure 1A The capacitor 10 can be formed by a process at a temperature not exceeding about 600°C, a temperature not exceeding about 430°C, or a temperature not exceeding about 400°C. This can advantageously reduce the process temperature compared to conventional methods for forming capacitors (e.g., methods for forming capacitors in which the dielectric material includes a mixture of HfO and ZrO).

[0030] Figure 1A The example demonstrates a representative capacitor configuration 10 using discrete HfO blocks 18 and ZrO blocks 20. Figures 1B to 1G Other representative capacitor configurations are shown. Configurations may include more than one in the doped layer (e.g., ...). Figure 1C and 1G (As shown in the diagram). The configuration may include being centered within the dielectric material 16 (e.g., Figure 1A , 1B (as shown in 1E) or offset from the center position (as shown in 1E) Figure 1C ,1D The doped layer (as shown in 1G). The dielectric material 16 can be symmetrical between electrodes 12 and 14 (as shown in 1G). Figure 1A , 1C (as shown in 1G), or may be asymmetrical between electrodes (as shown in 1G). Figure 1B , 1D (As shown in 1E and 1F). Dopants can be provided in individual doped layers other than the interface layer (e.g., Figure 1A , 1B (as shown in 1C, 1D, 1E, and 1G) or not provided in individual doped layers other than the interface layer (such as... Figure 1F (as shown in the image). Figure 1F The embodiments may or may not include suitable dopants dispersed in the HfO-containing layer and the ZrO-containing layer.

[0031] The capacitors described above can include any suitable three-dimensional configuration. For example, Figure 2A A cross-sectional side view of an example configuration of capacitor 10 is shown, wherein electrodes 12 and 14 each have a planar configuration, and wherein dielectric material 16 is provided between the planar electrodes 12 and 14. Figure 2A The capacitor 10 can be considered as an example of a planar capacitor configuration. Figure 2A The dielectric material 16 may include Figures 1A to 1G Any of the example embodiments, or those with the above references Figure 1A Any other suitable embodiments of the type described, including HfO block 18 and ZrO block 20.

[0032] As another example, Figure 2B A cross-sectional side view of an example configuration of capacitor 10 is shown, wherein electrode 12 is container-shaped, and wherein dielectric material 16 and electrode 14 extend into this container shape. Figure 2B The capacitor 10 can be considered as an example of a container-shaped capacitor configuration. Figure 2B The dielectric material 16 may include Figures 1A to 1G Any of the example embodiments, or those with the above references Figure 1A Any other suitable embodiments of the type described, including HfO block 18 and ZrO block 20.

[0033] Figure 2C Another example configuration of capacitor 10 is shown. Figure 2C The example capacitor has an electrode 12 configured as a pillar. A dielectric material 16 and an electrode 14 extend around the outer surface of this pillar. Figure 2C The capacitor 10 can be considered as an example of a pillar-based capacitor configuration. Figure 2C The dielectric material 16 may include Figures 1A to 1G Any of the example embodiments, or those with the above references Figure 1A Any other suitable embodiments of the type described, including HfO block 18 and ZrO block 20.

[0034] Figures 2A to 2C The capacitor 10 is shown as being incorporated into the memory cell 30, wherein such memory cell includes the capacitor 10 coupled to the access device 28. In the illustrated embodiment, the access device corresponds to a transistor. In other embodiments, the access device may have other suitable configurations (e.g., it may correspond to a bidirectional threshold switch, a diode, etc.).

[0035] The access device 28 is shown to have a gate 32 coupled to a word line 34, a first source / drain region 36 coupled to a capacitor 10, and a second source / drain region 38 coupled to a digital line 40.

[0036] Memory cell 30 may be provided within a memory array (e.g., a DRAM array), wherein instance array 50 is located within... Figure 3 The memory array is shown in the diagram. It includes multiple word lines 34 (labeled WL1 to WL4) coupled to word line driver circuitry 52. ​​The memory array also includes multiple digital lines 40 (labeled DL1 to DL4) coupled to sense amplifier circuitry 54. The memory array includes multiple memory cells 30, each of which includes a capacitor 10 coupled to access device 28.

[0037] Each memory cell 30 is uniquely addressed by a combination of one of the word lines 34 and one of the digital lines 40.

[0038] The illustrated area of ​​the memory array 50 can be considered a representative portion of the memory array. In practice, the memory array may include hundreds, thousands, hundreds of thousands, millions, or even hundreds of millions of memory cells 30. The memory cells may be substantially identical to each other, where the term "substantially identical" means identical within reasonable manufacturing and measurement tolerances.

[0039] Although the dielectric material 16 described herein is specifically described as being used within a capacitor configuration, it should be understood that this dielectric material can be used within any suitable component. For example, in some embodiments, the dielectric material 16 may be incorporated as a gate dielectric material into a transistor, or into a sensor, etc.

[0040] The structure described above with reference to Figures 1 to 3 may be supported by an underlying substrate (not shown). The substrate may include semiconductor materials; and may include, for example, monocrystalline silicon, substantially composed of monocrystalline silicon, or composed of monocrystalline silicon. The substrate may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction that includes semiconductor materials, including but not limited to bulk semiconductor materials, such as semiconductor wafers (alone or in combinations of other materials), and semiconductor material layers (alone or in combinations of other materials). The term "substrate" refers to any support structure, including but not limited to the semiconductor substrate described above. In some applications, the substrate may correspond to a semiconductor substrate housing one or more materials associated with integrated circuit manufacturing. Such materials may include one or more of, for example, refractory metals, barrier materials, diffusion materials, insulating materials, etc.

[0041] The assemblies and structures discussed above can be utilized within integrated circuits (where the term "integrated circuit" refers to electronic circuits supported by a semiconductor substrate); and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can comprise multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0042] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed by any suitable method now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0043] The terms “dielectric” and “insulating” are used to describe materials having insulating electrical properties. These terms are considered synonymous in this disclosure. The term “dielectric” in some cases and the term “insulating” (or “electrically insulating”) in others may be used within this disclosure to provide linguistic variation to simplify the premises within the appended claims, rather than to indicate any significant chemical or electrical differences.

[0044] The terms "electrical connection" and "electrical coupling" are both used in this disclosure. The terms are considered synonymous. One term may be used in some cases and another in others to provide linguistic variation within this disclosure to simplify the presuppositions in the appended claims.

[0045] The specific orientations of the various embodiments in the drawings are for illustrative purposes only, and in some applications, embodiments may be rotated relative to the shown orientation. The descriptions provided herein and the appended claims relate to any structure having the described relationships between various features, regardless of whether the structure is in a specific orientation of the drawings or rotated relative to such an orientation.

[0046] Unless otherwise indicated, the cross-sectional views in the accompanying drawings show only the features within the plane of the cross-section and do not show the material behind the plane of the cross-section in order to simplify the illustration.

[0047] When a structure is referred to as "on another structure," "adjacent to another structure," or "against another structure," the structure may be directly on the other structure or there may be an intervening structure. Conversely, when a structure is referred to as "directly on another structure," "directly adjacent to another structure," or "directly against another structure," there is no intervening structure. The terms "directly below," "directly above," etc., do not indicate direct physical contact (unless otherwise explicitly stated), but instead indicate upright alignment.

[0048] A structure (e.g., a layer, material, etc.) may be described as “vertically extending” to indicate that the structure extends generally upward from the underlying substrate (e.g., a base plate). A vertically extending structure may or may not extend generally orthogonally relative to the upper surface of the substrate.

[0049] Some embodiments include a dielectric material having a first region containing HfO and a second region containing ZrO, wherein the chemical formula indicates the major component rather than a specific stoichiometry. The first region is substantially free of Zr, and the second region is substantially free of Hf.

[0050] Some embodiments include a capacitor having a first electrode, a second electrode, and a dielectric material between the first and second electrodes. The dielectric material includes one or more insulating first regions and one or more insulating second regions. The one or more insulating first regions contain Hf and are substantially free of Zr. The one or more insulating second regions contain Zr and are substantially free of Hf.

[0051] Some embodiments include a memory array comprising memory cells. Each memory cell has an access means coupled to a capacitor. Each capacitor includes a dielectric material between a pair of electrodes, wherein the dielectric material comprises a stack of insulating layers. Some insulating layers within the stack are Hf-containing layers that are substantially free of Zr, and some insulating layers within the stack are Zr-containing layers that are substantially free of Hf.

[0052] As per the description, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes exemplary embodiments. Therefore, the claims have the full scope as stated in the writings and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. A dielectric material comprising a first region containing HfO and a second region containing ZrO, wherein the chemical formula indicates the principal component rather than a specific stoichiometry; the first region is free of Zr and the second region is free of Hf, and the dielectric material comprises at least one dopant layer, the at least one dopant layer being a separate and discrete layer located between and in contact with the first region and the second region, and the at least one dopant layer comprising one or more oxides.

2. The dielectric material according to claim 1, wherein the first region and the second region directly abut each other along the abrupt boundary, and wherein there is no mixing of Hf and Zr across the abrupt boundary.

3. The dielectric material according to claim 1, comprising a boundary region between the first region and the second region, wherein the boundary region comprises both Hf and Zr.

4. The dielectric material according to claim 1, wherein the first region and the second region have a first thickness and a second thickness, respectively; wherein the first thickness and the second thickness are in the range of 5 Å to 50 Å.

5. The dielectric material according to claim 4, wherein the first thickness and the second thickness are the same as each other.

6. The dielectric material according to claim 4, wherein the first thickness and the second thickness are different from each other.

7. The dielectric material according to claim 1, wherein the first region and the second region are the main regions of the dielectric material; and wherein the dielectric material includes the main regions in a total number ranging from 2 to 10.

8. The dielectric material according to claim 1, wherein the one or more oxides comprise one or more of Al, Y, La, Si, Ge, Zr, Hf, Sr, Mg, Ca, Ce, Pr, Nb and Ti.

9. The dielectric material according to claim 1, wherein the one or more oxides comprise one or more lanthanides.

10. The dielectric material according to claim 1, wherein the at least one dopant layer has a thickness of less than or equal to 6 Å.

11. A capacitor comprising: First electrode; Second electrode; The dielectric material between the first electrode and the second electrode; The dielectric material includes one or more insulating first regions and one or more insulating second regions; wherein the one or more insulating first regions include Hf but do not include Zr, and wherein the one or more insulating second regions include Zr but do not include Hf; and At least one dopant layer, the at least one dopant layer being a separate and discrete layer located between one of the one or more insulating first regions and one of the one or more insulating second regions and in contact with one of the one or more insulating first regions and one of the one or more insulating second regions, and the at least one dopant layer comprising one or more oxides.

12. The capacitor of claim 11, wherein the one or more insulating first regions are composed of HfO, wherein the chemical formula indicates the major component rather than a specific stoichiometry.

13. The capacitor of claim 11, wherein the one or more insulating second regions are composed of ZrO, wherein the chemical formula indicates the major component rather than a specific stoichiometry.

14. The capacitor of claim 11, wherein the total thickness of the dielectric material between the first electrode and the second electrode is in the range of 40 Å to 400 Å.

15. The capacitor of claim 11, wherein the total thickness of the dielectric material between the first electrode and the second electrode is in the range of 30 Å to 60 Å.

16. The capacitor of claim 11, wherein the total thickness of the dielectric material between the first electrode and the second electrode is in the range of 40 Å to 100 Å.

17. The capacitor of claim 11, wherein the dielectric material has a total thickness between the first electrode and the second electrode; and wherein the one or more insulating first regions comprise 15% to 25% of the total thickness by volume.

18. The capacitor of claim 11, wherein the dielectric material has a total thickness between the first electrode and the second electrode; and wherein the one or more insulating first regions comprise 15% to 55% of the total thickness by volume.

19. The capacitor of claim 11, wherein the dielectric material has a total thickness between the first electrode and the second electrode; and wherein the one or more insulating second regions comprise 40% to 80% of the total thickness by volume.

20. The capacitor of claim 11, wherein the dielectric material has a total thickness between the first electrode and the second electrode; and wherein the one or more insulating second regions, by volume, comprise a larger portion of the total thickness than the one or more insulating first regions.

21. The capacitor of claim 11, wherein the dielectric material comprises one or more insulating third regions; wherein the one or more insulating third regions comprise one or more oxides containing one or more lanthanide elements.

22. The capacitor of claim 11, wherein the dielectric material comprises one or more insulating third regions; wherein the one or more insulating third regions comprise one or more oxides comprising one or more of Al, Y, La, Si, Ge, Zr, Hf, Sr, Mg, Ca, Ce, Pr, Nb and Ti.

23. The capacitor of claim 22, wherein at least one of the one or more insulating third regions is continuous.

24. The capacitor of claim 22, wherein at least one of the one or more insulating third regions is discontinuous.

25. The capacitor according to claim 11, wherein it is formed by a process at a temperature not exceeding 600°C.

26. The capacitor according to claim 11, wherein it is formed by a process at a temperature not exceeding 430°C.

27. The capacitor according to claim 11, wherein it is formed by a process at a temperature not exceeding 400°C.

28. The capacitor of claim 11, further comprising: The first interface layer between the dielectric material and the first electrode; and The second interface layer between the dielectric material and the second electrode.

29. The capacitor of claim 28, wherein the first interface layer and the second interface layer comprise one or more oxides.

30. The capacitor of claim 29, wherein the one or more oxides comprise one or more of Al, Y, La, Si, Ge, Zr, Hf, Sr, Mg, Ca, Ce, Pr, Nb and Ti.

31. The capacitor of claim 29, wherein the one or more oxides comprise one or more of the lanthanides.

32. A memory array comprising memory cells, each of the memory cells including an access means coupled to a capacitor; each of the capacitors including a dielectric material between a pair of electrodes, wherein the dielectric material comprises a stack of insulating layers; some of the insulating layers within the stack are Hf-containing layers excluding Zr, and some of the insulating layers within the stack are Zr-containing layers excluding Hf; and The dielectric material includes at least one dopant layer, which is a separate and discrete layer located between one of the Hf-containing layers and one of the Zr-containing layers and in contact with one of the Hf-containing layers and one of the Zr-containing layers, and the at least one dopant layer comprises one or more oxides.

33. The memory array of claim 32, wherein the stack comprises dopants distributed in the Hf-containing layer and the Zr-containing layer.

34. The memory array of claim 33, wherein the dopant comprises one or more of Al, Y, La, Si, Ge, Zr, Hf, Sr, Mg, Ca, Ce, Pr, Nb and Ti.

35. The memory array of claim 32, wherein the stack comprises one or more dopant layers.

36. The memory array of claim 35, wherein the one or more dopant layers comprise oxygen and one or more of Al, Y, La, Si, Ge, Zr, Hf, Sr, Mg, Ca, Ce, Pr, Nb and Ti.

37. The memory array of claim 35, wherein the one or more dopant layers comprise a combination of oxygen and one or more lanthanides.

38. The memory array of claim 32, wherein the stack comprises a first interface layer along one of the electrodes of the pair of electrodes and a second interface layer along the other of the electrodes of the pair of electrodes; and wherein the first interface layer and the second interface layer comprise oxygen and one or more of Al, Y, La, Si, Ge, Zr, Hf, Sr, Mg, Ca, Ce, Pr, Nb and Ti.

39. The memory array of claim 32, wherein one of the Hf-containing layers is directly adjacent to one of the Zr-containing layers; wherein the boundary is between the one of the Hf-containing layers and the one of the Zr-containing layers; and wherein there is no mixing of Hf and Zr along the boundary.

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