Integrated circuit comprising at least one capacitive element and corresponding manufacturing method
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- STMICROELECTRONICS (ROUSSET) SAS
- Filing Date
- 2022-04-20
- Publication Date
- 2026-07-21
AI Technical Summary
Existing MIM type capacitors occupy a large area in integrated circuits and are at risk of dielectric layer breakdown. They are also susceptible to tip effect and undercutting problems during manufacturing, making it difficult to increase the capacitance per unit area while reducing thickness.
By employing a special structural design of a low-voltage dielectric layer and a second conductive layer, the ridges and vertices of the first conductive layer are covered to avoid tip effects and protect the dielectric layer during wet etching, thereby reducing topological constraints and enabling co-manufacturing with low-voltage transistors.
This increases the capacitance per unit area of the capacitor element, reduces the occupied area, avoids dielectric layer breakdown, and enhances the reliability of the capacitor element and its synergistic integration with other components of the integrated circuit.
Smart Images
Figure CN115224195B_ABST
Abstract
Description
[0001] Priority requirements
[0002] This application claims priority to French patent application No. 2104162, filed on April 21, 2021, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field
[0003] The embodiments and implementations relate to integrated circuits, and more specifically to capacitor elements and methods for manufacturing capacitor elements in integrated circuits. Background Technology
[0004] Some parts of integrated circuits, such as analog sections and radio frequency (RF) receiver chains, require linear capacitor elements within a given supply voltage range. The supply voltage in this type of integrated circuit section is typically in the range of 6V.
[0005] Metal-insulator-metal (MIM) type capacitors, which have two molds or conductive electrodes separated by a dielectric layer, typically have good linearity.
[0006] However, MIM-type capacitors can have relatively low capacitance per unit area, especially when these capacitors are manufactured in conjunction with other components of an integrated circuit. In practice, joint manufacturing steps are not necessarily dedicated to and optimized for the production of capacitors.
[0007] Therefore, MIM-type capacitors can occupy up to 50% of the surface area of the analog and RF receiving sections of an integrated circuit.
[0008] Therefore, it is desirable to reduce the surface area occupied by capacitor elements with good linearity.
[0009] In this regard, embodiments and implementations have been proposed to reduce the thickness of the dielectric layer in order to increase the capacitance per unit area by two or even four times.
[0010] However, reducing the thickness of the dielectric layer in conventional structures is difficult because the resulting capacitor elements are subject to electrical degradation during use, chemical degradation during the steps of the process of manufacturing integrated circuits, or large topological constraints.
[0011] Reference in this regard Figure 1 .
[0012] Figure 1Cross-sectional views 11, 12, and 13 illustrate an embodiment of a MIM-type capacitor element for which it is desirable to increase the capacitance per unit area. The capacitor element is fabricated on the surface of a shallow trench isolation (STI) type dielectric region and includes an overlay of a first conductive layer 10, a dielectric layer 30, and a second conductive layer 20.
[0013] The dielectric layer 30 may consist of a stack of “ONO” type (i.e., oxide layer, nitride layer and silicon oxide layer) suitable for withstanding high voltage, which typically has a thickness in the range of 13 nm.
[0014] In cross-sectional view 11, the dielectric layer 30 and the second conductive layer 20 include edges, and in particular the upper ridge of the first conductive layer 10.
[0015] However, by reducing the thickness of the dielectric layer 30, the breakdown voltage of the dielectric layer 30 is also reduced. Therefore, for operating voltages below the breakdown voltage, the tip effect TPEF along the ridges and at the apex of the first conductive layer 10 can generate an electric field capable of breaking down the dielectric layer 30.
[0016] In cross-sectional view 12, a portion of the dielectric layer 30 is not covered at the edges, particularly on the ridges of the first conductive layer 10. The dielectric layer 30 is not at risk of breakdown due to the tip effect, but is exposed during some manufacturing steps.
[0017] However, the manufacturing process may include a wet etching-type process, which can dissolve the dielectric layer 30 between the two conductive layers 10 and 20 of the "undercut" UDCT, and dissolves more quickly when the dielectric layer 30 is thin. Undercutting the UDCT in the dielectric layer 30 can cause reliability issues, such as premature breakdown.
[0018] In cross-sectional view 13, the first conductive layer 10, the second conductive layer 20, and the dielectric layer 30 are self-aligned, i.e., have vertically aligned edges, typically achieved through common directional etching. This allows for a priori avoidance of breakdown problems caused by tip effects and undercutting. However, in practice, this type of high-topology overlay etching is not provided in analog and RF receiver sections, which typically have low topology. Due to constraints on the transition between regions of different topologies, this necessitates providing a margin of several micrometers (MRG) around the capacitor elements.
[0019] The space occupied by the spare MRG effectively reduces the capacitance per unit area in this embodiment. In small-scale embodiments of the capacitor element, this can even result in losses relative to conventional embodiments, even if gains are achieved by reducing the thickness of the dielectric layer 30.
[0020] Therefore, it is necessary to increase the capacitance per unit area of capacitor elements, especially voltage-linear capacitor elements, while avoiding the degradation risks of the integrated circuit during use and manufacturing. Simultaneously, it is desirable that the manufacturing of capacitor elements can be co-integrated with other common embodiments of the integrated circuit. Summary of the Invention
[0021] According to one aspect, an integrated circuit is proposed, comprising at least one capacitor element, the capacitor element comprising: a first conductive layer disposed on the front side of a semiconductor substrate, defined by a contour, and forming a first electrode of the capacitor element; a low-voltage dielectric layer covering the first conductive layer; and a second conductive layer. The second conductive layer comprises: a first portion located on a central region of the first conductive layer and forming a second electrode of the capacitor element; and a second portion, on one hand, located on the upper surface of the first conductive layer, on the inner boundary of the entire contour of the first conductive layer, and on the other hand, on the front side of the first conductive layer on the outer boundary of the entire contour of the first conductive layer; wherein the first portion and the second portion of the second conductive layer are electrically separated, and the first conductive layer is adapted to be electrically connected to the second portion of the second conductive layer.
[0022] The term "low-voltage" dielectric layer refers to a dielectric layer that has a breakdown voltage at the limit of the low-voltage domain of an integrated circuit. The term "low-voltage" is therefore defined in a relative manner to the voltage involved in a given embodiment of the integrated circuit. Typically, low voltage can be a voltage in the range of 1V to 2V, or more broadly, a voltage below 5V.
[0023] Compared to conventional dielectric layers of the "ONO" type, low-voltage dielectric layers can allow the capacitance per unit area to double, or even quadruple.
[0024] The term "high voltage" as used below also has a relative meaning relative to the voltage involved in a given embodiment of the integrated circuit. A high-voltage dielectric layer corresponds to a dielectric layer capable of withstanding the high-voltage domain of the integrated circuit. Typically, high voltage can be a voltage in the range of 12V, or more broadly, a voltage between 5V and 20V.
[0025] On one hand, a capacitor element defined according to this aspect does not have the risk of dielectric layer breakdown caused by the tip effect because the ridges and apexes of the first conductive layer, which lie over its entire outline, are covered by a second portion of the second conductive layer and have no potential difference with the first conductive layer.
[0026] On the other hand, the outer boundary of the second conductive layer (made in a single-thickness second conductive layer located on the front side) does not impose any specific topological constraints.
[0027] On the other hand, the structure of the capacitor element can be defined in such a way that the low-voltage dielectric layer is completely covered and thus protected during the wet etching step until electrical isolation is formed between the first and second portions of the second conductive layer.
[0028] According to one embodiment, the annular opening is arranged to extend through the entire thickness of the second conductive layer up to the first conductive layer, so as to separate a first portion of the second conductive layer inside the shape of the annular opening from a second portion of the second conductive layer outside the shape of the annular opening.
[0029] Similarly, the formation of the annular opening (made in a second conductive layer of a single thickness located on the first conductive layer) does not impose any specific topological constraints, nor does it impose any subsequent wet etching.
[0030] According to one embodiment, a first conductive layer is disposed on a shallow trench isolation type isolation region in a semiconductor substrate.
[0031] This corresponds to an embodiment of a MIM-type capacitor element, which exhibits a capacitance value with good voltage linearity. The term "good linearity" means that the capacitance value has an acceptable variation over the operating voltage range of the application (e.g., in RF receivers or analog circuits).
[0032] It should be noted that although the acronym MIM originates from the term "metal-insulator-metal," it more generally refers to the structure of conductive materials other than metals (such as polycrystalline silicon), and is specifically distinguished from MOS-type capacitor elements (an acronym for "metal-oxide-semiconductor" structure, which is generally less linear and well-known to those skilled in the art).
[0033] According to one embodiment, the low-voltage dielectric layer is a silicon oxide layer having a thickness between 1 nanometer and 6 nanometers.
[0034] According to one embodiment, the low-voltage dielectric layer has the same composition and the same thickness as the gate dielectric layer of a low-voltage transistor in an integrated circuit designed to operate at a low voltage of less than 5V.
[0035] This embodiment illustrates the collaborative fabrication of a low-voltage dielectric layer and the steps involved in manufacturing low-voltage transistors for integrated circuits.
[0036] According to one embodiment, the second conductive layer has the same composition and the same thickness as the gate conductive region of a low-voltage transistor in an integrated circuit designed to operate at a low voltage of less than 5V.
[0037] This embodiment reflects the coordinated fabrication of the second conductive layer and the steps involved in manufacturing the low-voltage transistor of the integrated circuit. Furthermore, this coordination reflects that the low-voltage dielectric layer can be covered by the second conductive layer throughout all steps of the manufacturing process, until it defines the gate region of the low-voltage transistor.
[0038] According to one embodiment, the first conductive layer has the same composition and the same thickness as the gate conductive region of a high-voltage transistor in an integrated circuit designed to operate at a high voltage greater than 5V.
[0039] This embodiment reflects the collaborative fabrication of the first conductive layer and the steps involved in manufacturing the high-voltage transistor of the integrated circuit.
[0040] According to another aspect, a method for manufacturing an integrated circuit including at least one capacitor element is proposed, the manufacturing of the capacitor element comprising: forming a first electrode of the capacitor element, including: depositing a first conductive layer on a front side of a semiconductor substrate, and etching to define the outline of the first conductive layer; forming a low-voltage dielectric layer covering the first conductive layer; depositing a second conductive layer on the front side and the first conductive layer covered by the low-voltage dielectric layer; performing a first etching to define the second conductive layer as covering the first conductive layer and the front side of the entire outline of the first conductive layer; performing a second etching to electrically separate a first portion and a second portion of the second conductive layer, the first portion of the second conductive layer being located in the central region of the first conductive layer and forming a second electrode of the capacitor element, the second portion of the second conductive layer being located on the upper surface of the first conductive layer, on the inner boundary of the entire outline of the first conductive layer, and on the front side of the outer boundary of the entire outline of the first conductive layer; and forming an electrical connection between the first conductive layer and the second portion of the second conductive layer.
[0041] According to one embodiment, the second etching is positioned to etch through the entire thickness of the second conductive layer until reaching the annular opening of the first conductive layer, the annular opening separating a first portion inside the shape of the annular opening of the second conductive layer from a second portion outside the shape of the annular opening of the second conductive layer.
[0042] According to one embodiment, the method includes: forming a shallow trench isolation type isolation region in a semiconductor substrate before forming a first electrode, wherein the first electrode is formed on the isolation region.
[0043] According to one embodiment, the low-voltage dielectric layer is formed of a silicon oxide layer having a thickness between 1 nanometer and 6 nanometers.
[0044] According to one embodiment, the fabrication of the integrated circuit also includes fabricating a low-voltage transistor intended to operate at a low voltage of less than 5V, wherein the formation of the low-voltage dielectric layer is performed simultaneously with the formation of the gate dielectric layer of the low-voltage transistor.
[0045] According to one embodiment, the fabrication of the integrated circuit further includes fabricating a low-voltage transistor intended to operate at a low voltage of less than 5V, wherein the deposition of a second conductive layer is performed simultaneously with the deposition of a gate conductive layer of the low-voltage transistor, and wherein a second etching of the second conductive layer is performed simultaneously with the etching of the gate conductive layer, the gate conductive layer defining a gate region of the low-voltage transistor.
[0046] According to one embodiment, the fabrication of the integrated circuit also includes fabricating a high-voltage transistor intended to operate at a high voltage greater than 5V, wherein the formation of a first electrode and the formation of a gate region of the high-voltage transistor are performed simultaneously. Attached Figure Description
[0047] Other advantages and features of the invention will become apparent upon examination of the detailed description of the embodiments and implementations, as well as the accompanying drawings, which are in no way limiting, wherein:
[0048] Figure 1 A cross-sectional view of an embodiment of a MIM-type capacitor element is shown;
[0049] Figure 2 and Figure 3 An embodiment of a capacitor element is illustrated; and
[0050] Figures 4A to 4I The illustration shows the process of manufacturing. Figure 2 and Figure 3 The steps and results of the method for the capacitor element CPP shown. Detailed Implementation
[0051] Figure 2 and Figure 3 An advantageous exemplary embodiment of the capacitor element CPP of the integrated circuit CI is illustrated.
[0052] Capacitor element CPP can, for example, be part of the radio frequency (RF) communication circuit of integrated circuit CI, such as in the filtering circuit of the RF receiver chain; or in the analog section of integrated circuit CI, such as in the compensation circuit or as a decoupling capacitor.
[0053] Figure 2 The figure shows a cross-sectional view of the capacitor element CPP in the xz plane of the reference mark (xyz), which is basically in Figure 3 Location II-II.
[0054] Figure 3 The diagram shows a top view of the capacitor element CPP in the xy plane with reference markings (xyz), basically in... Figure 2 Position III-III.
[0055] The capacitor element CPP includes a first conductive mold P1 of the first electrode E1, a dielectric interface GO, and a superposition of a second conductive mold P2int of the second electrode E2.
[0056] The consideration is that the electrode includes a corresponding conductive mold and electrode terminals, which are formed, for example, in the metal layer of the interconnect portion of the integrated circuit and are provided for coupling the capacitor element to its intended circuit.
[0057] The superposition is arranged in the order given above, starting from the front surface FA of the semiconductor substrate PSUB of the integrated circuit CI. Within the plane of the front surface FA, the surface of the front surface FA (on which the capacitor element CPP is disposed) is completely included in the upper surface of the shallow trench isolation type isolation region STI.
[0058] Shallow trench isolation (STI) is a common element that allows lateral isolation of the trap or active region of a substrate PSUB. STI is typically formed by etching openings called trenches in the substrate PSUB, filling the trenches with a dielectric material (typically silicon oxide), and polishing the excess dielectric until the front-side active material (FA) is exposed.
[0059] Therefore, the capacitor element CPP is a MIM-type implementation (generalized by extending to a conductor-insulator-conductor structure, i.e., a "metal-oxide-metal" structure), thus exhibiting good linearity of capacitance value relative to the applied voltage. Furthermore, the MIM-type capacitor element CPP has no specific connection to the semiconductor substrate PSUB, as such connections could propagate interference signals or require a bulky triple-well type insulating semiconductor structure.
[0060] The first mold frame includes a first conductive layer P1 made of polysilicon, which is therefore arranged on the isolation region STI at the front FA.
[0061] The first conductive layer P1 is defined by its outline P1cntr (in... Figure 3 The shape is defined by a rectangle, but it can have another shape that allows it to occupy the available surface in the integrated circuit; in this respect it is sometimes referred to as a "fill capacitor".
[0062] For example, the first conductive layer P1 can have the same characteristics as the high-voltage or medium-voltage transistor MOS HV-MV of the integrated circuit. Figure 4I The gate conductive region HVG ( Figure 4I With the same composition and thickness, this high-voltage or medium-voltage transistor MOS HV-MV is designed to operate at high or medium voltages greater than 5V.
[0063] The first conductive layer P1 can also have the same memory cell NVM cell as the integrated circuit. Figure 4I The floating gate conductive region of the floating gate transistor has the same composition and the same thickness.
[0064] The dielectric interface includes a low-voltage dielectric layer GO covering the first conductive layer P1.
[0065] The term "low-voltage" dielectric layer refers to a dielectric layer with a breakdown voltage suitable for low-voltage domains in integrated circuits, but not suitable for high-voltage domains.
[0066] The terms “low voltage” and “high voltage” are therefore defined in a relative manner with respect to the voltages involved in an integrated circuit. For example, low voltage can be a voltage in the range of 1V to 2V, or more broadly, a voltage below 5V (with tolerance margin), while high voltage can be a voltage in the range of 12V, or more broadly, a voltage between 5V and 20V.
[0067] For example, the low-voltage dielectric layer GO is a silicon oxide layer with a thickness between 1 nanometer and 6 nanometers.
[0068] Furthermore, the low-voltage dielectric layer GO can advantageously have the characteristics of a low-voltage transistor MOS LV (low-voltage transistor) in an integrated circuit designed to operate at a low voltage below 5V. Figure 4I The gate dielectric layer GO has the same composition and the same thickness.
[0069] In fact, two types of low-voltage transistors can be distinguished, which have corresponding gate dielectric layers of different thicknesses.
[0070] For example, a first low-voltage dielectric thickness “GO1” in the 2nm range specifically corresponds to a logic circuit transistor designed to operate at a voltage below 1.5V.
[0071] For example, the second low-voltage dielectric thickness "GO2" in the 5nm range specifically corresponds to an input / output interface circuit transistor designed to operate at voltages between 2V and 5V.
[0072] Finally, the second mold includes a first portion P2int of a second conductive layer P2 made of polysilicon, the first portion P2int being disposed on the dielectric layer GO and positioned in the central region of the first conductive layer P1.
[0073] The term "central region" refers to the surface located within the shape defined by the outline P1cntr of the first conductive layer P1. For example, the central region can be defined based on a similar reduced shape to the outline P1cntr of the first conductive layer P1.
[0074] For example, the second conductive layer P2 can have the same characteristics as the low-voltage transistor MOS LV (Low Voltage Module) of the integrated circuit. Figure 4I The conductive regions of the gate have the same composition and the same thickness.
[0075] The second conductive layer P2 can also have the same characteristics as the memory cell NVM cell of the integrated circuit. Figure 4I The floating gate transistor has the same composition and thickness as the control gate conductive region.
[0076] Furthermore, a second portion P2ext of the same second conductive layer P2 is disposed over the entire outline P1cntr of the first conductive layer P1.
[0077] In fact, the second part P2ext of the second conductive layer P2 is located on the upper surface of the first conductive layer P1, on the inner boundary brdr_int of the entire outline P1cntr of the first conductive layer, and on the front surface FA of the outer boundary brdr_ext of the entire outline P1cntr of the first conductive layer.
[0078] The second portion P2ext of the second conductive layer P2 therefore surrounds the first conductive layer P1 in a stepped manner, thereby enclosing the ridges and vertices above the entire outline P1cntr of the first conductive layer P1.
[0079] The first conductive layer P1 is electrically connected to the second part P2ext of the second conductive layer so that there is always a zero potential difference between them.
[0080] For example, contact post CT1P1 can link the first conductive layer P1 to the terminal of the first electrode E1, and contact post CT1P2 can link the second portion P2ext of the second conductive layer P2 to the terminal of the first electrode E1, so as to connect the first conductive layer P1 and the second portion P2ext.
[0081] Similarly, the first portion P2int of the second conductive layer P2 can be electrically connected to the terminal of the second electrode E2.
[0082] The annular opening OUV is formed to extend through the entire thickness of the second conductive layer P2 until it reaches the first conductive layer P1, in order to electrically separate the first portion P2int of the second conductive layer P2 from the second portion P2ext.
[0083] Therefore, the first part P2int of the second conductive layer is located inside the annular shape of the opening OUV, and the second part P2ext of the second conductive layer is located outside the annular shape of the opening OUV.
[0084] The ring shape of the open OUV is in Figure 3 In the representation, it is a rectangular ring. The terms "ring" and "annular" refer to a geometric region defined by mutually parallel inner and outer circumferences, and parallel to the contour P1cntr of the first conductive layer. In other words, the annular opening can be implemented by a strip extending along the contour P1cntr at an inward offset of a certain distance, which corresponds to the inner boundary brdr_int.
[0085] On the other hand, the opening formed in the second conductive layer P2 provides a channel to the first conductive layer P1, specifically for connecting the contact post CT1P1 to the first conductive layer P1.
[0086] Finally, the structure of the capacitor element CPP can be manufactured such that the low-voltage dielectric layer GO is completely covered until the annular opening OUV is formed. Therefore, the low-voltage dielectric layer GO is protected during the wet etching step. See reference in this regard. Figures 4A to 4I .
[0087] Figures 4A to 4I The illustration shows an example of the steps and results of a method for manufacturing a capacitor element CPP(GO) for an integrated circuit CI, as previously described. Figure 2 and Figure 3 As described.
[0088] In addition to the manufacture of capacitor components CPP(GO), Figures 4A to 4I The steps for manufacturing other components of an integrated circuit are also illustrated, which are carried out in conjunction with the steps for manufacturing capacitor components (CPP).
[0089] In this example, other components of the integrated circuit CI include the NVMcell non-volatile memory cell, the high-voltage capacitor CP1P2 (ONO), the high-voltage and medium-voltage transistors MOS HV-MV, and the low-voltage transistor MOS LV.
[0090] For the sake of simplicity, high-voltage and medium-voltage transistors will be referred to as "high-voltage transistors".
[0091] The fabrication of the capacitor element CPP can be co-integrated with the fabrication of only a few other components in the integrated circuit elements illustrated herein. In particular, for co-integration, the presence of the high-voltage capacitor element CP1P2 (ONO) is not required; for example, for complete co-integration of the fabrication of the capacitor element CPP (GO), the presence of the memory cell NVMcell, the low-voltage transistor MOS LV, and the high-voltage and medium-voltage transistors MOV HV-MV is sufficient.
[0092] Figure 4A The illustration shows the result 410 of forming shallow isolation regions (STI), particularly in the region housing capacitor elements CPP(GO) and CP1P2(ONO) to avoid forming a capacitor interface with the semiconductor substrate PSUB, but also in other regions forming typical lateral isolation regions.
[0093] In addition, triple-well TRPW implantation was performed in the region of the memory cell NVMcell, and high-voltage well HVW implantation was performed in the region of the high-voltage transistor MOS HV-MV.
[0094] The vertical gate region TRCH of the buried access transistor is formed in the open trench of the triple-well TRPW in the region of the memory cell NVMcell.
[0095] For example, a high-voltage dielectric layer HVOX is formed on the entire front FA of the substrate PSUB, except for the portion of the memory cell NVMcell, through thermal growth. In this portion of the memory cell NVMcell, the thickness of the dielectric has been reduced to a thickness known as tunnel TNOX, which is associated with the tunnel oxide layer of the memory cell transistor.
[0096] Finally, a first conductive layer P1, for example made of polysilicon, was deposited over all areas of the integrated circuit.
[0097] The first conductive layer P1 will form the first frame of the floating gate, capacitor element CPP(GO), CP1P2(ONO), and gate of the high-voltage transistor MOS HV-MV in part of the memory cell NVMcell.
[0098] Figure 4B The illustration shows an etching 420 of the first conductive layer P1, which allows the first conductive layer P1 to be removed from the region of the low-voltage transistor MOS LV and defines the position and shape of the gate structure of the high-voltage transistor MOS HV-MV, as well as the first mold that defines the high-voltage capacitor element CP1P2 (ONO).
[0099] Etching 420 also allows for defining the outline P1cntr of the first frame of the capacitor element CPP(GO).
[0100] Etching 420 uses a photomask M20 to define the areas to be exposed or not exposed to directional etching, which is typically a plasma-type dry etching process.
[0101] Figure 4C The illustration shows the result of implanting a low-voltage well (LVW) and forming a 430 dielectric layer (ONO) in a portion of a low-voltage transistor (LV MOS). The dielectric layer (ONO) typically comprises a stack of oxide, nitride, and silicon oxide layers formed over all areas of the integrated circuit. The formation of the dielectric layer (ONO) is isotropic, meaning that the layers grow to substantially equal thickness, regardless of the orientation of the surface on which they are grown.
[0102] The dielectric layer ONO specifically allows for the formation of a dielectric thickness with a breakdown voltage greater than that involved in the operation of the integrated circuit CI, particularly in the regions of the memory cell NVM cell and the high-voltage capacitor element CP1P2 (ONO). Furthermore, the dielectric layer ONO allows for the formation of a stop layer for the etching of the second conductive layer P2 (see [link to documentation]). Figure 4G).
[0103] Figure 4D The illustration shows step 440 of removing the dielectric layer ONO, particularly in the regions of the low-voltage transistor MOS LV and the capacitor element CPP(GO). Step 440 uses a photolithographic mask M40 to define areas that are exposed or not exposed to the directional etching.
[0104] Etching is typically provided to remove the flat dielectric thickness ONO, and the excess vertically thick portion (in the etch direction) can exist on the side of the first mold P1 of the capacitor element CPP(GO) in a manner equivalent to the grid spacers.
[0105] Figure 4E The illustration shows the formation of a 450 low-voltage dielectric layer GO over all areas of the integrated circuit.
[0106] The low-voltage dielectric layer GO is also formed isotropically and specifically covers the entire first mold P1 of the capacitor element CPP (GO).
[0107] The low-voltage dielectric layer GO is specifically designed to form the gate dielectric of a low-voltage transistor MOS LV.
[0108] In this respect, depending on the type of transistors formed and their intended voltage domain, the low-voltage dielectric layer GO can have a first thickness GO1, for example, between 1 nm and 3 nm for voltages below 1.5 V. An additional dielectric layer GO2 can be formed on top of layer GO1 to create a larger cumulative thickness, for example, between 3 nm and 6 nm for voltages below 5 V.
[0109] Figure 4F The illustration shows the formation 460 of a second conductive layer P2, for example, made of polysilicon, which is deposited over all areas of the integrated circuit.
[0110] The second conductive layer P2 will form the second frame of the control gate, capacitor element CPP(GO), CP1P2(ONO), and gate of the low-voltage transistor MOS LV in part of the memory cell NVMcell.
[0111] Figure 4G The illustration shows the first etch 470 of the second conductive layer P2, which allows the second conductive layer P2 to be removed from the region of the high-voltage transistor MOS HV-MV and defines the extent of the second mold of the high-voltage capacitor element CP1P2(ONO).
[0112] The high-voltage capacitor element CP1P2(ONO) thus formed can correspond to Figure 1 A typical example is 11.
[0113] The first etch 470 of the second conductive layer P2 also allows defining the extent of the second conductive layer P2 in the region of the capacitor element CPP(GO) so as to completely cover the first conductive layer P1 and overflow the entire outline P1cntr of the first conductive layer. Figure 3 ) boundary brdr_ext( Figure 3 On the front of FA.
[0114] The first etch 470 of the second conductive layer P2 again uses a photomask M70 to define the area exposed or not exposed to the directional etching, which is typically a plasma-type dry etching.
[0115] Furthermore, in the portion of the high-voltage transistor MOS HV-MV, the first etch 470 of the second conductive layer P2 is adapted to be selectively stopped by the dielectric layer ONO. During etch 470, the dielectric layer ONO is located between the second conductive layer P2 and the gate of the high-voltage transistor MOS HV-MV, which is defined in the first conductive layer P1.
[0116] After dry etching, the remaining portion of the dielectric layer ONO is typically present in the region of the high-voltage transistor MOS HV-MV, and the remaining portion is removed by isotropic wet etching, typically through an acid bath suitable for the composite.
[0117] During wet etching, the low-voltage dielectric layer GO completely covers the regions of the low-voltage transistor MOS LV and the capacitor element CPP (GO).
[0118] Figure 4H The illustration shows an etching step 480 suitable for high topology, which allows for the definition of floating gate and control gate stacks in a self-aligned manner within the region of the memory cell NVM cell. A photolithographic mask M80 positions the stacked grid regions.
[0119] The other areas of the integrated circuit that are particularly unsuitable for high-topology etching 480 are CP1P2, CPP, MOS HV-MV, and MOS LV, which are completely covered by the mask M80.
[0120] Figure 4I The illustration shows the second etch 490 of the second conductive layer P2, which allows for defining the location and shape of the gate structure of the low-voltage transistor MOS LV.
[0121] Furthermore, in the region of the capacitor element CPP(GO), the second etch 490 of the second conductive layer P2 allows an opening to be formed throughout the entire thickness of the second conductive layer P2, up to the first conductive layer P1.
[0122] Furthermore, the second etching 490 uses a photolithographic mask M90 to define the areas that are exposed or not exposed to the directional etching.
[0123] An opening is formed to electrically separate the first portion P2int of the second conductive layer P2 from the second portion P2ext. The first portion P2int is located in the central region of the first conductive layer P1 to form the second mold or electrode of the capacitor element CPP. The second portion P2ext is located on one side at the boundary brdr_int of the entire outline of the first conductive layer. Figure 3 On the first conductive layer P1 on the first conductive layer, on the other hand, the boundary brdr_ext of the entire outline of the first conductive layer is located at the boundary of the first conductive layer. Figure 3 On the front of FA.
[0124] Finally, conventional formation of contact posts (not shown) can be achieved in different regions of the integrated circuit to connect the resulting components to an interconnect network.
[0125] Specifically, the first metal contact CT1P1 placed in the opening allows the first mold P1 to be connected to the first electrode terminal of the capacitor element CPP(GO), and the second metal contact CT1P2 allows the second portion P2ext of the second conductive layer P2 to be connected to the first terminal of the capacitor element CPP(GO), in order to obtain the previously mentioned... Figure 2 and Figure 3 The structure described.
Claims
1. An integrated circuit including a capacitor element, comprising: A first conductive layer is disposed on the front side of the substrate, defined by a contour, and the first conductive layer forms a first component of the first electrode of the capacitor element; A low-voltage dielectric layer covers the first conductive layer; A second conductive layer is disposed on the low-voltage dielectric layer and includes: The first part is located on the upper surface of the first conductive layer at the central region of the first conductive layer, and forms the second electrode of the capacitor element; The second part includes an inner boundary portion located above the upper surface of the first conductive layer and surrounding the first part, and an outer boundary portion located above the front surface of the substrate and surrounding the first conductive layer. The second part forms the second component of the first electrode of the capacitor element; The first portion and the second portion of the second conductive layer are electrically separated; and The first conductive layer is electrically connected to the second portion of the second conductive layer.
2. The integrated circuit of claim 1, wherein the annular opening is arranged to extend through the entire thickness of the second conductive layer up to the first conductive layer, the annular opening separating the first portion of the second conductive layer located inside the shape of the annular opening from the inner boundary portion of the second portion of the second conductive layer located outside the shape of the annular opening.
3. The integrated circuit of claim 1, wherein the first conductive layer is disposed on an isolation region of the substrate of the shallow trench isolation type.
4. The integrated circuit according to claim 1, wherein the low-voltage dielectric layer is a silicon oxide layer having a thickness between 1 nanometer and 6 nanometers.
5. The integrated circuit of claim 1, wherein the low-voltage dielectric layer has the same composition and the same thickness as the gate dielectric layer of the low-voltage transistor of the integrated circuit designed to operate at a low voltage of less than 5V.
6. The integrated circuit of claim 1, wherein the second conductive layer has the same composition and the same thickness as the gate conductive region of the low-voltage transistor of the integrated circuit designed to operate at a low voltage of less than 5V.
7. The integrated circuit of claim 1, wherein the first conductive layer has the same composition and the same thickness as the gate conductive region of a high-voltage transistor of the integrated circuit designed to operate at a high voltage greater than 5V.
8. A method for manufacturing an integrated circuit including a capacitor element, comprising manufacturing the capacitor element by: A first portion of the first electrode of the capacitor element is formed by depositing a first conductive layer on the front side of the substrate and etching it to define the outline of the first conductive layer. A low-voltage dielectric layer is formed covering the first conductive layer; A second conductive layer is deposited on the front surface and on the first conductive layer covered by the low-pressure dielectric layer; A first etching defines a second conductive layer to cover the first conductive layer and the front side of the substrate, the front side surrounding the contour of the first conductive layer; The second etching electrically separates the second conductive layer into a first portion and a second portion. The first portion is located on the central region of the first conductive layer to provide a second electrode of the capacitor element. The second portion includes an inner boundary portion located above the upper surface of the first conductive layer and surrounding the first portion, and an outer boundary portion located above the front surface of the substrate and surrounding the first conductive layer to provide the first electrode. as well as An electrical connection is formed between the first conductive layer and the second portion of the second conductive layer.
9. The method of claim 8, wherein the second etching is positioned to etch an annular opening through the entire thickness of the second conductive layer up to the first conductive layer, the annular opening separating the first portion inside the shape of the annular opening of the second conductive layer from the second portion outside the shape of the annular opening of the second conductive layer.
10. The method of claim 8, further comprising: Prior to forming the first electrode, an isolation region is formed in the shallow trench isolation type substrate, wherein the first electrode is formed on the isolation region.
11. The method of claim 8, wherein the low-voltage dielectric layer is formed of a silicon oxide layer having a thickness between 1 nanometer and 6 nanometers.
12. The method of claim 8, wherein the method for manufacturing the integrated circuit further comprises manufacturing a low-voltage transistor supported by the substrate, the low-voltage transistor being intended to operate at a low voltage of less than 5V, and wherein the formation of the low-voltage dielectric layer is performed simultaneously with the formation of the gate dielectric layer of the low-voltage transistor.
13. The method of claim 8, wherein the method for manufacturing the integrated circuit further comprises manufacturing a low-voltage transistor supported by the substrate, the low-voltage transistor being intended to operate at a low voltage of less than 5V, and wherein the deposition of the second conductive layer is performed simultaneously with the deposition of a gate conductive layer of the low-voltage transistor, and wherein a second etching of the second conductive layer is performed simultaneously with the etching of the gate conductive layer, the gate conductive layer defining a gate region of the low-voltage transistor.
14. The method of claim 8, wherein the method for manufacturing the integrated circuit further comprises manufacturing a high-voltage transistor supported by the substrate, the high-voltage transistor being intended to operate at a high voltage greater than 5V, and wherein the formation of the first electrode is performed simultaneously with the formation of the gate region of the high-voltage transistor.