An on-chip soft-start circuit and control method for a switching power supply

Abstract

The application discloses an on-chip soft start circuit and a control method of a switching power supply, and the circuit comprises a current soft start control part, a voltage soft start control part, an error amplifier and a PWM comparator; wherein the current soft start control part comprises an M-bit counter, a decoder, a multi-way switch, a comparator A2, a double-way switch S2, a PMOS tube M1 and an AND gate AND1; the voltage soft start control part comprises a buffer, resistors R1 and R2, a low-pass filter, a variable current source Iref, a comparator A1, an N-bit counter and a double-way switch S1. The control method of the application divides a soft start stage into a current soft start stage and a voltage soft start stage, simultaneously considers output voltage overshoot and inrush current compared with the soft start circuit in the prior art, and shortens the soft start time.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and in particular to an on-chip soft-start circuit and control method for a switching power supply. Background Technology

[0002] Switching power supplies are widely used in various communication, industrial control, and consumer electronics products due to their high conversion efficiency, wide input / output range, small size, and stable operation. As an intermediary between power supply and consumer equipment, the startup process of a switching power supply must balance the needs of both. It must avoid generating large inrush currents that could burn out the lithium battery providing power, and it must also avoid generating large overvoltages that could damage the load. This is also to protect the switching power supply chip itself. Therefore, during the startup process, a dedicated soft-start circuit is needed to suppress both inrush current and voltage overshoot.

[0003] Traditional soft-start circuits, such as Figure 1 As shown, during the startup phase of the switching power supply, a small current Ichg charges capacitor C1, generating an error voltage at the output COMP point of EA, replacing the VBG and VFB voltages. This limits the peak value of the inductor current, allowing the output voltage to increase slowly. Whether a traditional soft-start circuit can suppress inrush current and output voltage overshoot depends on the rise rate of the voltage across capacitor C1. Only when the rise rate is slow enough can it drive the VFB voltage to rise slowly, thus suppressing output voltage overshoot. Similarly, only when the rise rate is slow enough can the COMP point voltage be adjusted to a lower value, thus suppressing inrush current.

[0004] To ensure a sufficiently slow voltage rise time (in milliseconds) across capacitor C1, the charging current Ichg needs to be in the nA range, or the size of capacitor C1 needs to be in the nF range. Small currents in the nA range are easily affected by variations in integrated circuit manufacturing processes, potentially interfering with the soft-start circuit and causing malfunctions during startup. NF-level capacitors are obviously difficult to integrate internally into the chip. Therefore, to reliably suppress voltage overshoot and inrush current, capacitor C1 needs to be externally connected to the chip.

[0005] The article "A Novel Soft-Start Circuit Design for a DC-DC Switching Power Supply," published in Volume 31, Issue 2 of *Electronic Devices*, proposes a novel soft-start circuit based on MOS technology. Utilizing peak current limiting in a current-mode DC-DC converter and digital soft-start technology, it achieves rapid and stable soft-start of the output voltage. However, it does not control the inductor current during startup. Data from the paper indicates that in the initial startup phase, the inductor current spikes to approximately 10A, failing to completely suppress the inrush current.

[0006] Patent No. 200810046622, titled "A Soft-Start Circuit for a Pulse Width Modulation DC-DC Switching Power Supply," discloses a soft-start circuit for a pulse width modulation DC-DC switching power supply. By limiting the phased, gradual increase of the peak current, the duty cycle is controlled to rise in a step-like manner, effectively avoiding inrush current during startup. However, this method is actually affected by the size of the external output capacitor; when the output capacitor is small, output voltage overshoot may occur.

[0007] Existing technologies can only effectively control output voltage overshoot or effectively suppress surge current, but cannot achieve both simultaneously. Summary of the Invention

[0008] The purpose of this invention is to provide an on-chip soft-start circuit and control method for a switching power supply, so as to simultaneously suppress the problems of output voltage overshoot and inrush current during the startup process of the switching power supply.

[0009] To solve the above-mentioned technical problems, the present invention provides an on-chip soft-start circuit for a switching power supply, comprising: a current soft-start control section, a voltage soft-start control section, an error amplifier, and a PWM comparator; The current soft-start control section includes: an M-bit counter, a decoder, a multiplexer, a comparator A2, a dual-channel switch S2, a PMOS transistor M1, and an AND gate AND1; the voltage soft-start control section includes: a buffer, resistors R1 and R2, a low-pass filter, a variable current source Iref, a comparator A1, an N-bit counter, and a dual-channel switch S1.

[0010] Furthermore, the enable signal EN and the clock signal CLK simultaneously enter the current soft-start control section and the voltage soft-start control section, and the enable signal EN and the clock signal CLK are respectively connected to the M-bit counter and the N-bit counter.

[0011] Furthermore, in the current soft-start control section, the output of the M-bit counter is connected to the input of the decoder; the output signal of the decoder controls the input Vref. <0> ~ Vref< -1> Multiplexer; the positive input of comparator A2 is connected to the voltage signal VSense obtained by current sampling, and the negative input is connected to the output signal of the multiplexer. The output of comparator A2 outputs the PeakLimit signal; the first and second inputs of dual-channel switch S2 are connected to clamping signals VclampH and VclampL respectively, and the output is connected to the gate of PMOS transistor M1. The drain of PMOS transistor M1 is connected to the output of the error amplifier and the negative input of the PWM comparator; the second input of AND gate AND1 is connected to the output of the PWM comparator, and the output outputs the PWM signal; the negative input of the error amplifier is connected to the VFB signal.

[0012] Furthermore, in the voltage soft-start control section, the bandgap reference VBG is simultaneously connected to the positive input terminal of the buffer and the first input terminal of the dual-channel switch S1. The output terminal of the buffer is connected to its own negative input terminal and one end of R1. The other end of R1 is connected to one end of R2 and one end of the low-pass filter. The second input terminal of the dual-channel switch S1 is connected to the output terminal of the low-pass filter, and the output terminal of the dual-channel switch S1 is connected to the positive input terminal of the error amplifier. The other end of R2 is connected to the variable current source Iref connected to ground and the negative input terminal of comparator A1. The positive input terminal of comparator A1 is connected to the VFB signal, and its output terminal is simultaneously connected to the third input terminal of the dual-channel switch S2, the first input terminal of the AND gate AND1, and the input terminal of the N-bit counter. The first output terminal of the N-bit counter outputs the Qb0~Qbn signals to the controllable current source Iref, and the second output terminal generates the SS_Finished control signal to the third input terminal of the dual-channel switch S1.

[0013] This invention also provides an on-chip soft-start control method for a switching power supply, comprising: During the current soft-start phase, the output voltage rises rapidly to near the set initial voltage soft-start value after the current soft-start process. During the voltage soft-start phase, the output voltage slowly rises to the final target voltage value without overshoot. After the soft start is completed, the positive input of the error amplifier is switched back to VBG via the dual-channel switch S1 to eliminate the influence of the buffer offset voltage on the accuracy of the system output voltage. At the same time, the comparator A2 is also switched back to the normal maximum current limiting reference voltage value, so that the system returns to its maximum load capacity.

[0014] Furthermore, including: Chip power-on enable; Upon entering the current soft-start stage, the positive input terminal of the error amplifier selects the VBG_SS signal, the output COMP of the error amplifier is switched to the preset VclampL high clamp, the output of the PWM comparator is shielded, and the peak current limit value is gradually increased over time. During this stage, the inductor current is set by the peak current limit comparator A2. When the VFB voltage rises to the point that comparator A1 flips, the voltage soft-start stage begins. The positive input of the error amplifier selects the VBG_SS signal, which gradually increases over time under the control of an N-bit counter. The error amplifier output COMP is high-clamped and switched to the preset VclampH. The PWM comparator output is released, and the peak current limit is the maximum value set in the current soft-start stage. When the N-bit counter finishes counting, it generates the soft-start end flag signal SS_Finished, switches the positive input of the error amplifier to the VBG voltage, switches the peak current limit value to the system's normally set current limit value, and the soft start ends.

[0015] Furthermore, during the current soft-start phase, the CLK signal, after being processed by an M-bit counter and decoder, is sequentially generated. A control signal controls a multiplexer to select different peak current limiting reference signals Vref. <0> ~ Vref< -1> causes the peak value of the inductor current to gradually increase.

[0016] Furthermore, during the voltage soft-start phase, comparator A1 judges the output voltage. When the VFB voltage rises to the preset initial value for voltage soft start, comparator A1 outputs the control signal V_SoftStart to start the N-bit counter, entering the voltage soft-start phase. The CLK signal, after passing through the N-bit counter, generates N-bit control signals Qb0~Qbn, forming... A combination of states gradually reduces the current of the variable current source Iref from Iref0 to 0, and the voltage VBG_SS at the positive input terminal of the error amplifier rises from the initial value k1*VBG to equal the voltage VBG, where k<1.

[0017] Furthermore, during the current soft-start phase, the output high clamping voltage of the error amplifier is set to a low value and the output of the PWM comparator is shielded, so that the constant voltage loop of the switching power supply operates in an open-loop state, and the peak value of the inductor current is only controlled by comparator A2 to gradually increase the current limiting value.

[0018] Furthermore, after entering the voltage soft-start stage, the output high clamping voltage of the error amplifier switches to a higher value, and the output of the PWM comparator is no longer shielded. Thus, the constant voltage loop of the switching power supply operates in a closed-loop state, and the peak value of the inductor current is jointly controlled by the PWM comparator and comparator A2.

[0019] Compared with the prior art, the present invention has at least the following beneficial effects: The technical solution of this invention divides the soft-start stage into a current soft-start stage and a voltage soft-start stage. In the current soft-start stage, a control signal controls a multiplexer to select different peak current-limiting signals, causing the inductor peak current to gradually increase, resulting in a rapid rise in the output voltage to near the set initial voltage soft-start value. In the voltage soft-start stage, the reference voltage is controlled to slowly increase from a lower initial value to the set value, thereby controlling the output voltage to slowly rise to the final target voltage value without overshoot. Compared with the soft-start circuits in the prior art, this invention simultaneously addresses output voltage overshoot and inrush current, and shortens the soft-start time. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the circuit structure of a soft-start circuit in the prior art; Figure 2 This is a schematic diagram of the circuit structure of the on-chip soft-start circuit of the switching power supply in one embodiment of the present invention; Figure 3 This is a flowchart illustrating an on-chip soft-start control method for a switching power supply according to an embodiment of the present invention. Figure 4 This is a schematic diagram of the output of an M-bit counter and decoder in one embodiment of the present invention; Figure 5 This is a schematic diagram illustrating the change of VBG_SS voltage over time in one embodiment of the present invention; Figure 6 This is a schematic diagram of the startup process of a switching power supply according to an embodiment of the present invention. Detailed Implementation

[0021] The on-chip soft-start circuit and control method of the switching power supply of the present invention will be described in more detail below with reference to the schematic diagrams, which illustrate preferred embodiments of the present invention. It should be understood that those skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the present invention.

[0022] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0023] Example 1 This embodiment 1 provides an on-chip soft-start circuit for a switching power supply. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. Please refer to... Figure 2 The on-chip soft-start circuit of the switching power supply includes: Current soft-start control section, voltage soft-start control section, error amplifier and PWM comparator; The current soft-start control section includes: an M-bit counter, a decoder, a multiplexer, a comparator A2, a dual-channel switch S2, a PMOS transistor M1, and an AND gate AND1; the voltage soft-start control section includes: a buffer, resistors R1 and R2, a low-pass filter, a variable current source Iref, a comparator A1, an N-bit counter, and a dual-channel switch S1.

[0024] Therefore, the on-chip soft-start circuit of the switching power supply proposed in this invention divides the soft-start stage into a current soft-start stage and a voltage soft-start stage, thereby simultaneously taking into account output voltage overshoot and surge current, and shortening the soft-start time.

[0025] Example 2 This embodiment 2 can be a further improvement on embodiment 1, with identical or similar parts omitted from the description. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. Specifically, as... Figure 2 As shown, this embodiment includes: The enable signal EN and the clock signal CLK simultaneously enter the current soft-start control section and the voltage soft-start control section, respectively, and are connected to the M-bit counter and the N-bit counter.

[0026] The output of the M-bit counter is connected to the input of the decoder; the output signal of the decoder controls the input as Vref. <0> ~ Vref< -1> Multiplexer; the positive input of comparator A2 is connected to the voltage signal VSense obtained by current sampling, and the negative input is connected to the output signal of the multiplexer. The output of comparator A2 outputs the PeakLimit signal; the first and second inputs of dual-channel switch S2 are connected to clamping signals VclampH and VclampL respectively, and the output is connected to the gate of PMOS transistor M1. The drain of PMOS transistor M1 is connected to the output of the error amplifier and the negative input of the PWM comparator; the positive input of the PWM comparator is connected to the VSlope signal, and the second input of AND gate AND1 is connected to the output of the PWM comparator. The output outputs the PWM signal; the negative input of the error amplifier is connected to the VFB signal.

[0027] The bandgap reference VBG is connected to both the positive input of the buffer and the first input a1 of the dual-channel switch S1. The output of the buffer is connected to its own negative input and one end of R1. The other end of R1 is connected to one end of R2 and one end of the low-pass filter. The second input of the dual-channel switch S1 is connected to the output of the low-pass filter, and the output of the dual-channel switch S1 is connected to the positive input of the error amplifier. The other end of R2 is connected to the variable current source Iref connected to ground and the negative input of comparator A1. The positive input of comparator A1 is connected to the VFB signal, and its output is connected to the third input of the dual-channel switch S2, the first input of the AND gate AND1, and the input of the N-bit counter. The first output of the N-bit counter outputs the Qb0~Qbn signals to the controllable current source Iref, and the second output generates the SS_Finished control signal to the third input of the dual-channel switch S1.

[0028] In one example, the low-pass filter can be composed of R3 and C1.

[0029] Example 3 This embodiment 3 can be a further implementation based on embodiment 1 or embodiment 2, and is not limited to the on-chip soft-start circuit of the switching power supply described in this invention. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this invention, and should not be construed as limiting this invention. Specifically, this embodiment includes: An on-chip soft-start control method for a switching power supply includes: During the current soft-start phase, the output voltage rises rapidly to near the set initial voltage soft-start value after the current soft-start process. During the voltage soft-start phase, the output voltage slowly rises to the final target voltage value without overshoot. After the soft start is complete, the input of the error amplifier is switched back to VBG, and at the same time, comparator A2 is switched back to the normal maximum current-limiting reference voltage value.

[0030] The above soft-start scheme gradually increases the current limiting value during the current soft-start phase, causing the inductor current to increase gradually from small to large. This is beneficial to the upstream power supply system, preventing damage caused by sudden current spikes. Furthermore, current soft-start allows the output voltage to reach k1 times the normal output voltage (typically k1 can be set between 0.8 and 0.9) within a short time, minimizing startup time. During the voltage startup phase, by slowly increasing the output voltage VFB, overshoot of the output voltage can be avoided.

[0031] Example 4 This embodiment 4 can be a further improvement on embodiment 3, with identical or similar parts omitted from the description. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. Specifically, please refer to... Figure 3 This embodiment includes: S1, chip power-on enable.

[0032] In S1, the bias voltage module and bias current module (not shown) operate normally, as does the clock module (not shown) that generates CLK, thus obtaining the enable signal EN and the clock signal CLK. The enable signal EN is valid, simultaneously enabling both the current soft-start control section and the voltage soft-start control section. Since the N-bit counter of the voltage soft-start control section is also controlled by the V_SoftStart signal output from comparator A1, and VFB has not yet risen above VBG-Iref0*(R1+R2), the V_SoftStart signal is invalid, therefore the voltage soft-start control circuit does not operate.

[0033] S2, enter the current soft start stage, the error amplifier selects the VBG_SS signal at the positive input terminal, the error amplifier output COMP high clamp switches to the preset VclampL, the PWM comparator output is shielded, and the peak current limit value is gradually increased over time. During this stage, the inductor current is completely set by the peak current limit comparator.

[0034] In S2, after the bias module and clock module are working normally, the current soft-start stage begins: the CLK signal is generated sequentially after passing through the M-bit counter and decoder. A control signal controls a multiplexer to select different peak current limiting reference signals Vref. <0> ~ Vref< -1> causes the peak value of the inductor current to gradually increase.

[0035] in, Figure 4 This diagram illustrates the output of an M-bit counter and decoder in one embodiment of the present invention.

[0036] For example, selecting the Vref <0> ~ Vref< The voltage signal -1> is used as the reference voltage of comparator A2 and compared with the voltage signal VSense, which represents the inductor current, obtained from current sampling. When the VSense signal is greater than the reference voltage signal at the negative input of comparator A2, comparator A2 outputs a high level to control the shutdown of the charging tube (not shown) of the switching power supply. Therefore, comparator A2 determines the peak current of the inductor. Vref <0> ~ Vref< 1> The reference voltage signal gradually increases over time, therefore, the peak current of the inductor also gradually increases.

[0037] During the current soft-start phase, the VBG_SS signal is selected at the positive input of the error amplifier (initial value set to k1*VBG, where k1<1). The error amplifier output COMP is then clamped at a high value, switching to a lower preset value VclampL. This is primarily because, since the positive input of the error amplifier is connected to VBG_SS, this voltage is always greater than VFB during the current soft-start phase. Therefore, the voltage at the COMP point of the error amplifier will be pushed to a high clamp value, i.e., VclampH+Vth, which is typically a relatively high value. When switching from current soft-start to voltage soft-start, the error amplifier output voltage needs to be adjusted from VclampH+Vth to a lower value. Due to the limitations of the error amplifier's slew rate and the loop bandwidth of the switching power supply, the adjustment speed is relatively slow, resulting in a large inrush current during the switching process. To ensure a smooth switching between current-based soft start and voltage-based soft start, and to prevent inrush current during the switching process, the COMP high-clamp reference voltage of the error amplifier is switched from VclampH+Vth to VclampL+Vth, and the COMP point voltage is made equal to VclampL+Vth, where Vth is the threshold voltage and VclampL+Vth is a relatively low value. This shortens the adjustment range of the error amplifier and allows for a faster response when switching to voltage-based soft start. Furthermore, the peak inductor current determined by this value may be smaller than the maximum peak current set for current-based soft start, potentially leading to significant differences in the load capacitance of the switching power supply system. Therefore, the PWM signal is disabled during the current-based soft start phase, effectively disconnecting the constant voltage loop of the switching power supply system and allowing the peak-limited current loop to operate independently. Thus, when switching to the voltage-based soft start phase, the COMP point voltage gradually rises from VclampL+Vth to the value required by the system loop, effectively avoiding inrush current during the switching process.

[0038] S3, when the VFB voltage rises to the point that comparator A1 flips, the voltage soft-start stage begins. The positive input of the error amplifier selects the VBG_SS signal, which gradually increases over time under the control of an N-bit counter. The error amplifier output COMP high clamp switches to the preset VclampH, the PWM comparator output is released, and the peak current limit is the maximum value set in the current soft-start stage.

[0039] In S3, when the VFB voltage rises to a level that causes comparator A1 to flip, for example, when VFB rises above VBG-Iref0*(R1+R2), the voltage soft-start stage begins. During the voltage soft-start stage, comparator A1 judges the output voltage. When the VFB voltage rises to the preset initial value for voltage soft-start, comparator A1 outputs a control signal V_SoftStart to start the N-bit counter, entering the voltage soft-start phase. The CLK signal, after passing through the N-bit counter, generates N-bit control signals Qb0~Qbn, forming... A combination of states gradually reduces the current of the variable current source Iref from Iref0 to 0, and the voltage VBG_SS at the positive input terminal of the error amplifier rises from the initial value k1*VBG to equal the voltage VBG, where k<1.

[0040] You can select Vref <0> The peak current-limiting reference voltage between ~Vref<2M-1> enters the voltage soft-start phase, depending on the load size, but the maximum value of the peak current is set by the reference voltage Vref<2M-1>. The advantage of this approach is that the duration of the current soft-start phase can be adaptively adjusted according to different loads, thus shortening the total soft-start time when the load is relatively small.

[0041] The positive input of the error amplifier is selected from the VBG_SS voltage signal. This signal is generated by the variable current source Iref through resistors R1 and R2 after the VBG voltage passes through the buffer. The voltage is less than VBG and the initial value is k1*VBG.

[0042] Please refer to Figure 5 Before the constant voltage loop starts working, the initial current on the variable current source Iref is Iref0. Ignoring the offset voltage of the buffer, its output voltage is equal to VBG. Therefore, the initial voltage of VBG_SS is: VBG_SS0=VBG-Iref0*R1 (1) For a variable current source, it is generally implemented through a VI conversion circuit, and its value is Iref0=VBG / R0. Substituting into (1), we get: VBG_SS0=VBG-Iref0*R1= VBG*(1-R1 / R0)= VBG*k1 (2) Where k1=(1-R1 / R0), is a constant less than 1. In the design, the ratio of R1 to R0 can be adjusted to set the initial voltage value of the constant voltage stage.

[0043] According to equation (1), when the variable current source Iref decreases to 0, VBG_SS becomes completely equal to VBG. Therefore, by controlling the variable current source to gradually decrease to 0 over time, VBG_SS can be gradually increased to the VBG voltage over time. A 2-bit counter, ranging from all 0s to all 1s, is generated. N There are two combinations, meaning the number of steps in the transformation of VBG_SS from VBG*k to VBG is 2. N The voltage increment at each step can be obtained as follows: △V = VBG*(1-k1) / 2 N (3) Unlike current-based soft-start time, voltage-based soft-start time is fixed, determined by the period Tclk of clock CLK and the number of steps within it. Its expression is as follows: T v_ss = 2 N *Tclk (4) During the voltage soft-start phase, the error amplifier output COMP high clamp switches to the preset VclampH, and the PWM comparator output is also released. The peak current limit is the maximum value set during the current soft-start phase. The VFB voltage is slowly increased by the VBG_SS voltage, thus preventing output voltage overshoot.

[0044] During the current soft-start phase, the output high clamping voltage of the error amplifier is set to a low value and the output of the PWM comparator is shielded, so that the constant voltage loop of the switching power supply works in an open-loop state, and the peak value of the inductor current is only controlled by comparator A2 to gradually increase the current limit value.

[0045] After entering the voltage soft-start stage, the output high clamping voltage of the error amplifier switches to a higher value and no longer shields the output of the PWM comparator. As a result, the constant voltage loop of the switching power supply operates in a closed loop state, and the peak value of the inductor current is jointly controlled by the PWM comparator and comparator A2.

[0046] S4, the N-bit counter completes counting, generating the soft-start end flag signal SS_Finished, switching the positive input of the error amplifier to VBG voltage, and switching the peak current limit value to the system's normally set current limit value, thus ending the soft start.

[0047] Before the N-bit counter reaches full count and outputs all 1s, the SS_Finished signal is low, controlling the dual-channel selection switch 1 to select the VBG_SS signal. The signal filtered by the low-pass filter composed of R3 and C1 enters the positive input of the error amplifier, controlling the pull voltage VFB to rise slowly. When the N-bit counter reaches full count and outputs all 1s, the SS_Finished signal is high, controlling the dual-channel selection switch 1 to select the VBG signal. This eliminates the influence of buffer offset voltage on the output voltage accuracy.

[0048] When SS_Finished is 1, it indicates that the soft start is over. This signal will also control the multiplexer to switch the peak current limiting reference voltage signal back to the current limiting value for normal system operation, ensuring the normal load-carrying capacity of the system.

[0049] Please refer to Figure 6 From the startup process results, the peak inductor current experienced three gradual increases during the current-driven startup phase, corresponding to three gradual increases in the output voltage slope during the current-soft-start phase. Upon entering the voltage-soft-start phase, the constant voltage loop intervenes, undergoing a period of loop adjustment in the early stages. Subsequently, the inductor current stabilizes, and the output voltage rises slowly with a small slope. As mentioned earlier, the solution of this invention can completely control the inductor current and output voltage throughout the entire startup phase, preventing inrush current and output voltage overshoot.

[0050] Compared with the prior art, the present invention has at least the following beneficial effects: The technical solution of this invention divides the soft-start stage into a current soft-start stage and a voltage soft-start stage. In the current soft-start stage, a control signal controls a multiplexer to select different peak current-limiting signals, causing the inductor peak current to gradually increase, resulting in a rapid rise in the output voltage to near the set initial voltage soft-start value. In the voltage soft-start stage, the reference voltage is controlled to slowly increase from a lower initial value to the set value, thereby controlling the output voltage to slowly rise to the final target voltage value without overshoot. Compared with the soft-start circuits in the prior art, this invention simultaneously addresses output voltage overshoot and inrush current, and shortens the soft-start time.

[0051] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. An on-chip soft-start circuit for a switching power supply, characterized in that, It includes a current soft-start control section, a voltage soft-start control section, an error amplifier, and a PWM comparator; The current soft-start control section includes: an M-bit counter, a decoder, a multiplexer, a comparator A2, a dual-channel switch S2, a PMOS transistor M1, and an AND gate AND1; the voltage soft-start control section includes: a buffer, resistors R1 and R2, a low-pass filter, a variable current source Iref, a comparator A1, an N-bit counter, and a dual-channel switch S1. The clock signal CLK enters the voltage soft-start control section. In the voltage soft-start control section, the bandgap reference voltage VBG is connected to both the positive input of the buffer and the first input of the dual-channel switch S1. The output of the buffer is connected to its own negative input and one end of R1. The other end of R1 is connected to one end of R2 and one end of the low-pass filter. The second input of the dual-channel switch S1 is connected to the output of the low-pass filter, and the output of the dual-channel switch S1 is connected to the positive input of the error amplifier. The other end of R2 is connected to the variable current source Iref connected to ground and the negative input of comparator A1. The positive input of comparator A1 is connected to the output voltage feedback voltage VFB, and its output is connected to the third input of the dual-channel switch S2, the first input of the AND gate AND1, and the input of the N-bit counter. The first output of the N-bit counter outputs the Qb0~Qbn signals to the variable current source Iref, and the second output generates the SS_Finished control signal to the third input of the dual-channel switch S1.

2. The on-chip soft-start circuit of the switching power supply as described in claim 1, characterized in that, The enable signal EN enters the current soft-start control section, and both the enable signal EN and the clock signal CLK are connected to the M-bit counter and the N-bit counter, respectively.

3. The on-chip soft-start circuit of the switching power supply as described in claim 2, characterized in that, In the current soft-start control section, the output of the M-bit counter is connected to the input of the decoder; the output signal of the decoder controls the input Vref. <0> ~Vref<2 M -1> Multiplexer; the positive input of comparator A2 is connected to the voltage signal VSense obtained by current sampling, and the negative input is connected to the output signal of the multiplexer. The output of comparator A2 outputs the PeakLimit signal; the first and second inputs of dual-channel switch S2 are connected to clamping signals VclampH and VclampL respectively, and the output is connected to the gate of PMOS transistor M1. The drain of PMOS transistor M1 is connected to the output of the error amplifier and the negative input of the PWM comparator. The second input of AND gate AND1 is connected to the output of the PWM comparator, and the output outputs the PWM signal; the negative input of the error amplifier is connected to the output voltage feedback voltage VFB.

4. An on-chip soft-start control method for a switching power supply, implemented using the on-chip soft-start circuit of the switching power supply as described in any one of claims 1-3, characterized in that, The method includes: During the current soft-start phase, the output voltage rises rapidly to near the set initial voltage soft-start value after the current soft-start process. During the voltage soft-start phase, the output voltage slowly rises to the final target voltage value without overshoot. After the soft start is complete, the positive input of the error amplifier is switched back to the bandgap reference voltage VBG, and at the same time, the comparator A2 is switched back to the normal maximum current-limiting reference voltage value.

5. The on-chip soft-start control method for a switching power supply as described in claim 4, characterized in that, include: Chip power-on enable; Upon entering the current soft-start stage, the positive input terminal of the error amplifier selects the VBG_SS signal; where the VBG_SS signal is the voltage generated across resistors R1 and R2 by the variable current source Iref after the bandgap reference voltage VBG is buffered; the error amplifier output COMP high clamp switches to the clamp signal VclampL, the PWM comparator output is shielded, and the peak current limit of the inductor current is gradually increased over time. During this stage, the inductor current is set by the peak current limit comparator A2; When the output voltage feedback voltage VFB rises to the point that comparator A1 flips, the voltage soft-start stage begins. The positive input terminal of the error amplifier selects the VBG_SS signal, which gradually increases over time under the control of an N-bit counter. The error amplifier output COMP high clamp switches to the clamp signal VclampH, the PWM comparator output is released, and the peak current limit of the inductor current is the maximum value set in the current soft-start stage. When the N-bit counter finishes counting, it generates a soft-start end flag signal SS_Finished, switches the positive input of the error amplifier to the bandgap reference voltage VBG, switches the peak current limit of the inductor current to the system's normally set current limit, and the soft start ends.

6. The on-chip soft-start control method for a switching power supply as described in claim 5, characterized in that, During the current soft-start phase, the clock signal CLK, after being processed by an M-bit counter and decoder, sequentially generates control signals to control the multiplexer to select different peak current limiting reference signals Vref. <0> ~Vref<2 M -1> causes the peak value of the inductor current to gradually increase.

7. The on-chip soft-start control method for a switching power supply as described in claim 5, characterized in that, During the voltage soft-start phase, comparator A1 judges the output voltage. When the output voltage feedback voltage VFB rises to the preset initial value for voltage soft start, comparator A1 outputs the control signal V_SoftStart to start the N-bit counter, entering the voltage soft start phase. The CLK signal, after passing through the N-bit counter, generates N-bit control signals Qb0~Qbn, forming a 2... N A combination of states gradually reduces the current of the variable current source Iref from Iref0 to 0, and the voltage VBG_SS at the positive input terminal of the error amplifier rises from the initial value k1×VBG to equal the bandgap reference voltage VBG, where k<1.

8. The on-chip soft-start control method for a switching power supply as described in claim 5, characterized in that, During the current soft-start phase, the high clamping voltage of the error amplifier is set to the clamping signal VclampL and the output of the PWM comparator is shielded, so that the constant voltage loop of the switching power supply works in an open-loop state, and the peak value of the inductor current is only controlled by comparator A2 to gradually increase the current limit value.

9. The on-chip soft-start control method for a switching power supply as described in claim 5, characterized in that, After entering the voltage soft-start stage, the high clamping voltage of the error amplifier is switched to the clamping signal VclampH, and the output of the PWM comparator is no longer shielded. Thus, the constant voltage loop of the switching power supply works in a closed loop state, and the peak value of the inductor current is jointly controlled by the PWM comparator and comparator A2.

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