A precision adjustable multi-phase clock generation circuit for a successive approximation analog-to-digital converter

Abstract

The application discloses a precision-adjustable multi-phase clock generation circuit for a successive approximation register analog-to-digital converter (SAR ADC), which comprises an AND gate, a NOT gate, an OR gate, a D flip-flop, an adjustable delay unit and a delay unit, the adjustable delay unit comprises a first adjustable delay unit and a second adjustable delay unit; the clock input end Ck of the D flip-flop is connected with the output end Q of the AND gate through the first adjustable delay unit, the output end Q of the AND gate is connected with the delay unit through the first adjustable delay unit, the delay unit is connected with the OR gate through the second adjustable delay unit, and the input end of the delay unit is connected with the OR gate through the NOT gate. The number of clock cycles is adjusted by adding the adjustable delay unit in the loop, and then the number of bits of the SAR ADC, that is, the precision, is adjusted, so that the ADC can adapt to different application scenarios.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, and more specifically to a precision-adjustable multiphase clock generation circuit for a successive approximation analog-to-digital converter. Background Technology

[0002] In recent years, successive approximation analog-to-digital converters (SAR ADCs) have become a hot topic in ADC research due to their high accuracy, simple circuit structure, low power consumption, and ease of integration with digital circuits. Generally, an N-bit SAR ADC requires one sampling and N comparisons to obtain the final output.

[0003] Traditional multiphase clock generation circuits based on single negative pulse generators (SNPGs) such as Figure 1-2 As shown, the shift register consists of a D flip-flop triggered by the rising edge of SNPG, a rising edge triggered negative pulse NPG, and an AND.

[0004] The working process is as follows: Before the conversion begins, the conversion enable signal F1 is low, the shift register composed of D flip-flops is asynchronously cleared, and the AND output is low. After the conversion begins, the conversion enable signal F1 changes from low to high, and the AND output signal generates a rising edge; the D flip-flops in the shift register are triggered, the output of the first D flip-flop changes from low to high, generating a new rising edge, while the outputs of the remaining D flip-flops remain unchanged; the NPG connected to the first D flip-flop receives the rising edge generated by the preceding D flip-flop and generates a negative pulse. After the negative pulse passes through the AND gate, a negative pulse also appears in the AND output signal; the newly generated rising edge in the AND output signal triggers the shift register, the output of the second D flip-flop changes from low to high, while the outputs of the remaining D flip-flops remain unchanged, and the remaining process is similar to the previous one until the required clock is generated.

[0005] The accuracy requirements of ADC vary depending on the application scenario. For example, in the scenario of biosignal measurement, the accuracy requirement of ADC is around 8-18 bits, while in the scenario of high-precision weighing scale, the accuracy requirement of ADC needs to reach more than 20 bits. It can be seen that if the accuracy of SAR ADC is not adjusted in time, it may not meet the operational requirements, and may also increase useless power consumption and redundant data. Summary of the Invention

[0006] This invention addresses the drawback of the inability to adjust the number of clock cycles generated by a multiphase clock generation circuit based on a traditional single negative pulse generator. It improves upon this by adding an adjustable delay unit to the loop to control the number of clock cycles, thereby enabling the SAR ADC to adjust its bit depth, i.e., its precision, so that the ADC can be adapted to different application scenarios.

[0007] An adjustable multiphase clock generation circuit for a successive approximation analog-to-digital converter includes AND gates, NOT gates, OR gates, D flip-flops, and delay units. It also includes an adjustable delay unit and a data processing unit. The adjustable delay unit includes a first adjustable delay unit and a second adjustable delay unit, which respectively employ a ring oscillator and a delay phase-locked loop. The clock input Ck of the D flip-flop is connected to the AND gate, and the output Q is connected to the delay unit through the first adjustable delay unit. The delay unit is connected to the OR gate through the second adjustable delay unit. The input of the delay unit is connected to the OR gate through the NOT gate. The data processing unit receives data input and connects to the adjustable delay unit and the output of the OR gate, respectively.

[0008] The delay time can be adjusted by using an adjustable delay unit, so that the circuit can generate the required clock cycle, thus achieving the adjustment of accuracy.

[0009] The adjustable delay unit uses a ring oscillator to form a ring by connecting several delay units end to end. The ring then oscillates to generate a multi-phase clock. At the same time, a delay phase-locked loop is used to control the voltage of the delay unit circuit to improve accuracy and enhance environmental adaptability.

[0010] Furthermore, the data processing unit includes a register, a comparator, and a counter connected in sequence.

[0011] Furthermore, in the data processing unit, a register receives data input and is connected to the first adjustable delay unit.

[0012] Furthermore, in the data processing unit, the comparator is connected to the second adjustable delay unit.

[0013] Furthermore, in the data processing unit, the counter is connected to the output of the OR gate.

[0014] Further, the number of clock cycles corresponding to the required number of bits is written into the register. Then, the counter measures the number of clock cycles and compares the result with the value in the register. If the comparison result is too large, the adjustable delay unit increases the delay time. If the comparison result is too small, the adjustable delay unit decreases the delay time. The above operation is repeated until the number of clock cycles measured by counter B meets the required number of cycles.

[0015] Furthermore, the adjustable delay unit employs a ring oscillator, which connects the delay units end to end to form a ring, and then the ring oscillates to generate a multi-phase clock.

[0016] Furthermore, the adjustable delay unit employs a delay phase-locked loop to achieve voltage-controlled delay of the delay unit circuit, thereby providing a precise multiphase clock.

[0017] The beneficial effects achieved by this invention are as follows: 1. The number of cycles can be adjusted by using an adjustable delay unit, thereby enabling the SAR ADC to achieve adjustable accuracy, meeting the requirements of SAR ADC sampling and detection accuracy in different application scenarios, while avoiding unnecessary power consumption and the increase of redundant data; 2. The circuit structure is simple, with low power consumption and low phase noise; 3. The adjustable delay unit can use a delay phase-locked loop, which improves high precision and enhances environmental adaptability through voltage control. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a traditional multiphase clock generation circuit based on a single negative pulse generator in an embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of a conventional single negative pulse generator circuit in an embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of an adjustable-precision multiphase clock generation circuit in an embodiment of the present invention.

[0021] Figure 4 This is a flowchart illustrating the working process of clock cycle number adjustment in the multiphase clock generation circuit of this invention.

[0022] Figure 5 This is a schematic diagram of the simulation results of the precision adjustable multiphase clock generation circuit in the embodiment of the present invention. Detailed Implementation

[0023] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings.

[0024] This invention solves this problem by incorporating an adjustable delay unit. For example... Figure 1 As shown, the adjustable delay unit includes a first adjustable delay unit Delay1 and a second adjustable delay unit Delay2; the clock input Ck of the D flip-flop is connected to the AND gate, and the output Q is connected to the delay unit BUF through the first adjustable delay unit Delay1. The delay unit BUF is connected to the OR gate I2 through the second adjustable delay unit Delay2; the input of the delay unit BUF is connected to the OR gate I2 through the NOT gate I1; the adjustable delay units Delay1 and Delay2 are inserted into the NPG, and by adjusting the delay time of Delay1 and Delay2, the clock period generated by the circuit is made close to the required period.

[0025] Specific implementation circuits for adjustable delay units include ring oscillators and delay phase-locked loops. A ring oscillator connects several delay units end to end to form a ring, and then the ring oscillates to generate a multi-phase clock. Its characteristics are low power consumption and low phase noise.

[0026] Delay-locked loops (PLLs) use PLL technology to voltage-control delay lines in delay unit circuits, thereby providing accurate multiphase clocks. The principle is that delay lines are less affected by noise compared to oscillators. Damaged zero-crossing points in the waveform disappear at the end of the delay line, while they would recycle in an oscillator circuit, thus causing more damage. Secondly, in voltage-controlled delay line circuits, changes in the control voltage can rapidly alter the delay time, significantly reducing stability and stabilization speed issues compared to oscillators.

[0027] like Figure 3 As shown, two adjustable delay units are added. The required number of clock cycles corresponding to the number of bits is written to register A. Then, counter B measures the number of clock cycles and compares the result with the value in register A. If the comparison result is too large, Delay1 and Delay2 will appropriately increase the delay time; if the comparison result is too small, Delay1 and Delay2 will appropriately decrease the delay time. The device automatically adjusts the delay. If there is a deviation in the comparison result, the delay time is adjusted by adjusting the number of inverters connected in the ring oscillator. The above operation is repeated until the number of clock cycles measured by counter B meets the required number of cycles, and the delay time is adjusted accordingly. This achieves the control of the number of cycles, thereby realizing the adjustable accuracy of the SAR ADC and ultimately meeting the requirements of SAR ADC sampling and detection accuracy in different application scenarios.

[0028] Successive approximation ADCs with 16 bits or more can be used in test instruments, sensor monitoring networks, medical electronics, and biological front-ends, where power consumption is relatively high. 12-14 bit ADCs are mainly used in voice and mobile communications. 8-10 bit ADCs are mainly used in sensors and RF circuits, where power consumption is generally lower. By setting the clock period, the number of comparisons of the SAR ADC can be set to meet the requirements of the effective number of bits for specific application scenarios, thereby effectively adjusting the sampling accuracy.

[0029] Figure 5 The simulation verification shows that the accuracy adjustment is achieved by changing the number of clock cycles in register A, where SNR is the signal-to-noise ratio and ENOB is the number of effective bits, i.e., the accuracy.

[0030] The above description is only a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. Any equivalent modifications or changes made by those skilled in the art based on the content disclosed in the present invention should be included within the scope of protection set forth in the claims.

Claims

1. A precision-adjustable multiphase clock generation circuit for a successive approximation analog-to-digital converter, comprising AND gates, NOT gates, OR gates, D flip-flops, and delay units, characterized in that: It also includes an adjustable delay unit and a data processing unit, wherein the adjustable delay unit includes a first adjustable delay unit and a second adjustable delay unit; The clock input Ck of the D flip-flop is connected to the AND gate, and the output Q is connected to the delay unit through the first adjustable delay unit. The delay unit is connected to the OR gate through the second adjustable delay unit. The input of the delay unit is connected to the OR gate through the NOT gate. The data processing unit receives data input and connects to the adjustable delay unit and the output of the OR gate, respectively. The delay time can be adjusted by using an adjustable delay unit, so that the circuit can generate the required clock cycle, that is, the accuracy can be adjusted. Two adjustable delay units write the required number of clock cycles corresponding to the number of bits into register A. Then, counter B measures the number of clock cycles and compares the result with the value in register A. If the comparison result is larger, the first adjustable delay unit Delay1 and the second adjustable delay unit Delay2 will increase the delay time. If the comparison result is smaller, Delay1 and Delay2 will decrease the delay time. The device adjusts automatically. If there is a deviation in the comparison result, the delay time is adjusted by adjusting the number of inverters connected in the ring oscillator. The above operation is repeated until the number of clock cycles measured by counter B meets the required number of cycles, and the delay time is adjusted accordingly. This achieves the control of the number of cycles and realizes the adjustable accuracy of the successive approximation analog-to-digital converter (SAR ADC).

2. The precision-adjustable multiphase clock generation circuit for a successive approximation analog-to-digital converter according to claim 1, characterized in that: The data processing unit includes a register, a comparator, and a counter connected in sequence.

3. The precision-adjustable multiphase clock generation circuit for a successive approximation analog-to-digital converter according to claim 2, characterized in that: In the data processing unit, the register receives data input and is connected to the first adjustable delay unit.

4. The precision-adjustable multiphase clock generation circuit for a successive approximation analog-to-digital converter according to claim 2, characterized in that: In the data processing unit, the comparator is connected to the second adjustable delay unit.

5. The precision-adjustable multiphase clock generation circuit for a successive approximation analog-to-digital converter according to claim 2, characterized in that: In the data processing unit, the counter is connected to the output of the OR gate.

6. The precision-adjustable multiphase clock generation circuit for a successive approximation analog-to-digital converter according to claim 1, characterized in that: Write the number of clock cycles corresponding to the required number of bits into the register. Then, the counter measures the number of clock cycles and compares the result with the value in the register. If the comparison result is too large, the adjustable delay unit increases the delay time. If the comparison result is too small, the adjustable delay unit decreases the delay time. Repeat the above operation until the number of clock cycles measured by counter B meets the required number of cycles.

7. The precision-adjustable multiphase clock generation circuit for a successive approximation analog-to-digital converter according to claim 1, characterized in that: The adjustable delay unit uses a ring oscillator. By connecting the delay units end to end to form a ring, the ring oscillates to generate a multi-phase clock.

8. The precision-adjustable multiphase clock generation circuit for a successive approximation analog-to-digital converter according to claim 1, characterized in that: The adjustable delay unit uses a delay phase-locked loop to achieve voltage-controlled delay of the delay unit circuit, thereby providing a precise multiphase clock.

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