Computing device, data processing method, and related products

Abstract

The present disclosure discloses a computing device, a data processing method and related products. The computing device can be included in a combined processing device, which can further include an interface device and other processing devices. The computing device interacts with the other processing devices to jointly complete a user-specified computing operation. The combined processing device can further include a storage device connected to the computing device and the other processing devices respectively, for storing data of the computing device and the other processing devices. The scheme of the present disclosure provides a hardware architecture for executing a Hamming weight instruction, which can simplify processing and improve the processing efficiency of the machine.

Description

Technical Field

[0001] This disclosure generally relates to the field of processors. More specifically, this disclosure relates to computing devices, data processing methods, chips, and circuit boards. Background Technology

[0002] In information theory, Hamming distance is defined as the distance between two strings of equal length, which is the number of distinct characters at corresponding positions in the two strings. For example, the Hamming distance between the binary character sequences 10011001 and 10101010 is 4; the Hamming distance between the number sequences 12345678 and 22345768 is 3; and the Hamming distance between the word sequences "familes" and "familar" is 2. Hamming weight is the Hamming distance of a string relative to a string of zeros of the same length; that is, it is the number of non-zero elements in the string. For binary strings, it is the number of 1s, so the Hamming weight of 11101 is 4. In fact, Hamming weight analysis is widely used in information theory, coding theory, cryptography, information retrieval, text translation, and other fields.

[0003] On the other hand, with the rapid development of deep learning, hardware architectures such as chips and processors suitable for deep learning processing have also made leaps and bounds. If Hamming weight analysis can be ported to hardware architectures suitable for deep learning processing, it is possible to accelerate Hamming weight analysis processing and improve the processing efficiency of related processes in various fields. Existing hardware and / or instruction sets cannot effectively support Hamming weight analysis-related operations. Summary of the Invention

[0004] In order to at least partially solve one or more of the technical problems mentioned in the background art, the present disclosure provides a computing device, a data processing method, a chip, and a board.

[0005] In a first aspect, this disclosure discloses a computing device including a control circuit and an arithmetic circuit, wherein: the control circuit is configured to parse a Hamming weight instruction, the Hamming weight instruction operating on a binary sequence, the Hamming weight instruction instructing the counting of the number of "1"s in the binary sequence to be used as its Hamming weight; and the arithmetic circuit includes a plurality of slave processing circuits, and the arithmetic circuit is configured to schedule a corresponding number of slave processing circuits to perform a Hamming weight calculation task according to the Hamming weight instruction, wherein each scheduled slave processing circuit counts the number of "1"s in a sequence segment of the assigned binary sequence.

[0006] In a second aspect, this disclosure provides a chip that includes a computing device according to any of the embodiments of the first aspect.

[0007] In a third aspect, this disclosure provides a board including the chip of any of the embodiments of the second aspect above.

[0008] In a fourth aspect, this disclosure provides a data processing method implemented by a computing device, the computing device including a control circuit and an arithmetic circuit, the arithmetic circuit including a plurality of slave processing circuits, the method comprising: the control circuit parsing a Hamming weight instruction, the Hamming weight instruction operating on a binary sequence, the Hamming weight instruction instructing the counting of the number of "1"s in the binary sequence as its Hamming weight; and the arithmetic circuit scheduling a corresponding number of slave processing circuits to perform a Hamming weight calculation task according to the Hamming weight instruction, wherein each scheduled slave processing circuit counts the number of "1"s in a sequence segment of the allocated binary sequence.

[0009] Using the computing device, data processing method, integrated circuit chip, and board provided above, this disclosure provides a scheme for performing Hamming weight analysis on a hardware architecture including multiple slave processing circuits. The Hamming weight calculation task can be distributed across multiple slave processing circuits, thereby fully utilizing the computational advantages of deep learning processing hardware architectures and improving machine processing efficiency through parallel computation. Attached Figure Description

[0010] The above and other objects, features, and advantages of exemplary embodiments of this disclosure will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0011] Figure 1 This diagram shows the structure of the board card according to an embodiment of this disclosure;

[0012] Figure 2 This diagram illustrates the structure of the combined processing apparatus according to an embodiment of the present disclosure.

[0013] Figure 3 A schematic diagram illustrating the internal structure of a processor core in a single-core or multi-core computing device according to embodiments of the present disclosure;

[0014] Figure 4 This diagram illustrates an exemplary structural schematic of a computing device according to an embodiment of the present disclosure.

[0015] Figure 5 A partial structural schematic diagram of the arithmetic circuit in a computing device according to an embodiment of this disclosure is shown;

[0016] Figure 6 This diagram shows partial structural schematics of the main processing circuit and the slave processing circuit according to embodiments of this disclosure; and

[0017] Figure 7 An exemplary flowchart of a data processing method according to an embodiment of this disclosure is shown. Detailed Implementation

[0018] The technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0019] It should be understood that the terms "first," "second," "third," and "fourth," etc., that may appear in the claims, specification, and drawings of this disclosure are used to distinguish different objects, rather than to describe a specific order. The terms "comprising" and "including" as used in the specification and claims of this disclosure indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

[0020] It should also be understood that the terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0021] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection."

[0022] The specific embodiments disclosed herein will now be described in detail with reference to the accompanying drawings.

[0023] Figure 1 A schematic diagram of the structure of a board 10 according to an embodiment of this disclosure is shown. Figure 1As shown, board 10 includes chip 101, which is a system-on-chip (SoC) integrating one or more combined processing units. These combined processing units are artificial intelligence computing units used to support various deep learning and machine learning algorithms, meeting the intelligent processing needs of complex scenarios in fields such as computer vision, speech, natural language processing, and data mining. In particular, deep learning technology is widely used in cloud intelligence. A significant characteristic of cloud intelligence applications is the large volume of input data, placing high demands on the platform's storage and computing capabilities. Board 10 in this embodiment is suitable for cloud intelligence applications, possessing massive off-chip storage, on-chip storage, and powerful computing capabilities.

[0024] Chip 101 is connected to external device 103 via external interface device 102. External device 103 may be, for example, a server, computer, camera, monitor, mouse, keyboard, network card, or Wi-Fi interface. Data to be processed can be transmitted from external device 103 to chip 101 via external interface device 102. The calculation results from chip 101 can be transmitted back to external device 103 via external interface device 102. Depending on the application scenario, external interface device 102 may have different interface forms, such as a PCIe interface.

[0025] The board 10 also includes a storage device 104 for storing data, which includes one or more memory cells 105. The storage device 104 is connected to and transmits data with the controller 106 and the chip 101 via a bus. The controller 106 in the board 10 is configured to regulate the state of the chip 101. Therefore, in one application scenario, the controller 106 may include a microcontroller (MCU).

[0026] Figure 2 This is a structural diagram illustrating the combined processing device in chip 101 of this embodiment. (As shown) Figure 2 As shown, the combined processing device 20 includes a computing device 201, an interface device 202, a processing device 203, and a storage device 204.

[0027] The computing device 201 is configured to perform user-specified operations. It is mainly implemented as a single-core intelligent processor or a multi-core intelligent processor to perform deep learning or machine learning calculations. It can interact with the processing device 203 through the interface device 202 to jointly complete the user-specified operations.

[0028] Interface device 202 is used to transmit data and control commands between computing device 201 and processing device 203. For example, computing device 201 can obtain input data from processing device 203 via interface device 202 and write it to on-chip storage device of computing device 201. Further, computing device 201 can obtain control commands from processing device 203 via interface device 202 and write them to on-chip control cache of computing device 201. Alternatively or optionally, interface device 202 can also read data from storage device of computing device 201 and transmit it to processing device 203.

[0029] Processing device 203, as a general-purpose processing device, performs basic control including but not limited to data transfer, and starting and / or stopping computing device 201. Depending on the implementation, processing device 203 may be one or more types of processors, including but not limited to digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As mentioned above, computing device 201 disclosed herein can be considered as having a single-core structure or a homogeneous multi-core structure. However, when computing device 201 and processing device 203 are considered together, they are considered to form a heterogeneous multi-core structure.

[0030] Storage device 204 is used to store data to be processed. It may be DRAM or DDR memory, typically 16G or larger in size, and is used to store data of computing device 201 and / or processing device 203.

[0031] Figure 3 The diagram shows the internal structure of the processing core when the computing device 201 is a single-core or multi-core device. The computing device 301 is used to process input data such as computer vision, speech, natural language, and data mining. The computing device 301 includes three main modules: a control module 31, a processing module 32, and a storage module 33.

[0032] The control module 31 coordinates and controls the operation of the computation module 32 and the storage module 33 to complete the deep learning task. It includes an instruction fetch unit (IFU) 311 and an instruction decode unit (IDU) 312. The instruction fetch unit 311 fetches instructions from the processing device 203, and the instruction decode unit 312 decodes the fetched instructions and sends the decoding result as control information to the computation module 32 and the storage module 33.

[0033] The computation module 32 includes a vector operation unit 321 and a matrix operation unit 322. The vector operation unit 321 is used to perform vector operations and can support complex operations such as vector multiplication, addition, and nonlinear transformations; the matrix operation unit 322 is responsible for the core computations of deep learning algorithms, namely matrix multiplication and convolution.

[0034] The storage module 33 is used to store or move relevant data, including a neuron RAM (NRAM) 331, a weight RAM (WRAM) 332, and a direct memory access (DMA) module 333. The NRAM 331 stores the input neurons, output neurons, and intermediate results after computation; the WRAM 332 stores the convolution kernels of the deep learning network, i.e., the weights; the DMA 333 is connected to the DRAM 204 via bus 34 and is responsible for data transfer between the computing device 301 and the DRAM 204.

[0035] Based on the aforementioned hardware environment, in one aspect, this disclosure provides a computing device that performs a Hamming weight calculation task according to a Hamming weight instruction. As mentioned earlier, Hamming distance is the number of different characters at corresponding positions between two strings of equal length, that is, the number of characters that need to be replaced to transform one string into another, which can represent the similarity between the two strings. The meaning of Hamming distance can also be extended to the distance between higher-dimensional data, such as the distance between two 2D images or two 3D images, counting the number of different data bits between them. Whether it is two-dimensional data, three-dimensional data, or higher-dimensional data, the Hamming distance can be converted into performing a bitwise XOR operation between the two data to be calculated to obtain a binary sequence, counting the number of "1"s in the binary sequence, that is, calculating the Hamming weight of the binary sequence, and thus using it as the Hamming distance between the two data. Here, "bit" can be each character bit, each number bit, each bit, or even a "bit" composed of multiple data units, depending on different application scenarios. This disclosure embodiment has no limitation in this regard. The binary sequence obtained after the bitwise XOR operation may be very long. Therefore, if the aforementioned hardware environment can be fully utilized to explore the possibilities of parallel data processing, computation can be accelerated and efficiency improved.

[0036] Figure 4 A schematic structural block diagram of a computing device 400 according to an embodiment of this disclosure is shown. It can be understood that this structure can be considered as... Figure 3 The refinement of the internal structure of a single processing core can also be viewed as the refinement of multiple cores. Figure 3 The diagram shows the functional partitioning based on the processing core. Figure 4 As shown, the computing device 400 of this embodiment can be used to perform Hamming weight calculation tasks. It may include a storage circuit 40, a control circuit 41 and an arithmetic circuit 42, which are interconnected to transmit various data and instructions.

[0037] The function of control circuit 41 and Figure 3Similar to the control module 31, it may also include, for example, an instruction fetch unit (IFU) 411 and an instruction decode unit (IDU) 412. In various arithmetic operations, such as computation, the control circuit 41 can be configured to fetch computation instructions, parse them to obtain arithmetic instructions, and then send the arithmetic instructions to the arithmetic circuit 42 and the storage circuit 40. The computation instructions can be a form of hardware instruction and include one or more opcodes, each opcode representing one or more specific operations to be executed by the arithmetic circuit 42. These operations can include different types depending on the application scenario, such as arithmetic operations like addition or multiplication, logical operations, comparison operations, or table lookup operations, or any combination of the aforementioned operations. Correspondingly, the arithmetic instructions can be one or more microinstructions executed internally by the arithmetic circuit after parsing the computation instructions.

[0038] Furthermore, depending on the application scenario, the arithmetic instruction obtained after parsing the calculation instruction can be an arithmetic instruction decoded by the control circuit 41 or an arithmetic instruction not decoded by the control circuit 41. When the arithmetic instruction is an arithmetic instruction not decoded by the control circuit 41, the arithmetic circuit 42 may include a corresponding decoding circuit to perform the decoding of the arithmetic instruction, so as to obtain, for example, multiple microinstructions.

[0039] The arithmetic circuit 42 may include a main processing circuit 421 and multiple slave processing circuits 422. The main processing circuit and the slave processing circuits, as well as the multiple slave processing circuits, can communicate with each other through various connections.

[0040] The main processing circuit and the slave processing circuits can cooperate to achieve parallel computation. In this configuration, the main processing circuit can, for example, perform pre-processing on the input data, such as splitting the data, and receive intermediate results from multiple slave processing circuits and perform subsequent processing to obtain the final computation result of the computation instruction. The slave processing circuits can, for example, perform intermediate operations in parallel on the corresponding data (e.g., split data) according to the computation instruction to obtain multiple intermediate results, and transmit the multiple intermediate results back to the main processing circuit.

[0041] In different application scenarios, the connection between multiple slave processing circuits can be either a hard connection arranged by hardwires or a logical connection configured according to, for example, microinstructions, to form various topologies of slave processing circuit arrays. The embodiments disclosed herein are not limited in this respect.

[0042] By configuring the arithmetic circuit 42 into a master-slave structure (e.g., a master-multiple-slave structure, or a multi-master-multiple-slave structure, which is not limited in this disclosure), for the calculation instructions of forward operation, the data can be split according to the calculation instructions, so that the part with a large amount of calculation can be performed in parallel by multiple slave processing circuits to improve the calculation speed, save the calculation time, and thus reduce the power consumption.

[0043] To support computational functions, the main processing circuit and the slave processing circuit can include various computing circuits, such as vector operation units and matrix operation units. The vector operation unit is used to perform vector operations and can support complex operations such as vector multiplication, addition, and nonlinear transformations; the matrix operation unit is responsible for the core computations of deep learning algorithms, such as matrix multiplication and convolution.

[0044] Storage circuit 40 is used to store or move relevant data. In deep learning, storage circuitry can be used to store computational data such as neurons and weights, or to store computation results. Storage circuitry may include, for example, one or any combination of cache 402, register 404, and direct memory access (DMA) module 406. DMA module 406 can be used to interact with off-chip memory (not shown).

[0045] The foregoing describes an exemplary computing device according to embodiments of the present disclosure, in which the main processing circuit and the slave processing circuit may belong to different modules of the same processor or chip, or to different processors, and the present disclosure is not limited in this respect.

[0046] In one embodiment, the control circuit 41 may be configured to, for example, parse a Hamming weight instruction using an instruction decoding unit 412. The Hamming weight instruction operates on a binary sequence. The Hamming weight instruction instructs the counting of "1"s in the binary sequence, i.e., calculating the Hamming weight of the binary sequence. Further, in this embodiment, the arithmetic circuit 42 may be configured to schedule a corresponding number of slave processing circuits 422 to perform the Hamming weight calculation task according to the Hamming weight instruction, wherein each scheduled slave processing circuit counts the number of "1"s in a sequence segment of the assigned binary sequence.

[0047] In some embodiments, in order to make full use of the parallel computing resources of the computing device, the main processing circuit 421 in the arithmetic circuit 42 may be configured to split the binary sequence to be counted according to the Hamming weight instruction and the processing capability of the slave processing circuit.

[0048] The amount of computation to be performed can be determined using the Hamming weight instruction. The Hamming weight instruction can specify the size information of the binary sequence to be counted.

[0049] The processing capacity of a slave processing circuit represents the available computing resources, which may include, for example, the number of available slave processing circuits, the amount of data that each slave processing circuit can process at one time, and so on.

[0050] Therefore, based on the amount of computation to be completed and the amount of available computing resources, the main processing circuit can break down the binary sequence to be counted.

[0051] Figure 5 A partial structural schematic diagram of the arithmetic circuitry in a computing device according to an embodiment of this disclosure is shown to describe the execution scheme of Hamming weight instructions by illustrating the allocation, transmission, and processing of various data in the arithmetic circuitry.

[0052] As shown in the figure, the operational circuit 500 (for example) Figure 4 In addition to the main processing circuit 510 and multiple slave processing circuits 520 described above, the arithmetic circuit 42) may also include a first storage circuit 530 and a second storage circuit 540.

[0053] The first storage circuit 530 can be used to store multicast data, meaning the data in the first storage circuit will be transmitted to multiple slave processing circuits via a broadcast bus, and these slave processing circuits will receive the same data. It is understood that broadcasting and multicasting can be implemented via a broadcast bus. Multicast refers to a communication method that transmits a single data set to multiple slave processing circuits; while broadcasting is a communication method that transmits a single data set to all slave processing circuits, and is a special case of multicast. Since both multicast and broadcasting correspond to one-to-many transmission methods, they are not specifically distinguished in this document; broadcasting and multicast can be collectively referred to as multicast, and those skilled in the art will understand their meaning from the context. The second storage circuit 540 can be used to store distributed data, meaning the data in the second storage circuit will be transmitted to different slave processing circuits respectively, and each slave processing circuit will receive different data. By providing the first storage circuit and the second storage circuit respectively, it is possible to support the transmission of data to be processed using different transmission methods, thereby reducing data throughput by multiplexing multicast data among multiple slave processing circuits.

[0054] In some embodiments, the main processing circuit 510 may be further configured to: store the binary sequence to be counted in the first storage circuit 530 for transmission to the scheduled slave processing circuits via a broadcast bus during operation.

[0055] It is understandable that the binary sequence to be counted may be very long. Therefore, the Hamming weight calculation task can be achieved by splitting the binary sequence to be counted and performing multiple rounds of operations.

[0056] Because the counting of "1"s in the binary sequence in Hamming weight calculation is independent of the position of each sequence segment within the binary sequence—meaning that counting any sequence segment first does not affect the final result—the splitting of the binary sequence can be arbitrary. Furthermore, each processing circuit can process one different sequence segment at a time, thus enabling parallel processing and improving efficiency.

[0057] Therefore, in some embodiments, the main processing circuit 510 may split the binary sequence into multiple sequence segments according to the storage order and alignment requirements, and transmit a different sequence segment for each scheduled slave processing circuit in each round of operation.

[0058] In this article, "alignment requirement" refers to the data size requirement imposed during computation, for example, to make full use of hardware, such as filling the arithmetic unit. In one example, the alignment requirement is, for example, 64 bytes, so the binary sequence can be split into 64-byte segments, so that each segment can fully utilize the scheduled slave processing circuitry.

[0059] When the length of the binary sequence exceeds the processing capacity of a single round (e.g., 64 slave processing circuits, each processing a 64-byte sequence segment), multiple rounds of the above operation need to be repeated. In each round, each slave processing circuit processes a different sequence segment.

[0060] Figure 6 A partial structural schematic diagram of the main processing circuit and slave processing circuit according to an embodiment of this disclosure is shown. In this embodiment, based on the requirements of the Hamming weight calculation task, each slave processing circuit 600 (e.g.) Figure 5 The slave processing circuit 520 may include a counting circuit 610 and an accumulating circuit 620.

[0061] In each round of operation, the counting circuit 610 is used to count the number of "1"s in the sequence segment transmitted to the current slave processing circuit.

[0062] In some implementations, the counting circuit 610 may include a plurality of counters 611, each counter being used, for example, to count the number of "1"s in a sub-sequence segment of a sequence segment assigned to the processing circuit. For example, for a 64-byte binary sequence segment assigned to the processing circuit, there may be 64 counters 611, each counting the number of "1"s in one of the 8-bit sub-sequence segments. The counters 611 may be implemented using various logic circuits, and the embodiments disclosed herein are not limited in this respect.

[0063] In each round of calculation, the accumulator circuit 620 can be used to accumulate the counting results of the counting circuit to obtain a partial count value; and to accumulate the partial count value with the partial count value of the previous round.

[0064] In some implementations, the accumulator circuit 620 may include an adder circuit 621 and a register 622. The adder circuit 621 performs an addition operation on the counting results of multiple counters to obtain a partial count value for the current round. Further, the adder circuit 621 may also perform an addition operation on the partial count value of the current round and the partial count value of the previous round to update the partial count value. The adder circuit may, for example, include a multi-level Wallace tree compressor group arranged in a multi-level tree structure; or the adder circuit may include a multi-level adder group arranged in a multi-level tree structure, and the embodiments disclosed herein are not limited in this respect.

[0065] Register 622 can be used in conjunction with adder circuit 621 to store updated partial count values, that is, the register stores the latest accumulation result.

[0066] In some implementations, the accumulator circuit 620 may also include a multiplier circuit 623. The multiplier circuit 623 is used to perform multiplication operations on the counting results of multiple counters with assigned weights to obtain multiple product results, wherein the assigned weight is 1; and to send the product results to the adder circuit 621 for accumulation.

[0067] As mentioned earlier, the Hamming weight calculation task in this disclosure embodiment can be fully utilized to implement the deep learning processing hardware architecture. Deep learning tasks typically involve a large number of multiply-accumulate operations; therefore, deep learning processors also include a large number of multipliers and adders. Although the description of the Hamming weight calculation task above indicates that it does not require the participation of multipliers, meaning the multipliers in the deep learning processor can be bypassed, in some embodiments these multipliers can still be used, simply by setting the weights to 1.

[0068] These weights can be pre-stored by the main processing circuit, for example... Figure 5 In the second storage circuit 540, these weights can then be loaded from the processing circuit before the operation so that a multiplication operation can be performed subsequently with the counting result.

[0069] Furthermore, in some embodiments, the arithmetic circuit can accumulate the partial count values ​​of the scheduled slave processing circuit to obtain the Hamming weight of the entire binary sequence.

[0070] As mentioned above, the main processing circuit can receive intermediate results from multiple slave processing circuits and perform subsequent processing to obtain the final result of the arithmetic instruction. Specifically, in the above embodiment, the main processing circuit 510 can be used to accumulate partial count values ​​from each slave processing circuit to obtain the final count value for the entire binary sequence, i.e., its Hamming weight.

[0071] In other implementations, the scheduled slave processing circuits can accumulate and summarize their respective partial count values ​​before returning them to the main processing circuit. For example, these slave processing circuits can follow a multi-level tree structure, accumulating and summing the values ​​pairwise before returning the final count value to the main processing circuit. The embodiments disclosed herein do not limit the specific accumulation method.

[0072] When the Hamming weight calculation task of the embodiments of this disclosure is applied to Hamming distance calculation, in some embodiments, the binary sequence to be counted is obtained by performing a bitwise XOR operation on two input data of equal size, so that the Hamming weight of the binary sequence is equal to the Hamming distance between the two input data. The XOR operation and the Hamming weight calculation operation can be implemented separately or together, and the embodiments of this disclosure are not limited in this respect. Since the input data may be data of various dimensions, implementing the XOR operation and the Hamming weight calculation separately can facilitate more flexible hardware deployment.

[0073] The above combination Figures 5-6 The breakdown method and computational process of the Hamming weight calculation task are described. Those skilled in the art will understand that, although... Figure 5 The various processing and storage circuits are shown as separate modules, but depending on the configuration, the storage and processing circuits can also be combined into a single module. For example, the first storage circuit 530 can be combined with the main processing circuit 510, while the second storage circuit 540 can be shared by multiple slave processing circuits 520, with each slave processing circuit allocated an independent storage area to accelerate access. This disclosure embodiment is not limited in this respect.

[0074] This disclosure also provides a method for performing data processing using the aforementioned computing device. Figure 7 An exemplary flowchart of a data processing method 700 according to an embodiment of this disclosure is shown.

[0075] like Figure 7 As shown, in step 710, the Hamming weight instruction is parsed. The Hamming weight instruction operates on the binary sequence to be counted, and instructs that the number of "1"s in the binary sequence be counted to determine its Hamming weight. This step can be, for example, performed by... Figure 4 The control circuit 41 is used to execute this.

[0076] Next, in step 720, according to the Hamming weight instruction, a corresponding number of slave processing circuits are scheduled to perform the Hamming weight calculation task, wherein each scheduled slave processing circuit counts the number of "1"s in a sequence segment of the assigned binary sequence. This step can be, for example, performed by... Figure 4 The operation circuit 42 is used to execute it.

[0077] In some embodiments, the arithmetic circuit includes a main processing circuit, multiple slave processing circuits, a first storage circuit, and / or a second storage circuit. Therefore, step 720 may further include sub-step 721, whereby the main processing circuit splits the binary sequence to be counted according to the Hamming weight instruction and the processing capabilities of the slave processing circuits; and sub-step 722, whereby the binary sequence is stored in the first storage circuit for transmission to the scheduled multiple slave processing circuits via a broadcast bus during the arithmetic operation. Optionally, it may also include sub-step 723, whereby weights with a value of 1 are stored in the second storage circuit for use when using a multiplier.

[0078] Specifically, in sub-step 721, the main processing circuit can split the binary sequence into multiple sequence segments according to the storage order and alignment requirements. Then, in sub-step 722, the main processing circuit transmits a different sequence segment to each scheduled slave processing circuit via the broadcast bus in each round of operation.

[0079] Step 720 may further include sub-step 724, whereby the processing circuit counts the number of "1"s in the transmitted sequence segment and returns the statistical result. Specifically, the processing circuit may include a counting circuit and an accumulation circuit to perform the task of counting the number of "1"s, as described above.

[0080] Step 720 may further include sub-step 725, which accumulates the partial count values ​​of the scheduled slave processing circuits to obtain the Hamming weight of the entire binary sequence. This step can be performed by either the slave processing circuit or the master processing circuit. For example, the scheduled multiple slave processing circuits can be arranged in a multi-level tree structure, accumulating and summing the count values ​​pairwise before returning the final count value to the master processing circuit. In this implementation, the multiple slave processing circuits can be designed with a suitable accumulation and summarization method based on the topology of the interconnecting circuits to save computation time. Alternatively, the master processing circuit can accumulate the partial count values ​​returned by the multiple slave processing circuits. Specifically, the master processing circuit may include an accumulation circuit to accumulate the partial count values ​​received from each slave processing circuit to obtain the Hamming weight of the entire binary sequence.

[0081] Those skilled in the art will understand that the steps described in the method flowchart are combined with the preceding steps. Figure 4-6 The various circuits of the described computing device correspond to each other, so the features described above also apply to the method steps, and will not be repeated here.

[0082] This disclosure also provides a chip that may include the computing device of any of the embodiments described above in conjunction with the accompanying drawings. Furthermore, this disclosure also provides a board that may include the aforementioned chip.

[0083] Depending on the application scenario, the electronic devices or apparatus disclosed herein may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablets, smart terminals, PC devices, IoT terminals, mobile terminals, mobile phones, dashcams, navigators, sensors, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, autonomous driving terminals, vehicles, home appliances, and / or medical devices. The vehicles include airplanes, ships, and / or vehicles; the home appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; the medical devices include MRI scanners, ultrasound machines, and / or electrocardiographs. The electronic devices or apparatus disclosed herein can also be applied in fields such as the Internet, IoT, data centers, energy, transportation, public management, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, and healthcare. Furthermore, the electronic devices or apparatus disclosed herein can also be used in application scenarios related to artificial intelligence, big data, and / or cloud computing, such as cloud computing, edge computing, and terminal applications. In one or more embodiments, the high-computing-power electronic devices or apparatuses according to the present disclosure can be applied to cloud devices (e.g., cloud servers), while the low-power electronic devices or apparatuses can be applied to terminal devices and / or edge devices (e.g., smartphones or cameras). In one or more embodiments, the hardware information of the cloud devices and the hardware information of the terminal devices and / or edge devices are compatible with each other, so that suitable hardware resources can be matched from the hardware resources of the cloud devices to simulate the hardware resources of the terminal devices and / or edge devices based on the hardware information of the terminal devices and / or edge devices, so as to complete the unified management, scheduling and collaborative work of end-to-cloud or cloud-edge-end integration.

[0084] It should be noted that, for the sake of brevity, this disclosure describes some methods and their embodiments as a series of actions and combinations thereof. However, those skilled in the art will understand that the solutions disclosed herein are not limited by the order of the described actions. Therefore, based on the disclosure or teachings of this document, those skilled in the art will understand that some steps can be performed in a different order or simultaneously. Furthermore, those skilled in the art will understand that the embodiments described in this disclosure can be considered optional embodiments, that is, the actions or modules involved are not necessarily essential for the implementation of one or more solutions disclosed herein. In addition, depending on the solution, the description of some embodiments in this disclosure may have different emphases. In view of this, those skilled in the art will understand that parts not described in detail in a certain embodiment of this disclosure can also be referred to the relevant descriptions of other embodiments.

[0085] In terms of specific implementation, based on the disclosure and teachings of this document, those skilled in the art will understand that several embodiments disclosed herein can also be implemented in other ways not disclosed herein. For example, regarding the various units in the electronic device or apparatus embodiments described above, this document has divided them based on logical functions, but in actual implementation, there may be other ways of division. As another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. Regarding the connection relationships between different units or components, the connections discussed above in conjunction with the accompanying drawings can be direct or indirect couplings between units or components. In some scenarios, the aforementioned direct or indirect couplings involve communication connections utilizing interfaces, where the communication interface can support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

[0086] In this disclosure, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed across multiple network units. Furthermore, depending on actual needs, some or all of the units can be selected to achieve the purpose of the solution described in the embodiments of this disclosure. Additionally, in some scenarios, multiple units in the embodiments of this disclosure may be integrated into one unit or each unit may exist physically independently.

[0087] In other implementation scenarios, the integrated units described above can also be implemented in hardware, i.e., as specific hardware circuits, which may include digital circuits and / or analog circuits. The physical implementation of the circuit's hardware structure may include, but is not limited to, physical devices, which may include, but are not limited to, transistors or memristors. Therefore, the various devices described herein (e.g., computing devices or other processing devices) can be implemented using appropriate hardware processors, such as central processing units, GPUs, FPGAs, DSPs, and ASICs. Furthermore, the aforementioned storage units or storage devices can be any suitable storage medium (including magnetic storage media or magneto-optical storage media), such as resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high-bandwidth memory (HBM), hybrid memory cube (HMC), ROM, and RAM.

[0088] The foregoing can be better understood in accordance with the following terms:

[0089] Clause 1. A computing device, comprising a control circuit and an arithmetic circuit, wherein:

[0090] The control circuit is used to parse the Hamming weight instruction, which operates on a binary sequence. The Hamming weight instruction instructs the counting of the number of "1"s in the binary sequence to determine its Hamming weight; and

[0091] The arithmetic circuit includes multiple slave processing circuits, and the arithmetic circuit is used to schedule a corresponding number of slave processing circuits to perform Hamming weight calculation tasks according to the Hamming weight instruction, wherein each scheduled slave processing circuit counts the number of "1"s in the sequence segment of the assigned binary sequence.

[0092] Clause 2. The computing device according to Clause 1, wherein the arithmetic circuitry further comprises a main processing circuitry and a first storage circuitry, the main processing circuitry being used for:

[0093] Based on the Hamming weight instruction and the processing capability of the processing circuitry, the binary sequence is split; and

[0094] The binary sequence is stored in the first storage circuit for transmission to multiple scheduled slave processing circuits via a broadcast bus during operation.

[0095] Clause 3. The computing device according to Clause 2, wherein the main processing circuitry is further configured to:

[0096] According to the storage order and alignment requirements, the binary sequence is split into multiple sequence segments, and in each round of operation, a different sequence segment is transmitted to each scheduled slave processing circuit.

[0097] Clause 4. The computing device according to Clause 3, wherein each of the slave processing circuits includes a counting circuit and an accumulating circuit, and in each round of operation:

[0098] The counting circuit is used to count the number of "1"s in a sequence segment transmitted to the current slave processing circuit; and

[0099] The accumulation circuit is used to accumulate the counting results of the counting circuit to obtain a partial count value, and to accumulate the partial count value with the partial count value of the previous round.

[0100] Clause 5. The computing device according to Clause 5, wherein the counting circuit includes a plurality of counters, each counter being used to count the number of "1"s in a sub-sequence segment of the sequence segment.

[0101] Clause 6. The computing device according to Clause 7, wherein the accumulation circuit includes an adder circuit and a register, wherein:

[0102] The addition circuit is used to perform an addition operation on the counting results of the plurality of counters to obtain a partial count value for the current round, and to perform an addition operation on the partial count value for the current round and the partial count value for the previous round to update the partial count value; and

[0103] The register is used to store the updated partial count value.

[0104] Clause 7. The computing device according to Clause 6, wherein the accumulation circuit further comprises a multiplication circuit, the multiplication circuit being used for:

[0105] The counting results of the plurality of counters are multiplied by the assigned weights to obtain a plurality of product results, wherein the assigned weight is 1; and

[0106] The product result is fed to the adder circuit for accumulation.

[0107] Clause 8. The computing device according to any one of Clauses 1-7, wherein the arithmetic circuitry is further configured to:

[0108] The partial count values ​​of the scheduled slave processing circuits are accumulated to obtain the Hamming weight of the binary sequence.

[0109] Clause 9. A computing device according to any one of Clauses 1-8, wherein the binary sequence is obtained by performing a bitwise XOR operation on two input data of equal size, and the Hamming weight of the binary sequence is equal to the Hamming distance between the two input data.

[0110] Clause 10. A chip comprising a computing device according to any one of Clauses 1-9.

[0111] Clause 11. A board including the chip described in Clause 10.

[0112] Clause 12. A data processing method implemented by a computing device, the computing device including a control circuit and an arithmetic circuit, the arithmetic circuit including a plurality of slave processing circuits, the method comprising:

[0113] The control circuit parses the Hamming weight command, which operates on a binary sequence. The Hamming weight command instructs the counting of the number of "1"s in the binary sequence to determine its Hamming weight; and

[0114] The arithmetic circuit schedules a corresponding number of slave processing circuits to perform Hamming weight calculation tasks according to the Hamming weight instruction, wherein each scheduled slave processing circuit counts the number of "1"s in the sequence segment of the assigned binary sequence.

[0115] Clause 13. The method according to Clause 12, wherein the arithmetic circuit further includes a main processing circuit and a first storage circuit, the method further comprising:

[0116] The main processing circuit splits the binary sequence according to the Hamming weight command and the processing capability of the slave processing circuit; and

[0117] The binary sequence is stored in the first storage circuit for transmission to multiple scheduled slave processing circuits via a broadcast bus during operation.

[0118] Clause 14. The method according to Clause 13, wherein the method further comprises:

[0119] The main processing circuit splits the binary sequence into multiple sequence segments according to the storage order and alignment requirements, and transmits a different sequence segment to each scheduled slave processing circuit in each round of operation.

[0120] Clause 15. The method according to Clause 14, wherein each of the slave processing circuits includes a counting circuit and an accumulating circuit, and the method includes: in each round of operation,

[0121] The counting circuit counts the number of "1"s in the sequence segment transmitted to the current slave processing circuit; and

[0122] The accumulator circuit accumulates the counting results of the counting circuit to obtain a partial count value, and then accumulates the partial count value with the partial count value of the previous round.

[0123] Clause 16. The method according to Clause 15, wherein the counting circuit includes a plurality of counters, each counter counting the number of "1"s in a sub-sequence segment of the sequence segment.

[0124] Clause 17. The method according to Clause 16, wherein the accumulator circuit includes an adder circuit and a register, and the method includes:

[0125] The addition circuit performs an addition operation on the counting results of the plurality of counters to obtain a partial count value for the current round, and performs an addition operation on the partial count value for the current round and the partial count value for the previous round to update the partial count value; and

[0126] The register stores the updated partial count value.

[0127] Clause 18. The method according to Clause 17, wherein the accumulation circuit further includes a multiplication circuit, and the method comprises:

[0128] The multiplication circuit performs multiplication operations on the counting results of the plurality of counters with the assigned weights to obtain a plurality of product results, wherein the assigned weight is 1; and

[0129] The product result is fed to the adder circuit for accumulation.

[0130] Clause 19. The method according to any one of Clauses 12-18, wherein the method further comprises:

[0131] The arithmetic circuit accumulates a portion of the count values ​​from the scheduled slave processing circuits to obtain the Hamming weight of the binary sequence.

[0132] Clause 20. The method according to any one of Clauses 12-19, wherein the binary sequence is obtained by performing a bitwise XOR operation on two input data of equal size, and the Hamming weight of the binary sequence is equal to the Hamming distance between the two input data.

[0133] The embodiments of this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

Claims

1. A computing device, comprising a control circuit and an arithmetic circuit, wherein: The control circuit is used to parse the Hamming weight instruction, the operation object of the Hamming weight instruction includes a binary sequence, and the Hamming weight instruction instructs to count the number of "1"s in the binary sequence to obtain its Hamming weight; as well as The arithmetic circuit includes multiple slave processing circuits, and the arithmetic circuit is used to schedule a corresponding number of slave processing circuits to perform Hamming weight calculation tasks according to the Hamming weight instruction, wherein each scheduled slave processing circuit counts the number of "1"s in the sequence segment of the allocated binary sequence. The arithmetic circuit further includes a main processing circuit and a first storage circuit, wherein the main processing circuit is used for: The binary sequence is split according to the Hamming weight instruction and the processing capability of the processing circuit; as well as The binary sequence is stored in the first storage circuit for transmission to multiple scheduled slave processing circuits via a broadcast bus during operation; The main processing circuit is also used for: According to the storage order and alignment requirements, the binary sequence is split into multiple sequence segments, and in each round of operation, a different sequence segment is transmitted to each scheduled slave processing circuit.

2. The computing device of claim 1, wherein each of the slave processing circuits includes a counting circuit and an accumulation circuit, and in each round of operation: The counting circuit is used to count the number of "1"s in a sequence segment transmitted to the current slave processing circuit; and The accumulation circuit is used to accumulate the counting results of the counting circuit to obtain a partial count value, and to accumulate the partial count value with the partial count value of the previous round.

3. The computing device according to claim 2, wherein the counting circuit includes a plurality of counters, each counter being used to count the number of "1"s in a sub-sequence segment of the sequence segment.

4. The computing device according to claim 3, wherein the accumulation circuit comprises an adder circuit and a register, wherein: The addition circuit is used to perform an addition operation on the counting results of the plurality of counters to obtain a partial count value for the current round, and to perform an addition operation on the partial count value for the current round and the partial count value for the previous round to update the partial count value; and The register is used to store the updated partial count value.

5. The computing device according to claim 4, wherein the accumulation circuit further comprises a multiplication circuit, the multiplication circuit being used for: The counting results of the plurality of counters are multiplied by the assigned weights to obtain a plurality of product results, wherein the assigned weight is 1; and The product result is fed to the adder circuit for accumulation.

6. The computing device according to any one of claims 1-5, wherein the arithmetic circuitry is further configured to: The partial count values ​​of the scheduled slave processing circuits are accumulated to obtain the Hamming weight of the binary sequence.

7. The computing device according to any one of claims 1-5, wherein the binary sequence is obtained by performing a bitwise XOR operation on two input data of equal size, and the Hamming weight of the binary sequence is equal to the Hamming distance between the two input data.

8. A chip comprising a computing device according to any one of claims 1-7.

9. A circuit board comprising the chip according to claim 8.

10. A data processing method implemented by a computing device, the computing device including a control circuit and an arithmetic circuit, the arithmetic circuit including a plurality of slave processing circuits, the method comprising: The control circuit parses the Hamming weight instruction, the operation object of which includes a binary sequence, and the Hamming weight instruction instructs to count the number of "1"s in the binary sequence to obtain its Hamming weight. as well as The arithmetic circuit schedules a corresponding number of slave processing circuits to perform Hamming weight calculation tasks according to the Hamming weight instruction, wherein each scheduled slave processing circuit counts the number of "1"s in the sequence segment of the assigned binary sequence. The arithmetic circuit further includes a main processing circuit and a first storage circuit, and the method further includes: The main processing circuit splits the binary sequence according to the Hamming weight command and the processing capability of the slave processing circuit; and The binary sequence is stored in the first storage circuit for transmission to multiple scheduled slave processing circuits via a broadcast bus during operation; The method further includes: The main processing circuit splits the binary sequence into multiple sequence segments according to the storage order and alignment requirements, and transmits a different sequence segment to each scheduled slave processing circuit in each round of operation.

11. The method of claim 10, wherein each of the slave processing circuits includes a counting circuit and an accumulation circuit, and the method comprises: In each round of calculation, The counting circuit counts the number of "1"s in the sequence segment transmitted to the current slave processing circuit; as well as The accumulator circuit accumulates the counting results of the counting circuit to obtain a partial count value, and then accumulates the partial count value with the partial count value of the previous round.

12. The method of claim 11, wherein the counting circuit comprises a plurality of counters, each counter counting the number of "1"s in a sub-sequence segment of the sequence segment.

13. The method of claim 12, wherein the accumulator circuit comprises an adder circuit and a register, and the method comprises: The addition circuit performs an addition operation on the counting results of the plurality of counters to obtain a partial count value for the current round, and performs an addition operation on the partial count value for the current round and the partial count value for the previous round to update the partial count value; and The register stores the updated partial count value.

14. The method of claim 13, wherein the accumulation circuit further comprises a multiplication circuit, and the method comprises: The multiplication circuit performs multiplication operations on the counting results of the multiple counters with the assigned weights to obtain multiple product results, wherein the assigned weight is 1; as well as The product result is fed to the adder circuit for accumulation.

15. The method according to any one of claims 10-14, wherein the method further comprises: The arithmetic circuit accumulates a portion of the count values ​​from the scheduled slave processing circuits to obtain the Hamming weight of the binary sequence.

16. The method according to any one of claims 10-14, wherein the binary sequence is obtained by performing a bitwise XOR operation on two input data of equal size, and the Hamming weight of the binary sequence is equal to the Hamming distance between the two input data.

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