Computing device, data processing method, and related products

Abstract

The present disclosure discloses a computing device, a data processing method and related products. The computing device can be included in a combined processing device, which can further include an interface device and other processing devices. The computing device interacts with the other processing devices to jointly complete a user-specified computing operation. The combined processing device can further include a storage device connected to the computing device and the other processing devices respectively, for storing data of the computing device and the other processing devices. The scheme of the present disclosure provides a hardware architecture for executing integral instructions, which can simplify processing and improve the processing efficiency of the machine.

Description

Technical Field

[0001] This disclosure generally relates to the field of processors. More specifically, this disclosure relates to computing devices, data processing methods, chips, and circuit boards. Background Technology

[0002] Integration is a very common data operation in scientific computing and data processing. It has been widely applied in various engineering fields. For example, in civil engineering, estimations of the volume and area of ​​building foundations and wing walls require integration. Similarly, in automotive software development, timers or counters are frequently used, such as to calculate the engine's runtime during a driving cycle or the number of times the car has been charged; this essentially applies the concept of integration.

[0003] On the other hand, with the rapid development of deep learning, hardware architectures such as chips and processors suitable for deep learning processing have also made leaps and bounds. If integration operations can be ported to hardware architectures suitable for deep learning processing, it is possible to accelerate integration operations and improve the processing efficiency of related processes in various engineering fields. Existing hardware and / or instruction sets cannot effectively support integration-related operations. Summary of the Invention

[0004] In order to at least partially solve one or more of the technical problems mentioned in the background art, the present disclosure provides a computing device, a data processing method, a chip, and a board.

[0005] In a first aspect, this disclosure discloses a computing device including a control circuit and an arithmetic circuit, wherein: the control circuit is configured to parse an integration instruction, the object of which the integration instruction includes data to be integrated, the integration instruction instructing an integration operation to be performed on the data to be integrated; and the arithmetic circuit includes a plurality of slave processing circuits, and the arithmetic circuit is configured to schedule a corresponding number of slave processing circuits to perform an integration operation task according to the integration instruction, wherein each scheduled slave processing circuit performs the integration operation on a corresponding portion of the data to be integrated according to an assigned accumulation index.

[0006] In a second aspect, this disclosure provides a chip that includes a computing device according to any of the embodiments of the first aspect.

[0007] In a third aspect, this disclosure provides a board including the chip of any of the embodiments of the second aspect above.

[0008] In a fourth aspect, this disclosure provides a data processing method implemented by a computing device, the computing device including a control circuit and an arithmetic circuit, the arithmetic circuit including a plurality of slave processing circuits, the method comprising: the control circuit parsing an integration instruction, the integration instruction operating on data to be integrated, the integration instruction instructing an integration operation on the data to be integrated; and the arithmetic circuit scheduling a corresponding number of slave processing circuits to perform integration operation tasks according to the integration instruction, wherein each scheduled slave processing circuit performs the integration operation on a corresponding portion of the data to be integrated according to an assigned accumulation index.

[0009] Using the computing device, data processing method, integrated circuit chip, and board provided above, this disclosure provides a scheme for executing integration instructions on a hardware architecture including multiple slave processing circuits. The integration task can be distributed across multiple slave processing circuits, thereby fully utilizing the computational advantages of the deep learning processing hardware architecture and improving machine processing efficiency through parallel computation. Attached Figure Description

[0010] The above and other objects, features, and advantages of exemplary embodiments of this disclosure will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0011] Figure 1 This diagram shows the structure of the board card according to an embodiment of this disclosure;

[0012] Figure 2 This diagram illustrates the structure of the combined processing apparatus according to an embodiment of the present disclosure.

[0013] Figure 3 A schematic diagram illustrating the internal structure of a processor core in a single-core or multi-core computing device according to embodiments of the present disclosure;

[0014] Figure 4 This diagram illustrates an exemplary structural schematic of a computing device according to an embodiment of the present disclosure.

[0015] Figure 5 A partial structural schematic diagram of the arithmetic circuit in a computing device according to an embodiment of this disclosure is shown;

[0016] Figure 6 A schematic diagram is shown of the accumulation index assigned to multiple slave processing circuits;

[0017] Figure 7 A partial structural schematic diagram of the main processing circuit and the slave processing circuit according to embodiments of this disclosure is shown; and

[0018] Figure 8 An exemplary flowchart of a data processing method according to an embodiment of this disclosure is shown. Detailed Implementation

[0019] The technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0020] It should be understood that the terms "first," "second," "third," and "fourth," etc., that may appear in the claims, specification, and drawings of this disclosure are used to distinguish different objects, rather than to describe a specific order. The terms "comprising" and "including" as used in the specification and claims of this disclosure indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

[0021] It should also be understood that the terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0022] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection."

[0023] The specific embodiments disclosed herein will now be described in detail with reference to the accompanying drawings.

[0024] Figure 1 A schematic diagram of the structure of a board 10 according to an embodiment of this disclosure is shown. Figure 1As shown, board 10 includes chip 101, which is a system-on-chip (SoC) integrating one or more combined processing units. These combined processing units are artificial intelligence computing units used to support various deep learning and machine learning algorithms, meeting the intelligent processing needs of complex scenarios in fields such as computer vision, speech, natural language processing, and data mining. In particular, deep learning technology is widely used in cloud intelligence. A significant characteristic of cloud intelligence applications is the large volume of input data, placing high demands on the platform's storage and computing capabilities. Board 10 in this embodiment is suitable for cloud intelligence applications, possessing massive off-chip storage, on-chip storage, and powerful computing capabilities.

[0025] Chip 101 is connected to external device 103 via external interface device 102. External device 103 may be, for example, a server, computer, camera, monitor, mouse, keyboard, network card, or Wi-Fi interface. Data to be processed can be transmitted from external device 103 to chip 101 via external interface device 102. The calculation results from chip 101 can be transmitted back to external device 103 via external interface device 102. Depending on the application scenario, external interface device 102 may have different interface forms, such as a PCIe interface.

[0026] The board 10 also includes a storage device 104 for storing data, which includes one or more memory cells 105. The storage device 104 is connected to and transmits data with the controller 106 and the chip 101 via a bus. The controller 106 in the board 10 is configured to regulate the state of the chip 101. Therefore, in one application scenario, the controller 106 may include a microcontroller (MCU).

[0027] Figure 2 This is a structural diagram illustrating the combined processing device in chip 101 of this embodiment. (As shown) Figure 2 As shown, the combined processing device 20 includes a computing device 201, an interface device 202, a processing device 203, and a storage device 204.

[0028] The computing device 201 is configured to perform user-specified operations. It is mainly implemented as a single-core intelligent processor or a multi-core intelligent processor to perform deep learning or machine learning calculations. It can interact with the processing device 203 through the interface device 202 to jointly complete the user-specified operations.

[0029] Interface device 202 is used to transmit data and control commands between computing device 201 and processing device 203. For example, computing device 201 can obtain input data from processing device 203 via interface device 202 and write it to on-chip storage device of computing device 201. Further, computing device 201 can obtain control commands from processing device 203 via interface device 202 and write them to on-chip control cache of computing device 201. Alternatively or optionally, interface device 202 can also read data from storage device of computing device 201 and transmit it to processing device 203.

[0030] Processing device 203, as a general-purpose processing device, performs basic control including but not limited to data transfer, and starting and / or stopping computing device 201. Depending on the implementation, processing device 203 may be one or more types of processors, including but not limited to digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As mentioned above, computing device 201 disclosed herein can be considered as having a single-core structure or a homogeneous multi-core structure. However, when computing device 201 and processing device 203 are considered together, they are considered to form a heterogeneous multi-core structure.

[0031] Storage device 204 is used to store data to be processed. It may be DRAM or DDR memory, typically 16G or larger in size, and is used to store data of computing device 201 and / or processing device 203.

[0032] Figure 3 The diagram shows the internal structure of the processing core when the computing device 201 is a single-core or multi-core device. The computing device 301 is used to process input data such as computer vision, speech, natural language, and data mining. The computing device 301 includes three main modules: a control module 31, an arithmetic module 32, and a storage module 33.

[0033] The control module 31 coordinates and controls the operation of the computation module 32 and the storage module 33 to complete the deep learning task. It includes an instruction fetch unit (IFU) 311 and an instruction decode unit (IDU) 312. The instruction fetch unit 311 fetches instructions from the processing device 203, and the instruction decode unit 312 decodes the fetched instructions and sends the decoding result as control information to the computation module 32 and the storage module 33.

[0034] The computation module 32 includes a vector operation unit 321 and a matrix operation unit 322. The vector operation unit 321 is used to perform vector operations and can support complex operations such as vector multiplication, addition, and nonlinear transformations; the matrix operation unit 322 is responsible for the core computations of deep learning algorithms, namely matrix multiplication and convolution.

[0035] The storage module 33 is used to store or move relevant data, including a neuron RAM (NRAM) 331, a weight RAM (WRAM) 332, and a direct memory access (DMA) module 333. The NRAM 331 stores the input neurons, output neurons, and intermediate results after computation; the WRAM 332 stores the convolution kernels of the deep learning network, i.e., the weights; the DMA 333 is connected to the DRAM 204 via bus 34 and is responsible for data transfer between the computing device 301 and the DRAM 204.

[0036] Based on the aforementioned hardware environment, in one aspect, this disclosure provides a computing device that executes an integration task according to integration instructions. An integration task can generally be understood as the accumulation of data to be integrated. It is understood that, depending on specific application requirements, the integration task may need to provide integration results at different stages; for example, for a counter in automotive software mentioned in the background art, it may be necessary to count counts over different time periods. Furthermore, the amount of data to be integrated may be very large. Therefore, by fully utilizing the aforementioned hardware environment and exploring the possibility of parallel data processing, computation can be accelerated and efficiency improved.

[0037] Figure 4 A schematic structural block diagram of a computing device 400 according to an embodiment of this disclosure is shown. It can be understood that this structure can be considered as... Figure 3 The refinement of the internal structure of a single processing core can also be viewed as the refinement of multiple cores. Figure 3 The diagram shows the functional partitioning based on the processing core. Figure 4As shown, the computing device 400 of this embodiment can be used to perform integration tasks. It may include a storage circuit 40, a control circuit 41 and an arithmetic circuit 42, which are interconnected to transmit various data and instructions.

[0038] The function of control circuit 41 and Figure 3 Similar to the control module 31, it may also include, for example, an instruction fetch unit (IFU) 411 and an instruction decode unit (IDU) 412. In various arithmetic operations, such as computation, the control circuit 41 can be configured to fetch computation instructions, parse them to obtain arithmetic instructions, and then send the arithmetic instructions to the arithmetic circuit 42 and the storage circuit 40. The computation instructions can be a form of hardware instruction and include one or more opcodes, each opcode representing one or more specific operations to be executed by the arithmetic circuit 42. These operations can include different types depending on the application scenario, such as arithmetic operations like addition or multiplication, logical operations, comparison operations, or table lookup operations, or any combination of the aforementioned operations. Correspondingly, the arithmetic instructions can be one or more microinstructions executed internally by the arithmetic circuit after parsing the computation instructions.

[0039] Furthermore, depending on the application scenario, the arithmetic instruction obtained after parsing the calculation instruction can be an arithmetic instruction decoded by the control circuit 41 or an arithmetic instruction not decoded by the control circuit 41. When the arithmetic instruction is an arithmetic instruction not decoded by the control circuit 41, the arithmetic circuit 42 may include a corresponding decoding circuit to perform the decoding of the arithmetic instruction, so as to obtain, for example, multiple microinstructions.

[0040] The arithmetic circuit 42 may include a main processing circuit 421 and multiple slave processing circuits 422. The main processing circuit and the slave processing circuits, as well as the multiple slave processing circuits, can communicate with each other through various connections.

[0041] The main processing circuit and the slave processing circuits can cooperate to achieve parallel computation. In this configuration, the main processing circuit can, for example, perform pre-processing on the input data, such as splitting the data, and receive intermediate results from multiple slave processing circuits and perform subsequent processing to obtain the final computation result of the computation instruction. The slave processing circuits can, for example, perform intermediate operations in parallel on the corresponding data (e.g., split data) according to the computation instruction to obtain multiple intermediate results, and transmit the multiple intermediate results back to the main processing circuit.

[0042] In different application scenarios, the connection between multiple slave processing circuits can be either a hard connection arranged by hardwires or a logical connection configured according to, for example, microinstructions, to form various topologies of slave processing circuit arrays. The embodiments disclosed herein are not limited in this respect.

[0043] By configuring the arithmetic circuit 42 into a master-slave structure (e.g., a master-multiple-slave structure, or a multi-master-multiple-slave structure, which is not limited in this disclosure), for the calculation instructions of forward operation, the data can be split according to the calculation instructions, so that the part with a large amount of calculation can be performed in parallel by multiple slave processing circuits to improve the calculation speed, save the calculation time, and thus reduce the power consumption.

[0044] To support computational functions, the main processing circuit and the slave processing circuit can include various computing circuits, such as vector operation units and matrix operation units. The vector operation unit is used to perform vector operations and can support complex operations such as vector multiplication, addition, and nonlinear transformations; the matrix operation unit is responsible for the core computations of deep learning algorithms, such as matrix multiplication and convolution.

[0045] Storage circuit 40 is used to store or move relevant data. In deep learning, storage circuitry can be used to store computational data such as neurons and weights, or to store computation results. Storage circuitry may include, for example, one or any combination of cache 402, register 404, and direct memory access (DMA) module 406. DMA module 406 can be used to interact with off-chip memory (not shown).

[0046] The foregoing describes an exemplary computing device according to embodiments of the present disclosure, in which the main processing circuit and the slave processing circuit may belong to different modules of the same processor or chip, or to different processors, and the present disclosure is not limited in this respect.

[0047] In one embodiment, the control circuit 41 may be configured to parse an integration instruction, for example, using an instruction decoding unit 412. The integration instruction operates on data to be integrated. The integration instruction instructs that integration be performed on the data to be integrated. Further, in this embodiment, the arithmetic circuit 42 may be configured to schedule a corresponding number of slave processing circuits 422 to perform integration tasks according to the integration instruction, wherein each scheduled slave processing circuit performs integration on a corresponding portion of the data to be integrated according to an assigned accumulation index. Here, the accumulation index is used to indicate the portion of the data to be integrated that participates in integration, which will be described in detail later.

[0048] In some embodiments, in order to make full use of the parallel computing resources of the computing device, the main processing circuit 421 in the arithmetic circuit 42 may be configured to split the data to be integrated according to the integration instructions and the processing capabilities of the slave processing circuits, in accordance with the splitting rules.

[0049] The amount of computation to be performed can be determined based on the integration instructions. The integration instructions can specify information such as the size of the data to be integrated and the granularity of integration. For example, the data to be integrated can be one-dimensional, two-dimensional, or higher-dimensional data; the granularity of integration can be in units of the number of data points, for example, the default is to integrate with a granularity of 1 data point, that is, the step size of each integration is one data point.

[0050] The processing capacity of a slave processing circuit represents the available computing resources, which may include, for example, the number of available slave processing circuits, the amount of data that each slave processing circuit can process at one time, and so on.

[0051] Therefore, based on the amount of computation to be completed and the amount of available computing resources, the main processing circuit can divide the data to be integrated according to the splitting rules.

[0052] Figure 5 A partial structural schematic diagram of the computing circuitry in a computing device according to an embodiment of this disclosure is shown in order to describe various splitting schemes by illustrating the allocation, transmission, and processing of various data in the computing circuitry.

[0053] As shown in the figure, the operational circuit 500 (for example) Figure 4 In addition to the main processing circuit 510 and multiple slave processing circuits 520 described above, the arithmetic circuit 42) may also include a first storage circuit 530 and a second storage circuit 540.

[0054] The first storage circuit 530 can be used to store multicast data, meaning the data in the first storage circuit will be transmitted to multiple slave processing circuits via a broadcast bus, and these slave processing circuits will receive the same data. It is understood that broadcasting and multicasting can be implemented via a broadcast bus. Multicast refers to a communication method that transmits a single data set to multiple slave processing circuits; while broadcasting is a communication method that transmits a single data set to all slave processing circuits, and is a special case of multicast. Since both multicast and broadcasting correspond to one-to-many transmission methods, they are not specifically distinguished in this document; broadcasting and multicast can be collectively referred to as multicast, and those skilled in the art will understand their meaning from the context. The second storage circuit 540 can be used to store distributed data, meaning the data in the second storage circuit will be transmitted to different slave processing circuits respectively, and each slave processing circuit will receive different data. By providing the first storage circuit and the second storage circuit respectively, it is possible to support the transmission of data to be processed using different transmission methods, thereby reducing data throughput by multiplexing multicast data among multiple slave processing circuits.

[0055] In some embodiments, the main processing circuit 510 may further be configured to: determine the data to be integrated as multicast data, and determine the accumulation index allocated to each scheduled slave processing circuit as distribution data. Further, the main processing circuit 510 may store the data to be integrated in a first storage circuit 530 for transmission to the multiple scheduled slave processing circuits via a broadcast bus during computation; and store the accumulation index allocated to each scheduled slave processing circuit in a second storage circuit 540 for the scheduled slave processing circuits to load the corresponding portion of the accumulation index for computation.

[0056] It is understandable that the data to be integrated is usually large in volume, so the integration task can be accomplished by splitting the data into multiple rounds of computation. Furthermore, considering that partial integration values ​​from different integration stages may be needed, different slave processing circuits can be used in each round of computation to calculate partial integration values ​​from different integration stages. That is, each slave processing circuit accumulates the corresponding portion of the data to be integrated according to its assigned accumulation index.

[0057] In some embodiments, the splitting rule may include splitting the data to be integrated in its lowest dimension according to alignment requirements. Although multidimensional data has multiple dimensions, because the layout of the storage circuits (e.g., a first storage circuit and a second storage circuit) is always one-dimensional, there is a correspondence between the multidimensional data and the storage order on the storage circuits. Multidimensional data is typically allocated in contiguous storage space, meaning it can be unfolded one-dimensionally and stored sequentially on the storage circuits. It is usually unfolded in order from low to high dimensions, i.e., a low-dimensional-first approach, thus ensuring that the low-dimensional data is contiguous on the storage circuits.

[0058] In this article, "alignment requirement" refers to the data size requirement imposed during computation, for example, to make full use of the hardware, such as filling the arithmetic unit. In one example, the alignment requirement is, for example, 64 bytes, so the data to be integrated can be split into 64-byte integration data blocks, so that each integration data block can fully utilize the scheduled slave processing circuitry.

[0059] Therefore, in some embodiments, the main processing circuit can split the data to be integrated into L parts according to the storage dimension from low to high. N The data is divided into L integral data blocks, allowing it to be directly split and read according to its storage order without needing to rearrange the storage order. N Each integral data block can be accessed via L N The above integration task is accomplished through round-robin operations, that is, in each round of operations, an integration data block is transmitted to the multiple scheduled slave processing circuits via a broadcast bus.

[0060] The master processing circuit can also assign an accumulation index to each of the scheduled slave processing circuits to indicate the data that each slave processing circuit needs to accumulate.

[0061] In some implementations, the cumulative index can be represented as a bit sequence, where "1" indicates that the corresponding bit of integration data participates in the integration, and "0" indicates that the corresponding bit of integration data does not participate in the integration.

[0062] Furthermore, in some implementations, the number of bits assigned to the accumulated index of the processing circuit with a value of "1" increases in a stepwise manner according to the order of the processing circuits.

[0063] Figure 6 A schematic diagram is shown of the accumulation index assigned to multiple slave processing circuits.

[0064] As shown in the figure, assume there are 64 slave processing circuits scheduled, and each slave processing circuit is assigned an accumulation index to calculate the corresponding partial integration value. Assume the data type of the data to be integrated is INT8, meaning 8 bits represent an integer. Each slave processing circuit can process 64 bytes of data at a time, that is, it can process 64 data points from the data to be integrated at a time.

[0065] Therefore, the data to be integrated can be divided into 64-byte blocks, with each block containing 64 data items. These blocks are then broadcast sequentially to the 64 scheduled slave processing circuits, allowing each circuit to calculate a partial integration value for that block. The accumulated data portion is indicated by an assigned accumulation index.

[0066] The diagram illustrates 64 accumulation indices assigned to 64 slave processing circuits. Each accumulation index can be a 64-bit sequence, with each bit indicating whether the corresponding integration data is included in the integration. For example, the accumulation index of the first slave processing circuit is 100000…0, indicating that only the first data is accumulated; the accumulation index of the second slave processing circuit is 1100000…0, indicating that the first and second data are accumulated; the accumulation index of the third slave processing circuit is 11100000…0, indicating that the first, second, and third data are accumulated; and so on, until the accumulation index of the 64th slave processing circuit is 111111…1, indicating that all 64 data are accumulated. As can be seen from the diagram, the number of bits with a value of "1" in the accumulation indices assigned to the slave processing circuits increases in a stepwise manner according to the order of the slave processing circuits. Therefore, the 64 slave processing circuits can obtain 64 incremental partial integration values ​​in one round of computation.

[0067] When the amount of data to be integrated exceeds the processing limit (e.g., 64 bytes), the above operation needs to be repeated multiple times. In each round of operation, the accumulation index of each slave processing circuit can remain unchanged.

[0068] Figure 7 A partial structural schematic diagram of the main processing circuit and the slave processing circuit according to an embodiment of this disclosure is shown. In this embodiment, based on the requirements of the integration operation task, each slave processing circuit 700 (e.g.) Figure 5 The processing circuit 520 in the middle may include a multiplication circuit 710 and a first accumulation circuit 720.

[0069] In each round of operation, the multiplication circuit 710 is used to perform positional multiplication of the accumulated index assigned to the current slave processing circuit with the integral data block of the current round and output the product result.

[0070] In some implementations, the multiplication circuit 710 may include multiple multipliers 711, each multiplier being used to multiply a bit in the accumulated index and a data in the integral data block allocated to the current slave processing circuit. Figure 6 As can be seen from the accumulation index, when the bit in the accumulation index indicates "1", the corresponding data in the integration data block needs to be accumulated; when the bit in the accumulation index indicates "0", the corresponding data in the integration data block does not need to be accumulated. Therefore, the data that needs to be accumulated can be filtered by bit-wise multiplication. It can be understood that for multiplier 711 with a bit in the accumulation index indicating "0", it can directly output 0 and turn off the corresponding multiplier to save power.

[0071] In each round of calculation, the first accumulator circuit 720 can be used to accumulate the product results of the multiplication circuit to obtain a partial integral value; and output the partial integral value to the main processing circuit.

[0072] In some implementations, the first accumulation circuit 720 may include an addition circuit. The addition circuit performs an addition operation on the product of multiple multipliers to obtain a partial integral value for the current round. The addition circuit may, for example, include a multi-level Wallace tree compressor group arranged in a multi-level tree structure; or the addition circuit may include a multi-level adder group arranged in a multi-level tree structure, and the embodiments disclosed herein are not limited in this respect.

[0073] When the data to be integrated is split into multiple integration data blocks, the partial integration value corresponding to the maximum accumulation index of the previous round needs to be accumulated in each round of calculation.

[0074] In this disclosed embodiment, based on the above requirements, the main processing circuit 750 (e.g.) Figure 5 The main processing circuit 510 may include a second accumulator circuit 760 and a register 770.

[0075] The second accumulation circuit 760 is used to accumulate the partial integral values ​​received from each slave processing circuit 700 in the current round with the partial integral values ​​corresponding to the maximum accumulation index in the previous round, thereby updating the individual partial integral values. Since the accumulation index of each slave processing circuit in each round of operation is fixed, that is, only a specified number of data in the current round's integral data block are accumulated in each round of operation, its essence is a local partial integral value in the data to be integrated. By accumulating the partial integral values ​​of the current round with the partial integral values ​​corresponding to the maximum accumulation index of the previous round, after multiple rounds of iteration, the final integral value on the entire data to be integrated can be obtained.

[0076] Register 770 can be used in conjunction with the second accumulator circuit 760 to store the partial integral value corresponding to the maximum accumulation index in the updated partial integral values. Register 770 can store the maximum accumulation index corresponding to each round of operation (e.g., Figure 6 The 64th partial integral value from the slave processing circuit is used to add to the integral result of the next round of calculation. It can be understood that register 770 can also store partial integral values ​​received from each slave processing circuit and update these partial integral values ​​as the second accumulator circuit 760 accumulates. Thus, multiple integral values ​​from different nodes can be provided when needed, such as the final 64 integral values.

[0077] The above combination Figures 5-7 The method for breaking down the integration task and the computation process are described. Those skilled in the art will understand that, although... Figure 5 The various processing and storage circuits are shown as separate modules, but depending on the configuration, the storage and processing circuits can also be combined into a single module. For example, the first storage circuit 530 can be combined with the main processing circuit 510, while the second storage circuit 540 can be shared by multiple slave processing circuits 520, with each slave processing circuit allocated an independent storage area to accelerate access. This disclosure embodiment is not limited in this respect.

[0078] This disclosure also provides a method for performing data processing using the aforementioned computing device. Figure 8 An exemplary flowchart of a data processing method 800 according to an embodiment of this disclosure is shown.

[0079] like Figure 8 As shown, in step 810, an integration instruction is parsed. The object of this integration instruction includes the data to be integrated, and the integration instruction instructs that integration be performed on the data to be integrated. This step can be, for example, performed by... Figure 4 The control circuit 41 is used to execute this.

[0080] Next, in step 820, according to the integration instruction, a corresponding number of slave processing circuits are scheduled to perform the integration operation task, wherein each scheduled slave processing circuit performs the integration operation on the corresponding part of the data to be integrated according to the assigned accumulation index. This step can be, for example, performed by... Figure 4 The operation circuit 42 is used to execute it.

[0081] In some embodiments, the arithmetic circuit includes a main processing circuit, multiple slave processing circuits, a first storage circuit, and a second storage circuit. Therefore, step 820 may further include sub-step 821, whereby the main processing circuit splits the data to be integrated according to the integration instruction and the processing capabilities of the slave processing circuits, following a splitting rule; sub-step 822, whereby the data to be integrated is stored in the first storage circuit for transmission to the scheduled multiple slave processing circuits via a broadcast bus during the arithmetic operation; and sub-step 823, whereby the accumulation index allocated to each scheduled slave processing circuit is stored in the second storage circuit for the scheduled slave processing circuits to load the corresponding portion of the accumulation index for arithmetic operation.

[0082] Specifically, in sub-step 821, the main processing circuit can split the data to be integrated into L parts according to the storage dimension from low to high. N A block of integral data, to be used by L N The round operation performs the integration operation. Then, in sub-step 822, the main processing circuit transmits an integration data block to the multiple scheduled slave processing circuits via the broadcast bus in each round operation.

[0083] Step 820 may further include sub-step 824, in which the processing circuit performs corresponding integration operations on the integration data block of the current round according to the allocated accumulation index to obtain a partial integration value, which is then returned to the main processing circuit. Specifically, the integration operation may include bitwise multiplication and accumulation operations, as described above.

[0084] Step 820 may further include sub-step 825, in which the main processing circuit accumulates the partial integral values ​​obtained from the slave processing circuits. Specifically, the accumulation circuit in the main processing circuit can accumulate the partial integral values ​​received from each slave processing circuit in the current round with the partial integral value corresponding to the maximum accumulation index in the previous round, thereby updating each partial integral value. The register in the main processing circuit stores the partial integral value corresponding to the maximum accumulation index among the updated partial integral values.

[0085] Those skilled in the art will understand that the steps described in the method flowchart are combined with the preceding steps. Figure 4-7 The various circuits of the described computing device correspond to each other, so the features described above also apply to the method steps, and will not be repeated here.

[0086] This disclosure also provides a chip that may include the computing device of any of the embodiments described above in conjunction with the accompanying drawings. Furthermore, this disclosure also provides a board that may include the aforementioned chip.

[0087] Depending on the application scenario, the electronic devices or apparatus disclosed herein may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablets, smart terminals, PC devices, IoT terminals, mobile terminals, mobile phones, dashcams, navigators, sensors, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, autonomous driving terminals, vehicles, home appliances, and / or medical devices. The vehicles include airplanes, ships, and / or vehicles; the home appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; the medical devices include MRI scanners, ultrasound machines, and / or electrocardiographs. The electronic devices or apparatus disclosed herein can also be applied in fields such as the Internet, IoT, data centers, energy, transportation, public management, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, and healthcare. Furthermore, the electronic devices or apparatus disclosed herein can also be used in application scenarios related to artificial intelligence, big data, and / or cloud computing, such as cloud computing, edge computing, and terminal applications. In one or more embodiments, the high-computing-power electronic devices or apparatuses according to the present disclosure can be applied to cloud devices (e.g., cloud servers), while the low-power electronic devices or apparatuses can be applied to terminal devices and / or edge devices (e.g., smartphones or cameras). In one or more embodiments, the hardware information of the cloud devices and the hardware information of the terminal devices and / or edge devices are compatible with each other, so that suitable hardware resources can be matched from the hardware resources of the cloud devices to simulate the hardware resources of the terminal devices and / or edge devices based on the hardware information of the terminal devices and / or edge devices, so as to complete the unified management, scheduling and collaborative work of end-to-cloud or cloud-edge-end integration.

[0088] It should be noted that, for the sake of brevity, this disclosure describes some methods and their embodiments as a series of actions and combinations thereof. However, those skilled in the art will understand that the solutions disclosed herein are not limited by the order of the described actions. Therefore, based on the disclosure or teachings of this document, those skilled in the art will understand that some steps can be performed in a different order or simultaneously. Furthermore, those skilled in the art will understand that the embodiments described in this disclosure can be considered optional embodiments, that is, the actions or modules involved are not necessarily essential for the implementation of one or more solutions disclosed herein. In addition, depending on the solution, the description of some embodiments in this disclosure may have different emphases. In view of this, those skilled in the art will understand that parts not described in detail in a certain embodiment of this disclosure can also be referred to the relevant descriptions of other embodiments.

[0089] In terms of specific implementation, based on the disclosure and teachings of this document, those skilled in the art will understand that several embodiments disclosed herein can also be implemented in other ways not disclosed herein. For example, regarding the various units in the electronic device or apparatus embodiments described above, this document has divided them based on logical functions, but in actual implementation, there may be other ways of division. As another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. Regarding the connection relationships between different units or components, the connections discussed above in conjunction with the accompanying drawings can be direct or indirect couplings between units or components. In some scenarios, the aforementioned direct or indirect couplings involve communication connections utilizing interfaces, where the communication interface can support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

[0090] In this disclosure, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed across multiple network units. Furthermore, depending on actual needs, some or all of the units can be selected to achieve the purpose of the solution described in the embodiments of this disclosure. Additionally, in some scenarios, multiple units in the embodiments of this disclosure may be integrated into one unit or each unit may exist physically independently.

[0091] In other implementation scenarios, the integrated units described above can also be implemented in hardware, i.e., as specific hardware circuits, which may include digital circuits and / or analog circuits. The physical implementation of the circuit's hardware structure may include, but is not limited to, physical devices, which may include, but are not limited to, transistors or memristors. Therefore, the various devices described herein (e.g., computing devices or other processing devices) can be implemented using appropriate hardware processors, such as central processing units, GPUs, FPGAs, DSPs, and ASICs. Furthermore, the aforementioned storage units or storage devices can be any suitable storage medium (including magnetic storage media or magneto-optical storage media), such as resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high-bandwidth memory (HBM), hybrid memory cube (HMC), ROM, and RAM.

[0092] The foregoing can be better understood in accordance with the following terms:

[0093] Clause 1. A computing device, comprising a control circuit and an arithmetic circuit, wherein:

[0094] The control circuit is used to parse integration instructions, the operation object of which includes data to be integrated, and the integration instructions instruct the integration operation to be performed on the data to be integrated; and

[0095] The arithmetic circuit includes multiple slave processing circuits, and the arithmetic circuit is used to schedule a corresponding number of slave processing circuits to perform integration tasks according to the integration instruction, wherein each scheduled slave processing circuit performs the integration operation on the corresponding part of the data to be integrated according to the assigned accumulation index.

[0096] Clause 2. The computing device according to Clause 1, wherein the arithmetic circuitry further comprises a main processing circuit, a first storage circuit, and a second storage circuit, the main processing circuitry being used for:

[0097] Based on the integration instruction and the processing capability of the processing circuit, the data to be integrated is split according to the splitting rules.

[0098] The data to be integrated is stored in the first storage circuit for transmission to multiple scheduled slave processing circuits via a broadcast bus during computation; and

[0099] The accumulated index allocated to each scheduled slave processing circuit is stored in the second storage circuit so that the scheduled slave processing circuit can load the corresponding portion of the accumulated index for calculation.

[0100] Clause 3. The computing device according to Clause 2, wherein the splitting rule includes splitting the data to be integrated in the lowest dimension according to alignment requirements.

[0101] Clause 4. The computing device according to any one of Clauses 2-3, wherein the main processing circuitry is further configured to:

[0102] The data to be integrated is split into L according to the storage dimension from low to high. N A block of integral data, to be used by L N The integration operation is implemented through round-robin processing, in which an integral data block is transmitted to the scheduled slave processing circuits via a broadcast bus in each round-robin process; and

[0103] Assign an accumulation index to each scheduled slave processing circuit to indicate the data that each slave processing circuit needs to accumulate.

[0104] Clause 5. The computing apparatus according to Clause 4, wherein the accumulation index is represented as a bit sequence, wherein "1" indicates that the bit-to-bit integration data participates in the integration, and "0" indicates that the bit-to-bit integration data does not participate in the integration.

[0105] Clause 6. The computing device according to Clause 5, wherein the number of bits with a value of "1" in the accumulation index increases in a stepwise manner according to the order of the processing circuit.

[0106] Clause 7. A computing device according to any one of Clauses 4-6, wherein each of the said slave processing circuits includes a multiplication circuit and an accumulation circuit, and in each round of operation:

[0107] The multiplication circuit is used to perform positional multiplication of the accumulated index allocated to the current slave processing circuit with the integral data block of the current round and output the product result;

[0108] The accumulator circuit is used to accumulate the product results of the multiplication circuit to obtain a partial integral value; and

[0109] The partial integral value is output to the main processing circuit.

[0110] Clause 8. The computing device according to Clause 7, wherein the main processing circuitry further comprises:

[0111] An accumulation circuit is used to accumulate the partial integral value received from each of the processing circuits in the current round with the partial integral value corresponding to the maximum accumulation index in the previous round, so as to update each partial integral value; and

[0112] The register is used to store the partial integral value corresponding to the maximum accumulated index in the updated partial integral value.

[0113] Clause 9. A chip comprising a computing device according to any one of Clauses 1-8.

[0114] Clause 10. A board card including the chip described in Clause 9.

[0115] Clause 11. A data processing method implemented by a computing device, the computing device including a control circuit and an arithmetic circuit, the arithmetic circuit including a plurality of slave processing circuits, the method comprising:

[0116] The control circuit parses the integration command, the object of which includes the data to be integrated, and the integration command instructs that integration be performed on the data to be integrated; and

[0117] The arithmetic circuit schedules a corresponding number of slave processing circuits to perform integration tasks according to the integration instruction, wherein each scheduled slave processing circuit performs the integration operation on the corresponding part of the data to be integrated according to the assigned accumulation index.

[0118] Clause 12. The method according to Clause 11, wherein the arithmetic circuit further includes a main processing circuit, a first storage circuit, and a second storage circuit, the method further comprising:

[0119] The main processing circuit splits the data to be integrated according to the integration instruction and the processing capability of the slave processing circuit, following the splitting rules.

[0120] The data to be integrated is stored in the first storage circuit for transmission to multiple scheduled slave processing circuits via a broadcast bus during computation; and

[0121] The accumulated index allocated to each scheduled slave processing circuit is stored in the second storage circuit so that the scheduled slave processing circuit can load the corresponding portion of the accumulated index for calculation.

[0122] Clause 13. The method according to Clause 12, wherein the splitting rule includes splitting the data to be integrated in the lowest dimension according to alignment requirements.

[0123] Clause 14. The method according to any one of Clauses 12-13, wherein the method further comprises:

[0124] The main processing circuit splits the data to be integrated into L parts according to the storage dimension from low to high. N A block of integral data, to be used by L N The integration operation is implemented through round-robin processing, in which an integral data block is transmitted to the scheduled slave processing circuits via a broadcast bus in each round-robin process; and

[0125] Assign an accumulation index to each scheduled slave processing circuit to indicate the data that each slave processing circuit needs to accumulate.

[0126] Clause 15. The method according to Clause 14, wherein the accumulated index is represented as a bit sequence, wherein "1" indicates that the bit-to-bit integration data participates in the integration, and "0" indicates that the bit-to-bit integration data does not participate in the integration.

[0127] Clause 16. The method according to Clause 15, wherein the number of bits with a value of "1" in the accumulated index increases in a stepwise manner according to the order of the processing circuit.

[0128] Clause 17. The method according to any one of Clauses 14-16, wherein each of the slave processing circuits includes a multiplication circuit and an accumulation circuit, and the method includes: in each round of operation,

[0129] The multiplication circuit will perform positional multiplication between the accumulated index assigned to the current slave processing circuit and the integral data block of the current round, and output the product result; and

[0130] The accumulator circuit accumulates the product results of the multiplication circuit to obtain a partial integral value; and outputs the partial integral value to the main processing circuit.

[0131] Clause 18. The method according to Clause 17, wherein the main processing circuit further includes an accumulation circuit and a register, and the method further includes:

[0132] The accumulation circuit accumulates the partial integral value received from each of the processing circuits in the current round with the partial integral value corresponding to the maximum accumulation index in the previous round, thereby updating each partial integral value; and

[0133] The register stores the portion of the updated partial integral value corresponding to the maximum accumulated index.

[0134] The embodiments of this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

Claims

1. A computing device, comprising a control circuit and an arithmetic circuit, wherein: The control circuit is used to parse integration instructions, the operation object of which includes data to be integrated, and the integration instructions instruct the integration operation to be performed on the data to be integrated; and The arithmetic circuit includes multiple slave processing circuits, and the arithmetic circuit is used to schedule a corresponding number of slave processing circuits to perform integration tasks according to the integration instruction, wherein each scheduled slave processing circuit performs the integration operation on the corresponding part of the data to be integrated according to the assigned accumulation index. The arithmetic circuit further includes a main processing circuit, a first storage circuit, and a second storage circuit. The main processing circuit is used for: Based on the integration instruction and the processing capability of the processing circuit, the data to be integrated is split according to the splitting rules. The data to be integrated is stored in the first storage circuit so that it can be transmitted to multiple scheduled slave processing circuits via a broadcast bus during the operation. as well as The accumulated index allocated to each scheduled slave processing circuit is stored in the second storage circuit so that the scheduled slave processing circuit can load the corresponding portion of the accumulated index for calculation.

2. The computing device according to claim 1, wherein the splitting rule includes splitting the data to be integrated in the lowest dimension according to alignment requirements.

3. The computing device according to claim 1, wherein the main processing circuitry is further configured to: The data to be integrated is split into L according to the storage dimension from low to high. N A block of integral data, to be used by L N The integration operation is implemented through round-robin processing, in which an integral data block is transmitted to the scheduled slave processing circuits via a broadcast bus in each round-robin process; and Assign an accumulation index to each scheduled slave processing circuit to indicate the data that each slave processing circuit needs to accumulate.

4. The computing device according to claim 3, wherein the accumulation index is represented as a bit sequence, wherein "1" indicates that the bit-to-bit integration data participates in the integration, and "0" indicates that the bit-to-bit integration data does not participate in the integration.

5. The computing device according to claim 4, wherein the number of bits with a value of "1" in the accumulated index increases in a stepwise manner according to the order of the processing circuit.

6. The computing device according to any one of claims 3-5, wherein each of the slave processing circuits includes a multiplication circuit and an accumulation circuit, and in each round of operation: The multiplication circuit is used to perform positional multiplication of the accumulated index allocated to the current slave processing circuit with the integral data block of the current round and output the product result; The accumulator circuit is used to accumulate the product results of the multiplication circuit to obtain a partial integral value; as well as The partial integral value is output to the main processing circuit.

7. The computing device of claim 6, wherein the main processing circuit further comprises: An accumulation circuit is used to accumulate the partial integral value received from each of the processing circuits in the current round with the partial integral value corresponding to the maximum accumulation index in the previous round, so as to update each partial integral value. as well as The register is used to store the partial integral value corresponding to the maximum accumulated index in the updated partial integral value.

8. A chip comprising a computing device according to any one of claims 1-7.

9. A circuit board comprising the chip according to claim 8.

10. A data processing method implemented by a computing device, the computing device including a control circuit and an arithmetic circuit, the arithmetic circuit including a plurality of slave processing circuits, the method comprising: The control circuit parses the integration command, the operation object of the integration command includes the data to be integrated, and the integration command instructs to perform integration operation on the data to be integrated; as well as The arithmetic circuit schedules a corresponding number of slave processing circuits to perform integration tasks according to the integration instruction, wherein each scheduled slave processing circuit performs the integration operation on the corresponding part of the data to be integrated according to the assigned accumulation index. The arithmetic circuit further includes a main processing circuit, a first storage circuit, and a second storage circuit, and the method further includes: The main processing circuit splits the data to be integrated according to the integration instruction and the processing capability of the slave processing circuit, following the splitting rules. The data to be integrated is stored in the first storage circuit for transmission to multiple scheduled slave processing circuits via a broadcast bus during computation; and The accumulated index allocated to each scheduled slave processing circuit is stored in the second storage circuit so that the scheduled slave processing circuit can load the corresponding portion of the accumulated index for calculation.

11. The method of claim 10, wherein the splitting rule includes splitting the data to be integrated in the lowest dimension according to alignment requirements.

12. The method of claim 10, wherein the method further comprises: The main processing circuit splits the data to be integrated into L parts according to the storage dimension from low to high. N A block of integral data, to be used by L N The round operation implements the integration operation, and in each round operation, an integration data block is transmitted to the multiple scheduled slave processing circuits via a broadcast bus; as well as Assign an accumulation index to each scheduled slave processing circuit to indicate the data that each slave processing circuit needs to accumulate.

13. The method of claim 12, wherein the cumulative index is represented as a bit sequence, wherein "1" indicates that the bit-specific integration data participates in the integration, and "0" indicates that the bit-specific integration data does not participate in the integration.

14. The method of claim 13, wherein the number of bits with a value of "1" in the accumulated index increases in a stepwise manner according to the order of the processing circuit.

15. The method according to any one of claims 12-14, wherein each of the slave processing circuits includes a multiplication circuit and an accumulation circuit, and the method comprises: In each round of calculation, The multiplication circuit will perform positional multiplication between the accumulated index assigned to the current slave processing circuit and the integral data block of the current round, and output the product result. as well as The accumulator circuit accumulates the product results of the multiplication circuit to obtain a partial integral value; And output the partial integral value to the main processing circuit.

16. The method of claim 15, wherein the main processing circuit further includes an accumulation circuit and a register, and the method further includes: The accumulation circuit accumulates the partial integral value received from each of the processing circuits in the current round with the partial integral value corresponding to the maximum accumulation index in the previous round, so as to update each partial integral value. as well as The register stores the partial integral value corresponding to the maximum accumulated index among the updated partial integral values.

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